onsemi-NTP125N02R
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onsemi
. “
T
ypical” parameters which may be provided in
onsemi
data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts.
onsemi
does not convey any license under any of its intellectual property rights nor the rights of others.
onsemi
products are not designed, intended, or authorized
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products for any such unintended or unauthorized application, Buyer shall indemnify and hol
d
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NTB125N02R, NTP125N02R
Power MOSFET
125 A, 24 V N−Channel
TO−220, D
2
PAK
Features
•
Planar HD3e Process for Fast Switching Performance
•
Body Diode for Low t
and Q
and Optimized for Synchronous
rr
rr
Operation
125 AMPERES, 24 VOLTS
•
Low C
to Minimize Driver Loss
iss
R
DS(on)
= 3.7 m
W
(Typ)
•
Optimized Q
and R
for Shoot−through Protection
gd
DS(on)
•
Low Gate Charge
•
Pb−Free Packages are Available
D
MAXIMUM RATINGS
(T =
25
°
C Unless otherwise specified)
J
G
Parameter
Drain−to−Source Voltage
Symbol Value
Unit
V
24
20
V
V
DSS
dc
S
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
V
GS
dc
R
P
1.1
113.6
°
C/W
W
q
JC
MARKING
DIAGRAMS
T
o
tal Power Dissipation @ T
= 25
°
C
C
D
Drain Current −
Continuous @ T
= 25
°
C, Chip
I
125
120.5
95
A
A
A
A
4
C
D
Continuous @ T
= 25
°
C, Limited by Package
I
I
I
C
D
D
D
Continuous @ T
= 25
°
C, Limited by Wires
A
Single Pulse (t
= 10
m
s)
250
p
TO−220AB
CASE 221A
STYLE 5
Thermal Resistance −
T
o
tal Power Dissipation @ T
= 25
°
C
Drain Current − Continuous @ T
= 25
°
C
125N2RG
AYWW
R
P
I
46
2.72
18.6
°
C/W
W
A
q
JA
A
D
A
D
Thermal Resistance −
T
o
tal Power Dissipation @ T
= 25
°
C
Drain Current − Continuous @ T
= 25
°
C
1
R
P
I
63
1.98
15.9
°
C/W
W
A
q
JA
2
2
A
D
3
3
A
D
Operating and Storage
T
e
mperature Range
T , T
−55 to
150
°
C
J
stg
125N2G
AYWW
2
4
D PAK
Single Pulse Drain−to−Source Avalanche
E
AS
120
mJ
CASE 418AA
STYLE 2
Energy − Starting T
= 25
°
C
J
1
(V =
50 V
, V
= 10 V
, I
= 15.5 A
,
DD
dc
GS
dc
L
pk
L = 1 mH, R
= 25
W
)
G
Maximum Lead
T
e
mperature for Soldering
Purposes, 1/8
″
from Case for 10 Seconds
T
L
260
°
C
125N2x =
Device Code
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
x
= R
A
Y
= Assembly Location
=
Y
e
ar
WW
G
= Work Week
= Pb−Free Package
1. When
surface mounted to an FR4 board using 1 inch pad size,
2
(Cu Area 1.127 in
).
2. When
surface mounted to an FR4 board using minimum recommended pad
2
size, (Cu Area 0.412 in
).
PIN ASSIGNMENT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
PIN
1
FUNCTION
Gate
2
Drain
3
Source
Drain
4
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 7
NTB125N02R/D
NTB125N02R, NTP125N02R
ELECTRICAL CHARACTERISTICS
(T =
25
°
C Unless otherwise specified)
J
Characteristics
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
(V =
0 V
, I
= 250
m
A
V
V
dc
(BR)DSS
)
dc
25
−
28
15
−
−
GS
dc
D
T
e
mperature Coefficient (Positive)
mV/
°
C
Zero Gate Voltage Drain Current
I
m
A
dc
DSS
(V =
20 V
, V
= 0 V
)
dc
−
−
−
−
1.5
10
DS
dc
GS
(V =
20 V
, V
= 0 V
, T
= 125
°
C)
DS
dc
GS
dc
J
Gate−Body Leakage Current
(V 20
V ,
V =
0 V
)
dc
I
nA
dc
GSS
=
−
−
100
GS
dc
DS
V
V
dc
GS(th)
(V =
V ,
I =
250
m
A )
1.0
−
1.5
5.0
2.0
−
DS
GS
D
dc
Threshold
T
e
mperature Coefficient (Negative)
mV/
°
C
m
W
R
DS(on)
(V =
10 V
, I
= 110 A
)
dc
−
−
−
−
3.7
4.9
3.7
4.7
−
−
4.6
6.2
GS
dc
D
(V =
4.5 V
, I
= 55 A
)
GS
dc
D
dc
(V =
10 V
, I
= 20 A
)
GS
dc
D
dc
(V =
4.5 V
, I
= 20 A
)
GS
dc
D
dc
(V =
10 V
, I
= 15 A
g
Mhos
pF
FS
)
dc
−
44
−
DS
dc
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
2710
1105
227
3440
1670
640
iss
Output Capacitance
C
oss
(V =
20 V
, V
= 0
V
, f = 1
M
Hz)
DS
dc
GS
Transfer Capacitance
C
rss
ns
Turn−On Delay Time
Rise Time
t
−
−
−
−
−
−
−
11
39
22
80
40
40
28
−
d(on)
t
r
(V =
10 V
, V
= 10 V
,
dc
GS
dc
DD
I
D
= 40 A
, R
= 3
W
)
dc G
Turn−Off Delay Time
Fall Time
t
27
d(off)
tf
21
Gate Charge
nC
Q
T
Q
1
Q
2
23.6
5.1
11
(V =
4.5 V
, I
= 40 A
,
dc
GS
dc
D
V
DS
dc
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
SD
−
−
−
0.82
0.99
0.65
1.2
−
−
V
dc
S
dc
GS
dc
(I =
55 A
, V
= 0 V
)
S
dc
GS
dc
(I =
20 A
, V
= 0 V
, T
= 125
°
C)
S
dc
GS
dc
J
Reverse Recovery Time
ns
t
−
−
−
−
36.5
17.7
−
−
−
−
rr
t
a
(I =
30 A
, V
= 0 V
,
dc
S
S
dc
GS
t
18.8
b
Reverse Recovery Stored Charge
Q
0.024
m
C
RR
3. Pulse
T
e
st: Pulse Width
v
300
m
s, Duty Cycle
v
2%.
4. Switching
characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
†
Device
Package
Shipping
NTP125N02R
TO−220AB
50 Units / Rail
50 Units / Rail
NTP125N02RG
TO−220AB
(Pb−Free)
2
NTB125N02R
50 Units / Rail
50 Units / Rail
D PAK
2
NTB125N02RG
D PAK
(Pb−Free)
2
NTB125N02RT4
800 Units /
T
a
pe & Reel
800 Units /
T
a
pe & Reel
D PAK
2
NTB125N02RT4G
D PAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
2
NTB125N02R, NTP125N02R
200
160
120
80
200
4.0 V
4.5 V
3.5 V
3.0 V
V
DS
≥
10 V
160
120
80
5.0 V
6.0 V
8.0 V
10 V
T =
125
°
C
J
V
GS
= 2.5 V
T =
25
°
C
J
40
0
40
0
T =
−55
°
C
J
0
2
4
6
8
10
0
0.8
1.6
2.4
3.2
4.0
V
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
DS
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.01
0.008
0.006
0.01
0.008
0.006
V
= 4.5 V
= 10 V
GS
GS
T =
125
°
C
J
T =
125
°
C
J
T =
25
°
C
J
T =
25
°
C
J
T =
−55
°
C
J
0.004
0.002
0.004
0.002
T =
−55
°
C
J
0
40
80
120
160
200
0
40
80
120
160
200
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Temperature
100,000
10,000
1.8
1.6
1.4
1.2
1.0
V
GS
= 0 V
I
V
= 55 A
D
= 4.5 V
GS
T =
150
°
C
J
T =
125
°
C
J
1000
100
10
T =
100
°
C
J
0.8
0.6
−50 −25
0
25
50
75
100
125 150
0
4.0
8.0
12
16
20
24
T , JUNCTION TEMPERATURE (
°
C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
3
NTB125N02R, NTP125N02R
10
7000
6000
5000
4000
3000
2000
V
= 0 V
= 0 V
V
DS
GS
C
C
iss
8.0
6.0
V
GS
rss
Q
T
C
iss
4.0
Q
Q
2
1
C
C
oss
2.0
0
I
= 40 A
D
1000
0
T =
25
°
C
J
rss
T =
25
°
C
J
10
5
0
5
10
15
20
0
8
16
24
32
40
48
V
GS
V
DS
Q ,
TOTAL GATE CHARGE (nC)
g
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
1000
60
50
40
30
20
10
0
V
= 10 V
= 40 A
= 10 V
DS
V
GS
= 0 V
I
D
T =
25
°
C
J
V
GS
100
t
r
t
d(off)
t
f
t
d(on)
10
1
10
R ,
GATE RESISTANCE (
W
)
100
0
0.2
0.4
0.6
0.8
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
G
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
1000
V
GS
= 20 V
SINGLE PULSE
= 25
°
C
T
C
100
100
m
s
1 ms
10 ms
10
dc
R
Limit
DS(on)
Thermal Limit
Package Limit
1.0
0.1
1.0
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
4
NTB125N02R, NTP125N02R
1
Normalized to R
at Steady State
q
JC
0.1
0.01
0.00001
0.0001
0.001
0.01
t, TIME (s)
0.1
1
10
Figure 12. Thermal Response
5
NTB125N02R, NTP125N02R
PACKAGE DIMENSIONS
D
2
PAK
CASE 418AA−01
ISSUE O
NOTES:
C
1. DIMENSIONING
AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING
DIMENSION: INCH.
E
V
−B−
W
INCHES
DIM MIN
MAX
MILLIMETERS
4
MIN
MAX
A
B
C
D
E
F
G
J
K
M
S
V
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.036
0.045 0.055
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
4.83
0.92
1.40
−−−
A
S
1
2
3
0.310
0.100 BSC
0.018 0.025
−−−
2.54 BSC
0.46
2.29
7.11
0.64
2.79
−−−
−T−
SEATING
PLANE
K
0.090
0.280
0.110
−−−
W
0.575 0.625 14.60 15.88
0.045 0.055
1.14 1.40
J
G
STYLE 2:
PIN 1.
GATE
D
3 PL
M
M
T B
0.13 (0.005)
2. DRAIN
3. SOURCE
4. DRAIN
VARIABLE
CONFIGURATION
ZONE
U
M
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
6
NTB125N02R, NTP125N02R
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING
AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING
DIMENSION: INCH.
3. DIMENSION
Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
B
F
T
S
4
INCHES
DIM MIN
MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
−−−
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
1
2
3
U
H
G
H
J
K
L
L
R
N
Q
R
S
T
V
J
G
D
U
V
Z
N
0.080
2.04
STYLE 5:
PIN 1.
GATE
2. DRAIN
3. SOURCE
4. DRAIN
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMEN
T
:
N. American Technical Support
: 800−282−9855
T
o
ll Free
USA/Canada
Literature Distribution Center for ON Semiconductor
P
.
O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone
: 480−829−7710 or 800−344−3860
T
o
ll Free USA/Canada
Fax
: 480−829−7709 or 800−344−3867
T
o
ll Free USA/Canada
Email
: orderlit@onsemi.com
Japan
: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku,
T
o
kyo, Japan 153−0051
Phone
: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NTB125N02R/D
