onsemi-NTP5864NG
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NTP5864N
MOSFET
– Power
60
V
,
6
3 A, 12.4 m
W
Features
•
Low R
DS(on)
•
High Current Capability
•
Avalanche Energy Specified
I
MAX
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
D
V
R
MAX
DS(ON)
(Note 1)
(BR)DSS
Compliant
60 V
12.4 m
Ω
@ 10 V
63 A
MAXIMUM RATINGS
(T =
25
°
C unless otherwise stated)
J
N
−
Channel
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value Units
D
V
DSS
60
20
30
V
V
V
Gate
−
to
−
Source Voltage
−
Continuous
Gate
−
to
−
Source Voltage
−
V
GS
GS
V
Non
−
Repetitive (t
= 10
ꢀ
s)
p
G
Continuous Drain
I
A
T
= 25
°
C
= 100
°
C
= 25
°
C
63
45
D
C
Steady
State
Current
−
R
ꢁ
JC
T
C
S
Power Dissipation
−
P
W
T
C
107
54
D
Steady
State
R
ꢁ
JC
T
C
= 100
°
C
MARKING DIAGRAM
& PIN ASSIGNMENT
Pulsed Drain Current
t =
10
ꢀ
s
p
I
252
A
DM
Operating Junction and Storage
T
e
mperature
T ,
STG
−
55 to
175
4
°
C
J
T
Drain
4
Source Current (Body Diode) Pulsed
I
63
80
A
mJ
A
S
Single Pulse Drain
−
to Source Avalanche
Energy
−
(L = 0.1 mH)
EAS
IAS
40
TO
−
220AB
CASE 221A
STYLE 5
Lead
T
e
mperature for Soldering Purposes
(1/8” from case for 10 s)
260
°
C
T
L
NTP5864NG
AYWW
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1
Gate
3
1
2
Source
3
THERMAL RESISTANCE RATINGS
2
Parameter
Symbol
Max
Units
A
Y
WW
G
= Assembly Location
=
Y
e
ar
= Work Week
Drain
Junction
−
to
−
Case (Drain)
−
Steady State
R
1.4
°
C/W
θ
JC
= Pb
−
Free Package
R
33
°
C/W
θ
JA
1. Surface
mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [2 oz] including traces).
ORDERING INFORMATION
Device
Package
Shipping
50 Units / Rail
NTP5864NG
TO
−
220
(Pb
−
Free)
©
Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
June, 2019
−
Rev. 1
NTP5864N/D
NTP5864N
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise stated)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
= 250
ꢀ
A
60
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/T
J
58
mV/
°
C
(BR)DSS
Zero Gate Voltage Drain Current
I
V
V
= 0
V
,
T =
25
°
C
1.0
ꢀ
A
DSS
GSS
GS
DS
J
= 60 V
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
GS
20 V
100
nA
DS
V
V
= V
, I
= 250
ꢀ
A
2.0
4.0
V
GS(TH)
GS
DS
D
Gate Threshold
T
e
mperature
Coefficient
V
/T
−
10
mV/
°
C
GS(TH)
J
Drain
−
to
−
Source On Resistance
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
R
V
= 10 V, I
= 20 A
10.2
10
12.4
m
ꢂ
DS(on)
GS
D
g
FS
V
= 15 V, I
= 20 A
S
DS
D
C
1680
189
124
31
pF
nC
ISS
V
GS
= 0
V
, f =
1
.0 MHz,
Output Capacitance
C
OSS
RSS
V
DS
= 25 V
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
Q
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Gate Resistance
Q
2.0
7.3
10
G(TH)
V
GS
= 10
V
, V
=
4
8 V,
DS
I
= 20 A
D
Q
GS
Q
GD
R
0.5
ꢂ
g
GS
Turn
−
On Delay Time
Rise Time
t
10
6.4
18
ns
d(ON)
t
r
V
= 10 V, V
= 48 V,
DD
GS
D
I
= 20 A, R
= 2.5
ꢂ
G
Turn
−
Off Delay Time
Fall Time
t
d(OFF)
t
f
4.6
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
0.94
0.84
24
1.2
V
SD
J
V
= 0
V
,
GS
S
I =
40 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
16
a
V
= 0
V
, dI
/dt = 100 A/
ꢀ
s,
SD
GS
I =
20 A
S
Discharge Time
7.9
20
b
Reverse Recovery Charge
Q
nC
RR
2. Pulse
T
e
st: pulse width
≤
300
ꢀ
s, duty cycle
≤
2%.
3. Switching
characteristics are independent of operating junction temperatures.
2
NTP5864N
TYPICAL CHARACTERISTICS
125
125
100
75
50
25
0
V
GS
= 10 V
7.5 V
7 V
T =
25
°
C
V
DS
≥
10 V
J
100
75
50
25
0
6.5 V
5.5 V
5.0 V
4.5 V
T =
25
°
C
J
T =
125
°
C
J
T =
−
55
°
C
J
0
1
2
3
4
5
2
3
4
5
6
7
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.030
0.025
0.020
0.015
0.010
0.005
0.000
0.0115
0.0110
0.0105
I
= 20 A
D
V
= 10 V
GS
T =
25
°
C
J
T =
25
°
C
J
0.0100
0.0095
4
5
6
7
8
9
10
10 15 20 25 30 35
40 45 50
55 60
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate Voltage
Figure 4. On
−
Resistance vs. Drain Current
100000
10000
1000
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
I
V
= 20 A
D
V
GS
= 0 V
= 10 V
GS
T =
150
°
C
J
T =
125
°
C
J
100
−
50
−
25
0
25
50
75
100 125 150 175
10
20
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
30
40
50
60
T , JUNCTION TEMPERATURE (
°
C)
J
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NTP5864N
TYPICAL CHARACTERISTICS
10
2500
2000
1500
1000
V
= 0 V
Q
GS
T
T =
25
°
C
J
8
6
4
C
iss
Q
Q
gd
gs
500
0
2
0
C
oss
I
= 20 A
D
T =
25
°
C
C
J
rss
0
5
10
15
20
25
30
0
10
20
30
40
50
60
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source vs. Total Charge
1000
100
10
100
90
80
70
60
50
40
30
20
V
= 0 V
V
I
= 48 V
= 20 A
= 10 V
GS
DD
T =
25
°
C
J
D
V
GS
t
d(off)
t
d(on)
t
r
t
f
10
0
1
1
10
R ,
GATE RESISTANCE (
ꢂ
)
100
0.40 0.50
0.60 0.70 0.80 0.90 1.00
1.10 1.20
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
80
70
60
50
40
30
20
10
0
I
D
= 40 A
10
ꢀ
s
100
ꢀ
s
1 ms
10 ms
dc
V
= 10 V
SINGLE PULSE
GS
T
C
= 25
°
C
1
R
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
DS(on)
0.1
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
T , STARTING JUNCTION TEMPERATURE
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
4
NTP5864N
TYPICAL CHARACTERISTICS
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.1
0.01
0.01
SINGLE PULSE
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
t, PULSE TIME (s)
Figure 13. Thermal Response
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO
−
220
CASE 221A
−
09
ISSUE AJ
DATE 05 NOV 2019
SCALE 1:1
STYLE 1:
PIN 1.
BASE
2. COLLECTOR
STYLE 2:
PIN 1.
BASE
2. EMITTER
STYLE 3:
STYLE 4:
PIN 1.
MAIN TERMINAL 1
PIN 1.
CATHODE
2. ANODE
3. GATE
2. MAIN
TERMINAL 2
3. GATE
3. EMITTER
3. COLLECTOR
4. EMITTER
4. COLLECTOR
4. ANODE
4. MAIN
TERMINAL 2
STYLE 5:
PIN 1.
GATE
STYLE 6:
PIN 1.
ANODE
STYLE 7:
STYLE 8:
PIN 1.
CATHODE
2. ANODE
PIN 1.
CATHODE
2. ANODE
2. DRAIN
3. SOURCE
4. DRAIN
2. CATHODE
3. ANODE
3. CATHODE
4. ANODE
3. EXTERNAL
TRIP/DELAY
4. ANODE
4. CATHODE
STYLE 9:
PIN 1.
GATE
STYLE 10:
PIN 1.
GATE
STYLE 11:
STYLE 12:
PIN 1.
DRAIN
2. SOURCE
3. GATE
PIN 1.
MAIN TERMINAL 1
2. MAIN
TERMINAL 2
3. GATE
2. COLLECTOR
3. EMITTER
2. SOURCE
3. DRAIN
4. COLLECTOR
4. SOURCE
4. SOURCE
4. NOT
CONNECTED
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42148B
TO
−
220
PAGE 1 OF 1
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Semiconductor Components Industries, LLC, 2019
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:
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