onsemi-NTP6412ANG

Part #onsemi-NTP6412ANG
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onsemi-NTP6412ANG
NTB6412AN, NTP6412AN,  
NVB6412AN  
N-Channel Power MOSFET  
100
V
,
5
8 A, 18.2 m
W
 
Features  
•
Low R  
DS(on)  
•
High Current Capability  
•
100% Avalanche Tested  
I
D
MAX  
V
R
MAX  
DS(ON)  
(Note 1)  
•
NVB Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q101  
Qualified and PPAP Capable  
(BR)DSS  
100 V  
18.2 m
W
@ 10 V  
58 A  
•
These Devices are Pb−Free and are RoHS Compliant  
N−Channel  
D
MAXIMUM RATINGS
(T =
 
25
°
C Unless otherwise specified)  
J
Parameter  
Drain−to−Source Voltage  
Gate−to−Source Voltage − Continuous  
Symbol Value  
Unit  
V
V
100  
$
20  
58  
DSS  
G
V
V
GS  
Continuous Drain Cur-
 
Steady  
T
C
= 25
°
C  
= 100
°
C  
= 25
°
C  
I
D
A
rent R  
State  
q
JC  
S
T
C
41  
4
Power Dissipation  
R
Steady  
State  
T
C
P
D
167  
W
q
JC  
4
Pulsed Drain Current  
t =
 
10
m
s  
p
I
240  
A
DM  
1
2
Operating Junction and Storage
T
e
mperature  
Range  
T , T  
−55 to  
+175  
°
C  
J
stg  
3
Source Current (Body Diode)  
I
S
58  
A
2
TO−220AB  
D PAK  
CASE 221A  
STYLE 5  
CASE 418B  
STYLE 2  
Single Pulse Drain−to−Source Avalanche  
E
AS  
300  
mJ  
1
Energy (V
 
= 50 Vdc, V
 
= 10 Vdc,  
DD  
GS  
2
I
= 44.7 A, L = 0.3 mH, R
 
= 25
W
)  
3
L(pk)  
G
Lead
T
e
mperature for Soldering  
Purposes, 1/8
″
from Case for 10 Seconds  
T
260  
°
C  
L
MARKING DIAGRAM  
& PIN ASSIGNMENT  
4
THERMAL RESISTANCE RATINGS  
Parameter  
4
Drain  
Drain  
Symbol  
Max  
0.9  
33  
Unit  
Junction−to−Case (Drain) Steady State  
Junction−to−Ambient

)  
R
°
C/W  
q
JC  
JA  
NTB  
R
q
NTP  
6412ANG  
AYWW  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
1. Surface
 
mounted on FR4 board using 1 sq in pad size,  
6412ANG  
AYWW  
2
1
Gate  
3
1
Gate  
3
Drain  
(Cu Area 1.127 sq in [2 oz] including traces).  
Source  
Source  
2
6412AN = Specific Device Code  
Drain  
G
A
Y
= Pb−Free Device  
= Assembly Location  
=
Y
e
ar  
WW =
 
Work Week  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on

©
Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
January, 2015 − Rev. 2  
NTB6412AN/D  
 

NTB6412AN, NTP6412AN, NVB6412AN  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C Unless otherwise specified)  
J
Characteristics  
OFF CHARACTERISTICS  
Drain−to−Source Breakdown Voltage  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
V
V
= 0
V
, I
 
=
2
50
m
A  
100  
V
(BR)DSS  
GS  
D
Drain−to−Source Breakdown Voltage
T
e
mper-  
ature Coefficient  
V
/T  
J
103  
mV/
°
C  
(BR)DSS  
Zero Gate Voltage Drain Current  
I
V
= 0
V
,  
= 100 V  
T =
 
25
°
C  
1.0  
100  
m
A  
DSS  
GS  
J
V
DS  
T =
 
125
°
C  
J
Gate−to−Source Leakage Current  
ON CHARACTERISTICS

Gate Threshold Voltage  
I
V
= 0
V
, V
 
=
$
20 V  
$
100  
nA  
GSS  
DS  
GS  
V
GS(th)  
V
= V
 
, I
 
= 250
m
A  
2.0  
4.0  
V
GS  
DS  
D
Negative Threshold
T
e
mperature Coefficient  
Drain−to−Source On−Resistance  
V
/T  
9.2  
16.8  
15.6  
31  
mV/
°
C  
m
W  
GS(th)  
J
R
V
= 10
V
, I
 
=
5
8 A  
18.2  
18.2  
DS(on)  
GS  
D
V
GS  
= 10
V
, I
 
=
2
0 A  
D
Forward Transconductance  
g
FS  
V
= 5
V
, I
 
=
2
0 A  
S
DS  
D
CHARGES, CAPACITANCES & GATE RESISTANCE  
Input Capacitance  
C
2700  
400  
150  
73  
3500  
500  
pF  
iss  
V
DS  
= 25
V
, V
 
= 0 V,  
f = 1 MHz  
GS  
Output Capacitance  
Reverse Transfer Capacitance  
T
o
tal Gate Charge  
C
oss  
C
rss  
Q
100  
nC  
G(TOT)  
Threshold Gate Charge  
Gate−to−Source Charge  
Gate−to−Drain Charge  
Plateau Voltage  
Q
2.5  
G(TH)  
V
GS  
= 10
V
, V
 
=
8
0
V
,  
DS  
Q
13.5  
35  
GS  
GD  
GP  
I
D
= 58 A  
Q
V
5.6  
V
Gate Resistance  
R
2.2  
W
G
SWITCHING CHARACTERISTICS, V
 
= 10 V

GS  
Turn−On Delay Time  
Rise Time  
t
16  
140  
70  
ns  
d(on)  
t
r
V
I
= 10
V
, V
 
=
8
0
V
,  
DD  
GS  
= 58 A, R
 
= 6.2
W  
D
G
Turn−Off Delay Time  
Fall Time  
t
d(off)  
t
f
126  
DRAIN−SOURCE DIODE CHARACTERISTICS  
Forward Diode Voltage  
V
T =
 
25
°
C  
0.96  
0.89  
85  
1.3  
V
SD  
J
I
S
= 58 A  
T =
 
125
°
C  
J
Reverse Recovery Time  
Charge Time  
t
ns  
rr  
t
60  
a
V
GS  
= 0
V
, I
 
=
5
8 A,  
S
dI /dt
 
= 100 A/
m
s  
SD  
Discharge Time  
t
b
25  
Reverse Recovery Charge  
Q
270  
nC  
RR  
2. Pulse
 
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.  
3. Switching
 
characteristics are independent of operating junction temperatures.  
2
 

NTB6412AN, NTP6412AN, NVB6412AN  
120  
100  
80  
60  
40  
20  
0
120  
V
DS  
w
10 V  
T =
 
25
°
C  
J
7.5 V  
6.5 V  
100  
80  
60  
40  
20  
0
10 V  
6.0 V  
T =
 
25
°
C  
5.4 V  
5.0 V  
= 4.4 V  
J
T =
 
125
°
C  
J
V
GS  
T =
 
−55
°
C  
J
0
1
2
3
4
5
2
3
4
5
6
7
8
V
GS  
, GATE−TO−SOURCE VOLTAGE (V)  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
Figure 2. Transfer Characteristics  
Figure 1. On−Region Characteristics  
0.04  
0.03  
0.02  
0.01  
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0
I
= 58 A  
D
V
GS  
= 10 V  
T =
 
25
°
C  
J
T =
 
175
°
C  
J
T =
 
125
°
C  
J
T =
 
25
°
C  
J
T =
 
−55
°
C  
J
5
6
7
8
9
10  
10  
20  
30  
40  
50  
60  
V
GS  
, GATE−TO−SOURCE VOLTAGE (V)  
I ,
 
DRAIN CURRENT (A)  
D
Figure 3. On−Region versus Gate Voltage  
Figure 4. On−Resistance versus Drain Current  
and Gate Voltage  
3
2.5  
2
100000  
10000  
1000  
V
GS  
= 0 V  
I
= 58 A  
= 10 V  
D
V
GS  
T =
 
150
°
C  
J
1.5  
1
T =
 
125
°
C  
J
0.5  
100  
−50 −25  
0
25  
50  
75  
100 125 150 175  
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
T , JUNCTION TEMPERATURE (
°
C)  
J
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
Figure 5. On−Resistance Variation with  
Figure 6. Drain−to−Source Leakage Current  
versus Voltage  
Temperature  
3

NTB6412AN, NTP6412AN, NVB6412AN  
10  
5000  
4000  
3000  
2000  
1000  
0
100  
80  
60  
40  
20  
0
Q
T = 25
°
C  
GS  
T
J
V
= 0 V  
8
6
4
2
0
V
GS  
V
DS  
Q
Q
gd  
gs  
C
iss  
V
= 80
 
V  
= 58 A  
DS  
I
D
C
oss  
T =
 
25
°
C  
J
C
rss  
0
10 20 30 40 50 60 70 80 90 100  
, DRAIN−TO−SOURCE VOLTAGE (V)  
0
10  
20  
30  
40  
50  
60  
70  
V
DS  
Q ,
 
TOTAL GATE CHARGE (nC)  
g
Figure 7. Capacitance Variation  
Figure 8. Gate−to−Source Voltage and  
Drain−to−Source Voltage
 
versus Total Charge  
1000  
100  
10  
60  
V
I
= 80 V  
= 58 A  
= 10 V  
T =
 
25
°
C  
GS  
DS  
J
V
= 0 V  
D
50  
40  
30  
20  
10  
0
V
GS  
t
f
t
r
t
d(off)  
t
d(on)  
1
1
10  
R ,
 
GATE RESISTANCE (
W
)  
100  
0.5  
0.6  
, SOURCE−TO−DRAIN VOLTAGE (V)  
SD  
0.7  
0.8  
0.9  
1.0  
V
G
Figure 9. Resistive Switching Time Variation  
versus Gate Resistance  
Figure 10. Diode Forward Voltage versus  
Current  
1000  
100  
10  
300  
200  
100  
0
I
D
= 44.7 A  
10
m
s  
100
m
s  
1 ms  
10 ms  
dc  
1
R
LIMIT  
DS(on)  
V
GS  
= 10 V  
THERMAL LIMIT  
PACKAGE LIMIT  
SINGLE PULSE  
T
C
= 25
°
C  
0.1  
1
10  
100  
1000  
25  
50  
75  
100  
125  
150  
175  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
T , STARTING JUNCTION TEMPERATURE  
J
Figure 11. Maximum Rated Forward Biased  
Safe Operating Area  
Figure 12. Maximum Avalanche Energy versus  
Starting Junction Temperature  
4

NTB6412AN, NTP6412AN, NVB6412AN  
1
0.1  
D = 0.5  
0.2  
0.1  
0.05  
0.02  
0.01  
SINGLE PULSE  
0.01  
0.001  
0.000001  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
t, PULSE TIME (s)  
Figure 13. Thermal Response  
ORDERING INFORMATION  
Device  
†
Package  
Shipping  
2
NTB6412ANG  
D PAK  
50 Units / Rail  
800 /
T
a
pe & Reel  
50 Units / Rail  
(Pb−Free)  
2
NTB6412ANT4G  
NTP6412ANG  
D PAK  
(Pb−Free)  
TO−220  
(Pb−Free)  
2
NVB6412ANT4G  
D PAK  
800 /
T
a
pe & Reel  
(Pb−Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging  
Specifications Brochure, BRD8011/D.  
5

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
TO
−
220  
CASE 221A
−
09  
ISSUE AJ  
DATE 05 NOV 2019  
SCALE 1:1  
STYLE 1:  
PIN 1.
 
BASE  
2. COLLECTOR  
STYLE 2:  
PIN 1.
 
BASE  
2. EMITTER  
STYLE 3:  
STYLE 4:  
PIN 1.
 
MAIN TERMINAL 1  
PIN 1.
 
CATHODE  
2. ANODE  
3. GATE  
2. MAIN
 
TERMINAL 2  
3. GATE  
3. EMITTER  
3. COLLECTOR  
4. EMITTER  
4. COLLECTOR  
4. ANODE  
4. MAIN
 
TERMINAL 2  
STYLE 5:  
PIN 1.
 
GATE  
STYLE 6:  
PIN 1.
 
ANODE  
STYLE 7:  
STYLE 8:  
PIN 1.
 
CATHODE  
2. ANODE  
PIN 1.
 
CATHODE  
2. ANODE  
2. DRAIN  
3. SOURCE  
4. DRAIN  
2. CATHODE  
3. ANODE  
3. CATHODE  
4. ANODE  
3. EXTERNAL
 
TRIP/DELAY  
4. ANODE  
4. CATHODE  
STYLE 9:  
PIN 1.
 
GATE  
STYLE 10:  
PIN 1.
 
GATE  
STYLE 11:  
STYLE 12:  
PIN 1.
 
DRAIN  
2. SOURCE  
3. GATE  
PIN 1.
 
MAIN TERMINAL 1  
2. MAIN
 
TERMINAL 2  
3. GATE  
2. COLLECTOR  
3. EMITTER  
2. SOURCE  
3. DRAIN  
4. COLLECTOR  
4. SOURCE  
4. SOURCE  
4. NOT
 
CONNECTED  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98ASB42148B  
TO
−
220  
PAGE 1 OF 1  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
D

2

PAK 3  
CASE 418B
−
04  
ISSUE L  
DATE 17 FEB 2015  
SCALE 1:1  
NOTES:  
1. DIMENSIONING
 
AND TOLERANCING  
PER ANSI Y14.5M, 1982.  
C
2. CONTROLLING
 
DIMENSION: INCH.  
3. 418B
−
01 THRU 418B
−
03 OBSOLETE,  
NEW STANDARD 418B
−
04.  
E
V
W
−
B
−  
INCHES  
DIM MIN
 
MAX  
MILLIMETERS  
4
MIN  
MAX  
A
B
C
D
E
F
G
H
J
0.340 0.380  
0.380 0.405  
0.160 0.190  
0.020 0.035  
0.045 0.055  
0.310 0.350  
0.100 BSC  
8.64  
9.65 10.29  
4.06  
0.51  
1.14  
7.87  
9.65  
4.83  
0.89  
1.40  
8.89  
A
S
1
2
3
2.54 BSC  
0.080  
0.018 0.025  
0.090 0.110  
0.110  
2.03  
0.46  
2.29  
1.32  
7.11  
5.00 REF  
2.00 REF  
0.99 REF  
2.79  
0.64  
2.79  
1.83  
8.13  
−
T
−  
SEATING  
PLANE  
K
W
J
K
L
G
0.052 0.072  
0.280 0.320  
0.197 REF  
0.079 REF  
0.039 REF  
0.575 0.625 14.60 15.88  
0.045 0.055  
M
N
P
R
S
V
H
D
3 PL  
M
M
T B  
0.13 (0.005)  
1.14  
1.40  
VARIABLE  
CONFIGURATION  
ZONE  
N
P
R
U
L
L
L
M
M
M
F
F
F
VIEW W
−
W  
VIEW W
−
W  
VIEW W
−
W  
1
2
3
STYLE 1:  
STYLE 2:  
STYLE 3:  
STYLE 4:  
STYLE 5:  
PIN 1.
 
CATHODE  
2. ANODE  
STYLE 6:  
PIN 1.
 
NO CONNECT  
2. CATHODE  
PIN 1.
 
BASE  
PIN 1.
 
GATE  
PIN 1.
 
ANODE  
2. CATHODE  
3. ANODE  
PIN 1.
 
GATE  
2. COLLECTOR  
3. EMITTER  
4. COLLECTOR  
2. DRAIN  
3. SOURCE  
4. DRAIN  
2. COLLECTOR  
3. EMITTER  
4. COLLECTOR  
3. CATHODE  
4. ANODE  
3. ANODE  
4. CATHODE  
4. CATHODE  
MARKING INFORMATION AND FOOTPRINT ON PAGE 2  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98ASB42761B  
D

2

PAK 3  
PAGE 1 OF 2  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

D

2

PAK 3  
CASE 418B
−
04  
ISSUE L  
DATE 17 FEB 2015  
GENERIC  
MARKING DIAGRAM*  
xx  
xxxxxxxxx  
AWLYWWG  
AYWW  
xxxxxxxxG  
AKA  
xxxxxxxxG  
AYWW  
IC  
Standard  
Rectifier  
xx  
A
WL  
Y
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
=
Y
e
ar  
WW  
G
AKA  
= Work Week  
= Pb
−
Free Package  
= Polarity Indicator  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
Pb
−
Free indicator, “G” or microdot “
G
”,  
may or may not be present.  
SOLDERING FOOTPRINT*  
10.49  
8.38  
16.155  
3.

2

5

X

04  
2X  
1.016  
5.080  
PITCH  
DIMENSIONS: MILLIMETERS  
*For additional information on our Pb
−
Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98ASB42761B  
D

2

PAK 3  
PAGE 2 OF 2  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent  
coverage may be accessed at

. ON Semiconductor reserves the right to make changes without further notice to any products herein.  
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,  
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer  
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not  
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