onsemi-NVD5C668NLT4G
| Part # | onsemi-NVD5C668NLT4G |
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NVD5C668NL
Power MOSFET
60
V
,
8
.9 m
W
, 49 A, Single N
−
Channel
Features
•
Low R
to Minimize Conduction Losses
•
Low Q
and Capacitance to Minimize Driver Losses
DS(on)
G
•
AEC
−
Q101 Qualified and P
P
A
P Capable
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
V
R
I
D
(BR)DSS
DS(on)
8.9 m
W
@ 10 V
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
60 V
49 A
12.8 m
W
@ 4.5 V
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
60
Unit
V
V
DSS
D
Gate
−
to
−
Source Voltage
V
“
20
49
V
GS
Continuous Drain Cur-
T
= 25
°
C
= 100
°
C
= 25
°
C
I
A
C
D
rent R
q
JC
T
C
34
Steady
State
Power Dissipation R
T
C
P
44
W
A
q
D
JC
G
T
C
= 100
°
C
22
Continuous Drain
Current R
T =
25
°
C
A
I
13
D
S
q
JA
T =
100
°
C
A
9.0
N
−
CHANNEL MOSFET
Steady
State
Power Dissipation R
T =
25
°
C
A
P
3.1
1.5
250
W
q
D
JA
4
T =
100
°
C
A
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
A
A
p
2
1
Operating Junction and Storage
T
e
mperature
T , T
J
−
55 to
175
°
C
stg
3
DPAK
Source Current (Body Diode)
I
25
A
CASE 369C
STYLE 2
S
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
104
mJ
Energy (T
= 25
°
C, I
= 3 A)
J
L(pk)
Lead
T
e
mperature for Soldering Purposes
T
260
°
C
L
MARKING DIAGRAM
& PIN ASSIGNMENT
(1/8
″
from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
4
Drain
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
R
3.4
°
C/W
q
JC
2
R
48.7
Drain
q
JA
1
3
Gate Source
1. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
A
Y
WW
= Assembly Location
=
Y
e
ar
= Work Week
2
2. Surface
−
mounted on FR4 board using a 650 mm
, 2 oz. Cu pad.
3. Maximum
current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
5C668L = Device Code
G
= Pb
−
Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
©
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
March, 2018
−
Rev. 1
NVD5C668NL/D
NVD5C668NL
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Parameter
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
60
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/T
J
27
mV/
°
C
(BR)DSS
Zero Gate Voltage Drain Current
I
m
A
T =
25
°
C
10
DSS
J
V
= 0
V
,
GS
DS
V
= 60 V
T =
125
°
C
J
250
100
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
2
0 V
nA
GSS
DS
GS
V
V
= V
, I
= 50
m
A
1.2
2.1
V
GS(TH)
GS
DS
D
Negative Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
V
/T
4.8
7.4
10.2
60
mV/
°
C
m
W
GS(TH)
J
R
V
= 10
V
, I
=
2
5 A
8.9
DS(on)
GS
D
V
GS
= 4.5
V
, I
=
2
5 A
12.8
D
Forward Transconductance
g
FS
V
= 15
V
, I
=
2
5 A
S
DS
D
CHARGES, CAPACITANCES AND GATE RESISTANCES
pF
Input Capacitance
C
1300
580
18
iss
V
= 0
V
, f =
1
.0 MHz,
DS
GS
Output Capacitance
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
oss
V
= 25 V
C
rss
Q
nC
nC
V
= 4.5 V
= 10 V
8.7
G(TOT)
GS
V
= 48
V
,
= 25 A
DS
I
D
V
18.7
2.4
GS
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Plateau Voltage
Q
G(TH)
Q
4.1
GS
GD
GP
V
GS
= 4.5
V
, V
=
4
8
V
,
DS
I
D
= 25 A
Q
V
2.0
3.1
V
Turn
−
On Delay Time
ns
t
12
74
26
62
d(on)
Rise Time
t
r
V
= 4.5
V
, V
=
4
8
V
,
GS
D
DS
I
= 25 A, R
= 2.5
W
G
Turn
−
Off Delay Time
t
d(off)
Fall Time
t
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
V
T =
25
°
C
0.87
0.76
32
1.2
SD
J
V
S
= 0
V
,
GS
I
= 20 A
T =
125
°
C
J
ns
Reverse Recovery Time
Charge Time
t
RR
ta
15
V
GS
= 0
V
,
d
Is/dt = 100 A/
m
s,
I
S
= 25 A
Discharge Time
tb
16
Reverse Recovery Charge
Q
20
nC
RR
4. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
5. Switching
characteristics are independent of operating junction temperatures.
2
NVD5C668NL
TYPICAL CHARACTERISTICS
100
80
100
V
GS
= 10 V to 5 V
V
DS
= 10 V
80
60
40
3.6 V
3.4 V
60
3.2 V
3.0 V
40
T =
25
°
C
J
20
0
20
0
2.8 V
2.6 V
T =
125
°
C
T =
−
55
°
C
J
J
0
0.5
1.0
1.5
2.0
2.5
0
1
2
3
4
5
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
35
30
25
20
15
10
14
12
T =
25
°
C
D
J
I
= 25 A
V
= 4.5 V
= 10 V
GS
10
8
V
GS
6
4
5
0
2
0
T =
25
°
C
J
3
4
5
6
7
8
9
10
10
20
30
40
50
60
70
80
90 100
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
2.0
1.8
1.6
1.4
1.2
1.0
100K
10K
1K
V
= 10 V
= 25 A
GS
I
D
T =
150
°
C
J
T =
125
°
C
J
T =
85
°
C
J
100
10
0.8
0.6
−
50
−
25
0
25
50
75 100
125 150 175
5
15
25
35
45
55
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NVD5C668NL
TYPICAL CHARACTERISTICS
10K
1K
10
V
= 48 V
= 25 A
DS
9
8
7
6
5
4
3
I
D
C
ISS
T =
25
°
C
J
C
OSS
100
Q
Q
GD
GS
C
RSS
10
1
V
= 0 V
GS
2
1
0
T =
25
°
C
J
f = 1 MHz
0
10
20
30
40
50
60
0
2
4
6
8
10 12 14
16 18
20
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source vs. Total Charge
1000
100
10
100
10
V
GS
= 0 V
V
V
= 4.5 V
= 48 V
= 25 A
GS
DS
I
D
t
r
t
f
1
t
t
d(off)
T =
125
°
C
T =
25
°
C T
=
−
55
°
C
J J
J
d(on)
0.1
1
10
R ,
GATE RESISTANCE (
W
)
100
0.3
0.4
0.5
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
SD
0.6
0.7
0.8
0.9
1.0
V
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
100
10
1
T
= 25
°
C
J(initial)
T
= 100
°
C
J(initial)
V
≤
10 V
GS
10
m
s
0.5 ms
1 ms
Single Pulse
= 25
°
C
T
C
1
R
Limit
DS(on)
Thermal Limit
Package Limit
10 ms
100
0.1
0.1
0.00001
0.1
1
10
1000
0.0001
0.001
0.01
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
4
NVD5C668NL
TYPICAL CHARACTERISTICS
10
1
Duty Cycle = 50%
20%
10%
5%
2%
0.1
1%
Single Pulse
0.01
0.001
1E
−
06
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
ORDERING INFORMATION
Order Number
†
Package
Shipping
NVD5C668NLT4G
DPAK
(Pb
−
Free)
2500 /
T
a
pe & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
4
ISSUE F
2
1
DATE 21 JUL 2015
3
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BOD
Y
.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
A
D
E
C
A
b3
B
c2
4
2
L3
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN
MAX
0.086 0.094
A1
0.000 0.005
0.025 0.035
MILLIMETERS
L4
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
b2
e
BOTTOM VIEW
A
SIDE VIEW
b
b
b2
0.028 0.045
b3
0.180 0.215
M
0.005 (0.13)
C
TOP VIEW
c
0.018 0.024
c2
0.018 0.024
Z
Z
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
GAUGE
PLANE
SEATING
PLANE
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L2
C
0.020 BSC
L3
0.035 0.050
L
BOTTOM VIEW
A1
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
L1
ALTERNATE
CONSTRUCTIONS
DETAIL A
ROTATED 9
0
5
CW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1.
BASE
STYLE 2:
PIN 1.
GATE
2. DRAIN
STYLE 3:
STYLE 4:
STYLE 5:
PIN 1.
GATE
PIN 1.
ANODE
2. CATHODE
3. ANODE
PIN 1.
CATHODE
2. ANODE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. ANODE
3. CATHODE
4. ANODE
3. SOURCE
4. DRAIN
3. GATE
4. ANODE
XXXXXXG
ALYWW
AYWW
XXX
4. CATHODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
PIN 1.
GATE
STYLE 8:
PIN 1.
N/C
STYLE 9:
PIN 1.
ANODE
2. CATHODE
STYLE 10:
PIN 1.
CATHODE
2. ANODE
XXXXXG
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
3. ANODE
4. CATHODE
3. RESISTOR
ADJUST
4. CATHODE
3. CATHODE
4. ANODE
IC
Discrete
SOLDERING FOOTPRINT*
XXXXXX =
Device Code
A
L
Y
WW
G
= Assembly Location
= Wafer Lot
=
Y
e
ar
= Work Week
= Pb−Free Package
6.20
0.244
3.00
0.118
2.58
0.102
*This information is generic. Please refer
to device data sheet for actual part
marking.
5.80
0.228
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
98AON10527D
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
REF TO JEDEC TO−252
NEW STANDARD:
DESCRIPTION: DPAK
SINGLE GAUGE SURFACE MOUNT
PAGE 1 O
F
2
DOCUMENT NUMBER:
98AON10527D
PAGE 2 OF 2
ISSUE
REVISION
RELEASED FOR PRODUCTION. REQ. BY L. GAN
ADDED STYLE 8. REQ. BY S. ALLEN.
DATE
O
A
B
C
D
24 SEP 2001
06 AUG 2008
16 JAN 2009
09 JUN 2009
29 JUN 2010
ADDED STYLE 9. REQ. BY D. WARNER.
ADDED STYLE 10. REQ. BY S. ALLEN.
RELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A.
CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE.
E
F
ADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS
b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAM-
BALIZA.
06 FEB 2014
21 JUL 2015
ADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K.
MUSTAFA.
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights
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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
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SCILLC is an Equal
Opportunity/Affirmative Action Employer.
This literature is subject to all applicable copyright laws and is not for resale in any manner.
©
Semiconductor Components Industries, LLC, 2015
Case Outline Number:
July, 2015 − Rev. F
369C
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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. ON Semiconductor reserves the right to make changes without further notice to any products herein.
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regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
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T
:
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o
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