onsemi-NVMD4N03R2G
| Part # | onsemi-NVMD4N03R2G |
Download  | onsemi-NVMD4N03R2G |
NTMD4N03, NVMD4N03
N-Channel, SO-8
4 A, 30 V
Features
•
Designed for use in low voltage, high speed switching applications
•
Ultra Low On
−
Resistance Provides
Higher Efficiency and Extends Battery Life
V
R
Typ
I Max
D
DSS
DS(ON)
−
R
−
R
= 0.048
W
, V
= 10 V (Typ)
DS(on)
DS(on)
GS
30 V
48 m
W
@ V
= 10 V
4.0 A
GS
= 0.065
W
, V
= 4.5 V (Typ)
GS
•
Miniature SO
−
8 Surface Mount Package
−
Saves Board Space
•
Diode is Characterized for Use in Bridge Circuits
•
Diode Exhibits High Speed, with Soft Recovery
N
−
Channel
D
D
•
NVMD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC
−
Q101
Qualified and PPAP Capable*
•
These Devices are Pb
−
Free and are RoHS Compliant
G
8
G
Applications
S
S
•
DC
−
DC Converters
•
Computers
•
Printers
•
Cellular and Cordless Phones
•
Disk Drives and Tape Drives
MARKING DIAGRAM
*
AND PIN ASSIGNMENT
D1 D1
D2 D2
8
1
SOIC
−
8
SUFFIX NB
CASE 751
STYLE 11
E4N03
AYWW
G
G
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Rating
Symbol
Value
Unit
1
S1 G1
S2 G2
Drain
−
to
−
Source Voltage
Gate
−
to
−
Source Voltage
−
Continuous
Drain Current
V
30
V
V
DSS
V
“
20
GS
E4N03 =
Specific Device Code
A
Y
WW
G
= Assembly Location
=
Y
e
ar
= Work Week
−
Continuous @ T
= 25
°
C
I
D
4.0
12
Adc
Apk
A
−
Single Pulse (tp
≤
10
m
s)
I
DM
T
o
tal Power Dissipation
P
2.0
W
°
C
mJ
D
= Pb
−
Free Package
A
(Note: Microdot may be in either location)
Operating and Storage
T
e
mperature Range
T , T
J
−
55 to
+150
stg
*For additional marking information, refer to
Application Note AND8002/D.
Single Pulse Drain
−
to
−
Source
E
80
AS
Avalanche Energy
−
Starting T
= 25
°
C
J
ORDERING INFORMATION
(V =
25 Vdc, V
= 5.0 Vdc,
DD
GS
Peak I
= 4.45 Apk, L = 8 mH,
L
†
Device
Package
Shipping
R
= 25
W
)
G
NTMD4N03R2G
SOIC
−
8
(Pb
−
Free)
2500 /
T
a
pe &
Reel
Thermal Resistance
R
62.5
260
°
C/W
°
C
q
JA
NVMD4N03R2G*
SOIC
−
8
(Pb
−
Free)
2500 /
T
a
pe &
Reel
Maximum Lead
T
e
mperature for
Soldering Purposes for 10 seconds
T
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specifications
Brochure, BRD8011/D
1. When
surface mounted to an FR4 board using 1
″
pad size, t
≤
10 s
©
Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
May, 2019
−
Rev. 4
NTMD4N03R2/D
NTMD4N03, NVMD4N03
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
(V =
0 Vdc, I
= 250
m
A)
V
Vdc
mV/
°
C
m
Adc
(BR)DSS
30
−
−
−
GS
D
−
32
T
e
mperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
DSS
(V =
30 Vdc, V
= 0 Vdc, T
= 25
°
C)
−
−
−
−
1.0
10
DS
GS
J
(V =
30 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate
−
Body Leakage Current
(V 20
Vdc, V
= 0 Vdc)
I
nAdc
GSS
=
−
−
100
GS
DS
Gate Threshold Voltage
V
Vdc
mV/
°
C
W
GS(th)
(V =
V ,
I =
250
m
Adc)
1.0
1.9
4.2
3.0
DS
GS
D
−
−
T
e
mperature Coefficient (Negative)
Static Drain
−
to
−
Source On
−
State Resistance
R
DS(on)
(V =
10 Vdc, I
= 4 Adc)
−
−
0.048
0.065
0.060
0.080
GS
D
(V =
4.5 Vdc, I
= 2 Adc)
GS
D
Forward Transconductance
(V =
3 Vdc, I
= 2 Adc)
g
Mhos
pF
FS
−
6.0
−
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
285
95
400
135
70
iss
(V =
20 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
35
rss
Turn
−
On Delay Time
t
−
−
−
−
−
−
−
7.0
14
15
30
30
20
16
−
ns
d(on)
(V =
20 Vdc, I
= 2 A,
DD
D
Rise Time
t
r
V
R
= 10
V
,
= 2
W
)
GS
Turn
−
Off Delay Time
Fall Time
t
16
d(off)
G
t
f
10
Gate Charge
Q
T
Q
1
Q
2
8.0
1.1
1.9
nC
(V =
10 Vdc,
V
DS
= 10 Vdc,
= 3.5 A)
GS
I
D
−
Diode Forward On
−
Voltage
(I =
2 Adc, V
= 0 V)
V
SD
−
−
0.82
0.63
1.0
−
Vdc
ns
S
GS
(I =
2 Adc, V
= 0
V
, T
=
1
50
°
C)
S
GS
J
Reverse Recovery Time
t
rr
−
−
−
−
14
10
−
−
−
−
(I =
2 A, V
= 0
V
,
S
GS
t
a
dI /dt
= 100 A/
m
s)
S
t
b
4.0
Reverse Recovery Stored Charge
Q
0.008
m
C
RR
(I =
2 A, dI
/dt = 100 A/
m
s, V
= 0 V)
S
S
GS
2. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
3. Switching
characteristics are independent of operating junction temperature.
2
NTMD4N03, NVMD4N03
TYPICAL MOSFET ELECTRICAL CHARACTERISTICS
7
8
6
4
3.6 V
4 V
10 V
V
DS
≥
10 V
6
5
4
3
2
8 V
6 V
5 V
4.5 V
T =
25
°
C
J
V
GS
= 3 V
2
0
1
0
T =
125
°
C
J
T =
−
55
°
C
J
T =
25
°
C
J
0
0.2
0.4
0.6
0.8
1.0
0
1
2
3
4
5
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.10
0.075
0.05
0.10
0.08
0.06
0.04
V
GS
= 10
T =
25
°
C
J
T = 125
°
C
V
= 4.5 V
= 10 V
GS
V
T = 25
°
C
GS
T =
−
55
°
C
0.025
0
0.02
0
2
3
4
5
6
7
8
2
3
4
5
6
7
8
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On
−
Resistance versus Drain Current
Figure 4. On
−
Resistance versus Drain Current
and Temperature
and Gate Voltage
10,000
1000
1.5
1.375
1.25
1.125
1
V
GS
= 0 V
I
V
= 2 A
D
= 10 V
GS
T =
150
°
C
J
100
10
T =
125
°
C
J
0.875
0.75
−
50
−
25
0
25
50
75
100
125 150
0
5
10
15
20
25
30
T , JUNCTION TEMPERATURE (
°
C)
J
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
versus Voltage
3
NTMD4N03, NVMD4N03
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
D
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C
) is read from the capacitance curve at
a voltage corresponding to the off
−
state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on
−
state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain
−
gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(
A
V
)
rudimentary analysis of the drive circuit so that
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
t =
Q x
R /(V
−
V )
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn
−
on and turn
−
off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
C In
[V /(V
−
V )]
G iss
GG GG
GSP
d(on)
d(off)
= R
C In
(V /V
)
GG GSP
G
iss
800
T =
25
°
C
J
C
C
iss
600
400
rss
C
iss
200
0
C
C
oss
rss
V
= 0 V
V
GS
= 0 V
5
DS
10
5
GS
0
10
15
20
25
V
V
DS
GATE
−
TO
−
SOURCE OR DRAIN
−
TO
−
SOURCE
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
NTMD4N03, NVMD4N03
30
10
100
t
Q
d(off)
T
V
I
= 15 V
= 4 A
= 10 V
DD
t
D
V
f
GS
V
GS
8
6
4
2
0
t
r
20
10
0
V
DS
10
Q
Q
2
1
2
t
d(on)
I
D
= 4 A
T =
25
°
C
J
1
0
1
3
4
5
6
7
8
9
10
1
10
100
Q ,
TOTAL GATE CHARGE (nC)
g
R ,
GATE RESISTANCE (
W
)
G
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
DRAIN
−
TO
−
SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
high di/dts. The diode’s negative di/dt during t
is directly
controlled by the device clearing the stored charge.
a
However, the positive di/dt during t
is an uncontrollable
b
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
/t serves
as a good indicator of recovery
b a
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
device, therefore it has a finite reverse recovery time, t
, due
rr
to the storage of minority carrier charge, Q
, as shown in
RR
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
), have less stored charge and a softer
rr
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
like a diode with short t
and low Q
specifications to
rr
RR
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
4
V
GS
= 0 V
T =
25
°
C
J
3
2
1
0
0.5
0.6
0.7
0.8
0.9
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
5
NTMD4N03, NVMD4N03
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
total power averaged over a complete switching cycle must
not exceed (T
−
T )/(R
).
the maximum simultaneous drain
−
to
−
source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
J(MAX)
C
q
JC
A power MOSFET designated E
−
FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non
−
linearly with an increase of peak current in avalanche
and peak junction temperature.
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance
−
General Data and Its Use.”
Switching between the off
−
state and the on
−
state may
traverse any load line provided neither rated peak current
(I )
nor rated voltage (V
) is exceeded, and that the
DM
DSS
transition time (t , t ) does not exceed 10
m
s. In addition the
r
f
100
10
1
80
V
= 20 V
GS
I
D
= 4.45 A
SINGLE PULSE
T
C
= 25
°
C
60
40
1.0 ms
10 ms
20
0
0.1
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1.0
10
25
50
75
100
125
150
100
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
6
NTMD4N03, NVMD4N03
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
0.1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.0106
W
0.0431
W
0.1643
W
0.3507
W
0.4302
W
CHIP
JUNCTION
0.01
0.0253 F
0.1406 F
0.5064 F
2.9468 F
177.14 F
AMBIENT
SINGLE PULSE
1.0E-04
0.001
1.0E-05
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
1.0E+02
1.0E+03
t, TIME (s)
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC
−
8 NB
CASE 751
−
07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING
AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−
X
−
A
4. MAXIMUM
MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION
D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751
−
01 THRU 751
−
06 ARE OBSOLETE. NEW
STANDARD IS 751
−
07.
S
M
M
Y
B
0.25 (0.010)
1
K
−
Y
−
MILLIMETERS
DIM MIN
MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N
X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−
Z
−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb
−
Free)
IC
IC
(Pb
−
Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
=
Y
e
ar
Y
Y
W
G
=
Y
e
ar
= Work Week
= Pb
−
Free Package
WW
G
= Work Week
= Pb
−
Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC
−
8 NB
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
SOIC
−
8 NB
CASE 751
−
07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1.
EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1.
COLLECTOR, DIE, #1
2. COLLECTOR,
#1
3. COLLECTOR,
#2
4. COLLECTOR,
#2
5. BASE,
#2
PIN 1.
DRAIN, DIE #1
2. DRAIN,
#1
3. DRAIN,
#2
4. DRAIN,
#2
5. GATE,
#2
PIN 1.
ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER,
#2
7. BASE,
#1
6. SOURCE,
#2
7. GATE,
#1
7. BASE
8. EMITTER
8. EMITTER,
#1
8. SOURCE,
#1
8. COMMON
CATHODE
STYLE 5:
STYLE 6:
PIN 1.
SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1.
COLLECTOR, DIE #1
2. BASE,
#1
PIN 1.
DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1.
INPUT
2. EXTERNAL
BYPASS
3. THIRD
STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE
3
7. SECOND
STAGE Vd
8. FIRST
STAGE Vd
3. DRAIN
3. BASE,
#2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR,
#2
5. COLLECTOR,
#2
6. EMITTER,
#2
7. EMITTER,
#1
8. COLLECTOR,
#1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1.
GROUND
2. BIAS
1
STYLE 11:
PIN 1.
SOURCE 1
2. GATE
1
STYLE 12:
PIN 1.
EMITTER, COMMON
2. COLLECTOR,
DIE #1
3. COLLECTOR,
DIE #2
4. EMITTER,
COMMON
5. EMITTER,
COMMON
6. BASE,
DIE #2
PIN 1.
SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS
2
7. INPUT
8. GROUND
3. SOURCE
2
4. GATE
2
5. DRAIN
2
6. DRAIN
2
7. DRAIN
1
8. DRAIN
1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE,
DIE #1
8. EMITTER,
COMMON
STYLE 13:
PIN 1.
N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1.
N
−
SOURCE
2. N
−
GATE
STYLE 15:
PIN 1.
ANODE 1
2. ANODE
1
STYLE 16:
PIN 1.
EMITTER, DIE #1
2. BASE,
DIE #1
3. P
−
SOURCE
4. P
−
GATE
5. P
−
DRAIN
6. P
−
DRAIN
7. N
−
DRAIN
8. N
−
DRAIN
3. ANODE
1
4. ANODE
1
5. CATHODE,
COMMON
6. CATHODE,
COMMON
7. CATHODE,
COMMON
8. CATHODE,
COMMON
3. EMITTER,
DIE #2
4. BASE,
DIE #2
5. COLLECTOR,
DIE #2
6. COLLECTOR,
DIE #2
7. COLLECTOR,
DIE #1
8. COLLECTOR,
DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1.
VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1.
SOURCE 1
2. GATE
1
STYLE 20:
PIN 1.
ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1.
SOURCE (N)
2. GATE
(N)
3. SOURCE
(P)
4. GATE
(P)
5. DRAIN
3. SOURCE
2
4. GATE
2
5. DRAIN
2
6. MIRROR
2
7. DRAIN
1
8. MIRROR
1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1.
CATHODE 1
2. CATHODE
2
3. CATHODE
3
4. CATHODE
4
5. CATHODE
5
6. COMMON
ANODE
7. COMMON
ANODE
8. CATHODE
6
PIN 1.
I/O LINE 1
PIN 1.
LINE 1 IN
PIN 1.
BASE
2. COMMON
CATHODE/VCC
3. COMMON
CATHODE/VCC
4. I/O
LINE 3
5. COMMON
ANODE/GND
6. I/O
LINE 4
7. I/O
LINE 5
8. COMMON
ANODE/GND
2. COMMON
ANODE/GND
3. COMMON
ANODE/GND
4. LINE
2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE
2 OUT
6. COMMON
ANODE/GND
7. COMMON
ANODE/GND
8. LINE
1 OUT
STYLE 25:
PIN 1.
VIN
2. N/C
STYLE 26:
PIN 1.
GND
2. dv/dt
STYLE 27:
PIN 1.
ILIMIT
2. OVLO
STYLE 28:
PIN 1.
SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1.
DRAIN 1
2. DRAIN
1
STYLE 29:
PIN 1.
BASE, DIE #1
2. EMITTER,
#1
3. BASE,
#2
3. GATE
2
4. SOURCE
2
5. SOURCE
1/DRAIN 2
6. SOURCE
1/DRAIN 2
7. SOURCE
1/DRAIN 2
8. GATE
1
4. EMITTER,
#2
5. COLLECTOR,
#2
6. COLLECTOR,
#2
7. COLLECTOR,
#1
8. COLLECTOR,
#1
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