onsemi-NVMFD5853NT1G
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NVMFD5853N,
NVMFD5853NWF
MOSFET
– Dual N-Channel,
Dual SO-8FL
40
V
,
1
0 m
W
, 53 A
Features
•
Small Footprint (5×6 mm) for Compact Designs
•
Low R
to Minimize Conduction Losses
DS(on)
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
•
Low Capacitance to Minimize Driver Losses
•
NVMFD5853NWF
−
Wettable Flanks Product
•
AEC
−
Q101 Qualified and P
P
A
P Capable
•
This is a Pb
−
Free and Halogen
−
Free Device
40 V
10 m
W
@ 10 V
53 A
Dual N
−
Channel
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
D1
D2
J
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
40
Unit
V
V
DSS
Gate
−
to
−
Source Voltage
V
“
20
53
V
GS
G1
G2
Continuous Drain Cur-
rent R
T
= 25
°
C
= 100
°
C
= 25
°
C
I
A
C
D
q
JC
S1
S2
T
C
37
Steady
State
Power Dissipation
T
C
P
58
W
A
D
R
MARKING DIAGRAM
q
JC
T
C
= 100
°
C
29
D1 D1
1
S1
G1
S2
G2
D1
D1
D2
D2
Continuous Drain Cur-
rent R
T =
25
°
C
A
I
12
D
DFN8 5×6
(SO8FL)
5853xx
AYWZZ
q
JA
T =
100
°
C
A
8.7
3.1
1.6
165
Steady
State
CASE 506BT
Power Dissipation
T =
25
°
C
A
P
W
D
D2 D2
R
q
JA
T =
100
°
C
A
5853N =
NVMFD5853N
5853WF = NVMFD5853NWF
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
A
A
p
A
Y
= Assembly Location
=
Y
e
ar
Operating Junction and Storage
T
e
mperature
T , T
−
55 to
175
°
C
J
stg
W
ZZ
= Work Week
= Lot Traceability
Source Current (Body Diode)
I
53
40
A
S
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
mJ
Energy (T
= 25
°
C, I
= 28.3 A, L = 0.1 mH)
J
L(pk)
ORDERING INFORMATION
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
L
260
°
C
†
Device
Package Shipping
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
NVMFD5853NT1G
DFN8
(Pb
−
Free)
1500 /
T
a
pe &
Reel
NVMFD5853NWFT1G
DFN8
(Pb
−
Free)
1500 /
T
a
pe &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specification
Brochure, BRD8011/D.
Parameter
Symbol
Value
2.6
Unit
R
°
C/W
q
JC
R
48
q
JA
1. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface
−
mounted on FR4 board using a 650 mm
, 2 oz. Cu pad.
3. Continuous
DC current rating. Maximum current for pulses as long as 1
second are higher but are dependent on pulse duration and duty cycle.
©
Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
July, 2019
−
Rev. 0
NVMFD5853N/D
NVMFD5853N, NVMFD5853NWF
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
40
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/T
J
41.5
mV/
°
C
(BR)DSS
Zero Gate Voltage Drain Current
I
T =
25
°
C
1.0
100
100
m
A
DSS
J
V
= 0
V
,
GS
DS
V
= 40 V
T =
125
°
C
J
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
GS
20 V
nA
GSS
DS
V
V
= V
, I
= 250
m
A
2.0
4.0
10
V
mV/
°
C
m
W
S
GS(TH)
GS
DS
D
Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
V
/T
J
−
7.2
8.4
44
GS(TH)
R
V
= 10
V
, I
= 15 A
DS(on)
GS D
g
V
= 5
V
, I
=
1
5 A
FS
DS D
C
1225
150
100
24
pF
nC
iss
Output Capacitance
C
oss
V
GS
= 0
V
, f =
1
.0 MHz, V
= 25 V
DS
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
rss
Q
G(TOT)
Threshold Gate Charge
Q
1.5
5.2
6.6
4.1
G(TH)
V
GS
= 10
V
, V
=
3
2
V
,
DS
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Q
GS
GD
GP
I
= 15 A
D
Q
V
Plateau Voltage
V
Turn
−
On Delay Time
Rise Time
t
9
20
21
3
ns
d(on)
t
r
V
V
= 10
V
, V
=
2
0
V
,
DS
GS
D
I
= 15 A, R
= 2.5
W
G
Turn
−
Off Delay Time
Fall Time
t
d(off)
t
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
0.82
0.72
16
10
6
1.1
V
SD
J
= 0
V
,
= 15 A
GS
I
S
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
a
V
= 0
V
, d
/
d =
100 A/
m
s,
IS t
GS
I
S
= 15 A
Discharge Time
b
Reverse Recovery Charge
Q
9
nC
RR
4. Pulse
T
e
st: pulse width = 300
m
s, duty cycle
v
2%.
5. Switching
characteristics are independent of operating junction temperatures.
2
NVMFD5853N, NVMFD5853NWF
TYPICAL CHARACTERISTICS
80
70
80
5.5 V
6.5 V
V
GS
= 5.4 V
5.0 V
70
60
50
40
30
20
V
= 5 V
DS
60
50
40
30
20
10 V
4.6 V
4.5 V
4.2 V
T =
25
°
C
J
T =
150
°
C
J
10
0
4.0 V
10
0
T =
−
55
°
C
J
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
2
3
4
5
6
V
DS
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.050
0.045
0.040
0.035
0.030
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
T =
25
°
C
D
J
T =
25
°
C
J
I
= 15 A
0.025
0.020
0.015
V
GS
= 10 V
40
0.010
0.005
0.005
0
4
5
6
7
8
9
10
0
10
20
30
50
60
70
80
V
GS
, GATE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.150
1.125
1.100
1.075
V
I
= 10 V
= 15 A
GS
I
D
= 250
m
A
D
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.7
0.6
−
50
−
25
0
25
50
75 100
125 150
175
−
50
−
25
0
25
50
75 100
125 150
175
T , JUNCTION TEMPERATURE (
°
C)
J
T , JUNCTION TEMPERATURE (
°
C)
J
Figure 5. On
−
Resistance Variation with
Figure 6. Breakdown Voltage Variation with
Temperature
Temperature
3
NVMFD5853N, NVMFD5853NWF
TYPICAL CHARACTERISTICS
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
100,000
T =
175
°
C
J
I
= 250
m
A
D
10,000
1000
100
T =
150
°
C
J
T =
125
°
C
J
T =
100
°
C
J
T =
85
°
C
J
T =
50
°
C
J
10
1
0.60
0.55
−
50
−
25
0
25
50
75 100 125
150 175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
Figure 7. Threshold Voltage Variation with
Temperature
Figure 8. Drain
−
to
−
Source Leakage Current
vs. Voltage
35
1600
1400
12
Q
T
11
10
9
C
ISS
30
25
20
15
10
V
V
DS
GS
1200
1000
800
8
7
V
= 0 V
6
GS
T =
25
°
C
J
5
4
Q
Q
GD
GS
600
f = 1 MHz
V
I
= 32 V
= 15 A
DS
400
C
3
OSS
D
T =
25
°
C
J
2
5
0
200
0
1
0
C
RSS
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
G
Figure 9. Capacitance Variation
Figure 10. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
1000
100
100
V
V
= 10 V
= 20 V
= 15 A
GS
T =
85
°
C
J
DD
I
D
T =
125
°
C
J
t
t
d(off)
10
f
t
r
T =
150
°
C
J
t
d(on)
T =
25
°
C
J
T =
−
55
°
C
J
10
1
1
0.1
1
10
R ,
GATE RESISTANCE (
W
)
100
0.4
0.5
0.6
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
SD
0.7
0.8
0.9
1.0
1.1
V
G
Figure 11. Resistive Switching Time Variation
vs. Gate Resistance
Figure 12. Diode Forward Voltage vs. Current
4
NVMFD5853N, NVMFD5853NWF
TYPICAL CHARACTERISTICS
1000
100
10
V
≤
10 V
GS
Single Pulse
= 25
°
C
T
C
10
m
s
100
m
s
1 ms
1
10 ms
dc
R
Limit
0.1
DS(on)
Thermal Limit
Package Limit
0.01
0.1
1
10
100
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
100
10
R
Steady State = 48
°
C/W
q
JA
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
1
0.1
Single Pulse
0.01
1E
−
06
1E
−
05
1E
−
04
1E
−
03
1E
−
02
1E
−
01
1E+00
1E+01
1E+02
1E+03
t, TIME (s)
Figure 14. Thermal Impedance (Junction
−
to
−
Ambient)
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5×6, 1.27P Dual Flag (SO8FL
−
Dual)
CASE 506BT
ISSUE F
1
DATE 23 NOV 2021
2X
SCALE 2:1
NOTES:
0.20
C
1. DIMENSIONING
AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
3. DIMENSION
b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TI
P
.
4. PROFILE
TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS
D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
6. SEATING
PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BOD
Y
.
7. A
VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
PIN ONE
E1
MILLIMETERS
IDENTIFIER
DIM
A
A1
b
b1
c
MIN
0.90
−−−
0.33
0.33
0.20
NOM
−−−
−−−
0.42
0.42
−−−
5.15 BSC
4.90
4.10
1.70
6.15 BSC
5.90
4.15
1.27 BSC
0.55
−−−
−−−
−−−
0.61
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
4X
h
1
2
3
4
c
TOP VIEW
D
A1
D1
D2
D3
E
E1
E2
e
G
h
K
K1
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
C
A
DETAIL B
5.70
3.90
6.10
4.40
ALTERNATE
SEATING
PLANE
NOTE 6
DETAIL A
CONSTRUCTION
C
NOTE 4
SIDE VIEW
DETAIL A
0.45
−−−
0.51
0.56
0.48
3.25
1.80
0.65
12
−−−
−−−
_
D2
D3
L
M
N
0.71
3.75
2.20
4X
L
K
3.50
2.00
e
1
4
SOLDERING FOOTPRINT*
DETAIL B
4.56
4X
2X
2.08
2X
0.56
b1
8X
0.75
N
E2
M
8
5
4X
G
b
8X
4X
1.40
0.10
0.05
C
C
A B
K1
6.59
4.84
NOTE 3
2.30
BOTTOM VIEW
3.70
GENERIC
MARKING DIAGRAM*
0.70
1
XXXXXX
AYWZZ
4X
1.27
PITCH
1.00
5.55
XXXXXX = Specific Device Code
DIMENSION: MILLIMETERS
A
Y
W
ZZ
= Assembly Location
=
Y
e
ar
= Work Week
= Lot Traceability
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL
−
DUAL)
PAGE 1 OF 1
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Semiconductor Components Industries, LLC, 2019
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