onsemi-NVMFD5C478NLT1G
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NVMFD5C478NL
Power MOSFET
40
V
,
1
4.5 m
W
, 29 A, Dual N−Channel
Features
•
Small Footprint (5 x 6 mm) for Compact Design
•
Low R
to Minimize Conduction Losses
DS(on)
•
Low Capacitance to Minimize Driver Losses
•
NVMFD5C478N
L
WF − Wettable Flanks Product
•
AEC−Q101 Qualified and P
P
A
P Capable
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
•
These Devices are Pb−Free and are RoHS Compliant
14.5 m
W
@ 10 V
25 m
W
@ 4.5 V
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
40 V
29 A
Parameter
Drain−to−Source Voltage
Symbol
Value
40
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
20
V
Dual−Channel
D1
D2
Continuous Drain
Current R
T
= 25
°
C
= 100
°
C
= 25
°
C
I
29
A
C
D
q
JC
T
C
20.6
23
Steady
State
Power Dissipation
T
C
P
W
A
D
R
q
JC
G1
G2
T
C
= 100
°
C
12
Continuous Drain
Current R
T =
25
°
C
A
I
D
10.5
7.5
3.1
1.5
98
S1
S2
q
JA
T =
100
°
C
A
Steady
State
MARKING AND PIN
CONNECTION DIAGRAM
D1 D1
Power Dissipation
T =
25
°
C
A
P
W
D
R
q
JA
T =
100
°
C
A
S1
G1
S2
G2
D1
D1
D2
D2
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
A
A
p
1
XXXXXX
AYWZZ
Operating Junction and Storage
T
e
mperature
T , T
−55 to
+175
°
C
J
stg
DFN8, 5×6
(S08FL)
CASE 506BT
Source Current (Body Diode)
I
19
48
A
D2 D2
S
XXXXXX = 5C478L (NVMFD5C478NL) or
478LWF (NVMFD5C478NLWF)
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (I
= 1.4 A)
L(pk)
A
Y
W
ZZ
G
= Assembly Location
=
Y
e
ar
= Work Week
= Lot Traceability
= Pb−Free Package
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
260
°
C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
(Note: Microdot may be in either location)
Parameter
Symbol
Value
6.4
Unit
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
R
°
C/W
q
JC
JA
R
48.8
q
1. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi
(
Y
) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
2
3. Surface−mounted
on FR4 board using a 650 mm
, 2 oz. Cu pad.
4. Continuous
DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
©
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
June, 2018 − Rev. 1
NVMFD5C478NL/D
NVMFD5C478NL
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
V
= 0
V
, I
=
2
50
m
A
40
V
(BR)DSS
GS
D
I
T =
25
°
C
J
10
m
A
DSS
V
V
= 0
V
,
GS
DS
= 40 V
T =
125
°
C
J
250
100
Gate−to−Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
2
0 V
nA
GSS
DS
GS
V
V
= V
, I
= 20
m
A
1.2
2.2
14.5
25
V
GS(TH)
GS
DS
D
Drain−to−Source On Resistance
R
V
= 10
V
, I
=
7
.5 A
12.1
20
m
W
DS(on)
GS
D
V
= 4.5
V
, I
=
7
.5 A
D
GS
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
V
= 15
V
, I
=
1
5 A
25
S
FS
DS
D
C
420
185
9
pF
iss
V
GS
= 0
V
, f =
1
.0 MHz,
Output Capacitance
C
oss
V
DS
= 25 V
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
rss
Q
Q
8.1
1.0
1.7
1.2
3.9
nC
nC
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
T
o
tal Gate Charge
Q
G(TH)
V
= 10
V
, V
=
3
2
V
, I
=
7
.5 A
DS D
GS
Q
GS
Q
GD
V
GS
= 4.5
V
, V
=
3
2
V
, I
=
7
.5 A
nC
ns
G(TOT)
DS
D
Turn−On Delay Time
Rise Time
t
6
d(on)
t
14
18
3.5
r
V
= 10
V
, V
=
3
2
V
,
DS
GS
I
D
= 7.5 A, R
= 1
W
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
V
= 0
V
,
= 7.5 A
T =
25
°
C
0.84
0.72
17
1.2
V
SD
GS
J
I
S
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
7.0
10
a
V
GS
= 0
V
,
d
l
/dt = 100 A/
m
s,
S
I
S
= 7.5 A
Discharge Time
b
Reverse Recovery Charge
Q
6
nC
RR
5. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
6. Switching
characteristics are independent of operating junction temperatures.
2
NVMFD5C478NL
TYPICAL CHARACTERISTICS
40
35
30
25
20
15
10
40
V
DS
= 10 V
6.0 V to 10 V
4.5 V
35
30
25
20
15
10
4.0 V
3.8 V
3.6 V
3.4 V
T =
25
°
C
J
5
0
5
0
T =
125
°
C
J
T =
−55
°
C
J
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
1
2
3
4
5
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
30
50
45
40
35
30
25
20
15
10
T =
25
°
C
J
T =
25
°
C
D
J
I
= 5 A
25
20
V
= 4.5 V
= 10 V
GS
GS
15
10
V
5
0
5
0
3
4
5
6
7
8
9
10
5
10
15
20
25
30
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.9
1.7
1.5
1.3
1.1
10K
1K
V
= 10 V
= 7.5 A
GS
I
D
T =
150
°
C
J
T =
125
°
C
J
100
10
T =
85
°
C
J
0.9
0.7
−50 −25
0
25
50
75
100 125 150 175
5
10
V
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (
°
C)
, DRAIN−TO−SOURCE VOLTAGE (V)
J
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
3
NVMFD5C478NL
TYPICAL CHARACTERISTICS
1000
100
10
9
C
ISS
8
7
6
5
4
3
2
C
OSS
Q
Q
GD
GS
10
1
C
RSS
V
DS
= 32 V
V
= 0 V
GS
I
D
= 7.5 A
T =
25
°
C
J
1
0
T =
25
°
C
J
f = 1 MHz
0
5
10
15
20
25
30
35
40
0
1
2
3
4
5
6
7
8
9
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Total
Charge
100
8.2
6.2
V
GS
= 0 V
t
d(off)
t
r
10
4.2
2.2
0.2
t
d(on)
t
f
T =
125
°
C
J
T =
25
°
C T =
−55
°
C
J J
V
GS
V
DS
= 10 V
= 32 V
1
1
10
R ,
GATE RESISTANCE (
W
)
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
100
10
T
V
= 25
°
C
≤
10 V
C
GS
Single Pulse
T (initial)
= 25
°
C
J
10
m
s
T (initial)
= 100
°
C
J
1
0.5 ms
1 ms
1
R
Limit
DS(on)
10 ms
Thermal Limit
Package Limit
0.1
0.1
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
V
DS
, DRAIN−TO−SOURCE VOLTAGE(V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. I
PEAK
vs. Time in Avalanche
4
NVMFD5C478NL
TYPICAL CHARACTERISTICS
100
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFD5C478NLT1G
5C478L
DFN8
(Pb−Free)
1500 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
NVMFD5C478NLWFT1G
478LWF
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5×6, 1.27P Dual Flag (SO8FL
−
Dual)
CASE 506BT
ISSUE E
1
DATE 26 FEB 2013
SCALE 2:1
2X
NOTES:
0.20
C
1. DIMENSIONING
AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
3. DIMENSION
b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TI
P
.
4. PROFILE
TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS
D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
6. SEATING
PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BOD
Y
.
7. A
VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
PIN ONE
IDENTIFIER
E1
4X
h
MILLIMETERS
GENERIC
MARKING DIAGRAM*
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
MIN
0.90
−−−
0.33
0.33
0.20
MAX
−−−
−−−
0.42
0.42
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
c
A1
1
1
2
3
4
XXXXXX
AYWZZ
−−−
TOP VIEW
5.15 BSC
4.90
4.10
1.70
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
C
DETAIL A
A
6.15 BSC
5.90
4.15
XXXXXX= Specific Device Code
5.70
3.90
6.10
4.40
A
Y
W
ZZ
= Assembly Location
=
Y
e
ar
= Work Week
= Lot Traceability
SEATING
PLANE
NOTE 6
C
NOTE 4
SIDE VIEW
1.27 BSC
0.55
DETAIL A
0.45
−−−
0.65
−−−
12
−−−
−−−
_
D2
D3
0.51
0.56
0.48
3.25
1.80
−−−
−−−
0.61
3.50
*This information is generic. Please refer
to device data sheet for actual part
marking.
0.71
3.75
2.20
4X
L
K
e
2.00
1
4
DETAIL B
ALTERNATE
DETAIL B
CONSTRUCTION
4X
b1
N
SOLDERING FOOTPRINT*
E2
M
4.56
2X
2.08
2X
0.56
8X
0.75
8
5
4X
G
b
8X
0.10
0.05
C
C
A B
K1
NOTE 3
BOTTOM VIEW
4X
1.40
6.59
4.84
2.30
3.70
0.70
4X
1.27
PITCH
1.00
5.55
DIMENSION: MILLIMETERS
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL
−
DUAL)
PAGE 1 OF 1
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