onsemi-NVMFD5C478NWFT1G

Part #onsemi-NVMFD5C478NWFT1G
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onsemi-NVMFD5C478NWFT1G
NVMFD5C478N  
Power MOSFET  
40
V
,
1
7.0 m
W
, 27 A, Dual N
−
Channel  
Features  
•
Small Footprint (5 x 6 mm) for Compact Design  
•
Low R  
to Minimize Conduction Losses  
DS(on)  
•
Low Capacitance to Minimize Driver Losses  
•
NVMFD5C478NWF
−
Wettable Flanks Product  
•
AEC
−
Q101 Qualified and P
P
A
P Capable  
V
R
MAX  
I MAX  
D
(BR)DSS  
DS(on)  
•
These Devices are Pb
−
Free and are RoHS Compliant  
40 V  
17.0 m
W
@ 10 V  
27 A  
MAXIMUM RATINGS
(T =
 
25
°
C unless otherwise noted)  
J
Parameter  
Drain
−
to
−
Source Voltage  
Symbol  
Value  
40  
Unit  
V
V
DSS  
Dual
−
Channel  
D1  
D2  
Gate
−
to
−
Source Voltage  
V
GS  
20  
V
Continuous Drain  
Current R  
T
= 25
°
C  
= 100
°
C  
= 25
°
C  
I
27  
A
C
D
q
JC  
T
C
19  
Steady  
State  
G1  
G2  
Power Dissipation  
T
C
P
23  
W
A
D
R
q
JC  
T
C
= 100
°
C  
12  
S1  
S2  
Continuous Drain  
Current R  
T =
 
25
°
C  
A
I
D
9.8  
6.9  
3.1  
1.5  
90  
q
JA  
PIN CONNECTION &  
MARKING DIAGRAM  
T =
 
100
°
C  
A
Steady  
State  
Power Dissipation  
T =
 
25
°
C  
A
P
W
D
D1 D1  
1
R
q
JA  
S1  
G1  
D1  
D1  
D2  
D2  
T =
 
100
°
C  
A
1
XXXXXX  
AYWZZ  
Pulsed Drain Current  
T =
 
25
°
C, t
 
= 10
m
s  
I
DM  
A
DFN8, 5×6  
(S08FL)  
CASE 506BT  
A
p
S2  
G2  
Operating Junction and Storage
T
e
mperature  
T , T  
−
55 to  
+175  
°
C  
J
stg  
D2 D2  
XXXXXX = 5C478N (NVMFD5C478N) or  
478NWF (NVMFD5C478NWF)  
Source Current (Body Diode)  
I
19  
48  
A
S
Single Pulse Drain
−
to
−
Source Avalanche  
E
AS  
mJ  
A
= Assembly Location  
=
Y
e
ar  
Energy (I  
= 1.4 A)  
L(pk)  
Y
ZZ  
WW  
G
= Lot Traceability  
= Work Week  
= Pb
−
Free Package  
Lead
T
e
mperature for Soldering Purposes  
T
260  
°
C  
L
(1/8
″
from case for 10 s)  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
(Note: Microdot may be in either location)  
THERMAL RESISTANCE MAXIMUM RATINGS

ORDERING INFORMATION  
See detailed ordering, marking and shipping information on  
Parameter  
Symbol  
Value  
6.5  
Unit  
Junction
−
to
−
Case
−

Junction
−
to
−
Ambient
−

R
R
°
C/W  
q
JC  
JA  
48.8  
q
1. The
 
entire application environment impacts the thermal resistance values shown,  
they are not constants and are only valid for the particular conditions noted.  
2. Psi
 
(
Y
) is used as required per JESD51
−
12 for packages in which  
substantially less than 100% of the heat flows to single case surface.  
2
3. Surface
−
mounted on FR4 board using a 650 mm
 
, 2 oz. Cu pad.  
4. Continuous
 
DC current rating. Maximum current for pulses as long as 1  
second is higher but is dependent on pulse duration and duty cycle.  
©
Semiconductor Components Industries, LLC, 2017  
1
Publication Order Number:  
December, 2018
−
Rev. 1  
NVMFD5C478N/D  
 

NVMFD5C478N  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted)  
J
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Drain
−
to
−
Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
V
V
= 0
V
, I
 
=
2
50
m
A  
40  
V
(BR)DSS  
GS  
D
I
T =
 
25
°
C  
10  
m
A  
DSS  
J
V
= 0
V
,  
= 40 V  
GS  
DS  
V
T =
 
125
°
C  
J
250  
100  
Gate
−
to
−
Source Leakage Current  
ON CHARACTERISTICS

Gate Threshold Voltage  
I
V
= 0
V
, V
 
=
2
0 V  
nA  
GSS  
DS  
GS  
GS  
V
V
= V
 
, I
 
= 20
m
A  
2.5  
3.5  
17  
V
m
W  
S
GS(TH)  
DS  
D
Drain
−
to
−
Source On Resistance  
Forward Transconductance  
CHARGES AND CAPACITANCES  
Input Capacitance  
R
V
= 10
V
, I
 
=
7
.5 A  
14  
2
DS(on)  
GS  
D
g
FS  
V
= 3
V
, I
 
=
7
.5 A  
DS D  
C
325  
165  
10  
pF  
iss  
V
GS  
= 0
V
, f =
1
.0 MHz,  
Output Capacitance  
C
oss  
V
DS  
= 25 V  
Reverse Transfer Capacitance  
T
o
tal Gate Charge  
C
rss  
Q
6.3  
1.3  
2.0  
1.2  
nC  
nC  
G(TOT)  
Threshold Gate Charge  
Q
G(TH)  
V
= 10
V
, V
 
=
3
2
V
, I
 
=
7
.5 A  
DS D  
GS  
Gate
−
to
−
Source Charge  
Gate
−
to
−
Drain Charge  
Q
GS  
GD  
Q
SWITCHING CHARACTERISTICS

Turn
−
On Delay Time  
Rise Time  
t
7
ns  
d(on)  
t
r
13  
14  
4.5  
V
= 10
V
, V
 
=
3
2
V
,  
DS  
GS  
D
I
= 7.5 A, R
 
= 1
W  
G
Turn
−
Off Delay Time  
Fall Time  
t
d(off)  
t
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS  
Forward Diode Voltage  
V
V
S
= 0
V
,  
T =
 
25
°
C  
0.84  
0.72  
18  
1.2  
V
SD  
GS  
J
I
= 7.5 A  
T =
 
125
°
C  
J
Reverse Recovery Time  
Charge Time  
t
ns  
RR  
t
t
7.0  
11  
a
V
GS  
= 0
V
,
d
l
 
/dt = 100 A/
m
s,  
S
I
S
= 7.5 A  
Discharge Time  
b
Reverse Recovery Charge  
Q
6
nC  
RR  
5. Pulse
 
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.  
6. Switching
 
characteristics are independent of operating junction temperatures.  
2
 

NVMFD5C478N  
TYPICAL CHARACTERISTICS  
30  
30  
25  
20  
15  
10  
6 V  
7 V to 10 V  
V
DS  
= 10 V  
25  
20  
15  
10  
5 V  
4 V  
T =
 
25
°
C  
J
5
0
5
0
T =
 
125
°
C  
J
T =
 
−
55
°
C  
J
0
1
2
3
3
4
5
6
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
V
GS  
, GATE
−
TO
−
SOURCE VOLTAGE (V)  
Figure 1. On
−
Region Characteristics  
Figure 2. Transfer Characteristics  
20  
100  
90  
80  
70  
60  
50  
40  
30  
20  
T =
 
25
°
C  
D
J
T =
 
25
°
C  
J
18  
16  
14  
12  
10  
8
I
= 7.5 A  
V
GS  
= 10 V  
6
4
2
0
10  
0
4
5
6
7
8
9
10  
0
5
10  
15  
20  
25  
30  
V
GS  
, GATE
−
TO
−
SOURCE VOLTAGE (V)  
I ,
 
DRAIN CURRENT (A)  
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source  
Figure 4. On
−
Resistance vs. Drain Current and  
Voltage  
Gate Voltage  
1.9  
1.7  
1.5  
1.3  
1.1  
10K  
1K  
V
= 10 V  
= 7.5 A  
GS  
I
D
T =
 
150
°
C  
J
T =
 
125
°
C  
J
100  
10  
T =
 
85
°
C  
J
0.9  
0.7  
−
50
−
25  
0
25  
50  
75  
100 125 150 175  
5
10  
15  
20  
25  
30  
35  
40  
T , JUNCTION TEMPERATURE (
°
C)  
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
DS  
Figure 5. On
−
Resistance Variation with  
Figure 6. Drain
−
to
−
Source Leakage Current  
Temperature  
vs. Voltage  
3

NVMFD5C478N  
TYPICAL CHARACTERISTICS  
10  
9
10,000  
1000  
100  
8
7
C
ISS  
6
5
4
3
2
Q
Q
GD  
GS  
C
OSS  
RSS  
C
10  
1
V
DS  
= 32 V  
V
= 0 V  
GS  
I
D
= 7.5 A  
T =
 
25
°
C  
J
1
0
T =
 
25
°
C  
J
f = 1 MHz  
0
5
10  
15  
20  
25  
30  
35  
40  
0
1
2
3
4
5
6
7
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
Q ,
 
TOTAL GATE CHARGE (nC)  
G
Figure 7. Capacitance Variation  
Figure 8. Gate
−
to
−
Source Voltage vs. Total  
Charge  
100  
8.2  
6.2  
V
GS  
= 0 V  
t
r
t
d(off)  
10  
4.2  
2.2  
0.2  
t
d(on)  
T =
 
125
°
C  
J
t
f
T =
 
25
°
C  
J
V
GS  
V
DS  
= 10 V  
= 32 V  
T =
 
−
55
°
C  
J
1
1
10  
R ,
 
GATE RESISTANCE (
W
)  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
V
SD  
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)  
G
Figure 9. Resistive Switching Time Variation  
vs. Gate Resistance  
Figure 10. Diode Forward Voltage vs. Current  
1000  
100  
10  
100  
10  
T
V
= 25
°
C  
C
≤
10 V  
GS  
Single Pulse  
T (initial)
 
= 25
°
C  
J
10
m
s  
T (initial)
 
= 100
°
C  
J
1
0.5 ms  
1 ms  
1
R
Limit  
DS(on)  
10 ms  
Thermal Limit  
Package Limit  
0.1  
0.1  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE(V)  
TIME IN AVALANCHE (s)  
Figure 11. Maximum Rated Forward Biased  
Safe Operating Area  
Figure 12. I

PEAK

vs. Time in Avalanche  
4

NVMFD5C478N  
TYPICAL CHARACTERISTICS  
100  
10  
1
50% Duty Cycle  
20%  
10%  
5%  
2%  
1%  
0.1  
Single Pulse  
0.01  
0.000001  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
PULSE TIME (sec)  
Figure 13. Thermal Characteristics  
DEVICE ORDERING INFORMATION  
Device  
†
Marking  
Package  
Shipping  
NVMFD5C478NT1G  
5C478N  
DFN8  
1500 /
T
a
pe & Reel  
1500 /
T
a
pe & Reel  
(Pb
−
Free)  
NVMFD5C478NWFT1G  
478NWF  
DFN8  
(Pb
−
Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging  
Specifications Brochure, BRD8011/D.  
5

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
DFN8 5×6, 1.27P Dual Flag (SO8FL
−
Dual)  
CASE 506BT  
ISSUE F  
1
DATE 23 NOV 2021  
2X  
SCALE 2:1  
NOTES:  
0.20  
C
1. DIMENSIONING
 
AND TOLERANCING PER ASME Y14.5M, 1994.  
2. CONTROLLING
 
DIMENSION: MILLIMETERS.  
3. DIMENSION
 
b APPLIES TO PLATED TERMINAL AND IS MEASURED  
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TI
P
.  
4. PROFILE
 
TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL  
AS THE TERMINALS.  
5. DIMENSIONS
 
D1 AND E1 DO NOT INCLUDE MOLD FLASH,  
PROTRUSIONS, OR GATE BURRS.  
D
A
B
E
2X  
D1  
0.20  
C
8
7
6
5
6. SEATING
 
PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED  
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST  
POINT ON THE PACKAGE BOD
Y
.  
7. A
 
VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.  
PIN ONE  
E1  
MILLIMETERS  
IDENTIFIER  
DIM  
A
A1  
b
b1  
c
MIN  
0.90  
−−−  
0.33  
0.33  
0.20  
NOM  
−−−  
−−−  
0.42  
0.42  
−−−  
5.15 BSC  
4.90  
4.10  
1.70  
6.15 BSC  
5.90  
4.15  
1.27 BSC  
0.55  
−−−  
−−−  
−−−  
0.61  
MAX  
1.10  
0.05  
0.51  
0.51  
0.33  
NOTE 7  
4X  
h
1
2
3
4
c
TOP VIEW  
D
A1  
D1  
D2  
D3  
E
E1  
E2  
e
G
h
K
K1  
4.70  
3.90  
1.50  
5.10  
4.30  
1.90  
0.10  
0.10  
C
C
A
DETAIL B  
5.70  
3.90  
6.10  
4.40  
ALTERNATE  
SEATING  
PLANE  
NOTE 6  
DETAIL A  
CONSTRUCTION  
C
NOTE 4  
SIDE VIEW  
DETAIL A  
0.45  
−−−  
0.51  
0.56  
0.48  
3.25  
1.80  
0.65  
12  
−−−  
−−−  
_
D2  
D3  
L
M
N
0.71  
3.75  
2.20  
4X
L  
K
3.50  
2.00  
e
1
4
SOLDERING FOOTPRINT*  
DETAIL B  
4.56  
4X  
2X  
2.08  
2X  
0.56  
b1  
8X  
0.75  
N
E2  
M
8
5
4X  
G
b
8X  
4X  
1.40  
0.10  
0.05  
C
C
A B  
K1  
6.59  
4.84  
NOTE 3  
2.30  
BOTTOM VIEW  
3.70  
GENERIC  
MARKING DIAGRAM*  
0.70  
1
XXXXXX  
AYWZZ  
4X  
1.27  
PITCH  
1.00  
5.55  
XXXXXX = Specific Device Code  
DIMENSION: MILLIMETERS  
A
Y
W
ZZ  
= Assembly Location  
=
Y
e
ar  
= Work Week  
= Lot Traceability  
*For additional information on our Pb
−
Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
Pb
−
Free indicator, “G” or microdot “
G
”, may  
or may not be present. Some products may  
not follow the Generic Marking.  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON50417E  
DFN8 5X6, 1.27P DUAL FLAG (SO8FL
−
DUAL)  
PAGE 1 OF 1  
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and  
are trademarks of Semiconductor Components Industries, LLC dba
onsemi
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reserves  
the right to make changes without further notice to any products herein.
onsemi
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onsemi
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©
Semiconductor Components Industries, LLC, 2019  

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,  
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onsemi
” or its affiliates  
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−
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T
:  
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−
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−
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o
ll Free USA/Canada  
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