onsemi-NVMFS4C03NT3G
| Part # | onsemi-NVMFS4C03NT3G |
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NVMFS4C03N
N-Channel, Logic Level,
SO-8FL
30
V
,
1
.7 m
W
, 159 A
Features
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
•
Small Footprint (5×6 mm) for Compact Design
•
Low R
to Minimize Conduction Losses
1.7 m
W
@ 10 V
2.4 m
W
@ 4.5 V
DS(on)
30 V
159 A
•
Low Q
and Capacitance to Minimize Driver Losses
G
•
NVMFS4C03NWF
−
Wettable Flanks Option for Enhanced Optical
Inspection
D (5,6)
•
AEC
−
Q101 Qualified and P
P
A
P Capable
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
G (4)
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
30
Unit
V
S (1,2,3)
N
−
CHANNEL MOSFET
V
DSS
Gate
−
to
−
Source Voltage
V
GS
“
20
159
V
MARKING
DIAGRAM
Continuous Drain Cur-
T
T
= 25
°
C
= 25
°
C
I
D
A
C
rent R
q
JC
Steady
State
D
Power Dissipation
P
D
77
W
A
C
S
S
S
G
D
D
1
R
q
JC
4C03xx
AYWZZ
SO
−
8 FLAT LEAD
CASE 488AA
STYLE 1
Continuous Drain Cur-
T =
25
°
C
A
I
D
34.9
rent R
q
JA
Steady
State
D
Power Dissipation
T =
25
°
C
A
P
D
3.71
900
W
4C03N =
Specific Device Code for
NVMFS4C03N
4C03WF= Specific Device Code of
NVMFS4C03NWF
R
q
JA
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
A
I
DM
A
p
Operating Junction and Storage
T
e
mperature
T , T
−
55 to
175
°
C
J
stg
A
Y
= Assembly Location
=
Y
e
ar
W
ZZ
= Work Week
= Lot Traceabililty
Source Current (Body Diode)
I
64
A
S
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
549
mJ
Energy (I
= 11 A)
L(pk)
ORDERING INFORMATION
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
260
°
C
L
†
Device
Package
Shipping
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
NVMFS4C03NT1G
SO
−
8 FL
(Pb
−
Free)
T
a
pe
& Reel
1500 /
NVMFS4C03NT3G
SO
−
8 FL
5000 /
(Pb
−
Free)
T
a
pe
& Reel
SO
−
8 FL
1500 /
(Pb
−
Free)
T
a
pe
& Reel
SO
−
8 FL
5000 /
(Pb
−
Free)
T
a
pe
& Reel
Parameter
Symbol
Value
Unit
NVMFS4C03NWFT1G
R
1.95
40
°
C/W
q
JC
R
q
JA
NVMFS4C03NWFT3G
1. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specifications
Brochure, BRD8011/D.
2. Surface
−
mounted on FR4 board using a 650 mm
, 2 oz. Cu pad.
3. Maximum
current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
©
Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
July, 2019
−
Rev. 2
NVMFS4C03N/D
NVMFS4C03N
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
30
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/
18.2
(BR)DSS
mV/
°
C
T
J
Zero Gate Voltage Drain Current
I
V
= 0
V
,
= 24 V
T =
25
°
C
1
DSS
GS
DS
J
V
m
A
T =
125
°
C
J
10
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
2
0 V
100
nA
GSS
DS
GS
GS
V
V
= V
, I
= 250
m
A
1.3
2.2
V
GS(TH)
DS
D
Negative Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
V
/T
4.8
1.4
2.0
136
1.0
mV/
°
C
GS(TH)
J
R
V
= 10 V
I
I
= 30 A
= 30 A
1.7
2.4
DS(on)
GS
D
m
W
V
GS
= 4.5 V
D
Forward Transconductance
Gate Resistance
g
FS
V
= 3
V
, I
=
3
0 A
S
DS
D
R
T =
25
°
C
A
W
G
CHARGES AND CAPACITANCES
Input Capacitance
C
3071
1673
67
ISS
Output Capacitance
C
V
= 0
V
, f = 1
M
Hz, V
= 15 V
pF
OSS
RSS
GS
DS
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
Q
20.8
4.9
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
T
o
tal Gate Charge
Q
G(TH)
V
GS
= 4.5
V
, V
=
1
5 V; I
= 30 A
nC
nC
DS
D
Q
8.5
GS
GD
Q
4.7
Q
V
GS
= 10
V
, V
=
1
5
V
,
45.2
G(TOT)
DS
I
= 30 A
D
Turn
−
On Delay Time
t
14
32
27
17
d(ON)
Rise Time
t
r
V
GS
= 4.5
V
, V
=
1
5
V
, I
=
1
5 A,
DS D
ns
V
R
= 3.0
W
G
Turn
−
Off Delay Time
t
d(OFF)
Fall Time
t
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
0.75
0.6
47
1.1
SD
J
V
S
= 0
V
,
GS
I
= 10 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
RR
t
23
ns
a
V
= 0
V
,
d
I
/dt = 100 A/
m
s,
S
GS
I
S
= 30 A
Discharge Time
t
24
b
Reverse Recovery Charge
Q
39
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.
5. Switching
characteristics are independent of operating junction temperatures.
2
NVMFS4C03N
TYPICAL CHARACTERISTICS
250
250
225
200
175
150
125
100
75
V
DS
= 3 V
T =
25
°
C
J
4.5 V
3.8 V
225
200
175
150
125
100
75
3.6 V
3.4 V
3.2 V
3.0 V
V
GS
= 10 V
T =
150
°
C
J
2.8 V
2.6 V
50
50
T =
25
°
C
J
T =
−
55
°
C
J
25
25
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
1.5
2
2.5
3
3.5
4
4.5
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
3.1
3.1
I
= 30 A
T =
25
°
C
D
J
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
T =
25
°
C
J
V
GS
= 4.5 V
V
GS
= 10 V
3
4
5
6
7
8
9
10
0
25 50
75 100
125 150 175 200
225 250
I ,
DRAIN CURRENT (A)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
D
Figure 3. On
−
Resistance vs. V
GS
Figure 4. On
−
Resistance vs. Drain Current and
Gate Voltage
1.8
1.6
1.4
1.2
1.0
0.8
0.6
10000
V
GS
= 0 V
I
V
= 30 A
D
T =
125
°
C
J
= 10 V
GS
1000
T =
100
°
C
J
T =
85
°
C
J
100
10
0
5
10
15
20
25
30
−
50
−
25
0
25
50
75
100 125 150 175
T , JUNCTION TEMPERATURE (
°
C)
J
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NVMFS4C03N
TYPICAL CHARACTERISTICS
12
11
18
15
12
9
10000
1000
100
Q
T
C
iss
10
9
8
7
6
5
4
3
2
1
0
C
oss
V
V
GS
DS
Q
gd
6
Q
gs
C
rss
V
= 0 V
T =
25
°
C
J
DS
I =
30 A
D
GS
3
T =
25
°
C
V
= 15 V
J
f = 1 MHz
0
10
0.1
1
10
100
0
5
10 15 20 25 30 35 40 45 50
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
1000
100
10
1000
100
10
V
= 0 V
GS
V
= 15 V
= 15 A
= 4.5 V
DD
I
D
V
GS
t
d(off)
t
f
T =
150
°
C
J
t
r
T =
25
°
C
J
1
t
d(on)
T =
−
55
°
C
J
0.1
0.1
1
10
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
R ,
GATE RESISTANCE (
W
)
G
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10 ms
10
m
s
V
T
≤
10 V
= 25
°
C
GS
10
1
100
m
s
C
R
Limit
DS(on)
Thermal Limit
Package Limit
1 ms
100
0.1
1
10
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
4
NVMFS4C03N
TYPICAL CHARACTERISTICS
100
10
R
Steady State = 40
°
C/W
q
JA
Duty Cycle = 50%
20%
10%
5%
P
CB
Cu Area = 650 mm2
P
CB
Cu Thk = 2 oz
2%
1%
1
0.1
0.01
0.001
Single Pulse
1E
−
06
1E
−
05
1E
−
04
1E
−
03
1E
−
02
1E
−
01
1E+00
1E+01
1E+02
1E+03
PULSE TIME (sec)
Figure 12. Thermal Impedance
(Junction
−
to
−
Ambient)
100
T
= 25
°
C
J(initial)
10
T
= 100
°
C
J(initial)
1
1.00E
−
04
1.00E
−
03
1.00E
−
02
TIME IN AVALANCHE (s)
Figure 13. Avalanche Characteristics
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5×6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N
1
SCALE 2:1
2 X
DATE 25 JUN 2018
NOTES:
1. DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M, 1994.
0.20
C
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
D
A
2
B
E
2 X
D1
MILLIMETERS
0.20
C
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
MIN
0.90
0.00
0.33
0.23
5.00
4.70
3.80
6.00
5.70
3.45
NOM
1.00
−−−
0.41
0.28
5.15
4.90
4.00
6.15
MAX
1.10
0.05
0.51
0.33
5.30
5.10
4.20
6.30
6.10
3.85
4 X
q
E1
2
c
A1
5.90
3.65
1
2
3
4
1.27 BSC
0.575
1.35
0.575
0.125 REF
3.40
0.51
1.20
0.51
0.71
1.50
0.71
TOP VIEW
C
SEATING
DETAIL A
PLANE
0.10
0.10
C
C
3.00
0
3.80
q
−−−
12
A
_
_
GENERIC
SIDE VIEW
MARKING DIAGRAM*
DETAIL A
1
8X
b
A B
XXXXXX
AYWZZ
0.10
0.05
C
c
e/2
e
L
1
4
XXXXXX =
Specific Device Code
A
Y
= Assembly Location
=
Y
e
ar
K
RECOMMENDED
SOLDERING FOOTPRINT*
W
ZZ
= Work Week
= Lot Traceability
E2
2X
PIN 5
M
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “
G
”,
may or may not be present. Some products
may not follow the Generic Marking.
(EXPOSED PAD)
L1
0.495
4.560
2X
1.530
D2
G
2X
BOTTOM VIEW
0.475
3.200
1.330
4.530
STYLE 1:
STYLE 2:
PIN 1.
ANODE
2. ANODE
2X
0.905
PIN 1.
SOURCE
2. SOURCE
3. SOURCE
4. GATE
1
3. ANODE
4. NO
CONNECT
5. CATHODE
0.965
5. DRAIN
4X
1.000
1.270
PITCH
4X
0.750
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5×6, 1.27P (SO−8FL)
PAGE 1 OF 1
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©
Semiconductor Components Industries, LLC, 2018
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−
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