onsemi-NVMFS5C404NLWFAFT3G
| Part # | onsemi-NVMFS5C404NLWFAFT3G |
Download  | onsemi-NVMFS5C404NLWFAFT3G |
DATA SHEET
N-Channel
40
V
,
0
.67 m
W
, 370 A
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
0.67 m
W
@ 10 V
1.0 m
W
@ 4.5 V
40 V
370 A
NVMFS5C404NL
D (5)
Features
•
Small Footprint (5×6 mm) for Compact Design
•
Low R
to Minimize Conduction Losses
G (4)
DS(on)
•
Low Q
and Capacitance to Minimize Driver Losses
G
•
NVMFS5C404N
L
WF
−
Wettable Flank Option for Enhanced Optical
S (1,2,3)
N
−
CHANNEL MOSFET
Inspection
•
AEC
−
Q101 Qualified and P
P
A
P Capable
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING
DIAGRAMS
DFN5
CASE 506EZ
D
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
S
S
S
G
D
D
1
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
40
Unit
V
XXXXXX
AYWZZ
V
DSS
DFNW5
CASE 507BA
Gate
−
to
−
Source Voltage
V
GS
20
V
D
Continuous Drain
Current R
T
= 25
°
C
I
370
A
C
D
q
JC
XXXXXX = Specific Device Code
T
C
= 100
°
C
260
Steady
State
A
Y
= Assembly Location
=
Y
e
ar
Power Dissipation
T
C
= 25
°
C
P
200
100
52
W
A
D
R
W
ZZ
= Work Week
= Lot Traceability
q
JC
T
C
= 100
°
C
Continuous Drain
Current R
T =
25
°
C
A
I
D
q
JA
T =
100
°
C
A
37
Steady
State
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
Power Dissipation
T =
25
°
C
A
P
3.9
1.9
900
W
D
R
q
JA
T =
100
°
C
A
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
A
A
p
Operating Junction and Storage
T
e
mperature
T , T
−
55 to
+ 175
°
C
J
stg
Source Current (Body Diode)
I
191
907
A
S
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
mJ
Energy (I
= 38 A)
L(pk)
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
L
260
°
C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction
−
to
−
Case
−
Steady State
R
0.75
39
°
C/W
q
JC
R
q
JA
1. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface
−
mounted on FR4 board using a 650 mm
, 2 oz. Cu pad.
3. Maximum
current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
©
Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
August, 2022
−
Rev. 9
NVMFS5C404NL/D
NVMFS5C404NL
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
40
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/
21.6
(BR)DSS
mV/
°
C
T
J
Zero Gate Voltage Drain Current
I
V
= 0
V
,
T =
25
°
C
10
DSS
GS
DS
J
V
= 40 V
m
A
T =
125
°
C
J
250
100
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
2
0 V
nA
GSS
DS
GS
GS
V
V
= V
, I
= 250
m
A
1.2
2.0
V
GS(TH)
DS
D
Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
V
/T
−
6.2
0.52
0.75
270
mV/
°
C
GS(TH)
J
R
V
= 10 V
I
I
= 50 A
= 50 A
0.67
1.0
DS(on)
GS
D
m
W
V
GS
= 4.5 V
D
Forward Transconductance
g
FS
V
=15
V
, I
=
5
0 A
S
DS
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
12168
4538
79.8
81
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0
V
, f = 1
M
Hz, V
= 25 V
pF
GS
DS
Reverse Transfer Capacitance
T
o
tal Gate Charge
Q
Q
V
= 4.5
V
, V
=
2
0 V; I
= 50 A
G(TOT)
G(TOT)
GS DS
D
T
o
tal Gate Charge
V
GS
= 10
V
, V
=
2
0 V; I
= 50 A
181
8.5
DS
D
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Plateau Voltage
Q
G(TH)
nC
V
Q
27.8
23.8
2.7
GS
GD
GP
V
GS
= 4.5
V
, V
=
2
0 V; I
= 50 A
DS D
Q
V
Turn
−
On Delay Time
t
24
135
87
d(ON)
Rise Time
t
r
V
= 4.5
V
, V
=
2
0
V
,
DS
GS
D
ns
V
I
= 50 A, R
= 1.0
W
G
Turn
−
Off Delay Time
t
d(OFF)
Fall Time
t
157
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
T =
25
°
C
0.7
1.2
J
V
S
= 0
V
,
GS
I
= 50 A
T =
125
°
C
J
0.61
97.4
46.5
50.9
190
Reverse Recovery Time
Charge Time
t
RR
t
a
ns
V
= 0
V
,
d
IS/dt = 100 A/
m
s,
GS
I
S
= 50 A
Discharge Time
t
b
Reverse Recovery Charge
Q
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.
5. Switching
characteristics are independent of operating junction temperatures.
2
NVMFS5C404NL
TYPICAL CHARACTERISTICS
800
10 V to 3.2 V
280
240
200
160
120
80
3.0 V
700
600
500
2.8 V
400
300
200
T =
25
°
C
J
40
0
T =
125
°
C
100
0
J
T =
−
55
°
C
J
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5 4.0
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.0015
0.0014
0.0013
0.0012
0.0011
0.0010
0.0009
0.0008
0.0007
0.0006
0.0010
0.0008
0.0006
V
= 4.5 V
= 10 V
GS
T =
25
°
C
D
J
I
= 50 A
V
GS
0.0004
0.0002
T =
25
°
C
J
0.0005
0.0004
3
4
5
6
7
8
9
10
10
50
90
130
170
210
250
290
V
GS
, GATE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
1M
100k
10k
1k
2.1
1.9
1.7
V
= 10 V
= 50 A
GS
T =
150
°
C
J
I
D
T =
125
°
C
J
1.5
1.3
1.1
0.9
T =
85
°
C
J
100
10
0.7
0.5
−
50
−
25
0
25
50
75 100
125 150 175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NVMFS5C404NL
TYPICAL CHARACTERISTICS
14k
13k
12k
11k
10k
9k
8k
7k
6k
5k
10
8
30
25
20
Q
T
C
ISS
C
OSS
V
= 0 V
GS
6
4
T =
25
°
C
J
15
10
f = 1 MHz
Q
GD
Q
GS
V
= 20 V
DS
4k
3k
2k
T =
25
°
C
J
2
0
I
D
= 50 A
5
0
C
1k
RSS
0
0
5
10
15
20
25
30
35
40
0
20
40
60
80 100
120 140
160 180
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
10,000
1000
46
41
36
31
26
21
16
11
V
V
= 4.5 V
= 20 V
= 50 A
GS
DD
I
D
t
d(off)
t
t
f
T =
125
°
C
J
r
t
d(on)
100
10
T =
150
°
C
J
T =
25
°
C
J
6
1
T =
−
55
°
C
J
1
10
R ,
GATE RESISTANCE (
W
)
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
1000
100
T
V
= 25
°
C
C
≤
10 V
GS
0.01 ms
0.1 ms
1 ms
T
= 25
°
C
J(initial)
10 ms
dc
T
= 100
°
C
J(initial)
10
1
10
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
1
10
100
1E
−
04
1E
−
03
TIME IN AVALANCHE (s)
1E
−
02
V
DS
(V)
Figure 11. Safe Operating Area
Figure 12. I
PEAK
vs. Time in Avalanche
4
NVMFS5C404NL
100
10
50% Duty Cycle
20%
10%
5%
2%
1%
2
1
NVMFS5C404NL 650 mm
, 2 oz., Cu Single Layer Pad
0.1
Single Pulse
0.0001 0.001
0.01
0.000001 0.00001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
†
Device
Case
Marking
Package
Shipping
NVMFS5C404N
L
T
1G
506EZ
507BA
506EZ
507BA
506EZ
507BA
5C404L
DFN5
1500 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
5000 /
T
a
pe & Reel
5000 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
(Pb
−
Free)
NVMFS5C404N
L
W
FT1G
NVMFS5C404N
L
T
3G
404LWF
5C404L
404LWF
5C404L
404LWF
DFN5
(Pb
−
Free, Wettable Flanks)
DFN5
(Pb
−
Free)
NVMFS5C404N
L
W
FT3G
NVMFS5C404NLAFT1G
NVMFS5C404N
L
W
FAFT1G
DFN5
(Pb
−
Free, Wettable Flanks)
DFN5
(Pb
−
Free)
DFN5
(Pb
−
Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5×6, 1.27P (SO
−
8FL)
CASE 506EZ
ISSUE A
1
DATE 25 AUG 2021
SCALE 2:1
q
q
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
XXXXXX =
Specific Device Code
A
Y
= Assembly Location
=
Y
e
ar
W
ZZ
= Work Week
= Lot Traceability
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON24855H
DFN5 5×6, 1.27P (SO
−
8FL)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2018
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW5 5×6 (FULL
−
CUT SO8FL WF)
CASE 507BA
ISSUE A
DATE 03 FEB 2021
q
q
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
XXXXXX =
Specific Device Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present. Some products
may not follow the Generic Marking.
A
Y
= Assembly Location
=
Y
e
ar
W
ZZ
= Work Week
= Lot Traceability
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON26450H
DFNW5 5×6 (FULL
−
CUT SO8FL WF)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2018
onsemi
,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “
onsemi
” or its affiliates
and/or subsidiaries in the United States and/or other countries.
onsemi
owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of
onsemi
’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
.
onsemi
reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as
−
is” and
onsemi
makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does
onsemi
assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using
onsemi
products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by
onsemi
. “Typical” parameters which may be provided in
onsemi
data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
onsemi
does not convey any license
under any of its intellectual property rights nor the rights of others.
onsemi
products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use
onsemi
products for any such unintended or unauthorized application, Buyer shall indemnify and hold
onsemi
and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that
onsemi
was negligent regarding the design or manufacture of the part.
onsemi
is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMEN
T
:
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800
−
282
−
9855
T
o
ll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
◊
