onsemi-NVMFS5C410NLAFT3G
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NVMFS5C410NL
N-Channel
40
V
,
0
.82 m
W
, 330 A
Features
•
Small Footprint (5×6 mm) for Compact Design
•
Low R
to Minimize Conduction Losses
DS(on)
•
Low Q
and Capacitance to Minimize Driver Losses
V
R
MAX
I MAX
D
G
(BR)DSS
DS(ON)
•
NVMFS5C410N
L
WF
−
Wettable Flank Option for Enhanced Optical
0.82 m
W
@ 10 V
1.2 m
W
@ 4.5 V
40 V
330 A
Inspection
•
AEC
−
Q101 Qualified and P
P
A
P Capable
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
D (5,6)
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
40
Unit
V
V
DSS
G (4)
Gate
−
to
−
Source Voltage
V
GS
20
V
S (1,2,3)
N
−
CHANNEL MOSFET
Continuous Drain
Current R
T
= 25
°
C
I
330
A
C
D
q
JC
T
C
= 100
°
C
230
Steady
State
Power Dissipation
T
C
= 25
°
C
P
167
83
W
A
D
R
q
JC
T
C
= 100
°
C
MARKING
DIAGRAM
Continuous Drain
Current R
T =
25
°
C
A
I
D
50
q
JA
D
T =
100
°
C
A
35
1
Steady
State
S
S
S
G
D
D
Power Dissipation
T =
25
°
C
A
P
3.8
1.9
900
W
D
DFN5
(SO
−
8FL)
CASE 488AA
STYLE 1
XXXXXX
AYWZZ
R
q
JA
T =
100
°
C
A
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
A
A
p
D
Operating Junction and Storage
T
e
mperature
T , T
−
55 to
°
C
J
stg
XXXXXX = 5C410L
XXXXXX =
(NVMFS5C410NL) or
XXXXXX =
410LWF
+175
Source Current (Body Diode)
I
S
169
706
A
XXXXXX =
(NVMFS5C410NLWF)
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
mJ
A
Y
= Assembly Location
=
Y
e
ar
Energy (I
= 29 A)
L(pk)
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
L
260
°
C
W
ZZ
= Work Week
= Lot Traceability
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction
−
to
−
Case
−
Steady State
R
0.9
39
°
C/W
q
JC
R
q
JA
1. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface
−
mounted on FR4 board using a 650 mm
, 2 oz. Cu pad.
3. Maximum
current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
©
Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
July, 2019
−
Rev. 7
NVMFS5C410NL/D
NVMFS5C410NL
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
40
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/
21.2
(BR)DSS
mV/
°
C
T
J
Zero Gate Voltage Drain Current
I
V
= 0
V
,
T =
25
°
C
10
DSS
GS
DS
J
V
= 40 V
m
A
T =
125
°
C
J
250
100
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
2
0 V
nA
GSS
DS
GS
GS
V
V
= V
, I
= 250
m
A
1.2
2.0
V
GS(TH)
DS
D
Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
V
/T
−
5.75
0.65
0.95
190
mV/
°
C
GS(TH)
J
R
V
= 10 V
I
I
= 50 A
= 50 A
0.82
1.2
DS(on)
GS
D
m
W
V
GS
= 4.5 V
D
Forward Transconductance
g
FS
V
= 15
V
, I
=
5
0 A
S
DS
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
8862
4156
116
66
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0
V
, f = 1
M
Hz, V
= 25 V
pF
GS
DS
Reverse Transfer Capacitance
T
o
tal Gate Charge
Q
Q
V
= 4.5
V
, V
=
2
0 V; I
= 50 A
G(TOT)
G(TOT)
GS DS
D
T
o
tal Gate Charge
V
GS
= 10
V
, V
=
2
0 V; I
= 50 A
143
6.75
21.4
22
DS
D
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Plateau Voltage
Q
G(TH)
nC
V
Q
GS
GD
GP
V
GS
= 4.5
V
, V
=
2
0 V; I
= 50 A
DS D
Q
V
2.7
Turn
−
On Delay Time
t
20
130
66
d(ON)
Rise Time
t
r
V
= 4.5
V
, V
=
2
0
V
,
DS
GS
D
ns
V
I
= 50 A, R
= 1.0
W
G
Turn
−
Off Delay Time
t
d(OFF)
Fall Time
t
177
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
0.73
0.6
1.2
SD
RR
J
V
S
= 0
V
,
GS
I
= 50 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
79.5
39
t
a
ns
V
= 0
V
,
d
IS/dt = 100 A/
m
s,
GS
I
S
= 50 A
Discharge Time
t
b
40.5
126
Reverse Recovery Charge
Q
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.
5. Switching
characteristics are independent of operating junction temperatures.
2
NVMFS5C410NL
TYPICAL CHARACTERISTICS
180
200
180
160
140
120
100
80
10 V to 3.2 V
160
3.0 V
140
120
2.8 V
100
80
60
40
T =
25
°
C
J
60
40
T =
125
°
C
20
0
J
20
0
T =
−
55
°
C
J
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5 4.0
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.0013
0.0012
0.0011
0.0010
0.0009
0.0008
0.0012
0.0011
T =
25
°
C
J
V
= 4.5 V
= 10 V
GS
0.0010
0.0009
0.0008
0.0007
0.0006
T =
25
°
C
D
J
I
= 50 A
V
GS
0.0007
0.0006
0.0005
0.0004
3
4
5
6
7
8
9
10
10
20
30
40
50
60
V
GS
, GATE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
1.9
1.7
1.5
1.3
1.1
1M
100k
10k
1k
V
= 10 V
= 40 A
GS
T =
150
°
C
J
I
D
T =
125
°
C
J
T =
85
°
C
J
100
10
0.9
0.7
−
50
−
25
0
25
50
75 100
125 150 175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NVMFS5C410NL
TYPICAL CHARACTERISTICS
11k
10k
9k
10
8
30
25
20
Q
T
C
ISS
8k
C
OSS
7k
V
= 0 V
GS
6
4
T =
25
°
C
6k
J
15
10
f = 1 MHz
5k
Q
GD
Q
GS
4k
V
= 20 V
DS
3k
T =
25
°
C
J
2
0
I
D
= 50 A
2k
5
0
1k
0
C
RSS
0
5
10
15
20
25
30
35
40
0
20
40
60
80
100
120
140
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
10,00
100
t
t
d(off)
46
41
36
31
26
21
16
11
f
t
r
t
d(on)
T =
125
°
C
J
10
1
V
V
I
= 4.5 V
= 20 V
= 50 A
GS
T =
150
°
C
J
DD
T =
25
°
C
J
6
1
D
T =
−
55
°
C
J
1
10
R ,
GATE RESISTANCE (
W
)
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
1000
100
T
V
= 25
°
C
C
≤
10 V
GS
0.01 ms
0.1 ms
1 ms
T
= 25
°
C
J(initial)
10 ms
dc
T
= 100
°
C
J(initial)
10
1
10
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
1
10
100
1E
−
04
1E
−
03
TIME IN AVALANCHE (s)
1E
−
02
V
DS
(V)
Figure 11. Safe Operating Area
Figure 12. I
PEAK
vs. Time in Avalanche
4
NVMFS5C410NL
100
10
50% Duty Cycle
20%
10%
5%
2%
1%
2
1
NVMFS5C410NL 650 mm
, 2 oz., Cu Single Layer Pad
0.1
Single Pulse
0.0001 0.001
0.01
0.000001 0.00001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFS5C410N
L
T
1G
5C410L
DFN5
1500 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
5000 /
T
a
pe & Reel
5000 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
(Pb
−
Free)
NVMFS5C410N
L
W
FT1G
NVMFS5C410N
L
T
3G
410LWF
5C410L
410LWF
5C410L
410LWF
DFN5
(Pb
−
Free, Wettable Flanks)
DFN5
(Pb
−
Free)
NVMFS5C410N
L
W
FT3G
NVMFS5C410NLAFT1G
NVMFS5C410N
L
W
FAFT1G
DFN5
(Pb
−
Free, Wettable Flanks)
DFN5
(Pb
−
Free)
DFN5
(Pb
−
Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5×6, 1.27P
(SO
−
8FL)
CASE 488AA
ISSUE N
1
SCALE 2:1
2 X
DATE 25 JUN 2018
NOTES:
1. DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M, 1994.
0.20
C
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
D
A
2
B
E
2 X
D1
MILLIMETERS
0.20
C
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
MIN
0.90
0.00
0.33
0.23
5.00
4.70
3.80
6.00
5.70
3.45
NOM
1.00
−−−
0.41
0.28
5.15
4.90
4.00
6.15
MAX
1.10
0.05
0.51
0.33
5.30
5.10
4.20
6.30
6.10
3.85
4 X
q
E1
2
c
A1
5.90
3.65
1
2
3
4
1.27 BSC
0.575
1.35
0.575
0.125 REF
3.40
0.51
1.20
0.51
0.71
1.50
0.71
TOP VIEW
C
SEATING
DETAIL A
PLANE
0.10
0.10
C
C
3.00
0
3.80
q
−−−
12
A
_
_
GENERIC
SIDE VIEW
MARKING DIAGRAM*
DETAIL A
1
8X
b
A B
XXXXXX
AYWZZ
0.10
0.05
C
c
e/2
e
L
1
4
XXXXXX =
Specific Device Code
A
Y
= Assembly Location
=
Y
e
ar
K
RECOMMENDED
SOLDERING FOOTPRINT*
W
ZZ
= Work Week
= Lot Traceability
E2
2X
PIN 5
M
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present. Some products
may not follow the Generic Marking.
(EXPOSED PAD)
L1
0.495
4.560
2X
1.530
D2
G
2X
BOTTOM VIEW
0.475
3.200
1.330
4.530
STYLE 1:
STYLE 2:
PIN 1.
ANODE
2. ANODE
2X
0.905
PIN 1.
SOURCE
2. SOURCE
3. SOURCE
4. GATE
1
3. ANODE
4. NO
CONNECT
5. CATHODE
0.965
5. DRAIN
4X
1.000
1.270
PITCH
DIMENSIONS: MILLIMETERS
4X
0.750
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5×6, 1.27P (SO
−
8FL)
PAGE 1 OF 1
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and
are trademarks of Semiconductor Components Industries, LLC dba
onsemi
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onsemi
reserves
the right to make changes without further notice to any products herein.
onsemi
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onsemi
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onsemi
does not convey any license under its patent rights nor the rights of others.
©
Semiconductor Components Industries, LLC, 2018
onsemi
,
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onsemi
” or its affiliates
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A listing of
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’s product/patent coverage may be accessed at
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−
Marking.pdf
.
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−
is” and
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