onsemi-NVMFS5C442NLAFT3G
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DATA SHEET
N-Channel, DFN5/DFNW5
40
V
,
2
.5 m
W
, 130 A
V
R
MAX
I
D
MAX
(BR)DSS
DS(ON)
2.5 m
W
@ 10 V
3.7 m
W
@ 4.5 V
40 V
130 A
NVMFS5C442NL
D (5)
Features
•
Small Footprint (5×6 mm) for Compact Design
•
Low R
to Minimize Conduction Losses
G (4)
DS(on)
•
Low Q
and Capacitance to Minimize Driver Losses
G
•
NVMFS5C442N
L
WF
−
Wettable Flank Option for Enhanced Optical
Inspection
S (1,2,3)
N
−
CHANNEL MOSFET
•
AEC
−
Q101 Qualified and P
P
A
P Capable
•
These Devices are Pb
−
Free and are RoHS Compliant
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
40
Unit
V
1
V
DSS
DFN5 (SO
−
8FL)
DFNW5
CASE 488AA
(FULL
−
CUT SO8FL WF)
Gate
−
to
−
Source Voltage
V
GS
20
V
CASE 507BA
Continuous Drain
Current R
T
= 25
°
C
= 100
°
C
= 25
°
C
I
130
95
A
C
D
q
JC
MARKING DIAGRAM
T
C
Steady
State
D
Power Dissipation
T
C
P
83
W
A
D
R
S
S
S
G
D
D
q
JC
T
C
= 100
°
C
42
XXXXXX
AYWZZ
Continuous Drain
Current R
T =
25
°
C
A
I
D
28
q
JA
T =
100
°
C
A
20
D
Steady
State
Power Dissipation
T =
25
°
C
A
P
3.7
1.8
900
W
D
XXXXXX = 5C442L
R
q
JA
XXXXXX =
(NVMFS5C442NL) or
XXXXXX =
442LWF
XXXXXX =
(NVMFS5C442NLWF)
T =
100
°
C
A
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
A
A
p
A
Y
W
ZZ
= Assembly Location
=
Y
e
ar
= Work Week
= Lot Traceability
Operating Junction and Storage
T
e
mperature
Range
T , T
−
55 to
°
C
J
stg
+175
Source Current (Body Diode)
I
S
81
A
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
265
mJ
Energy (I
= 10 A)
L(pk)
Lead
T
e
mperature for Soldering Purposes
T
260
°
C
L
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
(1/8
″
from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
1.8
Unit
Junction
−
to
−
Case
−
Steady State
R
°
C/W
q
JC
R
41
q
JA
1. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface
−
mounted on FR4 board using a 650 mm
, 2 oz. Cu pad.
3. Maximum
current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
©
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
March, 2023
−
Rev. 10
NVMFS5C442NL/D
NVMFS5C442NL
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
OFF CHARACTERISTICS
Symbol
Test Condition
Min
Typ
Max
Unit
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
40
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/
24.8
mV/
°
C
(BR)DSS
T
J
Zero Gate Voltage Drain Current
I
V
= 0
V
,
T =
25
°
C
10
250
20
m
A
DSS
GS
DS
J
V
= 40 V
T =
125
°
C
J
V
= 0
V
, V
=
2
0
V
, T
=
1
25
°
C
DS J
GS
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
2
0 V
100
nA
GSS
DS
GS
V
V
GS
= V
, I
= 90
m
A
1.2
2.0
V
GS(TH)
DS
D
Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
V
/T
−
5.4
2.0
mV/
°
C
m
W
GS(TH)
J
R
V
= 10 V
I
I
= 50 A
= 50 A
2.5
3.7
DS(on)
GS
D
V
GS
= 4.5 V
2.9
D
Forward Transconductance
g
FS
V
DS
= 15
V
, I
=
5
0 A
116
S
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
3100
1100
37
pF
ISS
Output Capacitance
C
OSS
C
RSS
V
= 0
V
, f = 1
M
Hz, V
= 25 V
DS
GS
Reverse Transfer Capacitance
T
o
tal Gate Charge
Q
Q
V
GS
= 4.5
V
, V
=
3
2 V; I
= 50 A
23
nC
G(TOT)
G(TOT)
DS
D
T
o
tal Gate Charge
V
GS
= 10
V
, V
=
3
2 V; I
= 50 A
50
DS
D
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Plateau Voltage
Q
5.0
9.8
6.7
3.1
G(TH)
Q
GS
GD
GP
V
GS
= 4.5
V
, V
=
3
2 V; I
= 50 A
DS D
Q
V
V
Turn
−
On Delay Time
t
12
8.3
28
ns
d(ON)
Rise Time
t
r
V
= 4.5
V
, V
=
3
2
V
,
DS
GS
D
I
= 50 A, R
= 1.0
W
G
Turn
−
Off Delay Time
t
d(OFF)
Fall Time
t
f
9.4
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
0.85
0.73
46
1.2
V
SD
J
V
S
= 0
V
,
GS
I
= 50 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
23
a
V
= 0
V
,
d
I
/dt = 100 A/
m
s,
S
GS
I
S
= 50 A
Discharge Time
23
b
Reverse Recovery Charge
Q
40
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.
5. Switching
characteristics are independent of operating junction temperatures.
2
NVMFS5C442NL
TYPICAL CHARACTERISTICS
180
220
200
180
160
140
120
100
80
4.0 V
10 V to 4.5 V
V
DS
= 3 V
160
140
120
100
80
3.8 V
3.6 V
3.4 V
3.2 V
T =
25
°
C
J
60
3.0 V
2.8 V
60
40
40
T =
125
°
C
20
0
J
20
0
T =
−
55
°
C
J
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5 4.0
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
5.0
5.0
4.5
4.0
3.5
3.0
T =
25
°
C
J
4.5
4.0
T =
25
°
C
D
J
I
= 50 A
V
= 4.5 V
= 10 V
3.5
3.0
2.5
2.0
GS
V
GS
2.5
2.0
1.5
1.0
2
3
4
5
6
7
8
9
10
0
20 40 60 80
100 120
140 160 180
200
I ,
DRAIN CURRENT (A)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
2.0
100,000
10,000
1000
V
I
= 10 V
= 50 A
GS
1.8
1.6
1.4
1.2
1.0
D
T =
150
°
C
J
T =
125
°
C
J
T =
85
°
C
J
100
10
0.8
0.6
−
50
−
25
0
25
50
75 100
125 150 175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NVMFS5C442NL
TYPICAL CHARACTERISTICS
10
8
30
25
20
Q
3600
3200
2800
2400
2000
1600
1200
800
T
C
C
ISS
V
= 0 V
GS
6
4
T =
25
°
C
J
OSS
15
10
f = 1 MHz
Q
GD
Q
GS
V
= 32 V
DS
T =
25
°
C
J
2
0
I
D
= 50 A
5
0
400
0
C
RSS
0
5
10
15
20
25
30
35
40
0
4
8
12 16 20 24 28 32 36 40 44 48
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
1000
100
46
T =
125
°
C
J
41
36
31
26
t
d(off)
t
f
t
r
T =
25
°
C
J
t
d(on)
21
16
10
1
T =
−
55
°
C
J
V
V
= 4.5 V
= 32 V
= 50 A
GS
11
DD
6
1
I
D
1
10
R ,
GATE RESISTANCE (
W
)
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
G
SD
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
1000
100
T
V
= 25
°
C
C
0.01 ms
0.1 ms
≤
10 V
GS
T
= 25
°
C
J(initial)
10
1 ms
T
= 100
°
C
J(initial)
10
1
10 ms
R
Limit
DS(on)
Thermal Limit
Package Limit
1
0.1
1
10
100
1E
−
04
1E
−
03
TIME IN AVALANCHE (s)
1E
−
02
V
DS
(V)
Figure 11. Safe Operating Area
Figure 12. I
PEAK
vs. Time in Avalanche
4
NVMFS5C442NL
100
10
50% Duty Cycle
20%
10%
5%
2%
1%
2
1
NVMFS5C442NL 650 mm
, 2 oz., Cu Single Layer Pad
0.1
Single Pulse
0.000001 0.00001
0.0001
0.01
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFS5C442N
L
T
1G
5C442L
DFN5
1500 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
5000 /
T
a
pe & Reel
5000 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
(Pb
−
Free)
NVMFS5C442N
L
W
FT1G
NVMFS5C442N
L
T
3G
442LWF
5C442L
442LWF
5C442L
5C442L
442LWF
DFNW5
(Pb
−
Free, Wettable Flanks)
DFN5
(Pb
−
Free)
NVMFS5C442N
L
W
FT3G
NVMFS5C442NLAFT1G
NVMFS5C442NLAFT1G
−
YE
NVMFS5C442N
L
W
FAFT1G
DFNW5
(Pb
−
Free, Wettable Flanks)
DFN5
(Pb
−
Free)
DFN5
(Pb
−
Free)
DFNW5
(Pb
−
Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5×6, 1.27P
(SO
−
8FL)
CASE 488AA
ISSUE N
1
SCALE 2:1
2 X
DATE 25 JUN 2018
NOTES:
1. DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M, 1994.
0.20
C
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
D
A
2
B
E
2 X
D1
MILLIMETERS
0.20
C
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
MIN
0.90
0.00
0.33
0.23
5.00
4.70
3.80
6.00
5.70
3.45
NOM
1.00
−−−
0.41
0.28
5.15
4.90
4.00
6.15
MAX
1.10
0.05
0.51
0.33
5.30
5.10
4.20
6.30
6.10
3.85
4 X
q
E1
2
c
A1
5.90
3.65
1
2
3
4
1.27 BSC
0.575
1.35
0.575
0.125 REF
3.40
0.51
1.20
0.51
0.71
1.50
0.71
TOP VIEW
C
SEATING
DETAIL A
PLANE
0.10
0.10
C
C
3.00
0
3.80
q
−−−
12
A
_
_
GENERIC
SIDE VIEW
MARKING DIAGRAM*
DETAIL A
1
8X
b
A B
XXXXXX
AYWZZ
0.10
0.05
C
c
e/2
e
L
1
4
XXXXXX =
Specific Device Code
A
Y
= Assembly Location
=
Y
e
ar
K
RECOMMENDED
SOLDERING FOOTPRINT*
W
ZZ
= Work Week
= Lot Traceability
E2
2X
PIN 5
M
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present. Some products
may not follow the Generic Marking.
(EXPOSED PAD)
L1
0.495
4.560
2X
1.530
D2
G
2X
BOTTOM VIEW
0.475
3.200
1.330
4.530
STYLE 1:
STYLE 2:
PIN 1.
ANODE
2. ANODE
2X
0.905
PIN 1.
SOURCE
2. SOURCE
3. SOURCE
4. GATE
1
3. ANODE
4. NO
CONNECT
5. CATHODE
0.965
5. DRAIN
4X
1.000
1.270
PITCH
DIMENSIONS: MILLIMETERS
4X
0.750
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5×6, 1.27P (SO
−
8FL)
PAGE 1 OF 1
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onsemi
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onsemi
reserves
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onsemi
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©
Semiconductor Components Industries, LLC, 2018
onsemi
,
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onsemi
” or its affiliates
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−
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.
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−
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