onsemi-NVMTS0D6N04CTXG
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N-Channel
40
V
,
0
.48 m
W
, 533 A
NVMTS0D6N04C
Features
•
Small Footprint (8×8 mm) for Compact Design
•
Low R
to Minimize Conduction Losses
DS(on)
•
Low Q
and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
•
Wettable Flank Plated for Enhanced Optical Inspection
•
AEC
−
Q101 Qualified and P
P
A
P Capable
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
40 V
0.48 m
W
@ 10 V
533 A
D (5
−
8)
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
40
Unit
V
G (1)
V
DSS
Gate
−
to
−
Source Voltage
V
GS
20
V
S (2
−
4)
Continuous Drain
Steady
State
T
= 25
°
C
= 100
°
C
= 25
°
C
I
533
377
245
122.7
76
A
C
D
Current R
q
JC
N
−
CHANNEL MOSFET
T
C
Power Dissipation
Steady
State
T
C
P
W
A
D
R
q
JC
T
C
= 100
°
C
Continuous Drain
Current R
Steady
State
T =
25
°
C
A
I
D
q
JA
T =
100
°
C
A
54
Power Dissipation
Steady
State
T =
25
°
C
P
D
5.0
W
A
R
q
JA
T =
100
°
C
A
2.5
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
900
A
A
p
DFNW8
CASE 507AP
Operating Junction and Storage
T
e
mperature
T , T
−
55 to
+175
°
C
J
stg
Source Current (Body Diode)
I
204.5
2058
A
S
MARKING DIAGRAM
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
mJ
Energy (I
= 53 A)
L(pk)
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
L
260
°
C
0D6N04C
AWLYWW
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
A
= Assembly Location
THERMAL RESISTANCE MAXIMUM RATINGS
WL =
2
−
digit Wafer Lot Code
=
Y
ear Code
WW = Work Week Code
Parameter
Symbol
Value
0.61
Unit
Y
R
°
C/W
q
JC
R
30.2
q
JA
2
1. Surface
−
mounted on FR4 board using a 1 in
pad size, 1 oz. Cu pad.
2. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
©
Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
January, 2020
−
Rev. 2
NVMTS0D6N04C/D
NVMTS0D6N04C
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
40
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/
I
D
= 250
m
A, ref to 25
°
C
13.19
(BR)DSS
mV/
°
C
T
J
Zero Gate Voltage Drain Current
I
V
= 0
V
,
T =
25
°
C
10
DSS
GS
DS
J
V
= 40 V
m
A
T =
125
°
C
J
250
100
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
2
0 V
nA
GSS
DS
GS
GS
V
V
= V
, I
= 250
m
A
2.0
4.0
V
mV/
°
C
m
W
S
GS(TH)
DS
D
Negative Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
Forward Transconductance
V
/T
J
I
= 250
m
A, ref to 25
°
C
−
8.28
0.39
233
GS(TH)
D
R
V
GS
= 10 V
I =
50 A
D
0.48
DS(on)
g
FS
V =5
V
, I
=
5
0 A
DS D
Gate Resistance
R
T =
25
°
C
A
1.0
W
G
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
11800
7030
199
ISS
Output Capacitance
C
V
GS
= 0
V
, f = 1
M
Hz, V
= 20 V
pF
nC
OSS
RSS
DS
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
Q
187
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Q
29.7
46.6
38.2
G(TH)
V
GS
= 10
V
, V
=
2
0 V; I
= 50 A
DS D
Q
GS
Q
GD
GS
Turn
−
On Delay Time
Rise Time
t
33.6
27.9
86.0
32.3
d(ON)
t
r
V
= 10
V
, V
=
2
0
V
,
DS
GS
D
ns
V
I
= 50 A, R
= 2.5
W
G
Turn
−
Off Delay Time
Fall Time
t
d(OFF)
t
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
0.76
0.6
105
60
1.2
SD
RR
J
V
S
= 0
V
,
= 50 A
GS
I
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
t
a
ns
V
= 0
V
,
d
IS/dt = 100 A/
m
s,
GS
I
S
= 50 A
Discharge Time
t
b
45
Reverse Recovery Charge
Q
274
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.
4. Switching
characteristics are independent of operating junction temperatures.
2
NVMTS0D6N04C
TYPICAL CHARACTERISTICS
800
400
360
320
280
240
V
= 6 V to 10 V
GS
V
DS
= 10 V
700
4.8 V
600
500
400
300
200
100
0
4.5 V
200
160
120
80
T =
25
°
C
J
4.0 V
3.6 V
T =
125
°
C
J
40
T =
−
55
°
C
J
0
2
3
4
5
6
7
0
1
2
3
4
5
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
4.0
3.5
3.0
2.5
2.0
1.5
1.0
T =
25
°
C
J
T =
25
°
C
D
J
I
= 50 A
V
GS
= 10 V
0.5
0
0.1
0
4
5
6
7
8
9
10
5
15
25
35
45
55
65
75
85 95
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
2.0
1E+06
1E+05
1E+04
1E+03
1E+02
T =
175
°
C
J
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
V
I
= 10 V
= 50 A
GS
T =
150
°
C
J
D
T =
125
°
C
J
T =
85
°
C
J
T =
25
°
C
J
1E+01
1E+00
0.2
0
−
55
−
25
0
25
50
75 100 125
150 175
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NVMTS0D6N04C
TYPICAL CHARACTERISTICS
100K
10K
8
7
C
6
5
4
OSS
Q
Q
GD
C
GS
ISS
V
= 0 V
GS
T =
25
°
C
J
f = 1 MHz
3
2
1
0
1K
V
DS
= 20 V
T =
25
°
C
J
C
I
D
= 50 A
RSS
100
0
20
40
60
80
100
120
0
10
20
30
40
Q ,
TOTAL GATE CHARGE (nC)
G
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source Voltage vs. Total
Charge
1E
−
06
1E
−
07
1E
−
08
V
V
= 10 V
= 20 V
= 50 A
GS
V
= 0 V
GS
DS
I
D
10
t
t
d(off)
T =
175
°
C
J
t
f
T =
150
°
C
J
d(on)
1
t
r
T =
25
°
C
J
T =
−
55
°
C
J
T =
125
°
C
J
0.1
1
3
5
7
9
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
1
R ,
GATE RESISTANCE (
W
)
V
SD
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
1000
100
10
T
= 25
°
C
J(initial)
10
m
s
T
= 25
°
C
C
0.5 ms
1 ms
T
= 100
°
C
Single Pulse
≤
10 V
J(initial)
V
GS
10
1
10 ms
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
0.1
1
10
100
1000
0.00001
0.0001
0.001
0.01
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. I
PEAK
vs. Time in Avalanche
4
NVMTS0D6N04C
TYPICAL CHARACTERISTICS
100
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
0.01
Single Pulse
0.001
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
DFNW8
Shipping
NVMTS0D6N04CTXG
0D6N04C
3000 /
T
a
pe & Reel
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TDFNW8 8.3×8.4, 2.0
P
,
S
INGLE COOL
CASE 507AP
ISSUE D
DATE 29 MAR 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
A
= Assembly Location
WL =
Wafer Lot Code
=
Y
ear Code
Y
WW =
Work Week Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON80534G
TDFNW8 8.3×8.4, 2.0
P
,
S
INGLE COOL
PAGE 1 OF 1
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−
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