onsemi-NVMYS4D6N04CLTWG

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onsemi-NVMYS4D6N04CLTWG
NVMYS4D6N04CL  

MOSFET

– Powe
r
,
S
ingle  
N-Channel  
40
V
,
4
.5 m
W
, 78 A  
Features  
•
Small Footprint (5×6 mm) for Compact Design  
•
Low R  
to Minimize Conduction Losses  
DS(on)  
•
Low Q
 
and Capacitance to Minimize Driver Losses  
G
V
R
MAX  
I MAX  
D
(BR)DSS  
DS(ON)  
•
LFPAK4 Package, Industry Standard  
4.5 m
W
@ 10 V  
7.2 m
W
@ 4.5 V  
•
AEC
−
Q101 Qualified and P
P
A
P Capable  
•
These Devices are Pb
−
Free and are RoHS Compliant  
40 V  
78 A  
MAXIMUM RATINGS
(T =
 
25
°
C unless otherwise noted)  
J
D (5,6)  
Parameter  
Drain
−
to
−
Source Voltage  
Symbol  
Value  
40  
Unit  
V
V
DSS  
Gate
−
to
−
Source Voltage  
V
GS  
20  
V
G (4)  
Continuous Drain  
Current R  
Steady  
State  
T
= 25
°
C  
= 100
°
C  
= 25
°
C  
I
78  
A
C
D
q
JC  
T
C
55  
S (1,2,3)  
N
−
CHANNEL MOSFET  
Power Dissipation  
T
C
P
50  
W
A
D
R
q
JC  
T
C
= 100
°
C  
25  
Continuous Drain  
Current R  
Steady  
State  
T =
 
25
°
C  
A
I
D
21  
q
JA  
MARKING  
DIAGRAM  
T =
 
100
°
C  
A
15  
Power Dissipation  
T =
 
25
°
C  
P
3.6  
1.8  
520  
W
A
D
R
q
JA  
T =
 
100
°
C  
A
4D6N04  
CL  
Pulsed Drain Current  
T =
 
25
°
C, t
 
= 10
m
s  
I
DM  
A
A
p
AWLYW  
Operating Junction and Storage
T
e
mperature  
Range  
T , T  
−
55 to  
+175  
°
C  
J
stg  
LFPAK4  
CASE 760AB  
Source Current (Body Diode)  
I
S
56  
A
4D6N04CL =
 
Specific Device Code  
Single Pulse Drain
−
to
−
Source Avalanche  
E
107  
mJ  
AS  
Energy (I  
= 5 A)  
A
WL  
Y
= Assembly Location  
=Wafer Lot  
=
Y
e
ar  
L(pk)  
Lead
T
e
mperature for Soldering Purposes  
(1/8
″
from case for 10 s)  
T
260  
°
C  
L
W
= Work Week  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information in the  
package dimensions section on p

THERMAL RESISTANCE MAXIMUM RATINGS  
Parameter  
Symbol  
Value  
3.0  
Unit  
Junction
−
to
−
Case
−
Steady State  
Junction
−
to
−
Ambient
−

R
°
C/W  
q
JC  
R
40  
q
JA  
1. The
 
entire application environment impacts the thermal resistance values shown,  
they are not constants and are only valid for the particular conditions noted.  
2
2. Surface
−
mounted on FR4 board using a 650 mm
 
, 2 oz. Cu pad.  
3. Maximum
 
current for pulses as long as 1 second is higher but is dependent  
on pulse duration and duty cycle.  
©
Semiconductor Components Industries, LLC, 2017  
1
Publication Order Number:  
June, 2019
−
Rev. 0  
NVMYS4D6N04CL/D  
 

NVMYS4D6N04CL  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise specified)  
J
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Drain
−
to
−
Source Breakdown Voltage  
V
V
GS  
= 0
V
, I
 
=
2
50
m
A  
40  
V
(BR)DSS  
D
Drain
−
to
−
Source Breakdown Voltage  
T
e
mperature Coefficient  
V
/
21  
mV/
°
C  
(BR)DSS  
T
J
Zero Gate Voltage Drain Current  
I
V
= 0
V
,  
T =
 
25
°
C  
10  
m
A  
DSS  
GS  
DS  
J
V
= 40 V  
T =
 
125
°
C  
J
250  
100  
Gate
−
to
−
Source Leakage Current  
ON CHARACTERISTICS

Gate Threshold Voltage  
I
V
= 0
V
, V
 
=
2
0 V  
nA  
GSS  
DS  
GS  
V
V
= V
 
, I
 
= 40
m
A  
1.2  
2.0  
V
GS(TH)  
GS  
DS  
D
Threshold
T
e
mperature Coefficient  
Drain
−
to
−
Source On Resistance  
V
/T  
−
5.5  
5.8  
3.7  
72  
mV/
°
C  
m
W  
GS(TH)  
J
R
V
= 4.5 V  
I
I
= 35 A  
= 35 A  
7.2  
4.5  
DS(on)  
GS  
D
V
= 10 V  
GS  
D
Forward Transconductance  
g
FS  
V
=15
V
, I
 
=
3
5 A  
S
DS  
D
CHARGES, CAPACITANCES & GATE RESISTANCE  
Input Capacitance  
C
V
= 0
V
, f = 1
M
Hz, V
 
= 25 V  
1300  
530  
22  
pF  
ISS  
GS  
DS  
Output Capacitance  
C
OSS  
C
RSS  
Reverse Transfer Capacitance  
T
o
tal Gate Charge  
Q
Q
V
GS  
= 10
V
, V
 
=
2
0 V; I
 
= 35 A  
23  
nC  
nC  
G(TOT)  
G(TOT)  
DS  
D
T
o
tal Gate Charge  
V
GS  
= 4.5
V
, V
 
=
2
0 V; I
 
= 35 A  
11  
DS  
D
Threshold Gate Charge  
Gate
−
to
−
Source Charge  
Gate
−
to
−
Drain Charge  
Plateau Voltage  
Q
2.5  
4.7  
3.0  
3.3  
G(TH)  
Q
GS  
GD  
GP  
Q
V
V
SWITCHING CHARACTERISTICS

Turn
−
On Delay Time  
t
V
= 4.5
V
, V
 
=
2
0
V
,  
9.2  
3.4  
17  
ns  
d(ON)  
GS  
D
DS  
I
= 35 A, R
 
= 1
W  
G
Rise Time  
t
r
Turn
−
Off Delay Time  
t
d(OFF)  
Fall Time  
t
f
4.4  
DRAIN
−
SOURCE DIODE CHARACTERISTICS  
Forward Diode Voltage  
V
V
S
= 0
V
,  
T =
 
25
°
C  
0.86  
0.75  
29  
1.2  
V
SD  
GS  
J
I
= 35 A  
T =
 
125
°
C  
J
Reverse Recovery Time  
Charge Time  
t
V
GS  
= 0
V
,
d
Is/dt = 100 A/
m
s,  
ns  
RR  
I
S
= 35 A  
t
t
14  
a
Discharge Time  
14  
b
Reverse Recovery Charge  
Q
12  
nC  
RR  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
4. Pulse
 
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.  
5. Switching
 
characteristics are independent of operating junction temperatures.  
2
 

NVMYS4D6N04CL  
TYPICAL CHARACTERISTICS  
100  
90  
80  
70  
60  
50  
40  
30  
20  
100  
4.0 V  
90  
80  
70  
60  
50  
40  
30  
20  
V
DS  
= 10 V  
V
GS  
= 4.5 V to 10 V  
3.6 V  
3.2 V  
2.8 V  
T =
 
25
°
C  
J
10  
0
10  
0
T =
 
125
°
C  
J
T =
 
−
55
°
C  
J
0
0.4  
0.8  
1.2  
1.6  
2.0  
2.4  
2.8  
0
1
2
3
4
5
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
V
GS  
, GATE
−
TO
−
SOURCE VOLTAGE (V)  
Figure 1. On
−
Region Characteristics  
Figure 2. Transfer Characteristics  
8
7
6
5
4
20  
18  
16  
14  
12  
10  
8
T =
 
25
°
C  
D
T =
 
25
°
C  
J
J
I
= 35 A  
V
= 4.5 V  
= 10 V  
GS  
V
GS  
6
3
2
4
2
2
3
4
5
6
7
8
9
10  
0
10 20 30 40  
50 60 70 80 90
 
100  
V
GS  
, GATE
−
TO
−
SOURCE VOLTAGE (V)  
I ,
 
DRAIN CURRENT (A)  
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source  
Figure 4. On
−
Resistance vs. Drain Current and  
Voltage  
Gate Voltage  
1.9  
100000  
10000  
1000  
T =
 
175
°
C  
J
1.8  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
V
= 10 V  
GS  
= 35 A  
I
D
T =
 
125
°
C  
J
T =
 
85
°
C  
J
100  
10  
0.8  
0.7  
−
50
−
25  
0
25  
50  
75  
100 125 150 175  
5
10  
15  
20  
25  
30  
35  
40  
T , JUNCTION TEMPERATURE (
°
C)  
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
DS  
Figure 5. On
−
Resistance Variation with  
Figure 6. Drain
−
to
−
Source Leakage Current  
Temperature  
vs. Voltage  
3

NVMYS4D6N04CL  
TYPICAL CHARACTERISTICS  
10000  
1000  
100  
10  
9
Q
T
C
ISS  
8
7
6
5
4
3
2
C
OSS  
Q
Q
GD  
GS  
C
RSS  
10  
1
V
DS  
= 20 V  
V
= 0 V  
GS  
T =
 
25
°
C  
J
T =
 
25
°
C  
J
1
0
I
D
= 35 A  
f = 1 MHz  
0
5
10  
15  
20  
25  
30  
35  
40  
0
5
10  
15  
20  
25  
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
Q ,
 
TOTAL GATE CHARGE (nC)  
G
Figure 7. Capacitance Variation  
Figure 8. Gate
−
to
−
Source vs. Total Charge  
1000  
100  
100  
10  
1
V
GS  
= 0 V  
t
r
t
f
t
d(off)  
t
d(on)  
0.1  
T =
 
125
°
C  
J
10  
1
V
V
= 4.5 V  
= 20 V  
= 35 A  
GS  
0.01  
DS  
T =
 
25
°
C  
J
I
D
T =
 
−
55
°
C  
J
0.001  
1
10  
R ,
 
GATE RESISTANCE (
W
)  
100  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
V
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)  
G
SD  
Figure 9. Resistive Switching Time Variation  
vs. Gate Resistance  
Figure 10. Diode Forward Voltage vs. Current  
100  
10  
1000  
100  
10  
T (initial)=
 
25
°
C  
J
T
V
= 25
°
C  
≤
10 V  
C
T (initial)=
 
100
°
C  
J
GS  
500
m
s  
1 ms  
10 ms  
1
Single Pulse  
1
R
Limit  
0.1  
DS(on)  
Thermal Limit  
Package Limit  
0.1  
0.01  
1E
−
4  
1E
−
3  
10E
−
2  
0.1  
1
10  
100  
V
DS  
(V)  
TIME IN AVALANCHE (s)  
Figure 11. Safe Operating Area  
Figure 12. I

PEAK

vs. Time in Avalanche  
4

NVMYS4D6N04CL  
TYPICAL CHARACTERISTICS  
100  
10  
1
50% Duty Cycle  
20%  
10%  
5%  
2%  
1%  
0.1  
Single Pulse  
0.01  
0.000001  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
PULSE TIME (sec)  
Figure 13. Thermal Characteristics  
DEVICE ORDERING INFORMATION  
Device  
†
Marking  
Package  
Shipping  
NVMYS4D6N04C
L
T
WG  
4D6N04CL  
LFPAK4  
(Pb
−
Free)  
3000 /
T
a
pe & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging  
Specifications Brochure, BRD8011/D.  
5

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
LFPAK4 5×6  
CASE 760AB  
ISSUE C  
DATE 19 NOV 2019  
GENERIC  
MARKING DIAGRAM*  
XXXXXX =
 
Specific Device Code  
A
WL  
Y
= Assembly Location  
= Wafer Lot  
=
Y
e
ar  
XXXXXX  
XXXXXX  
AWLYW  
W
= Work Week  
*This information is generic. Please refer  
to device data sheet for actual part  
marking. Some products may not follow  
the Generic Marking.  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON82777G  
LFPAK4 5×6  
PAGE 1 OF 1  
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disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2018  

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