onsemi-NVTFS4C13NWFTAG
| Part # | onsemi-NVTFS4C13NWFTAG |
Download  | onsemi-NVTFS4C13NWFTAG |
NVTFS4C13N
N-Channel,
m
8FL
30
V
,
9
.4 m
W
, 40 A
Features
•
Low R
to Minimize Conduction Losses
DS(on)
•
Low Capacitance to Minimize Driver Losses
•
Optimized Gate Charge to Minimize Switching Losses
•
NVTFS4C13NWF
−
Wettable Flanks Product
•
NVT Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC
−
Q101
Qualified and PPAP Capable
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
9.4 m
W
@ 10 V
14 m
W
@ 4.5 V
30 V
40 A
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
D (5,6)
MAXIMUM RATINGS
(T =
25
°
C unless otherwise stated)
J
Parameter
Drain
−
to
−
Source Voltage
Symbol Value Unit
V
30
20
14
V
V
A
DSS
G (4)
Gate
−
to
−
Source Voltage
V
GS
Continuous Drain
Current R
T =
25
°
C
I
D
A
S (1,2,3)
N
−
CHANNEL MOSFET
q
JA
T =
100
°
C
A
10
T =
25
°
C
P
3.0
1.5
40
W
Power Dissipation R
q
A
D
JA
MARKING DIAGRAM
T =
100
°
C
A
Steady
State
1
Continuous Drain
T
C
= 25
°
C
I
D
1
S
S
S
G
D
D
D
D
Current R
q
JC
XXXX
AYWW
G
G
WDFN8
(
m
8FL)
CASE 511AB
T
C
= 100
°
C
28
A
Power Dissipation
T
= 25
°
C
P
D
26
13
W
C
R
q
JC
T
C
= 100
°
C
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
152
A
A
p
4C13
= Specific Device Code for
NVMTS4C13N
Operating Junction and Storage
T
e
mperature
T ,
−
55 to
+175
°
C
J
stg
T
13WF =
Specific Device Code of
NVTFS4C13NWF
A
Source Current (Body Diode)
I
S
24
10
A
= Assembly Location
=
Y
e
ar
= Work Week
Single Pulse Drain
−
to
−
Source Avalanche Energy
E
AS
mJ
Y
(T =
25
°
C, I
= 14 A
, L = 0.1 mH)
J
L
pk
WW
G
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
L
260
°
C
= Pb
−
Free Package
(Note: Microdot may be in either location)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction
−
to
−
Case
−
Steady State (Drain)
R
5.8
q
JC
°
C/W
Junction
−
to
−
Ambient – Steady State
R
50
q
JA
1. The
entire application environment impacts the thermal resistance values
shown, they are not constants and are only valid for the particular conditions
noted.
2
2. Surface
−
mounted on FR4 board using a 650 mm
2 oz. Cu pad.
3. Assumes
heat
−
sink sufficiently large to maintain constant case temperature
independent of device power.
4. Continuous
DC current rating. Maximum current for pulses as long as
1 second is higher but is dependent on pulse duration and duty cycle.
©
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
August, 2019
−
Rev. 2
NVTFS4C13N/D
NVTFS4C13N
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
30
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/
14.9
(BR)DSS
mV/
°
C
T
J
Zero Gate Voltage Drain Current
I
V
= 0
V
,
= 24 V
T =
25
°
C
1.0
10
DSS
GS
DS
J
V
m
A
T =
125
°
C
J
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
GS
20 V
100
nA
GSS
DS
V
V
= V
, I
= 250
m
A
1.3
2.1
V
GS(TH)
GS
DS
D
Negative Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
V
/T
4.8
7.5
11.2
40
mV/
°
C
GS(TH)
J
R
V
= 10 V
I
I
= 30 A
= 12 A
9.4
14
DS(on)
GS
D
m
W
V
GS
= 4.5 V
D
Forward Transconductance
Gate Resistance
g
FS
V
= 1.5
V
, I
=
1
5 A
S
DS
D
R
T =
25
°
C
A
1.0
W
G
CHARGES AND CAPACITANCES
Input Capacitance
C
770
443
127
0.165
7.8
ISS
Output Capacitance
C
V
= 0
V
, f = 1
M
Hz, V
= 15 V
pF
nC
OSS
RSS
GS
DS
Reverse Transfer Capacitance
Capacitance Ratio
C
C
/C
V
GS
= 0
V
, V
=
1
5
V
, f = 1
M
Hz
RSS ISS
DS
T
o
tal Gate Charge
Q
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Gate Plateau Voltage
T
o
tal Gate Charge
Q
1.4
G(TH)
Q
2.9
V
= 4.5
V
, V
=
1
5 V; I
= 30 A
GS
GD
GP
GS
DS
D
Q
V
3.7
3.6
V
Q
V
= 10
V
, V
=
1
5 V; I
= 30 A
15.2
nC
G(TOT)
GS
DS
D
Turn
−
On Delay Time
Rise Time
t
9
d(ON)
t
r
35
13
5
V
= 4.5
V
, V
=
1
5
V
,
DS
GS
D
ns
ns
V
I
= 15 A, R
= 3.0
W
G
Turn
−
Off Delay Time
Fall Time
t
d(OFF)
t
f
Turn
−
On Delay Time
Rise Time
t
6.0
26
16
3.0
d(ON)
t
r
V
= 10
V
, V
=
1
5
V
,
DS
GS
I
D
= 15 A, R
= 3.0
W
G
Turn
−
Off Delay Time
Fall Time
t
d(OFF)
t
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
T =
25
°
C
0.82
0.69
23.4
12.1
11.3
9.7
1.1
J
V
S
= 0
V
,
= 30 A
GS
I
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
RR
t
a
ns
V
= 0
V
,
d
IS/dt = 100 A/
m
s,
GS
I
S
= 30 A
Discharge Time
t
b
Reverse Recovery Charge
Q
nC
RR
5. Pulse
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.
6. Switching
characteristics are independent of operating junction temperatures.
2
NVTFS4C13N
TYPICAL CHARACTERISTICS
70
70
60
50
40
30
20
10
0
10 V
6.5 V
V
DS
= 5 V
4.5 V
60
50
40
30
20
10
0
4.2 V
4 V
3.8 V
3.6 V
3.4 V
3.2 V
T =
125
°
C
J
3.0 V
2.8 V
T =
25
°
C
J
T =
−
55
°
C
J
T =
25
°
C
J
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.015
0.014
0.013
0.012
0.011
0.010
0.009
0.008
0.007
0.006
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
I
D
= 30 A
T =
25
°
C
J
V
= 4.5 V
GS
V
= 10 V
GS
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
10
20
30
40
50
60
70
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. V
GS
Figure 4. On
−
Resistance vs. Drain Current and
Gate Voltage
10000
1000
100
1.8
1.6
1.4
1.2
1.0
0.8
0.6
I
V
= 30 A
V
GS
= 0 V
D
= 10 V
GS
T =
150
°
C
J
T =
125
°
C
J
T =
85
°
C
J
10
−
50
−
25
0
25
50
75
100 125 150 175
5
10
15
20
25
30
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NVTFS4C13N
TYPICAL CHARACTERISTICS
1000
900
800
700
600
500
400
300
200
100
0
11
V
= 0 V
GS
10
9
8
7
6
5
4
3
2
1
0
Q
T
T =
25
°
C
J
C
iss
C
oss
Q
gd
T =
25
°
C
J
Q
gs
V
V
= 15 V
= 10 V
C
DD
rss
GS
I
D
= 30 A
0
5
10
15
20
25
30
0
2
4
6
8
10
12
14
16
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
1000
100
10
30
25
20
15
10
5
V =
0 V
GS
V
= 15 V
= 15 A
= 10 V
DD
I
D
V
GS
T =
25
°
C
J
t
r
t
d(off)
T =
125
°
C
J
t
d(on)
t
f
1
0
1
10
R ,
GATE RESISTANCE (
W
)
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
10
1
10
m
s
100
m
s
1 ms
V
GS
= 10 V
T
= 25
°
C
C
dc
2
650 mm
2 oz Cu Pad
10 ms
0.1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.01
0.1
1
10
100
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
4
NVTFS4C13N
TYPICAL CHARACTERISTICS
100
10
Duty Cycle = 50%
20%
10%
5%
2%
1
1%
0.1
0.01
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
100
50
45
40
35
30
25
20
15
10
5
T
= 25
°
C
J(initial)
10
T
= 125
°
C
1.0E
−
05
J(initial)
1
1.0E
−
06
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
(A)
1.0E
−
04
1.E
−
03
I
D
T ,
TIME IN AVALANCHE (s)
AV
Figure 13. G
FS
vs. I
D
Figure 14. Avalanche Characteristics
ORDERING INFORMATION
Device
†
Package
Shipping
NVTFS4C13NTAG
WDFN8
1500 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
5000 /
T
a
pe & Reel
5000 /
T
a
pe & Reel
(Pb
−
Free)
NVTFS4C13NWFTAG
NVTFS4C13NTWG
WDFN8
(Pb
−
Free)
WDFN8
(Pb
−
Free)
NVTFS4C13NWFTWG
WDFN8
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3×3.3, 0.65P
CASE 511AB
ISSUE D
1
DATE 23 APR 2012
SCALE 2:1
2X
NOTES:
0.20
C
1. DIMENSIONING
AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
3. DIMENSION
D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
D
A
B
E
2X
D1
MILLIMETERS
INCHES
NOM
0.030
−−−
0.012
0.20
C
8
1
7
6
5
4
DIM
A
A1
b
c
MIN
0.70
0.00
0.23
0.15
NOM
0.75
−−−
0.30
0.20
MAX
MIN
MAX
0.031
0.002
0.016
0.010
0.80
0.05
0.40
0.25
0.028
0.000
0.009
0.006
4X
q
E1
0.008
D
3.30 BSC
3.05
2.11
3.30 BSC
3.05
1.60
0.30
0.65 BSC
0.41
0.80
0.43
0.130 BSC
0.120
0.083
0.130 BSC
0.120
0.063
0.012
0.026 BSC
0.016
0.032
0.017
0.005
0.059
−−−
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
2.95
1.98
3.15
2.24
0.116
0.078
0.124
0.088
c
2
3
A1
TOP VIEW
2.95
1.47
0.23
3.15
1.73
0.40
0.116
0.058
0.009
0.124
0.068
0.016
0.10
0.10
C
C
A
C
6X
e
0.012
0.026
0.012
0.002
0.055
0
0.020
0.037
0.022
0.008
0.063
0.30
0.65
0.30
0.06
1.40
0
0.51
0.95
0.56
0.20
1.60
SEATING
PLANE
0.13
1.50
−−−
DETAIL A
SIDE VIEW
DETAIL A
q
12
12
_
_
_
_
8X
b
0.10
0.05
C
C
A
B
SOLDERING FOOTPRINT*
8X
e/2
0.42
0.65
4X
L
4X
0.66
PITCH
1
8
4
5
PACKAGE
OUTLINE
K
E2
M
E3
3.60
L1
D2
G
2.30
BOTTOM VIEW
0.57
0.47
0.75
GENERIC
MARKING DIAGRAM*
2.37
3.46
1
XXXXX
DIMENSION: MILLIMETERS
AYWW
G
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
G
XXXXX =
Specific Device Code
A
Y
= Assembly Location
=
Y
e
ar
WW
G
= Work Week
= Pb
−
Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30561E
WDFN8 3.3X3.3, 0.65P
PAGE 1 OF 1
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©
Semiconductor Components Industries, LLC, 2019
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