onsemi-NVTFS5C658NLTAG
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NVTFS5C658NL
Power MOSFET
60
V
,
5
.0 m
W
, 109 A, Single N
−
Channel
Features
•
Small Footprint (3.3 x 3.3 mm) for Compact Design
•
Low R
to Minimize Conduction Losses
DS(on)
•
Low Capacitance to Minimize Driver Losses
•
NVTFS5C658NLWF
−
Wettable Flanks Product
•
AEC
−
Q101 Qualified and P
P
A
P Capable
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
5.0 m
W
@ 10 V
7.3 m
W
@ 4.5 V
•
These Devices are Pb
−
Free and are RoHS Compliant
60 V
109 A
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
N
−
Channel
D (5
−
8)
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
60
Unit
V
V
DSS
Gate
−
to
−
Source Voltage
V
GS
20
V
Continuous Drain Cur-
T
= 25
°
C
= 100
°
C
= 25
°
C
I
109
77
A
C
D
rent R
q
JC
T
C
G (4)
Steady
State
Power Dissipation
T
C
P
114
57
W
A
D
R
q
S (1, 2, 3)
JC
T
C
= 100
°
C
Continuous Drain Cur-
T =
25
°
C
A
I
D
18
MARKING DIAGRAM
rent R
q
JA
T =
100
°
C
A
15
1
Steady
State
1
S
S
S
G
D
D
D
D
Power Dissipation
T =
25
°
C
A
P
3.2
2.2
440
W
D
XXXX
AYWW
G
G
WDFN8
(
m
8FL)
CASE 511AB
R
q
JA
T =
100
°
C
A
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
A
A
p
Operating Junction and Storage
T
e
mperature
T , T
−
55 to
°
C
J
stg
XXXX =
Specific Device Code
+175
A
Y
= Assembly Location
=
Y
e
ar
Source Current (Body Diode)
I
S
127
142
A
WW
G
= Work Week
= Pb
−
Free Package
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
mJ
Energy (I
= 5.0 A)
L(pk)
(Note: Microdot may be in either location)
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
L
260
°
C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
Parameter
Symbol
Value
1.3
Unit
R
°
C/W
q
JC
R
47
q
JA
1. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi
(
Y
) is used as required per JESD51
−
12 for packages in which
substantially less than 100% of the heat flows to single case surface.
2
3. Surface
−
mounted on FR4 board using a 650 mm
, 2 oz. Cu pad.
4. Continuous
DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
©
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
March, 2018
−
Rev. 1
NVTFS5C658NL/D
NVTFS5C658NL
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
V
= 0
V
, I
=
2
50
m
A
60
V
(BR)DSS
GS
D
I
T =
25
°
C
10
m
A
DSS
J
V
V
= 0
V
,
= 60 V
GS
DS
T =
125
°
C
J
250
100
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
V
V
= 0
V
, V
=
2
0 V
nA
GSS
DS
GS
V
= V
, I
= 75
m
A
1.2
2.2
5.0
7.3
V
GS(TH)
GS
DS
D
Drain
−
to
−
Source On Resistance
R
V
= 10
V
, I
=
5
0 A
4.2
5.8
m
W
DS(on)
GS
D
= 4.5
V
, I
=
5
0 A
GS
D
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
V
= 15
V
, I
=
5
0 A
100
S
FS
DS
D
C
V
GS
= 0
V
, f =
1
.0 MHz,
1935
890
16
pF
iss
V
DS
= 25 V
Output Capacitance
C
oss
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
rss
Q
Q
12
nC
nC
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
T
o
tal Gate Charge
Q
3.5
7
G(TH)
V
= 4.5
V
, V
=
4
8
V
, I
=
5
0 A
DS D
GS
Q
GS
GD
Q
2.4
27
V
= 10
V
, V
=
4
8
V
, I
=
5
0 A
nC
ns
G(TOT)
GS
DS
D
Turn
−
On Delay Time
Rise Time
t
16
96
d(on)
t
r
V
= 4.5
V
, V
=
4
8
V
,
DS
GS
I
D
= 50 A
Turn
−
Off Delay Time
Fall Time
t
36
d(off)
t
105
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
V
= 0
V
,
T =
25
°
C
0.9
0.8
39
21
18
15
1.2
V
SD
GS
S
J
I
= 50 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
a
V
GS
= 0
V
,
d
l
/dt = 100 A/
m
s,
S
I
S
= 50 A
Discharge Time
b
Reverse Recovery Charge
Q
nC
RR
5. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
6. Switching
characteristics are independent of operating junction temperatures.
2
NVTFS5C658NL
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
40
30
20
10
0
100
10 V to 4.5 V
3.6 V
3.4 V
V
DS
= 5 V
90
80
70
60
50
40
30
20
10
0
3.2 V
3.0 V
T =
25
°
C
J
2.8 V
2.6 V
T =
125
°
C
J
T =
−
55
°
C
J
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5 4.0
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
10
9
10
9
T =
25
°
C
J
T =
25
°
C
D
J
I
= 50 A
8
8
7
7
6
5
4
V
= 4.5 V
= 10 V
GS
6
5
4
V
GS
3
2
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
20
30
40
50
60
70
80
V
GS
, GATE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
2.0
100000
10000
1000
V
I
= 10 V
= 50 A
GS
1.8
1.6
1.4
1.2
1.0
T =
175
°
C
J
D
T =
125
°
C
J
T =
85
°
C
J
100
10
0.8
0.6
−
50
−
25
0
25
50
75 100
125 150 175
10
20
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
30
40
50
60
T , JUNCTION TEMPERATURE (
°
C)
J
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NVTFS5C658NL
TYPICAL CHARACTERISTICS
10000
1000
100
10
10
9
C
ISS
8
C
7
OSS
6
5
Q
GD
4
3
2
1
0
Q
GS
C
RSS
V
= 48 V
= 50 A
DS
V
= 0 V
T =
25
°
C
GS
I
D
J
T =
25
°
C
J
f = 1 MHz
1
0
10
20
30
40
50
60
0
2
4
6
8
10 12 14 16 18
20
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Q ,
TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
1000
100
10
100
10
1
V
V
= 4.5 V
= 48 V
= 50 A
GS
DS
I
D
t
f
t
r
t
t
d(off)
d(on)
T =
125
°
C
J
T =
25
°
C
J
T =
−
55
°
C
J
1
1
10
R ,
GATE RESISTANCE (
W
)
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
100
10
1
T
= 25
°
C
J(initial)
V
≤
10 V
GS
T
= 100
°
C
J(initial)
10
m
s
0.5 ms
1 ms
Single Pulse
= 25
°
C
T
C
1
R
Limit
DS(on)
Thermal Limit
Package Limit
10 ms
100
0.1
0.00001
0.1
0.1
1
10
0.0001
0.001
0.01
V
DS
(V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
4
NVTFS5C658NL
TYPICAL CHARACTERISTICS
100
10
1
50% Duty Cycle
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVTFS5C658NLTAG
658L
WDFN8
1500 /
T
a
pe & Reel
1500 /
T
a
pe & Reel
(Pb
−
Free)
NVTFS5C658NLWFTAG
58LW
WDFN8
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3×3.3, 0.65P
CASE 511AB
ISSUE D
1
DATE 23 APR 2012
SCALE 2:1
2X
NOTES:
0.20
C
1. DIMENSIONING
AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
3. DIMENSION
D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
D
A
B
E
2X
D1
MILLIMETERS
INCHES
NOM
0.030
−−−
0.012
0.20
C
8
1
7
6
5
4
DIM
A
A1
b
c
MIN
0.70
0.00
0.23
0.15
NOM
0.75
−−−
0.30
0.20
MAX
MIN
MAX
0.031
0.002
0.016
0.010
0.80
0.05
0.40
0.25
0.028
0.000
0.009
0.006
4X
q
E1
0.008
D
3.30 BSC
3.05
2.11
3.30 BSC
3.05
1.60
0.30
0.65 BSC
0.41
0.80
0.43
0.130 BSC
0.120
0.083
0.130 BSC
0.120
0.063
0.012
0.026 BSC
0.016
0.032
0.017
0.005
0.059
−−−
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
2.95
1.98
3.15
2.24
0.116
0.078
0.124
0.088
c
2
3
A1
TOP VIEW
2.95
1.47
0.23
3.15
1.73
0.40
0.116
0.058
0.009
0.124
0.068
0.016
0.10
0.10
C
C
A
C
6X
e
0.012
0.026
0.012
0.002
0.055
0
0.020
0.037
0.022
0.008
0.063
0.30
0.65
0.30
0.06
1.40
0
0.51
0.95
0.56
0.20
1.60
SEATING
PLANE
0.13
1.50
−−−
DETAIL A
SIDE VIEW
DETAIL A
q
12
12
_
_
_
_
8X
b
0.10
0.05
C
C
A
B
SOLDERING FOOTPRINT*
8X
e/2
0.42
0.65
4X
L
4X
0.66
PITCH
1
8
4
5
PACKAGE
OUTLINE
K
E2
M
E3
3.60
L1
D2
G
2.30
BOTTOM VIEW
0.57
0.47
0.75
GENERIC
MARKING DIAGRAM*
2.37
3.46
1
XXXXX
DIMENSION: MILLIMETERS
AYWW
G
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
G
XXXXX =
Specific Device Code
A
Y
= Assembly Location
=
Y
e
ar
WW
G
= Work Week
= Pb
−
Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30561E
WDFN8 3.3X3.3, 0.65P
PAGE 1 OF 1
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©
Semiconductor Components Industries, LLC, 2019
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−
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