onsemi-PCFA86561F
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60
V
,
0
.95 m
W
PCFA86561F
Features
•
Typical R
•
Typical Q
= 0.75 m
ꢀ
at V
= 10 V
GS
DS(on)
= 170 nC at V
= 10 V
g(tot)
GS
•
AEC
−
Q101 Qualified and P
P
A
P Capable
•
RoHS Compliant
DIMENSION (
m
m)
Die Size
6604 x 3683
Die Size (Sawn)
Source Attach Area
Gate Attach Area
Die Thickness
6584 15
x 3663
15
6405 x 3455
446.3 x 715
101.6 19.1
ORDERING INFORMATION
Gate and Source: AlSiCu
Drain: Ti
−
NiV
−
Ag (back side of die)
Passivation: Polyimide
Device
Package
PCFA86561F
Wafer
Sawn on Foil
Wafer Diameter: 8 inch
Wafer sawn on UV
T
a
pe
Bad dice identified in inking
Gross Die Counts: 1038
RECOMMENDED STORAGE CONDITIONS
The Chip is 100% Probed to Meet the Conditions and Limits
T
e
mperature
RH
22 to 28
°
C
Specified at T
= 25
°
C.
J
40 to 66%
Symbol
BV
Parameter
Condition
I =
250
ꢁ
A, V
= 0 V
D
Min
60
−
Typ
−
Max
−
Unit
V
Drain to Source Breakdown Voltage
Drain to Source Leakage Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
Bare Die Drain to Source On Resistance
Source to Drain Diode Voltage
DSS
GS
I
V
DS
V
GS
V
GS
= 60
V
, V
= 0 V
−
1
ꢁ
A
nA
V
DSS
GS
I
=
20
V
, V
= 0 V
−
−
100
4.0
0.95
1.25
GSS
DS
V
GS(th)
= V
, I
= 250
ꢁ
A
2.0
−
−
DS
D
*R
I
I
= 5 A, V
= 10 V
0.75
−
m
ꢀ
DS(on)
D
GS
V
SD
= 5 A, V
= 0 V
−
V
SD
GS
*Accurate R
test at die level is not feasible as limited by the test contact precision attainable in a die form. The max R
specification
performance
DS(on)
DS(on)
DS(on)
is defined from the historical performance of the die in package but is not guaranteed by test in production. The die R
depends on the Source wire/ribbon bonding layout.
©
Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
July, 2021
−
Rev. 1
PCFA86561F/D
PCFA86561F
ABSOLUTE MAXIMUM RATINGS
in Reference to the FDBL86561
−
F085 electrical data in TOLL (T
= 25
°
C unless otherwise noted)
J
Symbol
Parameter
Ratings
60
Unit
V
V
DSS
Drain to Source Voltage
Gate to Source Voltage
Continuous Drain Current R
V
GS
20
V
I
D
T
T
= 25
°
C
441
A
ꢂ
J
C
GS
C
= 100
°
C
312
A
C
E
1167
429
mJ
W
AS
P
Power Dissipation R
D
ꢂ
JC
Derate above 25
°
C
2.86
W/
°
C
°
C
T , T
Operating and Storage
T
e
mperature
−
55 to +175
0.35
J
STG
R
Thermal Resistance, Junction to Case
°
C/W
°
C/W
ꢂ
JC
R
43
ꢂ
JA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Current
is limited by silicon.
2. Starting
T =
25
°
C, L = 0.57 mH, I
= 64 A
J
AS
3. R
is the sum of the junction
−
to
−
case and case
−
to
−
ambient thermal resistance, where the case thermal reference is defined as the solder
ꢂ
JA
mounting surface of the drain pins. R
presented here is based on mounting on a 1 in
pad of 2oz copper.
is guaranteed by design, while R
is determined by the board design. The maximum rating
ꢂ
ꢂ
JC
JA
2
ELECTRICAL CHARACTERISTICS
in Reference to the FDBL86561
−
F085 electrical data in TOLL (T
= 25
°
C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
BV
I
Drain to Source Breakdown Voltage
Drain to Source Leakage Current
I
= 250
ꢁ
A, V
= 0 V
60
−
−
−
−
−
−
1
V
DSS
D
GS
V
V
= 60
V
,
= 0 V
T =
25
°
C
J
ꢁ
A
mA
nA
DSS
DS
GS
J
−
3
I
Gate to Source Leakage Current
V
=
20 V
−
100
GSS
GS
ON CHARACTERISTICS
V
R
Gate to Source Threshold Voltage
V
I
= V
, I
= 250
ꢁ
A
2.0
−
3.0
0.85
1.5
4.0
1.1
2.2
V
GS(th)
GS
DS
D
Drain to Source On
−
Resistance
= 80 A,
= 10 V
T =
25
°
C
J
m
ꢀ
ꢀ
DS(on)
D
V
GS
−
m
J
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 30
V
, V
= 0 V, f = 1
M
Hz
−
−
−
−
−
−
−
−
13650
3375
255
2.3
−
−
−
−
−
−
−
−
pF
iss
DS
GS
C
Output Capacitance
pF
pF
ꢀ
oss
C
Reverse Transfer Capacitance
Gate Resistance
rss
R
f = 1 MHz
g
Q
T
o
tal Gate Charge
V
GS
V
GS
V
DD
= 0 to 10
V
, V
=
4
8
V
, I
=
8
0 A
170
24
nC
nC
nC
nC
g(
T
o
T)
DD
D
Q
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
= 0 to 2
V
, V
=
4
8
V
, I
=
8
0 A
DD D
g(th)
Q
= 48
V
, I
=
8
0 A
56
gs
gd
D
Q
24
SWITCHING CHARACTERISTICS
t
Turn
−
On Delay Time
Rise Time
V
DD
V
GS
= 30
V
, I
=
8
0 A,
−
−
−
−
45
61
80
41
−
−
−
−
ns
ns
ns
ns
d(on)
D
= 10
V
, R
= 6
ꢀ
GEN
t
r
t
Turn
−
Off Delay Time
Fall Time
d(off)
t
f
2
PCFA86561F
ELECTRICAL CHARACTERISTICS
in Reference to the FDBL86561
−
F085 electrical data in TOLL (T
= 25
°
C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
DRAIN
−
SOURCE DIODE CHARACTERISTIC
V
Source to Drain Diode Voltage
I
I
= 80 A, V
= 0 V
−
−
−
−
−
1.25
1.2
−
V
V
SD
SD
GS
= 40 A, V
= 0 V
−
SD
GS
t
Reverse Recovery Time
I =
80 A, dI
/dt = 100 A/
ꢁ
s,
F
V
107
183
ns
nC
rr
SD
= 48 V
DD
Q
Reverse Recovery Charge
−
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. The
maximum value is specified by design at T
= 175
°
C. Product is not tested to this condition in production.
J
3
PCFA86561F
TYPICAL CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
0.2
0.0
500
400
300
V
= 10 V
CURRENT LIMITED
BY PACKAGE
GS
CURRENT LIMITED
BY SILICON
200
100
0
0
25
50
75
100
125
150 175
25
50
75
100 125
150 175
200
T ,
Case
T
e
mperature [
°
C]
C
T ,
Case
T
e
mperature [
°
C]
C
Figure 1. Normalized Power Dissipation
vs. Case Temperature
Figure 2. Maximum Continuous Drain
Current vs. Case Temperature
2
DUTY CYCLE
−
DESCENDING ORDER
1
D = 0.50
0.20
0.10
0.05
P
DM
0.02
0.1
0.01
t
1
t
2
NOTES:
Duty factor: D = t
/ t
SINGLE PULSE
1
2
Peak T
= P
×
Z
(t)
×
R
(t) + T
JC C
ꢂ
ꢂ
J
DM
JC
0.01
−
5
−
4
−
3
−
2
−
1
0
1
10
10
10
10
t, Rectangular Pulse Duration (s)
10
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
10000
1000
100
V
GS
= 10 V
T
25
°
C
C =
For temperatures above 25
°
C
derate peak current as follows:
175
*
T
C
Ǹ
I
+
I
ƪ ƫ
2
150
SINGLE PULSE
10
−
5
10
10
−
4
10
−
3
10
−
2
10
−
1
10
0
10
1
t, Rectangular Pulse Duration (s)
Figure 4. Peak Current Capability
4
PCFA86561F
TYPICAL CHARACTERISTICS
(continued)
2000
1000
2000
If R = 0
= (L)(I
) / (1.3
×
Rated BV
t
AV
V
)
1000
100
10
AS
DSS
−
DD
If R
≠
0
= (L/R)ln[(I
×
R) / (1.3
×
Rated BV
t
AV
V
) + 1]
AS
DSS
−
DD
100
10
1
100
ꢁ
s
Operation in this
area may be
Starting T
25
°
C
J =
limited by r
1 ms
DS(on)
Starting T
150
°
C
SINGLE PULSE
T =
max rated
J
J =
10 ms
100 ms
T
C
= 25
°
C
0.1
0.1
1
0.001 0.01 0.1
1
10
t ,
Time in Avalanche [ms]
AV
100 1000
10000
1
10
100 200
V
DS
, Drain to Source Voltage [V]
NOTE: Refer
to ON Semiconductor Application Notes
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching
Capability
300
240
180
120
60
400
100
V
= 0 V
Pulse duration = 80
ꢁ
s
Duty cycle = 0.5% MAX
GS
V
DD
= 5 V
T =
175
°
C
T =
25
°
C
J
J
10
1
T =
25
°
C
J
T =
175
°
C
J
T =
−
55
°
C
J
0
0.1
2
3
4
5
6
7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, Gate to Source Voltage [V]
V
SD
, Body Diode Forward Voltage [V]
Figure 7. Transfer Characteristics
Figure 8. Forward Diode Characteristics
400
400
V
GS
15 V
T
o
p
10 V
8 V
7 V
6 V
300
200
100
0
300
200
100
0
V
GS
5 V
15 V
T
o
p
10 V
5 V
5.5 V
5 V Bottom
8 V
7 V
6 V
5.5 V
5 V Bottom
80
ꢁ
s Pulse Width
80
ꢁ
s Pulse Width
T =
175
°
C
J
T =
25
°
C
J
0
1
2
3
4
5
0
1
2
3
4
5
V
DS
, Drain to Source Voltage [V]
V
DS
, Drain to Source Voltage [V]
Figure 9. Saturation Characteristics
Figure 10. Saturation Characteristics
5
PCFA86561F
TYPICAL CHARACTERISTICS
(continued)
2.4
20
16
12
I
80 A
Pulse duration = 80
ꢁ
s
Duty cycle = 0.5% MAX
D =
Pulse duration = 80
ꢁ
s
Duty cycle = 0.5% MAX
2.0
1.6
1.2
0.8
0.4
T
25
°
C
J =
8
4
0
T
175
°
C
J =
I
80 A
D =
V
GS
= 10 V
−
80
−
40
0
40
80
120
160 200
2
4
6
8
10
V
GS
, Gate to Source Voltage [V]
T , Junction
T
e
mperature [
°
C]
J
Figure 11. R
DSON
vs. Gate Voltage
Figure 12. Normalized R
DSON
vs. Junction
Temperature
1.5
1.2
0.9
0.6
0.3
0.0
1.2
V
I
= V
250
ꢁ
A
I
1 mA
GS
D =
DS
D =
1.1
1.0
0.9
0.8
−
80
−
40
0
40
80
120
160
200
−
80
−
40
0
40
80
120
160
200
T , Junction
T
e
mperature [
°
C]
J
T , Junction
T
e
mperature [
°
C]
J
Figure 13. Normalized Gate Threshold Voltage
vs. Temperature
Figure 14. Normalized Drain to Source
Breakdown Voltage vs. Junction Temperature
10
100000
I
80 A
D =
V
DD =
30 V
8
10000
1000
100
C
iss
V
DD =
24 V
V
DD =
36 V
6
4
C
oss
C
rss
2
0
f = 1 MHz
= 0 V
V
GS
10
0.1
1
10
100
0
20 40 60 80
100 120 140 160 180
Q ,
Gate Charge [nC]
V
DS
, Drain to Source Voltage [V]
g
Figure 15. Capacitance vs. Drain to Source
Voltage
Figure 16. Gate Charge vs. Gate to Source
Voltage
6
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,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “
onsemi
” or its affiliates
and/or subsidiaries in the United States and/or other countries.
onsemi
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A listing of
onsemi
’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
.
onsemi
reserves the right to make changes at any time to any
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−
is” and
onsemi
makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does
onsemi
assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using
onsemi
products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by
onsemi
. “Typical” parameters which may be provided in
onsemi
data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
onsemi
does not convey any license
under any of its intellectual property rights nor the rights of others.
onsemi
products are not designed, intended, or authorized for use as a critical component in life support systems
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:
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