onsemi-RF3S49092SM9A
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RF3S49092SM
Data Sheet
September 2004
20A/10A, 12
V
,
0
.060/0.140 Ohm, Logic
Level, Complementary Power MOSFET
Features
• 20A,
12V (N-Channel)
10A, 12V (P-Channel)
These complementary power MOSFETs are manufactured
using an advanced MegaFET process. This process, which
uses feature sizes approaching those of LSI integrated
circuits, gives optimum utilization of silicon, resulting in
outstanding performance. It is designed for use in
applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. This product achieves full rated conduction at a
gate bias in the 3V to 5V range, thereby facilitating true
on-off power control directly from logic level (5V) integrated
circuits.
• r
r
= 0.060
Ω
(N-Channel)
= 0.140
Ω
(P-Channel)
DS(ON)
DS(ON)
®
•
T
e
mperature
Compensating PSPICE
Model
• On-Resistance
vs Gate Drive Voltage Curves
• Peak
Current vs Pulse Width Curve
• UIS
Rating Curve
Symbol
Formerly developmental type
T
A
49092.
S2
G2
Ordering Information
PART NUMBER
PACKAGE
BRAND
F3S49092
RF3S49092SM
MO-169AB
NOTE: When
ordering, use the entire part number. For ordering the
MO-169AB in tape and reel, add the suffix 9A to the part number, i.e.,
RF3S49092SM9A.
D1
G1
S1
Packaging
JEDEC MO-169AB
G2
S2
D
G1
S1
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
o
Absolute Maximum Ratings
T =
25 C
Unless Otherwise Specified
C
N-CHANNEL
P-CHANNEL
UNITS
Drain to Source Voltage (Note 1
)
. . . . . . . . . . . . . . . . . . V
12
12
-12
-12
±
10
V
V
V
DSS
Drain to Gate Voltage (R
= 20k
Ω
, Note 1) . . . . . . . . .V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V
±
10
GS
Drain Current
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
I
20
10
A
D
Pulsed (Figures 5, 26) . . . . . . . . . . . . . . . . . . . . . . . . .
I
Refer to Peak Current Curve
Refer to Peak Current Curve
DM
Pulsed Avalanche Rating (Figures 6, 27). . . . . . . . . . . . . E
Refer to UIS Curve
Refer to UIS Curve
AS
Power Dissipation
o
T
= 25
C .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
50
0.33
50
0.33
W
W/ C
C
D
o
o
Derate Above 25
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
o
Operating and Storage
T
e
mperature . . . . . . . . . . . . T , T
J
-55 to 175
-55 to 175
C
STG
Maximum
T
e
mperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . .
T
Package Body for 10s, See
T
e
chbrief 334 . . . . . . . . . .T
o
300
260
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T
= 25
C to 150
C.
J
o
Electrical Specifications (N-Channel)
T =
25 C,
Unless Otherwise Specified
C
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
SYMBOL
BV
TEST CONDITIONS
= 250
µ
A, V
= 0V, (Figure 13)
MIN
TYP
–
MAX
UNITS
V
I
12
1
–
–
DSS
GS(TH)
D
GS
V
V
= V
, I
= 250
µ
A, (Figure 12)
–
–
1
V
GS
DS
D
o
Zero Gate Voltage Drain Current
I
V
V
= 12V,
= 0V
T
T
= 25
C
–
µ
A
µ
A
nA
Ω
DSS
DS
GS
C
C
o
= 150
C
–
–
50
±
100
0.060
100
–
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
I
V
=
±
10V
–
–
GSS
GS
r
I
= 20A, V
= 5V, (Figure 9, 11)
–
–
DS(ON)
D
GS
t
V
V
= 6V, I
≈
20A, R
= 0.24
Ω
,
–
–
ns
ON
DD
D
L
= 5V, R
= 25
Ω
GS
GS
Turn-On Delay Time
t
–
18
60
50
60
–
ns
d(ON)
(Figure 10)
Rise Time
t
–
–
ns
r
Turn-Off Delay Time
t
–
–
ns
d(OFF)
Fall Time
t
–
–
ns
f
Turn-Off Time
t
–
140
25
15
1.2
–
ns
OFF
Total Gate Charge
Q
V
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 9.6V,
= 20A,
= 0.42
Ω
–
20
12
0.9
750
700
275
–
nC
nC
nC
pF
pF
pF
g(TOT)
GS
GS
GS
DS
DD
I
D
Gate Charge at 5V
Q
–
g(5)
R
L
Threshold Gate Charge
Input Capacitance
Q
(Figure 15)
–
g(TH)
C
= 10V, V
GS
= 0V, f = 1MHz
–
ISS
OSS
RSS
(Figure 14)
Output Capacitance
C
C
–
–
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
–
–
o
R
–
3.00
62
C/W
JC
JA
θ
o
R
–
–
C/W
θ
N-Channel Source to Drain Diode Specifications
PARAMETER
Source to Drain Voltage
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.5
UNITS
V
I
I
= 20A
–
–
–
–
V
SD
SD
Reverse Recovery Time
t
= 20A, dI
/dt = 100A/
µ
s
SD
100
ns
rr
SD
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
o
Electrical Specifications (P-Channel)
T =
25 C,
Unless Otherwise Specified
C
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
SYMBOL
BV
TEST CONDITIONS
= 250
µ
A, V
= 0V, (Figure 34)
MIN
TYP
–
MAX
UNITS
V
I
-12
-1
–
–
DSS
D
GS
V
V
= V
, I
= 250
µ
A, (Figure 33)
–
–
-1
V
GS(TH)
GS
DS
D
o
Zero Gate Voltage Drain Current
I
V
V
= -12V,
= 0V
T
T
= 25
C
–
µ
A
µ
A
nA
Ω
DSS
DS
GS
C
C
o
= 150
C
–
–
-50
±
100
0.140
115
–
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
I
V
=
±
10V
–
–
GSS
GS
r
I
= 10A, V
= -5V, (Figures 30, 32)
–
–
DS(ON)
D
GS
t
V
V
= -6V, I
≈
10A, R
= 0.62
Ω
,
–
–
ns
ON
DD
GS
D
L
= -5V, R
= 25
Ω
GS
Turn-On Delay Time
t
–
25
65
40
45
–
ns
d(ON)
(Figure 31)
Rise Time
t
–
–
ns
r
Turn-Off Delay Time
t
–
–
ns
d(OFF)
Fall Time
t
–
–
ns
f
Turn-Off Time
t
–
110
24
14
1.1
–
ns
OFF
Total Gate Charge
Q
V
V
V
V
= 0V to -10V
= 0V to -5V
= 0V to -1V
V
= -9.6V,
= 10A,
= 1.0
Ω
–
19
10
0.8
775
550
150
–
nC
nC
nC
pF
pF
pF
g(TOT)
GS
GS
GS
DS
DD
I
D
Gate Charge at -5V
Q
–
g(-5)
R
L
(Figure 36)
Threshold Gate Charge
Input Capacitance
Q
–
g(TH)
C
= -10V, V
GS
= 0V, f = 1MHz
–
ISS
OSS
RSS
(Figure 35)
Output Capacitance
C
C
–
–
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
–
–
o
R
R
–
3.00
62
C/W
θ
JC
JA
o
–
–
C/W
θ
P-Channel Source to Drain Diode Specifications
PARAMETER
Source to Drain Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
= -10A
MIN
TYP
MAX
-1.5
100
UNITS
V
V
I
I
–
–
–
–
SD
SD
t
= -10A, dI
/dt = -100A/
µ
s
ns
rr
SD
SD
Typical Performance Curves (N-Channel)
1.2
25
20
15
10
5
1.0
0.8
0.6
0.4
0.2
0
0
0
25
50
75
100
125
o
150
175
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE (
C)
T ,
CASE TEMPERATURE (
C)
C
C
FIGURE 1.
NORMALIZED POWER DISSI
P
A
T
ION vs CASE
TEMPERATURE
FIGURE 2.
MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPER
A
T
URE
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
Typical Performance Curves (N-Channel)
(Continued)
DUTY CYCLE – DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
/t
1
2
SINGLE PULSE
0.01
PEAK T
= P
x Z
x R
+ T
JC C
J
DM
JC
θ
θ
-5
-4
-3
-2
-1
0
1
10
10
10
10
10
10
10
t, REC
T
A
NGULAR PULSE DURATION (s)
FIGURE 3.
NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000
100
10
1
o
o
T
= MAX RATED, T
= 25
C
C
T =
25 C FOR
TEMPER
A
T
URES
J
C
o
ABOVE 25
C DERATE PEAK
CURRENT AS FOLLOWS:
175 – T
150
C
I
=
I
25
5ms
10ms
100
V
= 5V
GS
100ms
1s
DC
OPERATION IN THIS
AREA M
A
Y
B
E
LIMITED BY r
DS(ON)
TRANSCONDUC
T
A
NCE
M
A
Y
L
IMIT CURRENT
IN THIS REGION
10
10
-5
-4
-3
-2
-1
0
1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
50
10
10
10
10
10
10
V
DS
t, PULSE WIDTH (s)
FIGURE 4.
FORWARD BIAS SAFE OPERATING AREA
FIGURE 5.
PEAK CURRENT CA
P
A
BILITY
100
50
40
30
20
10
0
V
= 10V
= 5V
GS
V
GS
V
= 4.5V
GS
o
V
= 4V
S
T
A
RTING T
= 25
C
GS
J
10
o
S
T
A
RTING T
= 150
C
J
V
= 3V
o
GS
If R = 0
= (L)(I
)/(1.3*R
A
T
ED BV
t
– V
)
DD
AV
If R
≠
0
= (L/R)ln[(I
*R)/(1.3*RATED BV
AS
DSS
PULSE DUR
A
T
ION = 80
µ
s, T
= 25
C
C
t
– V
) +1]
DD
DUTY CYCLE = 0.5% MAX
AV
AS
DSS
1
0.01
0.1
1
10
100
0
1
2
3
4
5
6
7
t
, TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
AV
DS
NOTE: Refer
to Fairchild Application Notes AN9321 and AN9322.
FIGURE 7.
SATURATION CHARACTERISTICS
FIGURE 6.
UNCLAMPED INDUCTIVE SWITCHING CA
P
A
BILITY
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
Typical Performance Curves (N-Channel)
(Continued)
50
200
150
100
50
o
V
= 6V
DD
25 C
o
175 C
I
= 5A
D
I
= 20A
D
40
30
20
10
0
o
-55 C
I
= 10A
D
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
0
0
2
4
6
8
10
200
200
0
1
2
3
4
5
6
7
V
, G
A
TE TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
GS
GS
FIGURE 8.
TRANSFER CHARACTERISTICS
FIGURE 9.
DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
140
120
100
80
1.6
V
= 6
V
, I
=
2
0A, R
= 0.24
Ω
PULSE DUR
A
T
ION = 80
µ
s, V
= 5
V
, I
=
2
0A
D
DD
D
L
GS
DUTY CYCLE = 0.5% MAX
t
r
1.4
t
D(OFF)
1.2
1.0
t
60
f
40
0.8
0.6
20
t
D(ON)
0
0
10
20
30
40
50
-80
-40
0
40
80
120
160
o
R
, G
A
T
E TO SOURCE RESIS
T
A
NCE (
Ω
)
T ,
JUNCTION TEMPERATURE (
C)
GS
J
FIGURE 10.
SWITCHING TIME vs G
A
T
E RESISTANCE
FIGURE 11.
NORMALIZED DRAIN TO SOURCE ON
RESIS
T
A
NCE vs JUNCTION TEMPERATURE
1.2
1.2
I
= 250
µ
A
V
= V
, I
= 250
µ
A
DS
D
GS
D
1.0
0.8
0.6
1.1
1.0
0.9
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
o
o
T ,
JUNCTION TEMPERATURE (
C)
T ,
JUNCTION TEMPERATURE (
C)
J
J
FIGURE 12.
NORMALIZED G
A
T
E THRESHOLD VO
L
TAGE vs
JUNCTION TEMPER
A
TURE
FIGURE 13.
NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
Typical Performance Curves (N-Channel)
(Continued)
10
V
= 9.6V
DD
1200
8
V
= 0
V
, f =
1
MHz
C
C
GS
ISS
ISS
C
C
C
= C
= C
GD
= C
+ C
900
600
300
0
GS GD
RSS
OSS
6
4
2
0
OSS
+ C
GD
DS
C
RSS
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
= 20A
= 10A
= 5A
D
D
D
0
5
10
15
20
25
0
2
4
6
8
10
Q ,
GATE CHARGE (nC)
g
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer
to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14.
CA
P
ACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 15.
NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms (N-Channel)
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t
TO OBTAIN
P
AS
+
–
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01
Ω
t
AV
FIGURE 16.
UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17.
UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
V
DS
t
t
f
r
V
DS
90%
90%
R
L
V
GS
+
10%
10%
0
0
V
DD
–
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
FIGURE 19.
RESISTIVE SWITCHING WAVEFORMS
FIGURE 18.
SWITCHING TIME TEST CIRCUIT
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
Test Circuits and Waveforms (N-Channel)
(Continued)
V
DS
V
Q
R
DD
g(TOT)
L
V
DS
V
= 10V
GS
V
GS
Q
+
–
g(5)
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 20.
GATE CHARGE TEST CIRCUIT
FIGURE 21.
GATE CHARGE WAVEFORMS
Typical Performance Curves (P-Channel)
1.2
-15
1.0
0.8
0.6
0.4
0.2
-10
-5
0
0
100
125
150
25
50
75
175
0
25
50
75
100
125
o
150
175
o
T
, CASE TEMPERATURE (
C)
T ,
CASE TEMPERATURE (
C)
C
C
FIGURE 22.
NORMALIZED POWER DISSI
P
A
T
ION vs CASE
TEMPERATURE
FIGURE 23.
MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPER
A
T
URE
DUTY CYCLE – DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
/t
1
2
SINGLE PULSE
0.01
PEAK T
= P
DM
x Z
x R
+ T
JC C
J
JC
θ
θ
-5
-4
10
-3
-2
-1
10
0
1
10
10
10
t,
R
EC
T
A
NGULAR PULSE DURATION (s)
10
10
FIGURE 24.
NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
Typical Performance Curves (P-Channel)
(Continued)
-100
-10
-1
-200
-100
o
o
T
= MAX R
A
T
ED, T
= 25
C
C
T
= 25
C FOR
TEMPERATURES
J
C
o
ABOVE 25
C DERATE PEAK
CURRENT AS FOLLOWS:
175 – T
150
C
I
=
I
25
V
= -10V
GS
5ms
10ms
V
= -5V
GS
-10
100ms
1s
DC
TRANSCONDUC
T
A
NCE
M
A
Y
L
IMIT CURRENT
IN THIS REGION
OPER
A
T
ION IN THIS
AREA M
A
Y
B
E
LIMITED BY r
DS(ON)
-1
-1
-10
, DRAIN TO SOURCE VOLTAGE (V)
-50
-5
-4
10
-3
-2
10
-1
0
1
10
10
10
10
10
V
DS
t, PULSE WIDTH (s)
FIGURE 25.
FORWARD BIAS SAFE OPERATING AREA
FIGURE 26.
PEAK CURRENT CA
P
A
BILITY
-40
-30
-20
-10
0
-100
PULSE DURATION = 80
µ
s,
V
= -10V
GS
o
T
= 25
C
C
DUTY CYCLE = 0.5% MAX
o
S
T
A
RTING T
= 25
C
J
V
= -5V
GS
-10
o
V
= -4.5V
= -4V
GS
S
T
A
RTING T
= 150
C
J
V
GS
If R = 0
= (L)(I
)/(1.3*R
A
T
ED BV
t
– V
)
DD
AV
If R
≠
0
= (L/R)ln[(I
*R)/(1.3*R
A
T
ED BV
– V
) +1]
DSS DD
AS
DSS
V
= -3V
GS
t
AV
AS
-1
0.01
0
-1
-2
-3
-4
-5
-6
-7
0.1
t
1
10
100
V
, DRAIN TO SOURCE VOLTAGE (V)
, TIME IN AVALANCHE (ms)
DS
AV
NOTE: Refer
to Fairchild Application Notes AN9321 and AN9322.
FIGURE 28.
S
A
T
UR
A
T
ION CHARACTERISTICS
FIGURE 27.
UNCLAMPED INDUCTIVE SWITCHING
CA
P
A
BILITY
-40
500
400
300
200
100
0
o
V
= -6V
I
= -3A
I =
-10A
D
DD
o
25 C
D
175 C
-30
-20
-10
0
I
= -6A
D
o
– 55
C
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
-10
0
-2
V
-4
-6
-8
0
-2 -4
, GATE TO SOURCE VOLTAGE (V)
GS
-6
-8
-10
, GATE TO SOURCE VOLTAGE (V)
V
GS
FIGURE 29.
TRANSFER CHARACTERISTICS
FIGURE 30.
DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
Typical Performance Curves (P-Channel)
(Continued)
120
1.6
1.4
1.2
1.0
0.8
PULSE DURATION = 80
µ
s, V
= -5
V
, I
=
–
10A
D
V
= -6
V
, I
=
–
10A, R
= 0.62
Ω
GS
DD
D
L
t
r
DUTY CYCLE = 0.5% MAX
100
80
60
40
20
0
t
f
t
D(OFF)
t
D(ON)
0
10
20
30
40
50
-80
-40
0
40
80
120
160
200
o
R
, GATE TO SOURCE RESISTANCE (
Ω
)
T ,
JUNCTION TEMPERATURE (
C)
GS
J
FIGURE 31.
SWITCHING TIME AS A FUNCTION OF G
A
T
E
RESIS
T
A
NCE
FIGURE 32.
NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.2
1.1
1.0
0.9
I
= -250
µ
A
V
= V
, I
= -250
µ
A
DS
D
GS
D
1.0
0.8
0.6
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T ,
JUNCTION TEMPERATURE (
C)
T ,
JUNCTION TEMPERATURE (
C)
J
J
FIGURE 33.
NORMALIZED G
A
T
E THRESHOLD VO
L
TAGE vs
JUNCTION TEMPER
A
TURE
FIGURE 34.
NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
1200
-10
V
= 0
V
, f =
1
MHz
GS
ISS
V
= -9.6V
DD
C
C
C
= C
+ C
GS
= C
GD
RSS
OSS
GD
= C
C
C
ISS
+ C
-8
-6
-4
-2
0
DS
GD
900
600
300
0
OSS
C
RSS
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
= -10A
= -6A
= -3A
D
D
D
0
-2
-4
-6
-8
-10
0
3
6
9
12
15
V
, DRAIN TO SOURCE VOLTAGE (V)
Q ,
GATE CHARGE (nC)
DS
g
NOTE: Refer
to Fairchild Application Notes AN7254 and AN7260.
FIGURE 36.
NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
FIGURE 35.
CA
P
ACITANCE vs DRAIN TO SOURCE VOLTAGE
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
Test Circuits and Waveforms (P-Channel)
V
DS
t
AV
L
0
VARY t
TO OBTAIN
P
–
R
REQUIRED PEAK I
G
AS
V
DD
+
DUT
0V
V
DD
t
P
I
AS
V
GS
V
DS
I
AS
t
P
0.01
Ω
BV
DSS
FIGURE 37.
UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 38.
UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
t
d(OFF)
d(ON)
t
t
f
V
r
DS
0
R
L
10%
10%
V
GS
V
DS
–
90%
90%
V
DD
V
0
GS
+
V
GS
10%
50%
DUT
R
GS
50%
90%
PULSE WIDTH
FIGURE 39.
SWITCHING TIME TEST CIRCUIT
FIGURE 40.
RESISTIVE SWITCHING WAVEFORMS
V
DS
V
DS
Q
R
g(TH)
L
0
V
= -1V
-V
GS
V
GS
–
V
= -5V
GS
GS
V
DD
Q
+
g(-5)
V
= -10V
GS
DUT
V
DD
I
g(REF)
Q
g(TOT)
0
I
g(REF)
FIGURE 41.
GATE CHARGE TEST CIRCUIT
FIGURE 42.
GATE CHARGE WAVEFORMS
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
Soldering Precautions
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliabilit
y
.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which the
devices are subjected.
1. Always
preheat the device.
2. The
delt
a
t
emperature between the prehea
t
a
n
d
s
oldering
o
should always be less than 100
C. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
3. The
maximum temperature gradient should be less than
o
5 C
per second when changing from preheating to
soldering.
4. The
peak temperature in the soldering process should be
o
at least 30
C higher than the melting point of the solder
chosen.
5. The
maximum soldering temperature and time must not
o
exceed 260
C for 10 seconds on the leads and case of
the device.
6. After
soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cool-
ing will increase the temperature gradient and may result
in latent failure due to mechanical stress.
7. During
cooling, mechanical stress or shock should be
avoided.
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
PSPICE Electrical Model
SUBCKT RF3S49092 2 1 3;
N-Channel Model rev 9/6/94
CA 12 8 9.77e-10
CB 15 14 9.19e-10
CIN 6 8 7.81e-10
DPLCAP
5
DRAIN
2
10
LDRAIN
DBODY 7 5 DBDMOD
DBREAK 5
11 DBKMOD
DPLCAP 10
5 DPLCAPMOD
DBREAK
RDRAIN
EBREAK 11 7 17 18 14.89
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
11
+
DBODY
6
8
ESG
17
18
16
EBREAK
MOS2
+
VTO
+
EVTO
21
GATE
1
9
20
+
6
18
8
IT 8 17 1
MOS1
LG
A
T
E
RGATE
LDRAIN 2 5 1e-9
RIN
CIN
LGATE 1
9 1.233e-9
LSOURCE 3 7 0.452e-9
LSOURCE
RSOURCE
8
7
3
SOURCE
MOS1 16 6 8 8 MOSMOD M
= 0.99
MOS2 16 21 8 8 MOSMOD M
= 0.01
S1A
S2A
RBREAK
12
15
13
14
13
17
18
8
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 4.91e-3
RGATE 9 20 2.74
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 5e-3
RVTO 18 19 RVTOMOD 1
S1B
CA
S2B
13
RVTO
19
CB
IT
14
+
+
VBAT
+
6
8
5
8
EDS
EGS
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6
0.3215
.MODEL DBDMOD D (IS = 7.00e-13
RS = 2.15e-2
TRS1 = 0.5e-3
TRS2 = 3.68e-6
CJO = 1.28e-9
TT = 1.8e-8)
.MODEL DBKMOD D (RS = 1.28e-1
TRS1 = 1.69e-3
TRS2 = -2.0e-6)
.MODEL DPLCAPMOD D (CJO = 0.84e-9
IS = 1e-30
N = 10)
.MODEL MOSMOD NMOS (VTO = 1.63
KP = 11.55
IS = 1e-30
N = 10
TOX = 1
L = 1u
W = 1u)
.MODEL RBKMOD RES (TC1 = 9.15e-4
TC2 = 3.13e-7)
.MODEL RDSMOD RES (TC1 = 7.00e-4
TC2 = 5.00e-6)
.MODEL RVTOMOD RES (TC1 = -2.155e-3
TC2 = -2.7e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -6.05
VOFF= -4.05)
.MODEL S1BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -4.05
VOFF= -6.05)
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -0.72
VOFF= 4.28)
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 4.28
VOFF= -0.72)
.ENDS
NOTE: For
further discussion of the PSPICE model, consult
A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature
Option
s
; IEEE Power Electronics Specialist Conference Records, 1991.
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
PSPICE Electrical Model
SUBCKT RF3S49092 2
1 3 ;
P-Channel Model
rev 11/8/94
CA 12 8 8.75e-10
CB 15 14 8.65e-10
CIN 6 8 7.65e-10
ESG
5
+
DRAIN
2
8
6
10
LDRAIN
DBODY
DBODY 5 7 DBDMOD
DBREAK 7
11 DBKMOD
DPLCAP 10
6 DPLCAPMOD
RDRAIN
DPLCAP
EBREAK 5 11 17 18 -23.75
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5
10 8
6 1
+
16
17
18
EBREAK
MOS2
VTO
+
EVTO 20 6 8 18 1
EVTO
21
GATE
1
9
20
+
11
6
8
IT 8 17 1
MOS1
DBREAK
18
LG
A
T
E
RGATE
RIN
CIN
LDRAIN 2 5 1e-9
LGATE 1
9 1.233e-9
LSOURCE 3 7 0.452e-9
LSOURCE
RSOURCE
8
7
3
SOURCE
MOS1 16 6 8 8 MOSMOD M
= 0.99
MOS2 16 21 8 8 MOSMOD M
= 0.01
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 7.36e-3
RGATE 9 20 6.1
S1B
CA
S2B
13
RVTO
19
CB
IT
RIN 6 8 1e9
14
+
+
VBAT
+
RSOURCE 8 7 RDSMOD 4.56e-2
RVTO 18 19 RVTOMOD 1
6
8
5
8
EDS
EGS
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6
-0.558
.MODEL DBDMOD D (IS = 3.0e-13
RS = 4.4e-2
TRS1 = 1.0e-3
TRS2 = -7.37e-6
CJO = 1.27e-9
TT = 2.2e-8)
.MODEL DBKMOD D (RS = 7.84e-2
TRS1 = -4.27e-3
TRS2 = 5.77e-5)
.MODEL DPLCAPMOD D (CJO = 2.85e-10
IS = 1e-30
N = 10)
.MODEL MOSMOD PMOS (VTO = -2.1423
KP = 9.206
IS = 1e-30
N = 10
TOX = 1
L = 1u
W = 1u)
.MODEL RBKMOD RES (TC1 = 9.61e-4
TC2 = -1.09e-6)
.MODEL RDSMOD RES (TC1 = 2.10e-3
TC2 = 6.99e-6)
.MODEL RVTOMOD RES (TC1 = -1.82e-3
TC2 = 1.47e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 5.47
VOFF= 3.47)
.MODEL S1BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 3.47
VOFF= 5.47)
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 1.05
VOFF= -3.95)
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -3.95
VOFF= 1.05)
.ENDS
NOTE: For
further discussion of the PSPICE model, consult
A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature
Options
; IEEE Power Electronics Specialist Conference Records, 1991.
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Power247™
PowerEdge™
PowerSaver™
PowerTrench
QFET
Stealth™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
FAST
FASTr™
FPS™
FRFET™
GlobalOptoisolator™
GTO™
ActiveArray™
Bottomless™
CoolFET™
CROSSVOLT
™
DOME™
EcoSPARK™
E
2
CMOS™
EnSigna™
FACT™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
QS™
QT Optoelectronics™
TinyLogic
HiSeC™
I
2
C™
Quiet Series™
RapidConfigure™
RapidConnect™
µ
SerDes™
TINYOPTO™
TruTranslation™
UHC™
i-Lo
™
ImpliedDisconnect™
FACT Quiet Series™
UltraFET
OPTOLOGIC
OPTOPLANAR™
PACMAN™
POP™
SILENT SWITCHER
VCX™
SMART START™
SPM™
Across the board. Around the world.™
The Power Franchise
Programmabl
e
A
ctive Droop™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVE
S
T
HE RIGH
T
T
O MAKE CHANGES WITHOU
T
F
URTHER NOTIC
E
T
O
A
NY
PRODUCTS HEREI
N
T
O IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGN. FAIRCHILD DOES NO
T
A
SSUM
E
A
N
Y
L
IABILITY
ARISING OU
T
O
F
T
H
E
A
PPLICATION OR USE O
F
A
N
Y
P
RODUC
T
O
R CIRCUI
T
D
ESCRIBED HEREIN; NEITHER DOES IT
CONVE
Y
A
N
Y
L
ICENSE UNDER ITS PATEN
T
R
IGHTS, NO
R
T
HE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOU
T
T
HE EXPRESS WRITTE
N
A
PPROVA
L
O
F FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I13
