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RFD16N05L, RFD16N05LSM
Data Sheet
December 2003
16A, 50
V
,
0
.047 Ohm, Logic Level,
N-Channel Power MOSFETs
Features
• 16A,
50V
• r
= 0.047
Ω
These are N-Channel logic level power MOSFETs
DS(ON)
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI
integrated circuits gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use with logic level (5V) driving sources in applications
such as programmable controllers, automotive switching,
switching regulators, switching converters, motor relay
drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate biases
in the 3V to 5V range, thereby facilitating true on-off power
control directly from logic circuit supply voltages.
• UIS
SOA Rating Curve (Single Pulse)
• Design
Optimized for 5V Gate Drives
• Can
be Driven Directly from CMOS, NMOS, TTL Circuits
• Compatible
with Automotive Drive Requirements
• SOA
is Power Dissipation Limited
• Nanosecond
Switching Speeds
• Linear
T
r
ansfer Characteristics
• High
Input Impedance
• Majority
Carrier Device
Formerly developmental type
T
A
09871.
• Related
Literature
Ordering Information
– TB334
“Guidelines for Soldering Surface Mount
Components to PC Boards”
PART NUMBER
RFD16N05L
RFD16N05LSM
PACKAGE
TO-251AA
TO-252AA
BRAND
RFD16N05L
RFD16N05LSM
Symbol
D
NOTE: When
ordering, include the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e. RFD16N05LSM9A
G
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
GATE
DRAIN (FLANGE)
SOURCE
©2003 Fairchild Semiconductor Corporation
RFD16N05L, RFD16N05LSM Rev. B1
RFD16N05L, RFD16N05LSM
o
Absolute Maximum Ratings
T =
25 C,
Unless Otherwise Specified
C
RFD16N05L,
RFD16N05LSM
UNITS
Drain to Source Voltage (Note 1
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
50
50
V
V
DS
Drain to Gate Voltage (R
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
GS
Continuous Drain Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
16
45
A
A
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
10
V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P
Derate Above 25
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
0.48
W
W/ C
D
o
o
o
Operating and Storage
T
e
mperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T , T
J
-55 to 150
C
STG
Maximum
T
e
mperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
T
Package Body for 10s, See
T
e
chbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T
= 25
C to 125
C.
J
o
Electrical Specifications
T
= 25
C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
= 250mA, V
= 0V, Figure 10
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate to Threshold Voltage
BV
I
50
1
–
–
–
–
2
DSS
D
GS
= V
, I
= 250mA, Figure 9
V
V
V
GS(TH)
GS
DS
DS
D
Zero Gate Voltage Drain Current
I
V
= 40V, V
= 0V
GS
–
1
µ
A
µ
A
nA
Ω
DSS
o
T
= 150
C
–
–
50
100
0.047
0.056
60
–
C
Gate to Source Leakage Current
I
V
=
±
10V, V
= 0V
DS
–
–
GSS
GS
Drain to Source On Resistance (Note 2)
r
I
I
= 16A, V
= 5V
= 4V
–
–
DS(ON)
D
GS
= 16A, V
–
–
Ω
D
GS
Turn-On Time
t
V
V
= 25V, I
= 8A,
–
–
ns
ns
ns
ns
ns
ns
nC
nC
nC
(ON)
DD
D
5V, R
= 12.5
Ω
GS =
GS
Turn-On Delay Time
Rise Time
t
–
14
30
42
14
–
d(ON)
Figures 15, 16
t
–
–
r
Turn-Off Delay Time
Fall Time
t
–
–
d(OFF)
t
–
–
f
Turn-Off Time
t
–
100
80
45
3
(OFF)
Total Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 40V,
–
–
g(TOT)
GS
GS
GS
DD
= 16A,
I
D
Gate Charge at 5V
Threshold Gate Charge
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Q
–
–
g(5)
R
= 2.5
Ω
L
Figures 17, 18
Q
–
–
g(TH)
o
R
–
–
2.083
100
C/W
θ
JC
θ
JA
o
R
–
–
C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Diode Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.5
UNITS
V
V
I
= 16A
SD
–
–
–
–
SD
t
I
= 16A, dI
/dt = 100A/
µ
s
125
ns
rr
SD SD
NOTES:
2. Pulse
Test: Pulse Width
≤
300ms, Duty Cycle
≤
2%.
3. Repetitive
Rating: Pulse Width limited by max junction temperature.
©2003 Fairchild Semiconductor Corporation
RFD16N05L, RFD16N05LSM Rev. B1
RFD16N05L, RFD16N05LSM
Typical Performance Curves
Unless Otherwise Specified
1.2
1.0
0.8
20
15
0.6
0.4
10
5
0.2
0
0
0
25
50
75
100
125
150
25
50
75
T ,
CASE TEMPERATURE (
C)
C
100
125
150
o
o
T
, CASE TEMPERATURE (
C)
C
FIGURE 1.
NORMALIZED POWER DISSI
P
A
T
ION vs CASE
TEMPERATURE
FIGURE 2.
MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPER
A
T
URE
2
2
10
10
o
T
= 25
C
C
T
= MAX RATED
J
Idm
I
MAX CONTINUOUS
D
o
STARTING T
= 25
C
J
10
o
OPERATION IN THIS AREA
LIMITED BY r
S
T
A
RTING T
= 150
C
10
J
DS(ON)
DC
1
If R = 0
= (L)(I
)/(1.3 RATED BV
t
– V
)
DD
AV
AS
DSS
If R
≠
0
AV
t
= (L/R)ln[(I
*R)/(1.3 R
A
T
ED BV
AS
– V
) +1]
DSS DD
0.1
1
0.01
2
1
10
, DRAIN TO SOURCE VOLTAGE (V)
10
0.10
1
10
V
t
, TIME IN AVALANCHE (ms)
DS
AV
FIGURE 3.
FORWARD BIAS SAFE OPERATING AREA
FIGURE 4.
UNCLAMPED INDUCTIVE SWITCHING SOA
(SINGLE PULSE UIS SOA)
45
45
o
V
= 15V
T
= 25
C
DS
C
V
= 10V
GS
V
= 4V
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX.
GS
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
V
= 5V
GS
30
15
0
30
15
0
V
= 3V
GS
V
= 2V
GS
0
1.5
3.0
4.5
6.0
7.5
0
1.5
3.0
4.5
6.0
V
, DRAIN TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
DS
GS
FIGURE 5.
SATURATION CHARACTERISTICS
FIGURE 6.
TRANSFER CHARACTERISTICS
©2003 Fairchild Semiconductor Corporation
RFD16N05L, RFD16N05LSM Rev. B1
RFD16N05L, RFD16N05LSM
Typical Performance Curves
Unless Otherwise Specified
(Continued)
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
2.5
2.0
1.5
1.0
0.5
0
I
= 16V
I =
16A
D
PULSE DURATION = 80
DUTY CYCLE = 0.5% MAX.
µ
s
D
V
= 15V
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX.
DS
-50
0
50
100
150
200
4
5
6
7
o
V ,
G
A
T
E TO SOURCE VOLTAGE (V)
GS
T ,
JUNCTION TEMPERATURE (
C)
J
FIGURE 7.
DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 8.
NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.4
1.4
I
= 250
µ
A
I
= 250
µ
A
D
D
V
= V
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
GS
DS
1.2
1.0
0.8
0.6
0
-50
0
50
100
150
200
-50
0
50
100
150
200
o
o
T ,
JUNCTION TEMPER
A
T
URE (
C)
T ,
JUNCTION TEMPERATURE (
C)
J
J
FIGURE 9.
NORMALIZED G
A
T
E THRESHOLD vs JUNCTION
TEMPERATURE
FIGURE 10.
NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
2000
10
V
= 0V
50
GS
R
= 3.125
Ω
,
V
= 5V
= 0.60mA
L
I
GS
f = 1MHz
G(REF)
1600
1200
800
400
0
PLATEAU VOLTAGES IN
8
6
4
2
0
37.5
DESCENDING ORDER:
V
V
V
V
= BV
DSS
DD
DD
DD
DD
C
= 0.75 BV
= 0.50 BV
= 0.25 BV
ISS
DSS
DSS
DSS
V
= BV
DSS
V
= BV
DD
DD
DSS
25
C
C
C
= C
+ C
GD
ISS
GS
= C
C
G
A
TE
RSS
OSS
GD
SOURCE
≈
+ C
GD
VOLTAGE
DS
12.5
C
OSS
C
RSS
DRAIN SOURCE VOLTAGE
I
0
0
5
10
15
20
25
I
G
(
REF
)
G
(
REF
)
t, TIME (
µ
s)
2
0
–
———————–
80
–
———————–
V
DRAIN TO SOURCE VOLTAGE (V)
DS,
I
I
G
(
ACT
)
G
(
ACT
)
FIGURE 11.
CA
P
ACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12.
NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
©2003 Fairchild Semiconductor Corporation
RFD16N05L, RFD16N05LSM Rev. B1
RFD16N05L, RFD16N05LSM
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t
TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
–
V
GS
DUT
t
P
I
0V
AS
0
0.01
Ω
t
AV
FIGURE 13.
UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14.
UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
r
R
L
V
DS
90%
90%
+
V
DD
10%
10%
R
G
0
0
–
DUT
90%
50%
V
GS
50%
PULSE WIDTH
10%
V
GS
FIGURE 15.
SWITCHING TIME TEST CIRCUIT
FIGURE 16.
RESISTIVE SWITCHING WAVEFORMS
V
DS
(ISOLATED
SUPP
L
Y
)
CURRENT
REGULATOR
V
DD
Q
SAME TYPE
AS DUT
g(TOT)
V
GS
12V
BATTERY
0.2
µ
F
Q
gd
50k
Ω
0.3
µ
F
Q
gs
D
S
V
DS
G
DUT
0
0
I
G(REF)
0
V
I
DS
G(REF)
I
CURRENT
SAMPLING
RESISTOR
I
CURRENT
SAMPLING
RESISTOR
G
D
FIGURE 17.
GATE CHARGE TEST CIRCUIT
FIGURE 18.
GATE CHARGE WAVEFORMS
©2003 Fairchild Semiconductor Corporation
RFD16N05L, RFD16N05LSM Rev. B1
RFD16N05L, RFD16N05LSM
PSPICE Electrical Model
.SUBCKT RFD16N05L 2 1 3 ; REV 4/8/92
Ca 12 8 3.33e-9
Cb 15 14 3.11e-9
Cin 6 8 1.21e-9
DPLCAP
5
5
DRAIN
2
10
Dbody 7 5 DBDMOD
LDRAIN
Dbreak 5 11 DBKMOD
Dplcap 10 5 DPLCAPMOD
RSCL1
51
+
DBREAK
RSCL2
Ebreak 11 7 17 18 70.9
Eds 14 8 5 8 1
ESCL
51
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evto 20 6 18 8 1
50
–
+
–
DBODY
6
8
11
RDRAIN
ESG
17
18
16
EBREAK
+
VTO
+
IT 8 17 1
MOS2
EVTO
GATE
1
21
+
–
6
9
20
18
8
Lgate 1 9 1.38e-9
Ldrain 2 5 1.0e-12
Lsource 3 7 1.0e-9
MOS1
8
LGATE RGATE
RIN
CIN
LSOURCE
RSOURCE
7
Mos1 16 6 8 8 MOSMOD M=0.99
Mos2 16 21 8 8 MOSMOD M=0.01
3
SOURCE
S1A
S2A
Rin 6 8 1e9
12
RBREAK
15
13
8
14
13
Rbreak 17 18 RBKMOD 1
Rdrain 5 16 RDSMOD 27.38e-3
Rgate 9 20 2.98
Rsource 8 7 RDSMOD 0.614e-3
Rvto 18 19 RVTOMOD 1
17
18
S1B
CA
S2B
13
RVTO
19
CB
+
IT
14
+
–
VBAT
5
8
6
8
EGS
EDS
+
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
–
Vbat 8 19 DC 1
Vto 21 6 0.448
.MODEL DBDMOD D (IS=1.34e-13 RS=1.21e-2 TRS1=1.64e-3 TRS2=2.59e-6
+CJO=1.13e-9 TT=4.14e-8)
.MODEL DBKMOD D (RS=8.82e-2 TRS1=-2.01e-3 TRS2=7.32e-10)
.MODEL DPLCAPMOD D (CJO=0.522e-9 IS=1e-30 N=10)
.MODEL MOSMOD NMOS (VTO=2.054 KP=24.73 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=1.01e-3 TC2=5.21e-8)
.MODEL RDSMOD RES (TC1=3.66e-3 TC2=1.46e-5)
.MODEL RVTOMOD RES (TC1=-1.81e-3 TC2=1.41e-6)
.MODEL S1AMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-4.25 VOFF=-2.25)
.MODEL S1BMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-2.25 VOFF=-4.25)
.MODEL S2AMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-0.65 VOFF=4.35)
.MODEL S2BMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=4.35 VOFF=-0.65)
.ENDS
NOTE: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; written by William J. Hepp and C. Frank Wheatley.
©2003 Fairchild Semiconductor Corporation
RFD16N05L, RFD16N05LSM Rev. B1
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Power247™
PowerTrench
QFET
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC
OPTOPLANAR™
PACMAN™
POP™
FACT Quiet Series™
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
ActiveArray™
Bottomless™
CoolFET™
CROSSVOLT
™
DOME™
EcoSPARK™
E
2
CMOS
TM
EnSigna
TM
FACT™
QS™
QT Optoelectronics™
TinyLogic
Quiet Series™
RapidConfigure™
RapidConnect™
TINYOPTO™
TruTranslation™
UHC™
HiSeC™
I
2
C™
SILENT SWITCHER
UltraFET
ImpliedDisconnect™
ISOPLANAR™
SMART START™
SPM™
Stealth™
VCX™
Across the board. Around the world.™
The Power Franchise™
Programmabl
e
A
ctive Droop™
SuperFET™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVE
S
T
HE RIGH
T
T
O MAKE CHANGES WITHOU
T
F
URTHER NOTIC
E
T
O
A
NY
PRODUCTS HEREI
N
T
O IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGN. FAIRCHILD DOES NO
T
A
SSUM
E
A
N
Y
L
IABILITY
ARISING OU
T
O
F
T
H
E
A
PPLICATION OR USE O
F
A
N
Y
P
RODUC
T
O
R CIRCUI
T
D
ESCRIBED HEREIN; NEITHER DOES IT
CONVE
Y
A
N
Y
L
ICENSE UNDER ITS PATEN
T
R
IGHTS, NO
R
T
HE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOU
T
T
HE EXPRESS WRITTE
N
A
PPROVA
L
O
F FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I6
