onsemi-RFD3055SM9A
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RFD3055, RFD3055SM, RFP3055
Data Sheet
January 2002
12A, 60
V
,
0
.150 Ohm, N-Channel Power
MOSFETs
Features
• 12A,
60V
These are N-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. These types can be operated directly
from integrated circuits.
• r
DS(ON)
= 0.150
Ω
®
•
T
e
mperature
Compensating PSPICE
Model
• Peak
Current vs Pulse Width Curve
• UIS
Rating Curve
o
• 175 C
Operating
T
e
mperature
• Related
Literature
– TB334
“Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type
T
A
49082.
Symbol
Ordering Information
D
PART NUMBER
PACKAGE
BRAND
FD3055
RFD3055
TO-251AA
G
RFD3055SM
RFP3055
TO-252AA
TO-220AB
FD3055
FP3055
S
NOTE: When
ordering, use the entire part number.
Add the suffix 9A,
to obtain the TO-252AA variant in tape and reel, i.e. RFD3055SM9A.
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
GATE
DRAIN (FLANGE)
SOURCE
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
©2002 Fairchild Semiconductor Corporation
RFD3055, RFD3055SM, RFP3055 Rev. B
RFD3055, RFD3055SM, RFP3055
o
Absolute Maximum Ratings
T =
25 C,
Unless Otherwise Specified
C
RFD3055, RFD3055SM, RFP3055
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
60
60
20
V
V
V
A
A
DSS
Drain to Gate Voltage (R
= 20K
Ω
) (Note 1
)
. . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Continuous Drain Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
GS
12
Refer to Peak Current Curve
Refer to UIS Curve
53
D
DM
Single Pulse Avalanche Rating (Figures 14, 15) . . . . . . . . . . . . . . . . . . . . . . . . . .
I
AS
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
W
D
o
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.357
-55 to 175
W/ C
o
Operating and Storage
T
e
mperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
, T
C
J
STG
Maximum
T
e
mperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See
T
e
chbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T
o
o
300
260
C
C
L
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T
= 25
C to 150
C.
J
o
Electrical Specifications
T =
25 C,
Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250
µ
A, V
= 0V (Figure 11)
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate Threshold Voltage
I
60
2
–
–
–
–
4
DSS
D
GS
= V
, I
= 250
µ
A (Figure 10)
V
V
V
GS(TH)
GS
DS D
Zero Gate Voltage Drain Current
I
V
= Rated BV
, V
= 0V
DSS GS
–
1
µ
A
µ
A
nA
Ω
DSS
GSS
DS
o
T
= 125
C, V
= 0.8 x Rated BV
–
–
25
100
0.150
40
–
C
DS
DSS
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
I
V
=
20V
= 12A, V
= 10V (Figure 9) (Note 2)
GS
–
–
GS
r
I
–
–
DS(ON)
D
t
V
= 30V, I
= 12A
–
–
ns
ON
DD
D
R =
2.5
Ω
, V
= +10V
L
GS
Turn-On Delay Time
Rise Time
t
–
7
ns
d(ON)
R
= 10
Ω
G
t
r
–
21
16
10
–
–
ns
(Figure 13)
Turn-Off Delay Time
Fall Time
t
–
–
ns
d(OFF)
t
–
–
ns
f
Turn-Off Time
t
–
40
23
12
0.8
–
ns
OFF
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Input Capacitance
Q
V
V
V
V
= 0 to 20V
= 0 to 10V
= 0 to 2V
V
= 48V,I
= 12A,
–
19
10
0.6
300
100
30
–
nC
nC
nC
pF
pF
pF
g(TOT)
GS
GS
GS
DS
DD
R =
4
Ω,
D
L
Q
–
g(10)
g(TH)
I
= 0.24mA
g(REF)
(Figure 13)
Q
–
C
= 25V, V
= 0V,
GS
–
ISS
OSS
RSS
f = 1MHz (Figure 12)
Output Capacitance
Reverse Transfer Capacitance
C
C
–
–
–
–
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
–
2.8
100
62.5
C/W
θ
JC
θ
JA
o
R
TO-251 and TO-252
TO-220
–
–
C/W
o
–
–
C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
NOTES:
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.5
UNITS
V
V
I
= 12A
–
–
–
–
SD
SD
SD
t
I
= 12A, dI
/dt = 100A/
µ
s
SD
100
ns
rr
2. Pulse
Test: Pulse Width
≤
300ms, Duty Cycle
≤
2%.
3. Repetitive
Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
©2002 Fairchild Semiconductor Corporation
RFD3055, RFD3055SM, RFP3055 Rev. B
RFD3055, RFD3055SM, RFP3055
Typical Performance Curves
Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
0
14
12
10
8
6
4
2
0
25
50
75
T ,
CASE TEMPERATURE (
C)
C
100
125
150
175
0
25
50
75
100
125
150
175
o
o
T
, CASE TEMPERATURE (
C)
C
FIGURE 1.
NORMALIZED POWER DISSI
P
A
T
ION vs CASE
TEMPERATURE
FIGURE 2.
MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
1
0.5
P
DM
0.2
0.1
0.1
t
0.05
1
0.02
0.01
t
2
NOTES:
DUTY FACTOR: D = t
/t
SINGLE PULSE
1
2
PEAK T
= P
DM
x Z
x R
+ T
θ
JC C
J
θ
JC
0.01
-5
10
-4
10
-3
10
-2
10
-1
10
0
1
10
10
t ,
RECTANGULAR PULSE DURATION (s)
1
FIGURE 3.
NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
50
10
o
o
T
= 25
C
FOR TEMPERATURES ABOVE 25
C
DERATE PEAK CURRENT
CA
P
A
BILITY AS FOLLOWS:
C
100
100
µ
s
175
–
T
C
I
=
I
*
———————
25
150
1ms
V
= 20V
= 10V
GS
OPERATION IN THIS
AREA M
A
Y
B
E
10ms
DC
1
LIMITED BY r
DS(ON)
V
GS
o
TRANSCONDUCTANCE
M
A
Y
L
IMIT CURRENT
IN THIS REGION
T
T
= 25
C
C
J
= MAX RATED
SINGLE PULSE
0.1
10
-3
10
-2
10
-1
10
0
1
2
3
4
10
, DRAIN TO SOURCE VOLTAGE (V)
100
1
10
10
10
10
10
V
DS
t, PULSE WIDTH (ms)
FIGURE 4.
FORWARD BIAS SAFE OPERATING AREA
FIGURE 5.
PEAK CURRENT CA
P
A
BILITY
©2002 Fairchild Semiconductor Corporation
RFD3055, RFD3055SM, RFP3055 Rev. B
RFD3055, RFD3055SM, RFP3055
Typical Performance Curves
Unless Otherwise Specified
(Continued)
24
18
12
50
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
V
= 10V
GS
V
= 8V
= 7V
GS
o
STARTING T
= 25
C
J
V
GS
10
o
STARTING T
= 150
C
J
V
= 6V
GS
If R = 0
6
0
t
= (L) (I
) / (1.3 RATED BV
– V
DD
)
AV
IF R
≠
0
AS DSS
V
= 5V
GS
V
= 4.5V
t
= (L/R) ln [(I
*R) / (1.3 RATED BV
AS
– V
) + 1]
DD
GS
AV
DSS
1
0
1.5
3.0
4.5
6.0
7.5
0.001
0.01
0.1
1
t
TIME IN AVALANCHE (ms)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
A
V
,
FIGURE 6.
UNCLAMPED INDUCTIVE SWITCHING
FIGURE 7.
SATURATION CHARACTERISTICS
2.5
2.0
1.5
1.0
0.5
0
24
18
12
V
= 15V
DS
PULSE DURATION = 80
µ
s
o
o
25 C
-55 C
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
V
= 10
V
, I
=
1
2A
GS
D
o
175 C
6
0
0
2
4
6
8
10
-80
-40
0
40
80
120
o
160
200
V
, GATE TO SOURCE VOLTAGE (V)
T ,
JUNCTION TEMPERATURE (
C)
GS
J
FIGURE 8.
TRANSFER CHARACTERISTICS
FIGURE 9.
NORMALIZED DRAI
N
T
O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0
2.0
1.5
I
= 250
µ
A
V
= V
, I
= 250
µ
A
DS
D
GS
D
1.5
1.0
0.5
0
1.0
0.5
0
-80
-40
0
40
80
120
160
200
-80
0
80
120
160
200
-40
40
o
o
T ,
JUNCTION TEMPERATURE (
C)
T ,
JUNCTION TEMPERATURE (
C)
J
J
FIGURE 10.
NORMALIZED GAT
E
T
HRESHOL
D
V
OLTAGE vs
TEMPERATURE
FIGURE 11.
NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RFD3055, RFD3055SM, RFP3055 Rev. B
RFD3055, RFD3055SM, RFP3055
Typical Performance Curves
Unless Otherwise Specified
(Continued)
10
7.5
5.0
2.5
0
600
400
200
0
60
45
30
15
0
V
= 0
V
, f =
1
MHz
GS
ISS
C
C
C
= C
+ C
GS
GD
V
= BV
DD
DSS
V
= BV
DSS
DD
= C
GD
RSS
OSS
≈
C
+ C
GD
DS
C
ISS
0.75 BV
0.75 BV
0.50 BV
0.25 BV
DSS
DSS
DSS
DSS
0.50 BV
0.25 BV
DSS
DSS
C
OSS
R
I
= 5
Ω
G(REF)
= 10V
L
= 0.24mA
C
RSS
V
GS
I
I
I
I
G(REF)
G(REF)
0
5
10
15
20
25
t
,
T
IME (
µ
s)
20
80
V
, DRAIN TO SOURCE VOLTAGE (V)
G(ACT)
G(ACT)
DS
NOTE: Refer
to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13.
NORMALIZED SWITCHIN
G
W
AVEFORMS FOR
CONSTANT GATE CURRENT
FIGURE 12.
CA
P
ACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
BV
DSS
t
L
P
V
DS
I
AS
VARY t
TO OBTAIN
P
+
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
–
V
GS
DUT
t
P
I
AS
0V
0
0.01
Ω
t
AV
FIGURE 14.
UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15.
UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
r
V
R
L
DS
90%
90%
+
V
10%
10%
DD
R
G
0
0
–
90%
50%
DUT
V
GS
50%
PULSE WIDTH
10%
V
GS
FIGURE 16.
SWITCHING TIME TEST CIRCUIT
FIGURE 17.
RESISTIVE SWITCHING WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFD3055, RFD3055SM, RFP3055 Rev. B
RFD3055, RFD3055SM, RFP3055
Test Circuits and Waveforms
(Continued)
V
DS
V
DD
Q
g(TOT)
R
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
–
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
0
I
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 19.
GATE CHARGE WAVEFORMS
FIGURE 18.
GATE CHARGE TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
RFD3055, RFD3055SM, RFP3055 Rev. B
RFD3055, RFD3055SM, RFP3055
PSPICE Electrical Model
.SUBCKT RFP3055
2 1 3 ;
rev 10/26/93
CA 12 8 0.540e-9
CB 15 14 0.540e-9
CIN 6 8
0.300e-9
DPLCAP
5
DRAIN
2
10
LDRAIN
DBODY 7
5 DBDMOD
DBREAK 5 11
DBKMOD
DPLCAP 10
5 DPLCAPMOD
RSCL1
DBREAK
RSCL2
51
+
5
ESCL
51
EBREAK 11 7
17 18
67.9
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
50
11
17
+
RDRAIN
DBODY
6
8
ESG
16
EBREAK
+
18
VTO
+
MOS2
EVTO
18
8
21
GATE
1
RGATE
9
IT 8 17 1
+
MOS1
8
6
LGATE
LDRAIN 2 5 1e-9
LG
A
T
E 1
9 4.61e-9
LSOURCE 3 7
4.61e-9
R
C
IN
IN
LSOURCE
RSOURCE
3
7
SOURCE
MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01
S1A
S2A
RBREAK
12
14
13
15
13
8
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 1e-4
RG
A
T
E 9 20 7.23
RIN 6 8 1e9
RSCL1 5 51 RS
L
V
CMOD
1e-6
RSCL2 5 50 1e3
18
17
S1B
CA
S2B
RVTO
19
VBAT
13
CB
IT
+
+
14
6
8
5
8
EDS
EGS
+
RSOURCE 8 7 RDSMOD 108e-3
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VB
A
T 8
1
9 DC 1
VTO 21 6
0.5
ESCL 51
50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/30,6.5))}
.MODEL DBDMOD D (IS=4.33e-14
RS=2.78e-2 TRS1=1.10e-3 TRS2=5.19e-6 CJO=3.94e-10 TT=7.63e-8)
.MODEL DBKMOD D (RS=0.676
TRS1=1.94e-3 TRS2=-1.09e-6)
.MODEL DPLCAPMOD D (CJO=0.238e-9
IS=1e-30 N=10)
.MODEL MOSMOD NMOS (VTO=4.078
KP=12 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=1.06e-3
TC2=-1.92e-6)
.MODEL RDSMOD RES (TC1=5.03e-3
TC2=1.53e-5)
.MODEL RS
L
V
CMOD RES (TC1=2.2e-3
TC2=-5e-6)
.MODEL RVTOMOD RES (TC1=-5.02e-3
TC2=-9.16e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5
ROFF=0.1 VON=-6.5 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5
ROFF=0.1 VON=-3.5 VOFF=-6.5)
.MODEL S2AMOD VSWITCH (RON=1e-5
ROFF=0.1 VON=-2.50 VOFF=2.50)
.MODEL S2BMOD VSWITCH (RON=1e-5
ROFF=0.1 VON=2.50 VOFF=-2.50)
.ENDS
NOTE: For further
discussion of
the PSPICE model consult
A New PSPICE Sub-Circuit for the Power MOSFet Featuring Globa
l
T
emperature
Options;
authored by William J. Hepp and C. Frank Wheatle
y
.
©2002 Fairchild Semiconductor Corporation
RFD3055, RFD3055SM, RFP3055 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
â
SMART START™
STAR*POWER™
Stealth™
VCX™
FAST
ACEx™
Bottomless™
CoolFET™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
FASTr™
FRFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOL
T
™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenc
h
â
QFET™
EcoSPARK™
E
2
CMOS
TM
TinyLogic™
QS™
EnSigna
TM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILEN
T
S
WITCHE
R
â
FACT™
FACT Quiet Series™
UltraFE
T
â
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILIT
Y
A
RISING OUT OF THE APPLICATION OR USE O
F
A
NY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICE
S
O
R
S
YSTEM
S
W
ITHOU
T
T
H
E
E
XPRES
S
W
RITTE
N
A
PPROVA
L
O
F
F
AIRCHIL
D
S
EMICONDUCTO
R
C
ORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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RFD3055SM
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General description
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Features
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Product
status/pricing/packaging
General description
These are N-Channel enhancement mode
silicon gate power field effect transistors. They
are advanced power MOSFETs designed,
tested, and guaranteed to withstand a specified
level of energy in the breakdown avalanche
mode of operation. All of these power
MOSFETs are designed for applications such
as switching regulators, switching convertors,
motor drivers, relay drivers, and drivers for
high power bipolar switching transistors
requiring high speed and low gate drive power.
These types can be operated directly from
integrated circuits.
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Design tools
Formerly developmental type TA49082.
company
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Features
●
●
12A, 60V
= 0.150
Ω
r
DS(ON)
●
Temperature Compensating PSPICE
Model
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●
●
Peak Current vs Pulse Width Curve
UIS Rating Curve
175°C Operating Temperature
Related Literature
❍
TB334 “Guidelines for
Soldering Surface Mount
Components to PC Boards”
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Product status/pricing/packaging
Product
RFD3055SM9A136
RFD3055SM9A
RFD3055SM
Product status
Pricing*
Package type
N/A TO-252(DPAK)
$0.54 TO-252(DPAK)
$0.51 TO-252(DPAK)
Leads Packing
method
Full Production
Full Production
Full Production
3
3
3
TAPE REEL
TAPE REEL
RAIL
* 1,000 piece Budgetary Pricing
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