onsemi-RFP40N10LE
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RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Data Sheet
January 2002
40A, 100
V
,
0
.040 Ohm, Logic Level
N-Channel Power MOSFETs
Features
• 40A,
100V
These N-Channel enhancement mode power MOSFETs are
manufactured using the latest manufacturing process
technolog
y
.
T
his process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers
.
T
hese transistors can be operated directly from
integrated circuits.
• r
= 0.040
Ω
DS(ON)
®
•
T
e
mperature
Compensating PSPICE
Model
• Peak
Current vs Pulse Width Curve
• UIS
Rating Curve
o
• 175 C
Operating
T
e
mperature
• Related
Literature
– TB334
“Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type
T
A
49163.
Symbol
Ordering Information
D
PART NUMBER
PACKAGE
BRAND
FG40N10L
RFG40N10LE
TO-247
RFP40N10LE
TO-220AB
TO-263AB
FP40N10L
F40N10LE
G
RF1S40N10LESM
NOTE: When
ordering, use the entire part number. Add the suffix, 9A, to
obtain the TO-263AB variant in tape and reel, i.e. RF1S40N10LESM9A.
S
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
SOURCE
DRAIN
GATE
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN (FLANGE)
JEDEC TO-263AB
DRAIN
(FLANGE)
GATE
SOURCE
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
o
Absolute Maximum Ratings
T =
25 C,
Unless Otherwise Specified
C
RFG40N10LE, RFP40N10LE,
RF1S40N10LESM
UNITS
Drain to Source Breakdown Voltage (Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . .
.
V
100
100
10
V
V
V
A
DSS
DGR
GS
D
DM
Drain to Gate Voltage (R
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . .
V
GS
Gate to Source Voltage (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
V
Continuous Drain Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
40
Refer to Peak Current Curve
Refer to UIS Curve
150
Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
W
D
o
o
Derate Above 25
C .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.00
-55 to 175
W/ C
o
Operating and Storage
T
e
mperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
C
J
STG
Maximum
T
e
mperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See
T
e
chbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
o
o
300
260
C
C
L
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T
= 25
C to 150
C.
J
o
Electrical Specifications
T =
25 C,
Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250
µ
A, V
= 0V (Figure 13)
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate Threshold Voltage
I
100
–
–
–
3
DSS
D
GS
= V
, I
= 250
µ
A (Figure 12)
V
V
V
V
V
1
–
–
–
–
–
–
–
–
–
–
–
–
–
V
GS(TH)
GS
DS
DS
GS
DS D
Zero Gate Voltage Drain Current
I
= 95V, V
= 90V, V
= 0V
–
1
µ
A
µ
A
µ
A
Ω
DSS
GSS
GS
GS
o
= 0V, T
= 150
C
–
250
10
0.040
200
–
C
Gate to Source Leakage Current
I
=
10V
–
Drain to Source On Resistance (Note 2)
Turn-On Time
r
I
= 40A, V
= 5V
GS
–
DS(ON)
D
t
V
V
= 50V, I
= 40A, R
= 1.25
Ω
,
–
ns
ON
DD
GS
D
L
= 5V, R
= 2.5
Ω
GS
Turn-On Delay Time
Rise Time
t
22
140
70
65
–
ns
d(ON)
(Figures 10, 18, 19)
t
–
ns
r
Turn-Off Delay Time
Fall Time
t
–
ns
d(OFF)
t
–
ns
f
Turn-Off Time
t
165
180
105
4
ns
OFF
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 80V,
= 40A,
145
85
3
nC
nC
nC
g(TOT)
GS
GS
GS
DD
I
D
Q
g(5)
R =
2.0
Ω
(Figures 20, 21)
L
Q
g(TH)
Input Capacitance
C
V
= 25V, V
= 0V,
GS
–
–
–
–
–
–
3000
–
–
pF
pF
pF
ISS
OSS
RSS
DS
f = 1MHz
(Figure 14)
Output Capacitance
C
C
500
Reverse Transfer Capacitance
Thermal Resistance Junction-to-Case
Thermal Resistance Junction-to-Ambient
200
–
o
R
All Packages
TO-247
–
–
–
1.0
30
80
C/W
θ
JC
θ
JA
o
R
C/W
o
TO-220AB and TO-263AB
C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Diode Reverse Recovery Time
NOTES:
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.5
UNITS
V
V
I
I
= 40A
–
–
–
–
SD
SD
SD
t
= 40A, dI
/dt = 100A/
µ
s
SD
205
ns
rr
2. Pulse
test: pulse width
≤
80
µ
s, duty cycle
≤
2%.
3. Repetitive
rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Typical Performance Curves
Unless Otherwise Specified
1.2
50
40
30
20
10
0
1.0
0.8
0.6
0.4
0.2
0
25
50
75
100
125
150
175
0
25
50
75
100
125
o
150
175
o
T
, CASE TEMPERATURE (
C)
T ,
CASE TEMPERATURE (
C)
C
C
FIGURE 1.
NORMALIZED POWER DISSI
P
A
T
ION vs CASE
TEMPERATURE
FIGURE 2.
MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
0.5
0.2
0.1
0.1
P
DM
0.05
t
t
1
2
0.02
0.01
NOTES:
DUTY FACTOR: D = t
/t
1
2
x R
SINGLE PULSE
0.01
PEAK T
= P
x Z
+ T
J
DM
θ
JC
θ
JC C
-5
10
-4
10
-3
10
-2
10
-1
10
0
1
10
10
t, REC
T
ANGULAR PULSE DURATION (s)
FIGURE 3.
NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
100
500
o
FOR TEMPERATURES
o
T
= 25
C
o
C
V
= 10V
= 5V
ABOVE 25
C DERATE PEAK
CURRENT AS FOLLOWS:
T
= 175
C
GS
J
V
GS
175
–
T
C
I = I
———————-
–
25
150
100
100
µ
s
1ms
THERMAL IMPEDANCE
M
A
Y
L
IMIT CURRENT
IN THIS REGION
10
1
10ms
OPERATION IN THIS
AREA M
A
Y
B
E
o
LIMITED BY r
T
= 25
C
DS(ON)
C
10
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
-5
10
-4
-3
10
-2
10
-1
0
1
10
10
t, PULSE WIDTH (s)
10
10
V
DS
FIGURE 4.
FORWARD BIAS SAFE OPERATING AREA
FIGURE 5.
PEAK CURRENT CA
P
A
BILITY
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Typical Performance Curves
Unless Otherwise Specified
(Continued)
500
80
60
40
20
0
If R = 0
= (L)(I
)/(1.3*RATED BV
V
= 10V
= 5V
GS
t
– V
)
DD
AV
If R
≠
0
= (L/R)ln[(I
*R)/(1.3*RATED BV
AS
DSS
V
GS
V
= 4V
GS
t
AV
– V
) +1]
DD
AS DSS
100
PULSE DURATION = 80
µ
s
o
DUTY CYCLE = 0.5% MAX
STARTING T
= 25
C
J
o
T
= 25
C
C
10
1
V
= 3V
GS
o
STARTING T
= 150
C
J
V
= 2.5V
GS
0.001
0.01
0.1
1
10
0
1.5
3.0
4.5
6.0
t
,
T
IME IN AVALANCHE (ms)
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer
to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6.
UNCLAMPED INDUCTIVE SWITCHING
FIGURE 7.
SATURATION CHARACTERISTICS
80
100
75
50
25
0
o
o
-55 C
25 C
V
= 15V
DD
I
= 40A
I
= 80A
I
= 10A
D
D
D
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
o
175 C
60
40
20
I
= 20A
D
PULSE DURATION = 80
µ
s, V
= 15V
DD
DUTY CYCLE = 0.5% MAX.
0
0
1.5
3.0
4.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
, GATE TO SOURCE VOLTAGE (V)
V
GS
, GATE TO SOURCE VOLTAGE (V)
GS
FIGURE 8.
TRANSFER CHARACTERISTICS
FIGURE 9.
DRAI
N
T
O SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
700
600
500
400
300
200
2.50
t
d(OFF)
V
= 50
V
, I
=
4
0A, R
= 1.25
Ω
D L
PULSE DURATION = 80
µ
s,
DUTY CYCLE = 0.5% MAX.
DD
V
= 5
V
, I
=
4
0A
GS
D
2.00
1.50
1.00
0.50
0
t
r
t
f
t
d(ON)
100
0
-80
-40
0
40
80
120
160
200
0
10
20
30
40
50
o
R
, GATE TO SOURCE RESISTANCE (
Ω
)
T ,
JUNCTION TEMPERATURE (
C)
GS
J
FIGURE 10.
SWITCHING TIME vs GATE RESISTANCE
FIGURE 11.
NORMALIZED DRAI
N
T
O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Typical Performance Curves
Unless Otherwise Specified
(Continued)
1.50
1.25
1.00
0.75
0.50
1.50
1.25
1.00
0.75
0.50
I
= 250
µ
A
D
V
= V
, I
= 250
µ
A
DS
GS
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T ,
JUNCTION TEMPERATURE (
C)
T ,
JUNCTION TEMPERATURE (
C)
J
J
FIGURE 12.
NORMALIZED GAT
E
T
HRESHOL
D
V
OLTAGE vs
JUNCTION TEMPERATURE
FIGURE 13.
NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
100
75
50
25
0
5.00
3.75
2.50
3500
C
V
= BV
V =
BV
DD DSS
ISS
DD
DSS
2800
V
= 0
V
, f =
1
MHz
GS
R
I
= 2.5
Ω
G(REF)
L
C
C
C
= C
+ C
ISS
GS
GD
= 1.7mA
2100
1400
700
0
= C
GD
RSS
OSS
V
= 5V
GS
≈
C
+ C
GD
DS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
V
V
V
V
= BV
DD
DD
DD
DD
DSS
1.25
0
= 0.75 BV
= 0.50 BV
= 0.25 BV
DSS
DSS
DSS
C
C
OSS
RSS
I
I
G
(
REF
)
G
(
REF
)
0
5
10
15
20
25
t,
T
IME (
µ
s)
———————
———————
20
80
I
I
G
(
ACT
)
G
(
ACT
)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer
to Fairchild Application Notes AN7254 and AN7260.
FIGURE 15.
SWITCHIN
G
W
AVEFORMS FOR CONSTANT GATE
CURRENT
FIGURE 14.
CA
P
ACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t
TO OBTAIN
P
AS
+
–
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01
Ω
t
AV
FIGURE 16.
UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17.
UNCLAMPED ENERGY WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Test Circuits and Waveforms
(Continued)
t
t
ON
OFF
t
d(OFF)
t
d(ON)
V
DS
t
t
f
r
V
DS
90%
90%
R
L
V
GS
+
10%
10%
0
V
DD
–
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18.
SWITCHING TIME TEST CIRCUIT
FIGURE 19.
RESISTIVE SWITCHING WAVEFORMS
V
DS
V
Q
R
DD
g(TOT)
L
V
DS
V
= 20V
GS
V
L
= 10V FOR
Q
OR Q
GS
DEVICES
g(10)
g(5)
V
GS
2
+
–
V
DD
V
= 10V
GS
V
GS
V
= 5V FOR
GS
2
L
DEVICES
DUT
V
= 2V
V
= 1V FOR
GS
GS
2
I
L DEVICES
0
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 20.
GATE CHARGE TEST CIRCUIT
FIGURE 21.
GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
PSPICE Electrical Model
SUBCKT 40N10LE 2 1 3 ;
rev 8/15/95
CA 12 8
3.50e-9
CB 15 14
3.50e-9
CIN 6 8
1.70e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11
DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
EBREAK 11 7 17
18 120.7
EDS 14 8 5 8
1
EGS 13 8 6 8
1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8
1
EVTEMP 20 6 18 22 1
DBREAK
+
RSLC2
5
ESLC
11
51
–
50
+
–
17
18
–
DBODY
RDRAIN
6
8
EBREAK
ESG
IT 8 17 1
EVTHRES
+
+
16
21
–
19
8
MWEAK
LDRAIN 2 5 1.00e-9
LGATE 1
9 5.17e-9
LSOURCE 3 7
2.13e-9
LGATE
EVTEMP
+
RGATE
GATE
1
6
–
18
22
MMED
9
20
MSTRO
8
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.04e-2
RGATE 9 20
2.15
RLDRAIN 2 5 10
RLGATE 1 9 51.7
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RLSOURCE 3 7 21.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD
4.85e-3
RVTHRES 22 8 RVTHRESMOD
1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
–
+
+
VBAT
6
8
5
8
EGS
EDS
+
–
–
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
22
RVTHRES
VBAT 22 19
DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*79),3.5))}
.MODEL DBODYMOD D (IS = 1.96e-12
RS = 3.87e-3
TRS1 = 9.93e-4
TRS2 = 4.97e-6
CJO = 1.53e-9
TT = 7.41e-8 M = 0.50)
.MODEL DBREAKMOD D (RS = 3.12e-1
TRS1 = 1.07e-3
TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 1.97e-9
IS = 1e-30
M = 0.87)
.MODEL MMEDMOD NMOS (VTO = 1.73 KP = 2.80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.15)
.MODEL MSTROMOD NMOS (VTO = 2.04 KP = 80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.50 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 21.5 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.74e-4
TC2 = -3.71e-7)
.MODEL RDRAINMOD RES (TC1 = 9.71e-3
TC2 = 2.90e-5)
.MODEL RSLCMOD RES (TC1 = 2.17e-3 TC2 = 1.27e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.08e-3 TC2 = -6.82e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.52e-3
TC2 = -1.21e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -6.00
VOFF= -1.50)
.MODEL S1BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -1.50
VOFF= -6.00)
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -0.50
VOFF= 0.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 0.0
VOFF= -0.50)
.ENDS
NOTE: For
further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatle
y
.
©2002 Fairchild Semiconductor Corporation
RFG40N10LE, RFP40N10LE, RF1S40N10LESM Rev. B
TRADEMARKS
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â
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GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOL
T
™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenc
h
â
QFET™
EcoSPARK™
E
2
CMOS
TM
TinyLogic™
QS™
EnSigna
TM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILEN
T
S
WITCHE
R
â
FACT™
FACT Quiet Series™
UltraFE
T
â
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILIT
Y
A
RISING OUT OF THE APPLICATION OR USE O
F
A
NY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICE
S
O
R
S
YSTEM
S
W
ITHOU
T
T
H
E
E
XPRES
S
W
RITTE
N
A
PPROVA
L
O
F
F
AIRCHIL
D
S
EMICONDUCTO
R
C
ORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
