onsemi-SFF9250L
| Part # | onsemi-SFF9250L |
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Advanced Power MOSFET
SFF9250L
FEATURES
BV
DSS
= -200
V
R
DS(on)
= 0.23
Ω
I
D
= -12.6
A
❑
Logic-Level Gate Drive
❑
Avalanche Rugged Technology
❑
Rugged Gate Oxide Technology
❑
Lower Input Capacitances
❑
Improved Gate Charge
❑
Extended Safe Operating Area
❑
Lower Leakage Current : 10uA (Max.) @ V
DS
=-200V
❑
Lower R
DS(ON)
: 0.175
Ω
(Typ.)
TO-3PF
1
2
3
1.Gate 2.
Drain 3.
Source
Absolute Maximum Ratings
Symbol
Characteristic
Drain-to-Source Voltage
Value
-200
-12.6
-7.9
Units
V
DSS
V
Continuous Drain Current (T
C
=25
°
C)
Continuous Drain Current (T
C
=100
°
C)
Drain Current-Pulsed
I
D
A
①
I
DM
V
GS
E
AS
I
AR
-50.4
±
20
990
A
V
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
②
①
①
③
mJ
A
-12.6
20.4
-5.0
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (T
C
=25
°
C)
Linear Derating Factor
E
AR
dv/dt
mJ
V/ns
W
90
P
D
T
J
, T
STG
T
L
0.72
W/
°
C
Operating Junction and
– 55
to +150
300
Storage Temperature Range
Maximum Lead Temp. for Soldering
°
C
Purposes, 1/8
″
from case for 5-seconds
Thermal Resistance
Symbol
Characteristic
Junction-to-Case
Junction-to-Ambient
Typ.
Max.
Units
R
θ
JC
0.61
40
—
—
°
C /W
R
θ
JA
Rev. A
P-CHANNEL
POWER MOSFET
SFF9250L
Electrical Characteristics
(T
C
=25
°
C unless
otherwise specified)
Symbol
Characteristic
Test Condition
Min. Typ. Max.
Units
BV
DSS
Drain-Source Breakdown Voltage
V
V
GS
=0V,I
D
=-250
μ
A
-200 —
— -0.17
-1.0 —
—
—
Δ
BV/
Δ
T
J
Breakdown Voltage Temp. Coeff.
V/
°
C I
D
=-250
μ
A
See Fig 7
DS
=-5V,I
D
=-250
μ
A
GS
=-20V
V
GS(th)
Gate Threshold Voltage
V
V
V
-2.0
100
-100
10
Gate-Source Leakage
, Forward
Gate-Source Leakage
, Reverse
—
—
—
—
—
—
—
—
I
GSS
nA
V
GS
=20V
V
DS
=-200V
I
DSS
Drain-to-Source Leakage Current
μ
A
V
DS
=-160V,T
C
=125
°
C
100
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
R
DS(on)
V
GS
=-5V,I
D
=-6.3A
④
④
Ω
— .175
0.23
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
S
V
DS
=-40V,I
D
=-6.3A
—
13
—
— 2500
3250
V
GS
=0V,V
DS
=-25V,f =1MHz
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
—
—
—
—
—
—
—
—
—
520 pF
270
400
210
20
See Fig 5
50
V
DD
=-100V,I
D
=-12.6A,
310
ns
150
100
65
R
G
=6.2
Ω
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
210
140
120
See Fig 13
④ ⑤
Q
g
Total Gate Charge
Gate-Source Charge
Gate-Drain(Miller) Charge
V
DS
=-160V,V
GS
=-5V,
I
D
=-12.6A
90
nC
—
Q
gs
Q
gd
12
See Fig 6 & Fig 12
④ ⑤
—
54
Source-Drain Diode Ratings and Characteristics
Symbol
I
S
Characteristic
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Min. Typ. Max.
Units
Test Condition
Integral reverse pn-diode
in the MOSFET
—
—
-12.6
-50.4
-1.5
—
—
—
—
—
—
A
V
I
SM
①
④
—
V
SD
t
rr
T
J
=25
°
C,I
S
=-12.6A,V
GS
=0V
260
2.8
ns T
J
=25
°
C,I
F
=-19.5A,V
DD
=-160V
μ
C di
F
/dt=100A/
μ
s
Q
rr
—
④
Notes ;
①
Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
②
L=3.9mH, I
AS
=-19.5A, V
DD
=-50V, R
G
=27
Ω
, Starting T
J
=25
℃
③
I
SD
≤
-19.5A, di/dt
≤
500A/
μ
s, V
DD
≤
BV
DSS
, Starting T
J
=25
℃
④
Pulse Test : Pulse Width
≤
300
μ
s, Duty Cycle
≤
2%
⑤
Essentially Independent of Operating Temperature
P-CHANNEL
POWER MOSFET
SFF9250L
Fig 1.
Output Characteristics
Fig 2.
Transfer Characteristics
V
G
S
-10.0 V
-8.0 V
-6.0 V
-5.0 V
-4.5 V
-4.0 V
-3.5 V
Top :
10
1
10
1
Bottom :
-3.0 V
℃
150
10
0
℃
25
℃
-55
10
0
※
※
Note
Note :
ꢀ
1. V
DS
= -40V
1. 250
s Pulse Test
ꢀ
℃
2. T
C
=
2
5
2. 250
s Pulse Test
-1
10
-1
10
10
0
10
1
2
4
6
8
10
-V
GS
, Gate-Source Voltage
[V]
-V
D
S
, Drain-Source Voltage [V]
Fig 3.
On-Resistance vs. Drain Current
Fig 4.
Source-Drain Diode Forward Voltage
0.8
0.6
0.4
0.2
0.0
10
1
V
GS
= – 5V
V
GS
= – 10V
10
0
℃
150
℃
25
※
Note :
1. V
GS
= 0V
※
℃
Note : T = 25
ꢀ
2. 250
s Pulse Test
J
-1
10
0
20
40
60
80
100
0.6
1.2
1.8
2.4
3.0
3.6
-I
D
, Drain Current
[A]
-V
SD
, Source-Drain Voltage
[V]
Fig 5.
Capacitance vs. Drain-Source Voltage
Fig 6.
Gate Charge vs. Gate-Source Voltage
12000
10500
9000
7500
6000
4500
3000
1500
0
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
rss
= C
gd
C
6
4
2
0
V
DS
= -40V
V
DS
= -100V
V
DS
= -160V
※
Note ;
C
1. V
G
S
= 0 V
2. f = 1 MHz
iss
C
oss
C
rss
※
Note : I
D
= -19.5 A
-1
10
10
0
10
1
0
20
40
60
80
100
Q
G
, Total Gate Charge [nC]
-V
D
S
, Drain-Source Voltage [V]
P-CHANNEL
POWER MOSFET
SFF9250L
Fig 7.
Breakdown Voltage vs. Temperature
Fig 8.
On-Resistance vs. Temperature
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
0.9
0.8
※
Note :
※
Note :
1. V
G
S
= 0 V
1. V
G
S
= -5 V
2. I
D
= -9.8 A
ꢀ
2. I
D
= -250
A
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
T
J
, Junction Temperature [
o
C
]
T
J
, Junction Temperature [
o
C]
Fig 9.
Max. Safe Operating Area
Fig 10.
Max. Drain Current vs. Case Temperature
20
Operation in This Area
is Limited by R
DS(on)
10
2
10
1
10
0
10
-1
15
10
5
100
µ
s
1 ms
10 ms
DC
※
Notes :
1. T
C
= 25
o
2. T
J
= 150
o
C
C
3. Single Pulse
0
25
10
0
10
1
10
2
50
75
100
125
150
℃
T
C
, Case Temperature [
]
-V
DS
, Drain-Source Voltage [V]
Fig 11.
Thermal Response
1 0
0
D = 0 .5
※
N o te s
1 .
Z
ꢁ
J
C
(
t)
2 .
D u
t
y
F a c to r,
D = t
1
/
t
2
:
0
.
2
℃
/W M
a x .
=
0
.
6 1
1 0
–
1
3 .
T
J M
– T
C
= P
D M
* Z
ꢁ
J
C
(
t)
0
.
1
0
.
0 5
P
DM
0
.
0 2
0
.
0 1
t
1
t
2
sin g le
p u lse
1 0
–
2
1 0
–
5
1 0
–
4
1 0
–
3
1 0
–
2
1 0
–
1
1 0
0
1 0
1
t
1
, S
q u a
r
e
W a
v e
P u ls e
D u ra tio n
[s e c ]
P-CHANNEL
POWER MOSFET
SFF9250L
Fig 12.
Gate Charge Test Circuit
& Waveform
V
GS
Same Type
50K
Ω
as DUT
Q
g
12V
200nF
-5V
300nF
V
DS
V
GS
Q
gs
Q
gd
DUT
-3mA
Charge
Fig 13.
Resistive Switching Test Circuit
& Waveforms
R
L
t
on
t
off
V
DS
t
f
t
d(on)
t
r
t
d(off)
V
DD
( 0.5 rated V
DS
)
R
G
V
in
10%
DUT
-5V
90%
V
DS
Fig 14.
Unclamped Inductive Switching Test Circuit
& Waveforms
BV
DSS
——————–
BV
DSS
— V
DD
L
1
2
2
—-
E
AS
=
L
L
I
AS
V
DS
V
DD
t
p
Time
I
D
V
DD
V
DS
(t)
R
G
I
D
(t)
DUT
-5V
I
AS
BV
DSS
P-CHANNEL
POWER MOSFET
SFF9250L
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
& Waveforms
DUT
+
V
DS
_
I
S
L
Driver
R
G
Compliment of DUT
(N-Channel)
V
DD
V
GS
• dv/dt controlled by
R
G
• I
S
controlled by pulse period
Gate Pulse Width
————————–
V
GS
D =
Gate Pulse Period
5V
( Driver )
I
FM
, Body Diode Forward Current
I
S
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
f
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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SFF9250L
200V P-Channel Logic Level A-FET
Contents
Features
|
Product status/pricing/packaging
Features
●
●
Logic-Level Gate Drive
Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : 10 µA (Max.)
This page
Print version
●
●
●
●
Design tools
@ V
= -200V
DS
●
Lower R
: 0.175
Ω
(Typ.)
DS
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Product status/pricing/packaging
Product
Product status
Pricing*
$2.00
Leads
Packing method
company
TO-3PF
SFF9250L
Full Production
3
RAIL
* 1,000 piece Budgetary Pricing
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