onsemi-SFM9110TF

SFM9110  

Advanced Power MOSFET  

FEATURES  

BV

DSS

= -100

 

V  

R

DS(on)

= 1.2

 

Ω

 

I

D

= -1.0

 

A  

n

Avalanche Rugged Technology  

n

Rugged Gate Oxide Technology  

n

Lower Input Capacitance  

n

Improved Gate Charge  

n

Extended Safe Operating Area  

n

Lower Leakage Current : 10

 

µ

A (Max.)

 

@ V

DS

= -100V  

n

Lower R

DS(ON)

: 0.912

 

Ω

(Typ.)  

SOT-223  

2

1

3

1. Gate

 

2. Drain

 

3. Source  

Absolute Maximum Ratings  

Symbol  

Characteristic  

Value  

-100  

-1.0  

-0.7  

-8.0  

±

30  

Units  

V

DSS  

Drain-to-Source Voltage  

V

Continuous Drain Current (T

A

=25

o

C)  

Continuous Drain Current (T

A

=70

o

C)  

Drain Current-Pulsed  

I

D  

A

1

I

DM  

V

GS  

E

AS  

I

AR  

O

A

V

Gate-to-Source Voltage  

2

Single Pulsed Avalanche Energy  

Avalanche Current  

mJ  

A

53  

O

1

-1.0  

0.25  

-6.5  

2.52  

0.02  

O

1

E

AR  

dv/dt  

Repetitive Avalanche Energy  

mJ  

V/ns  

W

O

3

Peak Diode Recovery dv/dt  

O

o

*

Total Power Dissipation (T

A

=25 C)  

P

D  

W/

o

C  

*

Linear Derating Factor  

Operating Junction and  

T

J

, T

STG  

– 55

 

to +150  

300  

Storage Temperature Range  

Maximum Lead Temp. for Soldering  

Purposes, 1/8”

 

from case for 5-seconds  

T

L  

Thermal Resistance  

Symbol  

Characteristic  

Junction-to-Ambient  

Typ.  

—  

Max.  

Units  

R

θ

JA  

*

50  

*

When mounted on the minimum pad size recommended

 

(PCB Mount).  

Rev. B  

P-CHANNEL  

POWER MOSFET  

SFM9110  

Electrical Characteristics

(T

C

=25

o

C unless otherwise specified)  

Symbol  

BV

DSS  

Characteristic  

Min. Typ. Max.

 

Units  

Test Condition  

V

Drain-Source Breakdown Voltage  

Breakdown Voltage Temp. Coeff.  

Gate Threshold Voltage  

V

V/

o

C  

V

-100 —  

— -0.1  

-2.0 —  

—  

—  

∆

BV/

∆

T

J  

V

GS(th)  

I

D

=-250

µ

A  

See Fig 7  

V

V

V

-4.0  

Gate-Source Leakage

 

, Forward  

Gate-Source Leakage

 

, Reverse  

—  

—  

—  

—  

— -100  

I

GSS  

nA  

—  

—  

100  

-10  

V

DS

=-100V  

I

DSS  

Drain-to-Source Leakage Current  

µ

A  

V

— -100  

Static Drain-Source  

On-State Resistance  

Forward Transconductance  

Input Capacitance  

4

R

DS(on)  

V

GS

=-10V,I

D

=-0.5A  

V

DS

=-40V,I

D

=-0.5A  

—  

—  

Ω

O

1.2  

4

g

fs  

C

iss  

C

oss  

C

rss  

t

d(on)  

t

r  

—  

—  

—  

—  

—  

—  

—  

—  

—  

—  

—  

1.3  

—  

S

O

260 335  

V

GS

=0V,V

DS

=-25V,f =1MHz  

Output Capacitance  

Reverse Transfer Capacitance  

Turn-On Delay Time  

Rise Time  

80  

25  

30  

50  

60  

35  

10  

—  

50  

17  

10  

20  

25  

12  

9

pF  

See Fig 5  

V

DD

=-50V,I

D

=-3.6A,  

Ω

R

G

=24  

ns  

t

d(off)  

t

f  

Turn-Off Delay Time  

Fall Time  

See Fig 13  

4

5

OO  

Q

g  

Total Gate Charge  

Gate-Source Charge  

Gate-Drain(“Miller”) Charge  

V

DS

=-80V,V

GS

=-10V,  

Q

gs  

Q

gd  

nC  

1.5  

4.3  

I

D

=-3.6A  

4

5

—  

See Fig 6 & Fig 12

 

OO  

Source-Drain Diode Ratings and Characteristics  

Symbol  

I

S  

Characteristic  

Continuous Source Current  

Pulsed-Source Current  

Diode Forward Voltage  

Reverse Recovery Time  

Reverse Recovery Charge  

Min. Typ. Max.

 

Units  

Test Condition  

Integral reverse pn-diode  

in the MOSFET  

T

J

=25

o

C,I

S

=-1.0A,V

GS

=0V  

T

J

=25

o

C,I

F

=-3.6A  

—  

—  

—  

—  

—  

—  

-1.0  

-8.0  

-3.8  

—  

A

1

I

SM  

O

4

V

SD  

t

rr  

V

O

ns  

µ

C  

— 100  

4

Q

rr  

— 0.35 —  

di

F

/dt=100A/

µ

s  

O

Notes ;  

1 Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature  

O

L=80mH, I

AS

=-1.0A, V

DD

=-25V, R

G

=27

Ω

*

, Starting T

J

=25

o

C  

2

O

I

<

-3.6A, di/dt

<

300A/

µ

s, V

 

<

BV

DSS

, Starting T

J

=25

o

C  

3

_

_

_

O

SD  

DD  

4

_

Pulse Test : Pulse Width = 250

µ

s, Duty Cycle

<

2%  

O

5

Essentially Independent of Operating Temperature  

O

P-CHANNEL  

POWER MOSFET  

SFM9110  

Fig 1.

 

Output Characteristics  

Fig 2.

 

Transfer Characteristics  

1

V

GS  

1

10  

10  

Top :  

–

1

5 V  

–

1

0 V  

– 8.0 V  

–

7

.0 V  

– 6.0 V  

–

5

.

5

V  

–

5

.0 V  

Bottom :

 

– 4.5V  

0

10  

0

10  

150

o

C  

25

o

C  

@

N

otes :  

1. V

 

= 0 V  

GS  

2. V

 

= -40 V  

@

N

otes :  

DS  

-1  

–

5

5

o

C  

µ

1. 250

 

s Pulse Test  

µ

3. 250

 

s Pulse Test  

10  

2. T

 

= 25

o  

C

C

-1  

10  

-1  

0

1

2

4

6

8

10  

10  

10  

10  

-V

G

S

,

G

ate-Source Voltage

 

[V]  

-V

D

S

,

D

rain-Source Voltage

 

[V]  

Fig 3.

 

On-Resistance vs. Drain Current  

Fig 4.

 

Source-Drain Diode Forward Voltage  

5

4

3

2

1

0

1

10  

V =

 

–

10 V  

GS  

0

10  

150

o

C  

@

N

otes :  

1. V

 

= 0 V  

25

o

C  

GS  

2. 250

 

s Pulse Test  

V =

 

–

20 V  

µ

GS  

@

N

ote : T

 

= 25

o

C  

J

-1  

10  

0

2

4

6

8

10  

12  

14  

0.5  

1.0  

1.5  

2.0  

2.5  

3.0  

3.5  

4.0  

-I , Drain Current [A]  

-V

S

D

,

S

ource-Drain Voltage

 

[V]  

D

Fig 5.

 

Capacitance vs. Drain-Source Voltage  

Fig 6.

 

Gate Charge vs. Gate-Source Voltage  

500  

400  

300  

200  

100  

C

gs ds  

C

ds gd  

V

10  

5

C

r

ss

=

C  

V

gd  

V

C

i

ss  

@

N

ote

s

:  

1. V

G

S

= 0 V  

2.

f

= 1

M

Hz  

C

o

ss  

C

r

ss  

@

N

ote

s

:I

=

-3.

6

A  

D

0

0  

10  

0

1

0

2

4

6

8

10  

10  

Q ,

T

otal Gate Charge [nC]  

-V ,

 

Drain-Source Voltage [V]  

G

DS  

P-CHANNEL  

POWER MOSFET  

SFM9110  

Fig 7.

 

Breakdown Voltage vs. Temperature  

Fig 8.

 

On-Resistance vs. Temperature  

1.2  

1.1  

1.0  

0.9  

0.8  

2.5  

2.0  

1.5  

1.0  

0.5  

0.0  

@

N

otes :  

@

N

otes :  

1. V

 

= -10 V  

1. V

 

= 0 V  

GS  

GS  

2. I

 

= -1.8 A  

2. I

 

= -250

 

A  

D

µ

D

-75 -50 -25  

0

25  

50  

75  

100 125 150 175  

o

-75 -50 -25  

0

25  

50  

75  

100 125 150 175  

o

T ,

J

unction Temperature

[

C

]  

T ,

J

unction Temperature

[

C

]  

J

J

Fig 9.

 

Max. Safe Operating Area  

Fig 10.

 

Max. Drain Current vs. Case Temperature  

1.2  

2

10  

Operation in This Area  

is Limited by R

DS(on)  

0.9  

0.6  

0.3  

0.0  

1

10  

0.01 ms  

0.1 ms  

0

1

m

s  

10  

10 ms  

DC  

@

N

otes :  

1. T

 

= 25

o

C  

-1  

C

10  

2. T

 

= 150

o

C  

J

3. Single Pulse  

-2  

10  

0

1

2

25  

50  

75  

100  

125  

150  

10  

10  

10  

o

T ,

C

ase Temperature

[

C

]  

-V

D

S

,

D

rain-Source Voltage

 

[V]  

c

Fig 11.

 

Thermal Response  

10

2  

D=0.5  

@ Notes :  

(t)=50

o

C/W Max.  

10

1  

1. Z  

0.2  

0.1  

2. Duty Factor, D=t

1

/t

2  

3. T

J

M

-T

C

=P

D

M

*Z

θ

J

C

(t)  

0.05  

0.02  

0.01  

P

.

DM  

t

1.  

t

2.  

10

0  

single pulse  

10

–

5  

10

–

4  

t

1  

10

–

3  

10

–

2  

10

–

1  

10

0  

10

1  

,

Square Wave Pulse Duration

 

[sec]  

P-CHANNEL  

POWER MOSFET  

SFM9110  

Fig 12.

 

Gate Charge Test Circuit

 

& Waveform  

“ Current Regulator ”  

V

GS  

Same Type  

as DUT  

50K

Ω  

Q

g  

12V  

200nF  

-10V  

300nF  

V

DS  

Q

gs  

Q

gd  

V

GS  

DUT  

R

2  

-3mA  

R

1  

Charge  

Current Sampling (I

G

) Current

 

Sampling (I

D

)  

Resistor Resistor  

Fig 13.

 

Resistive Switching Test Circuit

 

& Waveforms  

R

L  

t

on  

t

off  

V

out  

V

in  

t

f  

t

d(on)  

t

r  

t

d(off)  

V

DD  

( 0.5 rated V

DS  

)

V

in  

10%  

R

G  

DUT  

-10V  

90%  

V

out  

Fig 14.

 

Unclamped Inductive Switching Test Circuit

 

& Waveforms  

BV

DSS  

1

2

2

L

L  

I

D  

—-  

——————–  

BV

DSS

— V

DD  

E

AS  

=

L

L

I

AS  

V

DS  

t

p  

Time  

Vary t

p

to obtain  

required peak I

D  

V

DD  

V

DS

(t)  

R

G  

C

V

DD  

I

D

(t)  

DUT  

-10V  

I

AS  

BV

DSS  

t

p  

P-CHANNEL  

POWER MOSFET  

SFM9110  

Fig 15.

 

Peak Diode Recovery dv/dt Test Circuit

 

& Waveforms  

+

V

DS  

DUT  

—  

I

S  

L

Driver  

V

GS  

Compliment of DUT  

R

G  

(N-Channel)  

V

DD  

V

GS  

• dv/dt controlled by “R

G

”  

• I

S

controlled by Duty Factor “D”  

Gate Pulse Width  

V

GS  

————————–  

D =  

Gate Pulse Period  

10V  

( Driver )  

Body Diode Reverse Current  

I

RM  

I

S  

( DUT )  

di/dt  

I

FM

, Body Diode Forward Current  

V

f  

V

DS  

( DUT )  

Body Diode  

V

DD  

Forward Voltage Drop  

Body Diode Recovery dv/dt  

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F FAIRCHILD SEMICONDUCTOR CORPORATION.  

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PRODUCT STATUS DEFINITIONS  

Definition of Terms  

Datasheet Identification  

Product Status  

Definition  

Advance Information  

Formative or  

In Design  

This datasheet contains the design specifications for  

product development. Specifications may change in  

any manner without notice.  

Preliminary  

First Production  

This datasheet contains preliminary data, and  

supplementary data will be published at a later date.  

Fairchild Semiconductor reserves the right to make  

changes at any time without notice in order to improve  

design.  

No Identification Needed  

Obsolete  

Full Production  

This datasheet contains final specifications. Fairchild  

Semiconductor reserves the right to make changes at  

any time without notice in order to improve design.  

Not In Production  

This datasheet contains specifications on a product  

that has been discontinued by Fairchild semiconductor.  

The datasheet is printed for reference information only.  

Rev. I1