onsemi-SFP9614
| Part # | onsemi-SFP9614 |
Download  | onsemi-SFP9614 |
Advanced Power MOSFET
SFP9614
FEATURES
BV
DSS
= -250
V
R
DS(on)
= 4.0
Ω
I
D
= -1.
6 A
ν
ν
ν
ν
ν
ν
ν
Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : -10
µ
A (Max.)
@ V
DS
= -250V
Low R
DS(ON)
: 3.5
Ω
(Typ.)
TO-220
1
2
3
1.Gate 2.
Drain 3.
Source
Absolute Maximum Ratings
Symbol
Characteristic
Value
-250
-1.6
Units
V
DSS
Drain-to-Source Voltage
V
Continuous Drain Current (T
C
=25
o
C)
Continuous Drain Current (T
C
=100
o
C)
Drain Current-Pulsed
I
D
A
-1.0
I
DM
V
GS
E
AS
I
AR
1
A
V
-6.5
O
+
_
Gate-to-Source Voltage
30
2
Single Pulsed Avalanche Energy
Avalanche Current
112
-1.6
2.0
mJ
A
O
1
O
E
AR
dv/dt
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (T
C
=25
o
C)
Linear Derating Factor
1
mJ
V/ns
W
O
3
-4.8
20
O
P
D
T
J
, T
STG
T
L
0.16
W/
o
C
Operating Junction and
– 55
to +150
300
Storage Temperature Range
Maximum Lead Temp. for Soldering
o
C
Purposes, 1/8
“ from case for 5-seconds
Thermal Resistance
Symbol
R
θ
JC
Characteristic
Typ.
Max.
Units
Junction-to-Case
Case-to-Sink
—
0.5
—
6.25
—
o
C/W
R
θ
CS
R
θ
JA
Junction-to-Ambient
62.5
Rev. B1
2001 Fairchild Semiconductor Corporation
P-CHANNEL
POWER MOSFET
SFP9614
Electrical Characteristics
(T
C
=25
o
C unless otherwise specified)
Symbol
BV
DSS
Characteristic
Min. Typ. Max.
Units
Test Condition
V
GS
=0V,I
D
=-250
µ
A
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
V
V/
o
C
V
-250 —
— -0.21
—
-2.0 —
-4.0
— -100
—
∆
BV/
∆
T
J
V
GS(th)
I
D
=-250
µ
A
See Fig 7
V
V
V
DS
=-5V,I
D
=-250
µ
A
GS
=-30V
GS
=30V
Gate-Source Leakage
, Forward
Gate-Source Leakage
, Reverse
—
—
—
—
I
GSS
nA
—
—
100
-10
V
DS
=-250V
DS
=-200V,T
C
=125
o
C
I
DSS
Drain-to-Source Leakage Current
µ
A
V
— -100
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
4
R
DS(on)
V
GS
=-10V,I
D
=-0.8A
V
DS
=-40V,I
D
=-0.8A
—
—
Ω
4.0
O
4
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
—
—
—
—
—
—
—
—
—
—
—
1.0
—
S
O
225 295
V
GS
=0V,V
DS
=-25V,f =1MHz
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
55
20
30
45
60
30
11
—
35
13
10
18
24
11
9
pF
See Fig 5
V
DD
=-125V,I
D
=-1.6A,
R
G
=24
Ω
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
See Fig 13
4
5
O
O
Q
g
Total Gate Charge
Gate-Source Charge
Gate-Drain( “Miller” )
Charge
V
DS
=-200V,V
GS
=-10V,
Q
gs
Q
gd
nC
2.0
4.6
I
D
=-1.6A
4
5
O
—
See Fig 6 & Fig 12
O
Source-Drain Diode Ratings and Characteristics
Symbol
I
S
Characteristic
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Min. Typ. Max.
Units
Test Condition
—
—
—
— -1.6
— -6.5
— -4.0
Integral reverse pn-diode
in the MOSFET
T
J
=25
o
C,I
S
=-1.6A,V
GS
=0V
T
J
=25
o
C,I
F
=-1.6A
A
I
SM
1
O
4
V
SD
t
rr
V
O
ns
µ
C
— 130 —
— 0.61 —
4
Q
rr
di
F
/dt=100A/
µ
s
O
Notes ;
1 Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
O
L=70mH, I
AS
=-1.6A, V
DD
=-50V, R
G
=27
Ω
*
, Starting T
J
=25
o
C
2
O
I
_
-1.6A, di/dt
250A/
µ
s, V
_
BV
DSS
, Starting T
J
=25
o
C
3
_
<
<
SD
<
DD
O
_
<
4
Pulse Test : Pulse Width = 250
µ
s, Duty Cycle
2%
O
Essentially Independent of Operating Temperature
5
O
P-CHANNEL
POWER MOSFET
SFP9614
Fig 1.
Output Characteristics
Fig 2.
Transfer Characteristics
V
G
S
Top :
-15 V
-10 V
-8.0 V
-7.0 V
-6.0 V
-5.5 V
-5.0 V
10
0
10
-1
10
-2
10
0
10
-1
10
-2
Bottom :
-4.5 V
150
o
C
25
o
C
@ Notes
1. V
GS
2. V
DS
:
=
=
– 55
@ Notes
1. 250
µ
s Pulse Test
2. T
C
25
o
C
:
0 V
-40 V
3. 250
µ
s Pulse Test
=
10
-1
10
0
10
1
2
4
6
8
10
-V
GS
, Gate-Source Voltage
[V]
-V
DS
, Drain-Source Voltage
[V]
Fig 3.
On-Resistance vs. Drain Current
Fig 4.
Source-Drain Diode Forward Voltage
12
10
8
10
0
10
-1
10
-2
V
GS
= -10 V
6
150
o
C
25
o
C
4
V
GS
= -20 V
@ Notes :
1. V
GS
= 0 V
2. 250
µ
s Pulse Test
2
@ Note : T
J
= 25
o
C
0
0
1
2
3
4
5
6
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-I
D
, Drain Current
[A]
-V
SD
, Source-Drain Voltage
[V]
Fig 5.
Capacitance vs. Drain-Source Voltage
Fig 6.
Gate Charge vs. Gate-Source Voltage
400
300
200
100
12
C
=
C +C (C =
s
horted
)
iss gs gd
ds
V
DS
= -50 V
C
=
C +C
oss ds gd
10
8
C
=
C
rss gd
V
DS
= -125 V
V
DS
= -200 V
C
i
ss
C
o
ss
6
@
N
ote
s
:
1. V
=
0V
GS
4
C
r
ss
2.
f
= 1
M
Hz
2
@ Notes : I
D
= -1.6 A
0
0
10
0
1
10
0
2
4
6
8
10
-V
D
S
,
D
rain-Source Voltage [V]
Q
G
, Total Gate Charge
[nC]
P-CHANNEL
POWER MOSFET
SFP9614
Fig 7.
Breakdown Voltage vs. Temperature
Fig 8.
On-Resistance vs. Temperature
1.2
1.1
1.0
0.9
0.8
2.5
2.0
1.5
1.0
0.5
0.0
@ Notes
1. V
GS
2. I
D
:
=
=
@ Notes :
1. V
GS
= 0 V
2. I
D
= -250
µ
A
-10 V
-0.8
A
-75 -50 -25
0
25
50
75 100 125 150 175
-75 -50 -25
0
25
50
75 100 125 150 175
T
J
, Junction Temperature
[
o
C]
T
J
, Junction Temperature
[
o
C]
Fig 9.
Max. Safe Operating Area
Fig 10.
Max. Drain Current vs. Case Temperature
2.0
Operation in This Area
is Limited by R
DS(on)
1
10
1.6
1.2
0.8
0.4
0.0
0.1 ms
1
m
s
0
10
10 ms
DC
@
N
otes :
1. T
= 25
o
C
C
-1
10
2. T
= 150
o
C
J
3. Single Pulse
-2
10
0
1
2
25
50
75
100
125
150
10
10
10
o
T ,
C
ase Temperature
[
C
]
-V
D
S
,
D
rain-Source Voltage
[V]
c
Fig 11.
Thermal Response
D=0.5
@ Notes :
0.2
10
0
1. Z
J
C
(t)=6.25
o
C/W Max.
θ
2. Duty Factor, D=t
1
/t
2
3. T
J
M
-T
C
=P
D
M
*Z
J
C
(t)
0.1
θ
0.05
P
.
DM
0.02
0.01
t
1.
t
2.
10
–
1
single pulse
10
–
5
10
–
4
t
1
10
–
3
10
–
2
10
–
1
10
0
10
1
,
Square Wave Pulse Duration
[sec]
P-CHANNEL
POWER MOSFET
SFP9614
Fig 12.
Gate Charge Test Circuit
& Waveform
“ Current Regulator ”
V
GS
Same Type
as DUT
50K
Ω
Q
g
12V
200nF
-10V
300nF
V
DS
Q
gs
Q
gd
V
GS
DUT
R
2
-3mA
R
1
Charge
Current Sampling (I
G
) Current
Sampling (I
D
)
Resistor Resistor
Fig 13.
Resistive Switching Test Circuit
& Waveforms
R
L
t
on
t
off
V
out
V
in
t
f
t
d(on)
t
r
t
d(off)
V
DD
( 0.5 rated V
DS
)
V
in
10%
R
G
DUT
-10V
90%
V
out
Fig 14.
Unclamped Inductive Switching Test Circuit
& Waveforms
BV
DSS
1
2
2
L
L
I
D
—-
——————–
BV
DSS
— V
DD
E
AS
=
L
L
I
AS
V
DS
t
p
Time
Vary t
p
to obtain
required peak I
D
V
DD
V
DS
(t)
R
G
C
V
DD
I
D
(t)
DUT
-10V
I
AS
BV
DSS
t
p
P-CHANNEL
POWER MOSFET
SFP9614
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
& Waveforms
+
V
DS
DUT
—
I
S
L
Driver
V
GS
Compliment of DUT
R
G
(N-Channel)
V
DD
V
GS
• dv/dt controlled by “R
G
”
• I
S
controlled by Duty Factor “D”
Gate Pulse Width
V
GS
————————–
D =
Gate Pulse Period
10V
( Driver )
Body Diode Reverse Current
I
RM
I
S
( DUT )
di/dt
I
FM
, Body Diode Forward Current
V
f
V
DS
( DUT )
Body Diode
V
DD
Forward Voltage Drop
Body Diode Recovery dv/dt
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,
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A
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DEVICE
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YSTEM
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W
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XPRES
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RITTE
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PPROVA
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AIRCHIL
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the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
