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SI4410DY
N-channel TrenchMOS logic level FET
Rev. 03 — 4 December 2009
Product data sheet
1. Product
profile
1.1 General
description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features
and benefits
Low conduction losses due to low
Suitable for high frequency
applications due to fast switching
characteristics
on-state resistance
1.3 Applications
DC motor control
Notebook computers
Portable equipment
DC-to-DC convertors
Lithium-ion battery applications
1.4 Quick
reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
drain-source voltage
T
j
≥
25 °C; T
j
≤
150 °C
Min
Typ
Max Unit
V
DS
I
D
–
–
–
–
30
10
V
A
drain current
T
amb
= 25 °C; pulsed;
see
Figure 1
and
3
P
tot
total power
dissipation
T
amb
= 25 °C; pulsed;
see
Figure 2
–
–
–
2.5
–
W
Dynamic characteristics
Q
GD
gate-drain charge
V
GS
= 10 V; I
D
= 10 A;
V
DS
= 15 V; T
j
= 25 °C;
see
Figure 12
7
nC
Static characteristics
R
DSon
drain-source
on-state resistance
V
GS
= 4.5 V; I
D
= 5 A;
T
j
= 25 °C;
see
Figure 10
and
11
–
–
15
11
20
m
Ω
V
GS
= 10 V; I
D
= 10 A;
13.5 m
Ω
T
j
= 25 °C;
see
Figure 10
and
11
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning
information
Table 2.
Pinning information
Pin
1
Symbol Description
Simplified outline
Graphic symbol
S
S
S
G
D
D
D
D
source
source
source
gate
8
5
4
D
2
3
G
4
mbb076
S
5
drain
1
6
drain
SOT96-1 (SO8)
7
drain
8
drain
3. Ordering
information
Table 3.
Ordering information
Type number
Package
Name
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SI4410DY
SOT96-1
4. Limiting
values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
Parameter
Conditions
Min
Max
30
Unit
drain-source voltage
gate-source voltage
drain current
T
j
≥
25 °C; T
j
≤
150 °C
–
V
V
A
V
GS
-20
–
20
8
I
D
T
amb
= 70 °C; pulsed;
see
Figure 1
T
amb
= 25 °C; pulsed;
–
–
–
–
10
A
see
Figure 1
and
3
I
DM
P
tot
peak drain current
t
p
≤
10 µs; T
amb
= 25 °C; pulsed;
see
Figure 3
50
A
total power dissipation
T
amb
= 70 °C; pulsed;
see
Figure 2
1.6
2.5
W
W
T
amb
= 25 °C; pulsed;
see
Figure 2
T
stg
T
j
storage temperature
junction temperature
-55
-55
150
150
°C
°C
Source-drain diode
I
S
source current
T
amb
= 25 °C; pulsed
–
2.3
A
SI4410DY_3
© NXP B.
V
. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 December 2009
2 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa19
03aa11
120
120
I
der
(%)
P
der
(%)
80
40
0
80
40
0
0
50
100
150
200
amb
(
°
C)
0
50
100
150
200
T
T
amb
(
°
C)
Fig 1.
Normalized continuous drain current as a
function of ambient temperature
Fig 2.
Normalized total power dissipation as a
function of ambient temperature
03ae23
2
10
R
DSon
= V
/I
DS D
t
p
= 10
µ
s
I
D
(A)
1 ms
10
10 ms
1
100 ms
D.C.
t
p
P
δ
=
T
−
1
10
10 s
(V)
t
t
p
T
−
2
10
10
−
1
2
1
10
10
V
DS
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
SI4410DY_3
© NXP B.
V
. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 December 2009
3 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal
characteristics
Table 5.
Symbol
R
th(j-sp)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from
junction to solder point
–
–
–
K/W
R
th(j-a)
thermal resistance from
mounted on a printed-circuit board;
–
–
50
K/W
junction to ambient
minimum footprint; tp
≤
10 s;
see
Figure 4
03ad49
2
10
δ
= 0.5
Z
th(j-amb)
(K/W)
0.2
0.1
10
0.05
0.02
1
t
p
P
δ
=
T
−
1
10
single pulse
t
t
p
T
−
2
10
−
4
−
3
−
2
−
1
2
3
t (s)
10
10
10
10
1
10
10
10
p
Fig 4.
Transient thermal impedance from junction to solder point as a function of pulse duration
SI4410DY_3
© NXP B.
V
. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 December 2009
4 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V
GS(th)
gate-source threshold
I
D
= 250 µA; V
DS
= V
GS
; T
j
= 25 °C;
1
–
–
V
voltage
see
Figure 9
I
DSS
drain leakage current
V
DS
= 30 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 30 V; V
GS
= 0 V; T
j
= 55 °C
V
GS
= 20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -20 V; V
DS
= 0 V; T
j
= 25 °C
–
–
–
–
–
–
1
µA
µA
nA
nA
m
Ω
–
25
I
GSS
gate leakage current
–
100
100
20
–
R
DSon
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 5 A; T
j
= 25 °C;
see
Figure 10
and
11
15
V
GS
= 10 V; I
D
= 10 A; T
j
= 25 °C;
–
11
–
13.5
–
m
Ω
see
Figure 10
and
11
I
DSon
on-state drain-source
current
V
DS
≥
5 V; V
GS
= 10 V
20
A
Dynamic characteristics
Q
G(tot)
total gate charge
I
D
= 10 A; V
DS
= 15 V; V
GS
= 5 V;
T
j
= 25 °C; see
Figure 12
–
21.5
34
nC
I
D
= 10 A; V
DS
= 15 V; V
GS
= 10 V;
T
j
= 25 °C; see
Figure 12
–
–
–
–
–
–
–
–
40
8
60
–
nC
nC
nC
ns
ns
ns
ns
S
Q
GS
Q
GD
t
d(on)
t
r
gate-source charge
gate-drain charge
turn-on delay time
rise time
7
–
V
DS
= 25 V; R
L
= 25
Ω
; V
GS
= 10 V;
R
G(ext)
= 6
Ω
; T
j
= 25 °C
13.5
9
30
20
100
80
–
t
d(off)
t
f
turn-off delay time
fall time
70
30
34
g
fs
transfer conductance
V
DS
= 15 V; I
D
= 10 A; T
j
= 25 °C;
see
Figure 13
Source-drain diode
V
SD
source-drain voltage
I
S
= 2.3 A; V
GS
= 0 V; T
j
= 25 °C;
see
Figure 14
–
–
0.7
50
1.1
80
V
t
rr
reverse recovery time
I
S
= 2.3 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 25 V; T
j
= 25 °C
ns
SI4410DY_3
© NXP B.
V
. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 December 2009
5 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ad50
03ad52
50
50
I
D
10 V
5 V
3.8 V
I
D
(A)
V
> I
x R
DS
D
DSon
(A)
40
3.6 V
3.4 V
40
30
20
10
0
30
20
10
0
3.2 V
3 V
2.8 V
T =
150
°
C
V
= 2.6 V
j
GS
V
25
°
C
0
0.5
1
1.5
0
1
2
3
4
(V)
V
(V)
DS
GS
Fig 6.
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 5.
Output characteristics: drain current as a
function of drain-source voltage; typical values
03aa36
03ad54
10
-1
4
10
I
D
(A)
10
-2
10
-3
C
(pF)
C
iss
min
typ
max
3
10
10
-4
10
-5
10
-6
C
oss
C
rss
10
−
1
2
10
1
10
10
0
1
2
3
V
(V)
V
GS
(V)
DS
Fig 7.
Sub-threshold drain current as a function of
gate-source voltage
Fig 8.
Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
SI4410DY_3
© NXP B.
V
. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 December 2009
6 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa33
03ad51
2.5
V
GS(th)
(V)
0.03
3.4 V
3.6 V
3.8 V
R
T =
25
°
C
V
= 3.2 V
GS
DSon
(
Ω
)
j
2
1.5
1
max
0.02
typ
4.5 V
5 V
min
10 V
0.01
0.5
0
0
0
10
20
30
40
50
-60
0
60
120
180
I
(A)
D
T ( C)
°
j
Fig 10.
Drain-source on-state resistance as a function
of drain current; typical values
Fig 9.
Gate-source threshold voltage as a function of
junction temperature
03ad57
03ad55
2
10
V
GS
I
= 10 A
D
a
(V)
8
6
4
2
0
V
= 15 V
DD
1.5
T =
25 ºC
j
1
0.5
0
−
60
0
60
120
180
0
10
20
30
40
T (
°
C)
j
Q
(nC)
G
Fig 11.
Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig 12.
Gate-source voltage as a function of gate
charge; typical values
SI4410DY_3
© NXP B.
V
. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 December 2009
7 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ae24
03ad53
40
50
I
S
g
fs
V
> I
x R
D
V =
0 V
GS
DS
DSon
(A)
(S)
30
40
T
= 25
°
C
150
°
C
j
30
20
10
0
20
10
0
150
°
C
T =
25
°
C
j
0
0.4
0.8
1.2
1.6
0
10
20
30
40
50
V
(V)
I
(A)
SD
D
Fig 13.
Forward transconductance as a function of
drain current; typical values
Fig 14.
Source current as a function of source-drain
voltage; typical values
SI4410DY_3
© NXP B.
V
. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 December 2009
8 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package
outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8
o
0
o
0.010 0.057
0.004 0.049
0.019 0.0100
0.20
0.014 0.0075
0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT96-1
076E03
MS-012
Fig 15.
Package outline SOT96-1 (SO8)
SI4410DY_3
© NXP B.
V
. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 December 2009
9 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision
history
Table 7.
Revision history
Document ID
SI4410DY_3
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20091204
Product data sheet
–
SI4410D
Y
–
02
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
SI4410D
Y
–
02
SI4410D
Y
–
01
20010705
Product specification
–
SI4410D
Y
–
01
20010220
Product specification
–
–
SI4410DY_3
© NXP B.
V
. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 December 2009
10 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal
information
9.1 Data
sheet status
Document status
[1][2]
Product status
[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet
Qualification
Product [short] data sheet
Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
Applications
— Applications that are described herein for any of these
9.2 Definitions
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Draft
— The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Quick reference data
— The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values
— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet
— A short data sheet is an extract from a full data sheet with
the same product type number(s) and title. A short data sheet is intended for
quick reference only and should not be relied upon to contain detailed and full
information. For detailed and full information see the relevant full data sheet,
which is available on request via the local NXP Semiconductors sales office.
In case of any inconsistency or conflict with the short data sheet, the full data
sheet shall prevail.
Terms and conditions of sale
— NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3 Disclaimers
General
— Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license
— Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes
— NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control
— This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use
— NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS
— is a trademark of NXP B.V.
10. Contact information
SI4410DY_3
© NXP B.
V
. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 December 2009
11 of 12
SI4410DY
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description
. . . . . . . . . . . . . . . . . . . . . .1
Features and benefit
s
. . . . . . . . . . . . . . . . . . . . .1
Applications .
. . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data
. . . . . . . . . . . . . . . . . . . . .1
2
3
4
5
6
7
8
Pinning informatio
n
. . . . . . . . . . . . . . . . . . . . . . .2
Ordering informatio
n
. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics
. . . . . . . . . . . . . . . . . . .4
Characteristic
s
. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision histor
y
. . . . . . . . . . . . . . . . . . . . . . . . .10
9
Legal information. . . . . . . . . . . . . . . . . . . . . . .
.
1
1
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
.
1
1
Definition
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
1
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
1
9.1
9.2
9.3
9.4
10
Contact informatio
n
. . . . . . . . . . . . . . . . . . . . . .
1
1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V.
2009.
All rights reserved.
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 December 2009
Document identifier: SI4410DY_3
