onsemi-SI6463DQ

Part #onsemi-SI6463DQ
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onsemi-SI6463DQ
April 2001  
Si6463DQ  
P-Channel 2.5V Specified PowerTrench
 
MOSFET  
General Description  
Features  
This P-Channel 2.5V specified MOSFET is a rugged  
gate version of Fairchild Semiconductor’s advanced  
PowerTrench process. It has been optimized for power  
management applications with a wide range of gate  
drive voltage (2.5V – 12V).  
•
–8.8 A,
 
–20 V. R

DS(ON)

= 0.0125
Ω
@ V

GS

= –4.5 V  

DS(ON)

= 0.018
Ω
@ V

GS

= –2.5 V  
R
•
Extended V

GSS

range (
±
12V) for battery  
applications  
Applications  
•
•
Low gate charge  
•
•
•
•
Load switch  
High performance trench technology for extremely  
low R

DS(ON)  

Motor drive  
DC/DC conversion  
Power management  
•
Low profile TSSOP-8 package  
D
S
S
5
6
7
8
4
3
2
1
D
G
S
S
D
TSSOP-8  
Pin 1  
Absolute Maximum Ratings
 
T

A

=25

o

C unless otherwise noted  
Symbol  
V

DSS  

Parameter  
Drain-Source Voltage  
Ratings  
Units  
–20  
V
V
A
V

GSS  

Gate-Source Voltage  
Drain Current
 
– Continuous  
– Pulsed  
±
12  
–8.8  
I

D  

(Note 1)  
–50  
P

D  

Power Dissipation  
(Note 1a)  
(Note 1b)  
1.3  
W
0.6  
T

J

, T

STG  

Operating and Storage Junction Temperature Range  
–55 to +150  
°
C  
Thermal Characteristics  
Thermal Resistance, Junction-to-Ambient  
(Note 1a)  
(Note 1b)  
96  
R

θ
JA  

°
C/W  
208  
Package Marking and Ordering Information  
Device Marking  
Device  
Reel Size  
Tape width  
Quantity  
6463  
Si6463DQ  
13’’  
16mm  
3000 units  
Si6463DQ Rev. A(W)  
2001 Fairchild Semiconductor Corporation  

Electrical Characteristics  
T

A

= 25°C unless otherwise noted  
Symbol  
Parameter  
Test Conditions  
Min Typ Max Units  
Off Characteristics  
BV

DSS  

Drain–Source Breakdown Voltage  
–20  
V
V

GS

= 0 V, I

D

= –250
µ
A  
∆
BV
DSS  
∆
T

J  

Breakdown Voltage Temperature  
Coefficient  
–12  
I

D

= –250
µ
A, Referenced to 25
°
C  
V

DS

= –16 V,
 
V

GS

= 0 V  
mV/
°
C  
I

DSS  

Zero Gate Voltage Drain Current  
Gate–Body Leakage, Forward  
Gate–Body Leakage, Reverse  
–1  
µ
A  
nA  
nA  
I

GSSF  

I

GSSR  

V

GS

= –12 V,  
V

GS

= 12 V,  
V

DS

= 0 V  
V

DS

= 0 V  
–100  
100  
On Characteristics  
(Note 2)  
V

GS(th)  

Gate Threshold Voltage  
–0.6  
–50  
–0.8  
3.5  
–1.5  
V
V

DS

= V

GS

, I

D

= –250
µ
A  
∆
V
GS(th)  
∆
T

J  

Gate Threshold Voltage  
Temperature Coefficient  
I

D

= –250
µ
A, Referenced to 25
°
C  
mV/
°
C  
10  
14  
13  
12.5  
18  
19  
V
V

GS

= –4.5 V,
 
I

D

= –8.8 A  

GS

= –2.5 V,
 
I

D

= –7.2 A  
Static Drain–Source  
On–Resistance  
m
Ω  
R

DS(on)  

V

GS

= –4.5 V, I

D

= –8.8 A, T

J

= 125
°
C  
I

D(on)  

g

FS  

On–State Drain Current  
V

GS

= –4.5 V,  
V

DS

= –10 V,  
V

DS

= –5 V  
I

D

= –8.8 A  
A
S
Forward Transconductance  
46  
Dynamic Characteristics  
C

iss  

C

oss  

C

rss  

Input Capacitance  
5045  
1035  
549  
pF  
pF  
pF  
V

DS

= –10 V,  
f = 1.0 MHz  
V

GS

= 0 V,  
Output Capacitance  
Reverse Transfer Capacitance  
Switching Characteristics
 
(Note 2)  
t

d(on)  

t

r  

t

d(off)  

t

f  

Turn–On Delay Time  
Turn–On Rise Time  
Turn–Off Delay Time  
Turn–Off Fall Time  
Total Gate Charge  
Gate–Source Charge  
Gate–Drain Charge  
8
14  
130  
80  
41  
7
16  
25  
ns  
ns  
V

DD

= –10 V,  
V

GS

= –4.5 V,  
I

D

= –1 A,  
R

GEN

= 6
Ω  
208  
128  
66  
ns  
ns  
Q

g  

Q

gs  

Q

gd  

nC  
nC  
nC  
V

DS

= –10 V,  
I

D

= –8.8 A,  
V

GS

= –4.5 V  
11  
Drain–Source Diode Characteristics and Maximum Ratings  
I

S  

Maximum Continuous Drain–Source Diode Forward Current  
–1.2  
–1.2  
A
V
Drain–Source Diode Forward  
V

SD  

V

GS

= 0 V,
 
I

S

= –1.2 A
 
(Note 2)  
–0.6  
Voltage  
Notes:  
1.  
R

θ
JA

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface  
of the drain pins.
 
R

θ
JC

is guaranteed by design while R

θ
CA

is determined by the user’s board design.  
a) R

θ
JA

is 96
°
C/W (steady state) when mounted on a 1 inch² copper pad on FR-4.  
b) R

θ
JA

is 208
°
C/W (steady state) when mounted on a minimum copper pad on FR-4.  
2. Pulse
 
Test: Pulse Width < 300
µ
s, Duty Cycle < 2.0%  
Si6463DQ Rev. A(W)  

Typical Characteristics  
30  
2
1.8  
1.6  
1.4  
1.2  
1
V

GS

= -4.5V  
-2.5V  
25  
-3.0V  
-2.0V  
V

GS

= -2.0V  
20  
15  
-2.5V  
10  
-1.5V  
-3.0V  
-3.5V  
-4.0V  
5
0
-4.5V  
0.8  
0
0.5  
1
1.5  
0
6
12  
18  
24  
30  
-V

DS

, DRAIN TO SOURCE VOLTAGE (V)  
-I

D

, DIRAIN CURRENT (A)  
Figure 1. On-Region Characteristics.  
Figure 2. On-Resistance Variation with  
Drain Current and Gate Voltage.  
0.035  
1.5  
1.4  
1.3  
1.2  
1.1  
1
I

D

= -4.4A  
I

D

= -8.8A  
0.03  
0.025  
0.02  
V

GS

= -4.5V  
T

A

= 125

o

C  
0.015  
0.01  
T

A

= 25

o

C  
0.9  
0.8  
0.7  
0.005  
1.5  
2
2.5  
3
3.5  
4
4.5  
5
-50  
-25  
0
25  
50  
75  
100  
125  
150  
-V

GS

, GATE TO SOURCE VOLTAGE (V)  
T

J

, JUNCTION TEMPERATURE (

o

C)  
Figure 3. On-Resistance Variation with  
Temperature.  
Figure 4. On-Resistance Variation with  
Gate-to-Source Voltage.  
100  
50  
40  
30  
20  
10  
0
V

GS

= 0V  
T

A

= -55

o

C  
25

o

C  
125

o

C  
V

DS

= -5V  
10  
1
T

A

= 125

o

C  
25

o

C  
-55

o

C  
0.1  
0.01  
0.001  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
0.5  
1
1.5  
2
2.5  
-V

SD

, BODY DIODE FORWARD VOLTAGE (V)  
-V

GS

, GATE TO SOURCE VOLTAGE (V)  
Figure 5. Transfer Characteristics.  
Figure 6. Body Diode Forward Voltage Variation  
with Source Current and Temperature.  
Si6463DQ Rev. A(W)  

Typical Characteristics  
8000  
7000  
6000  
5000  
4000  
3000  
2000  
1000  
0
5
I

D

= -8.8A  
V

DS

= -5V  
f = 1 MHz  

GS

= 0 V  
-10V  
V
4
3
2
1
0
-15V  
C

ISS  

C

OSS  

C

RSS  

0
10  
20  
30  
40  
50  
0
3
6
9
12  
Q

g

, GATE CHARGE (nC)  
-V

DS

, DRAIN TO SOURCE VOLTAGE (V)  
Figure 7. Gate Charge Characteristics.  
Figure 8. Capacitance Characteristics.  
100  
10  
50  
40  
30  
20  
10  
0
µ
100  
10ms  
100ms  
s
SINGLE PULSE  
R

θ

JA

= 208°C/W  
R

DS(ON)

LIMIT  
T

A

= 25°C  
1s  
10s  
1
DC  
V

GS

= -4.5V  
SINGLE PULSE  
R

θ

JA

= 208

o

C/W  
0.1  
0.01  
T

A

= 25

o

C  
0.01  
0.1  
1
10  
100  
0.01  
0.1  
1
10  
100  
1000  
-V

DS

, DRAIN-SOURCE VOLTAGE (V)  
t

1

, TIME (sec)  
Figure 9. Maximum Safe Operating Area.  
Figure 10. Single Pulse Maximum  
Power Dissipation.  
1
D = 0.5  
R
θ

JA

(t) = r(t) + R
θ  
JA  
0.2  
R
θ

JA

= 208 °C/W  
0.1  
0.1  
0.05  
0.02  
P(pk)  
t

1  

0.01  
0.01  
t

2  

T

J

– T

A

= P * R
θ

JA

(t)  
SINGLE PULSE  
Duty Cycle, D = t

1

/ t

2  

0.001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
t

1

, TIME (sec)  
Figure 11. Transient Thermal Response Curve.  
Thermal characterization performed using the conditions described in Note 1b.  
Transient thermal response will change depending on the circuit board design.  
Si6463DQ Rev. A(W)  

TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
PACMAN™  
POP™  
PowerTrench  
QFET™  
QS™  
QT Optoelectronics™  
Quiet Series™  
SILENT SWITCHER  
SMART START™  
Star* Power™  
Stealth™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
TinyLogic™  
UHC™  
FAST  
FASTr™  
GlobalOptoisolator™  
GTO™  
HiSeC™  
ISOPLANAR™  
LittleFET™  
MicroFET™  
MICROWIRE™  
OPTOLOGIC™  
OPTOPLANAR™  
ACEx™  
Bottomless™  
CoolFET™  
CROSSVOLT
™  
DenseTrench™  
DOME™  
UltraFET  
VCX™  
EcoSPARK™  
E

2

CMOS

TM  

EnSigna

TM  

FACT™  
FACT Quiet Series™  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER  
NOTICE T
O
A
NY PRODUCTS HEREIN TO IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGN. FAIRCHILD  
DOES NO
T
A
SSUM
E
A
NY LIABILIT
Y
A
RISING OUT OF TH
E
A
PPLICATION OR USE O
F
A
NY PRODUCT  
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT  
RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOU
T
T
HE EXPRESS WRITTE
N
A
PPROVA
L
O
F FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, or (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in significant injury to the  
user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
Rev. H1