onsemi-SI6953DQ
| Part # | onsemi-SI6953DQ |
Download  | onsemi-SI6953DQ |
September 2001
Si6953DQ
Dual 20V P-Channel PowerTrench
MOSFET
General Description
Features
This P-Channel MOSFET is a rugged gate version of
Fairchild’s Semiconductor’s advanced PowerTrench
process. It has been optimized for power management
applications requiring a wide range of gate drive voltage
ratings (4.5V – 20V).
•
–1.9 A, –20 V,
R
DS(ON)
= 170
m
Ω
@ V
GS
= –10 V.
R
DS(ON)
= 320
m
Ω
@ V
GS
= –4.5V.
•
Extended V
GSS
range (
±
20V) for battery applications
•
Low gate charge
Applications
•
Load switch
•
High performance trench technology for extremely
low R
DS(ON)
•
Battery protection
•
DC/DC conversion
•
Power management
•
Low profile TSSOP-8 package
G
2
S
2
1
2
3
4
8
7
6
5
S
2
D
2
G
1
S
1
S
1
D
1
TSSOP-8
Pin 1
Absolute Maximum Ratings
T
A
=25
o
C unless otherwise noted
Symbol
V
DSS
Parameter
Drain-Source Voltage
Ratings
Units
V
–20
V
GSS
I
D
Gate-Source Voltage
Drain Current
– Continuous
– Pulsed
V
A
±
20
–1.9
–15
(Note 1)
P
D
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
1.0
0.6
W
T
J
, T
STG
Operating and Storage Junction Temperature Range
–55 to +150
°
C
Thermal Characteristic
Thermal Resistance, Junction-to-Ambient
(Note 1a)
(Note 1b)
100
125
R
θ
JA
°
C/W
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
6953
Si6953DQ
13’’
12mm
2500 units
Si6953DQ Rev. B (W)
2001 Fairchild Semiconductor Corporation
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
–20
V
V
GS
= 0 V, I
D
= –250
µ
A
–22
∆
BV
DSS
∆
T
J
Breakdown Voltage Temperature
I
D
= –250
µ
A, Referenced to 25
°
C
Coefficient
mV/
°
C
I
DSS
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
V
DS
= –20 V,
V
GS
= 0 V
–1
µ
A
nA
nA
I
GSSF
I
GSSR
V
GS
= –20 V,
V
GS
= 20 V,
V
DS
= 0 V
V
DS
= 0 V
–100
100
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
–1
–1.8
4
–3
V
V
DS
= V
GS
, I
D
= –250
µ
A
∆
V
GS(th)
∆
T
J
Gate Threshold Voltage
Temperature Coefficient
I
D
= –250
µ
A, Referenced to 25
°
C
mV/
°
C
R
DS(on)
Static Drain–Source
On–Resistance
V
GS
= –10 V,
GS
= –4.5 V,
I
D
= –1.3 A
V
GS
= –10 V, I
D
= –1.9 A, T
J
=125
°
C
I
D
= –1.9 A
96
151
134
170
320
254
m
Ω
V
I
D(on)
g
FS
On–State Drain Current
V
GS
= –10 V,
V
DS
= –5 V
–10
A
S
Forward Transconductance
V
DS
= –15 V,
I
D
= –1.9 A
4
Dynamic Characteristics
V
DS
= –10 V,
V
GS
= 0 V,
C
iss
C
oss
C
rss
Input Capacitance
218
65
pF
pF
pF
f = 1.0 MHz
Output Capacitance
Reverse Transfer Capacitance
31
Switching Characteristics
(Note 2)
V
DD
= –10V,
I
D
= –1 A,
R
GEN
= 6
Ω
t
d(on)
t
r
t
d(off)
t
f
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
6
20
25
30
15
70
ns
ns
ns
ns
ns
V
GS
= –10 V,
15
12
1.5
11
V
GS
= 0 V, I
F
= 1.5 A,
t
rr
Reverse Recovery Time
dI
F
/dt = 100A/
µ
s
V
DS
= –10V,
I
D
= –1.9 A,
Q
g
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
4
10
nC
nC
nC
V
GS
= –10 V
Q
gs
Q
gd
0.9
0.7
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
–1.25
–1.2
A
V
V
SD
Drain–Source Diode Forward
Voltage
V
GS
= 0 V,
I
S
= –1.25 A
(Note 2)
–0.8
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins.
R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user’s board design.
a)
b)
R
θ
JA
is 100
°
C/W (steady state) when mounted on a 1 inch² copper pad on FR-4.
θ
JA
is 125
°
C/W (steady state) when mounted on a minimum copper pad on FR-4.
R
2.
Pulse Test: Pulse Width < 300
µ
s, Duty Cycle < 2.0%
Si6953DQ Rev. B (W)
Typical Characteristics
12
2.4
2.2
2
V
GS
= -10V
-6.0V
V
GS
= -4.0V
9
-4.5V
1.8
1.6
1.4
1.2
1
-4.5V
-5.0V
6
3
0
-6.0V
-3.5V
-7.0V
-8.0V
-10V
-3.0V
0.8
0
1
2
3
4
5
0
3
6
-I
D
, DRAIN CURRENT (A)
9
12
-V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
1.4
1.2
1
0.55
I
D
= -1.9A
V
GS
= -10V
I
D
=-1A
0.45
0.35
0.25
0.15
0.05
T
A
= 125
o
C
0.8
0.6
T
A
= 25
o
C
-50
-25
0
25
50
75
100
125
150
2
4
6
8
10
T
J
, JUNCTION TEMPERATURE (
o
C)
-V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
10
6
T
A
= -55
o
C
25
o
C
V
GS
= 0V
V
DS
= -5V
5
4
3
2
1
0
1
T
A
= 125
o
C
125
o
C
0.1
25
o
C
0.01
-55
o
C
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1
1.5
2
2.5
3
3.5
4
4.5
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
-V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
Si6953DQ Rev. B (W)
Typical Characteristics
10
300
250
200
150
100
50
f = 1MHz
V
GS
= 0 V
I
D
= -1.9A
V
DS
= -5V
-10V
8
6
4
2
0
C
ISS
-15V
C
OSS
C
RSS
0
0
1
2
3
4
5
0
5
10
15
20
Q
g
, GATE CHARGE (nC)
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
100
10
50
40
30
20
10
0
SINGLE PULSE
R
θ
JA
= 125°C/W
100us
T
A
= 25°C
1ms
R
DS(ON)
LIMIT
10ms
100ms
1s
1
10s
DC
V
GS
= -10V
SINGLE PULSE
R
θ
JA
= 125
o
C/W
0.1
0.01
T
A
= 25
o
C
0.1
1
10
100
0.001
0.01
0.1
1
10
100
1000
-V
DS
, DRAIN-SOURCE VOLTAGE (V)
t
1
, TIME (sec)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
R
θ
JA
(t) = r(t) * R
θ
JA
R
θ
JA
=125 °C/W
0.2
0.1
0.1
P(pk)
0.05
0.02
t
1
t
2
J
– T
A
= P * R
θ
JA
(t)
Duty Cycle, D = t
1
/ t
2
0.01
0.01
T
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
Si6953DQ Rev. B (W)
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
â
SMART START™
STAR*POWER™
Stealth™
VCX™
FAST
ACEx™
Bottomless™
CoolFET™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
FASTr™
FRFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOL
T
™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenc
h
â
QFET™
EcoSPARK™
E
2
CMOS
TM
TinyLogic™
QS™
EnSigna
TM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILEN
T
S
WITCHE
R
â
FACT™
FACT Quiet Series™
UltraFE
T
â
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILIT
Y
A
RISING OUT OF THE APPLICATION OR USE O
F
A
NY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICE
S
O
R
S
YSTEM
S
W
ITHOU
T
T
H
E
E
XPRES
S
W
RITTE
N
A
PPROVA
L
O
F
F
AIRCHIL
D
S
EMICONDUCTO
R
C
ORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
