onsemi-SSP3N80A
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SSP3N80A
Advanced Power MOSFET
FEATURES
BV
DSS
= 800
V
R
DS(on)
= 4.8
W
I
D
= 3
A
Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : 25
m
A (Max.)
@ V
DS
= 800V
Low R
DS(ON)
: 3.800
W
(Typ.)
TO-220
1
2
3
1.Gate 2.
Drain 3.
Source
Absolute Maximum Ratings
Symbol
Characteristic
Drain-to-Source Voltage
Value
Units
800
V
DSS
V
O
Continuous Drain Current (T
C
=25
C
)
3
1.9
12
+
I
D
A
O
Continuous Drain Current (T
C
=100
C
)
1
I
DM
V
GS
E
AS
I
AR
Drain Current-Pulsed
O
A
V
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
_
30
2
O
1
O
240
3
mJ
A
E
AR
dv/dt
10
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
mJ
V/ns
W
1
O
2.0
100
0.8
3
O
O
Total Power Dissipation (T
C
=25
C
)
P
D
T
J
, T
STG
T
L
O
Linear Derating Factor
W/
C
Operating Junction and
– 55
to +150
300
Storage Temperature Range
Maximum Lead Temp. for Soldering
O
C
Purposes, 1/8“
from case for 5-seconds
Thermal Resistance
Symbol
Characteristic
Junction-to-Case
Case-to-Sink
Typ.
Max.
1.25
—
Units
R
q
—
0.5
—
JC
O
R
q
C
/W
CS
R
q
Junction-to-Ambient
62.5
JA
Rev. B
©1999 Fairchild Semiconductor Corporation
N-CHANNEL
POWER MOSFET
SSP3N80A
O
Electrical Characteristics
(T
C
=25
C
unless otherwise specified)
Symbol
BV
DSS
Characteristic
Min. Typ. Max.
Units
Test Condition
V
GS
=0V,I
D
=250
m
A
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
V
800 —
—
O
D
BV/
D
T
J
V
GS(th)
I
D
=250
m
A
See Fig 7
V/
C
— 1.01
—
V
DS
=5V,I
D
=250
m
A
V
GS
=30V
GS
=-30V
V
DS
=800V
V
2.0
—
—
—
3.5
Gate-Source Leakage
, Forward
Gate-Source Leakage
, Reverse
100
I
GSS
nA
V
—
— -100
—
—
—
25
I
DSS
Drain-to-Source Leakage Current
m
A
O
V
DS
=640V,T
C
=125
C
—
250
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
4
R
DS(on)
V
GS
=10V,I
D
=0.85A
O
*
—
—
W
W
4.8
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
—
—
—
—
—
—
—
—
—
—
—
V
DS
=50V,I
D
=0.85A
2.17 —
580 750
4
O
V
GS
=0V,V
DS
=25V,f =1MHz
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
75
30
40
60
100
60
35
—
60
23
pF
See Fig 5
16
V
DD
=400V,I
D
=2A,
26
R
G
=16
W
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
46
See Fig 13
4
5
OO
24
Q
g
Total Gate Charge
Gate-Source Charge
Gate-Drain(“ Miller” )
Charge
27
V
DS
=640V,V
GS
=10V,
Q
gs
Q
gd
nC
5.3
12.2
I
D
=2A
4
5
See Fig 6 & Fig 12
O
O
—
Source-Drain Diode Ratings and Characteristics
Symbol
Characteristic
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Min. Typ. Max.
Units
Test Condition
Integral reverse pn-diode
in the MOSFET
I
S
I
SM
V
SD
t
rr
—
—
—
—
—
—
3
12
1.4
—
A
1
O
O
4
O
V
—
T
J
=25
C
,I
S
=3A,V
GS
=0V
O
ns
m
C
330
T
J
=25
C
,I
F
=3A
4
Q
rr
— 1.52 —
di
F
/dt=100A/
m
s
O
Notes ;
Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
1
2
O
O
O
L=50mH, I
AS
=3A, V
DD
=50V, R
G
=27
W
, Starting T
J
=25
C
O
_
<
_
<
I
SD
3A, di/dt
100A
/
m
s, V
DD
_
BV
DSS
, Starting T
J
=25
C
3
<
O
Pulse Test : Pulse Width = 250
m
s, Duty Cycle
_
2%
<
4
O
Essentially Independent of Operating Temperature
5
O
N
–
C
HANNEL
POWER MOSFET
SSP3N80A
Fig 1.
Output Characteristics
Fig 2.
Transfer Characteristics
1
1
10
V
GS
10
Top :
1 5 V
1 0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
0
10
Bottom : 4.5
V
150
o
C
0
10
25
o
C
-1
10
@
N
otes :
1. V
= 0 V
GS
2. V
= 50 V
DS
@
N
otes :
1. 250 s Pulse Test
–
5
5
o
C
µ
3. 250
s Pulse Test
µ
2. T = 2
5
o
C
C
-2
-1
10
10
-1
0
1
2
4
6
8
10
10
10
10
V
G
S
,
G
ate-Source Voltage
[V]
V
D
S
,
D
rain-Source Voltage
[V]
Fig 3.
On-Resistance vs. Drain Current
Fig 4.
Source-Drain Diode Forward Voltage
20
15
10
5
1
10
V =
1
0 V
GS
0
10
-1
10
V =
2
0 V
GS
@
N
otes :
1. V
= 0 V
GS
150
o
C
2. 250
s Pulse Test
µ
@
N
ote : T
= 25
o
C
J
25
o
C
-2
0
10
0
3
6
9
12
0.2
0.4
V
0.6
0.8
1.0
1.2
I ,
D
rain Current [A]
SD
,
S
ource-Drain Voltage
[V]
D
Fig 5.
Capacitance vs. Drain-Source Voltage
Fig 6.
Gate Charge vs. Gate-Source Voltage
1000
800
600
400
200
C
iss
=
C
gs
+
C
gd
(
C
ds
=
s
horte
d
)
V
DS
=
1
60 V
DS
=
4
00 V
=
6
40 V
C
oss
=
C
ds
+ C
gd
10
C
rss
= C
gd
V
C
iss
V
DS
5
0
@
N
otes :
1. V
GS
= 0 V
2. f = 1 MHz
C
oss
C
rss
@
N
otes : I = 3.0 A
D
0
0
10
1
0
5
10
15
20
25
30
10
Q ,
T
otal Gate Charge
[nC]
V
D
S
,
D
rain-Source Voltage [V]
G
N
–
C
HANNEL
POWER MOSFET
SSP3N80A
Fig 7.
Breakdown Voltage vs. Temperature
Fig 8.
On-Resistance vs. Temperature
1.2
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.1
1.0
@
N
otes :
1. V
GS
=
1
0 V
2. I = 1.5 A
D
0.9
0.8
@
N
otes :
1.
V
GS
= 0 V
2. I = 250
A
µ
D
-75
-50
-25
0
25
50
75
100
125
150
175
-75
-50
-25
0
25
50
75
100
125
150
175
T ,
J
unction Temperature [
o
C
]
T ,
J
unction Temperature [
o
C
]
J
J
Fig 9.
Max. Safe Operating Area
F
4
ig 10.
Max. Drain Current vs. Case Temperature
2
10
Operation in This Area
is Limited by
R
DS(on)
1
3
2
1
0
10
10
s
µ
100
s
µ
1
m
s
10 ms
DC
0
10
@
N
otes :
1. T = 2
5
o
-1
10
C
C
2. T = 15
0
o
C
J
3. Single Pulse
-2
10
1
2
3
25
50
75
100
125
150
10
10
10
T ,
C
ase Temperature
[
o
C
]
V
D
S
,
D
rain-Source Voltage
[V]
c
Fig 11.
Thermal Response
10
0
10
–
1
10
–
2
D=0.5
0.2
@
Notes
:
1.
Z
θ
J
C
(t)=1.25
o
C/W Max.
2. Duty Factor, D=t /t
2
3. T
J
M
-T
C
=P
D
M
*Z
θ
J
C
(t)
1
0.1
0.05
0.02
0.01
P
DM
single pulse
t
1
t
2
10
–
5
10
–
4
10
–
3
10
–
2
10
–
1
10
0
10
1
t
1
, Square Wave Pulse Duration
[sec]
N
–
C
HANNEL
POWER MOSFET
SSP3N80A
Fig 12.
Gate Charge Test Circuit
& Waveform
* Current Regulator *
V
GS
Same Type
as DUT
50K
¥Ø
Q
g
12V
200nF
10V
300nF
V
DS
Q
gs
Q
gd
V
GS
DUT
R
2
3mA
R
1
Charge
Current Sampling (
I
G
)
Current Sampling (
I
D
)
Resistor
Resistor
Fig 13.
Resistive Switching Test Circuit
& Waveforms
R
L
V
out
V
in
V
out
90%
V
DD
( 0.5 rated V
DS
)
R
G
DUT
10%
V
in
10V
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
Fig 14.
Unclamped Inductive Switching Test Circuit
& Waveforms
BV
DSS
1
2
2
L
L
I
D
—-
——————–
E
AS
=
L
L
I
AS
BV
DSS
— V
DD
V
DS
BV
DSS
I
AS
Vary t
p
to obtain
required peak I
D
R
G
I
D
(t)
V
DD
C
DUT
V
DS
(t)
V
DD
10V
t
p
t
p
Time
N
–
C
HANNEL
POWER MOSFET
SSP3N80A
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
& Waveforms
+
DUT
V
DS
—
I
S
L
Driver
V
GS
Same Type
as DUT
R
G
V
DD
V
GS
• dv/dt controlled by
“R •
G
• I
S
controlled by Duty Factor
“D”
Gate Pulse Width
————————–
V
GS
D =
Gate Pulse Period
10V
( Driver )
I
FM
, Body Diode Forward Current
I
S
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
f
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
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Y
,
F
UNCTION OR DESIGN. FAIRCHILD
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systems which, (a) are intended for surgical implant into
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failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
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be reasonably expected to cause the failure of the life
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effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
