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STTFS010N10MCL  
MOSFE
T
,
N
-Channel,  
Shielded Gate,  
POWERTRENCH

)  

100
V
,
5
0 A, 10.6 m
W
 
General Description  
This N
−
Channel POWETRENCH
 
MOSFET is produced using  
ON Semiconductor’s
 
advanced POWERTRENCH
 
process that  
®
®
ELECTRICAL CONNECTION  
incorporates Shielded Gate technology. This process has been  
optimized to minimize on
−
state resistance and yet maintain superior  
switching performance with best in class soft body diode.  
S
S
D
D
D
Features  
S
•
Shielded Gate MOSFET Technology  
G
D
•
Max r  
•
Max r  
= 10.6 m
W
at V
 
= 10
V
, I
 
=
1
5 A  
GS D  
DS(on)  
= 15.9 m
W
at V
 
= 4.5
V
, I
 
=
1
2 A  
DS(on)  
GS  
D
N-Channel MOSFET  
•
50% Lower Qrr than Other MOSFET Suppliers  
•
Lowers Switching Noise/EMI  
•
MSL1 Robust Package Design  
•
100% UIL Tested  
8 7 6 5  
D D D D  
•
RoHS Compliant  
Pin 1  
Applications  
1 2 3 4  
Top  
G S S S  
Bottom  
Pin 1  
•
Primary DC
−
DC MOSFET  
•
Synchronous Rectifier in DC
−
DC and AC
−
DC  
•
Motor Drive  
WDFN8  
(3.3×3.3, 0.65 P)  
CASE 511DY  
MARKING DIAGRAM  
XXXX  
AYWW  
XXXX  
= Device Code  
A
= Assembly Location  
Y
=
Y
ear Code  
WW  
= Work Week Code  
ORDERING INFORMATION  
See detailed ordering and shipping information on page

of this data sheet.  
©
Semiconductor Components Industries, LLC, 2018  
1
Publication Order Number:  
September, 2018
−
Rev. 1  
STTFS010N10MCL/D  

STTFS010N10MCL  
MOSFET MAXIMUM RATINGS
(T =
 
25
°
C unless otherwise noted)  
A
Symbol  
Parameter  
Ratings  
Unit  
V
V
DS  
V
GS  
Drain to Source Voltage  
Gate to Source Voltage  
100  
20  
V
I
Drain Current  
−
Continuous  
T
T
= 25
°
C  
50  
A
D
C
C
−
Continuous  
−
Continuous  
−
Pulsed  
= 100
°
C  
32  
10.7  
T =
 
25
°
C  
A
250  
E
AS  
Single Pulse Avalanche Energy  
Power Dissipation  
73  
mJ  
W
P
T
= 25
°
C  
C
52  
D
Power Dissipation  
T =
 
25
°
C  
A
2.3  
T , T  
Operating and Storage Junction
T
e
mperature Range  
−
55 to +150  
°
C  
J
STG  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
THERMAL CHARACTERISTICS  
Symbol  
Parameter  
Thermal Resistance, Junction to Case  
Thermal Resistance, Junction to Ambient  
Ratings  
2.4  
Unit  
°
C/W  
R
q
JC  
R
53  
q
JA  
PACKAGE MARKING AND ORDERING INFORMATION  
Device Marking  
Device  
Package  
Reel Size  
Tape Width  
12 mm  
Quantity  
1500 Units  
S10L  
STTFS010N10MCL  
WDFN8 (3.3×3.3)  
7’’  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted)  
J
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
OFF CHARACTERISTICS  
BV  
Drain to Source Breakdown Voltage
 
I =
 
250
m
A, V  
= 0 V  
GS  
100  
V
DSS  
D
Breakdown Voltage  
T
e
mperature Coefficient  
I
D
= 250
m
A, referenced to 25
°
C  
64  
mV/
°
C  
D
BV

DSS  

D
T

J  

I
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
V
V
= 80
V
, V
 
= 0 V  
1
m
A  
DSS  
GSS  
DS  
GS  
I
=
20
V
, V
 
= 0 V  
100  
nA  
GS  
DS  
ON CHARACTERISTICS  
V
Gate to Source Threshold Voltage  
V
I
= V
 
, I
 
= 85
m
A  
1.0  
1.5  
3.0  
V
GS(th)  
GS  
DS  
D
Gate to Source Threshold Voltage  
T
e
mperature Coefficient  
= 85
m
A, referenced to 25
°
C  
−
5.3  
mV/
°
C  
D
V

GS(th)  

D
T

J  

D
r
Static Drain to Source On  
Resistance  
V
V
V
= 10 V, I
 
= 15 A  
9.1  
10.6  
15.9  
17.8  
m
W  
DS(on)  
GS  
GS  
GS  
D
= 4.5
V
, I
 
= 12 A  
13.5  
15.3  
D
= 10 V, I
 
= 15 A,  
D
T =
 
125
°
C  
J
g
FS  
Forward Transconductance  
V
DS  
= 5
V
, I
 
= 15 A  
54  
S
D
DYNAMIC CHARACTERISTICS  
C
Input Capacitance  
Output Capacitance  
V
= 50
V
, V
 
= 0 V,  
1530  
625  
10  
2150  
875  
18  
pF  
ISS  
DS  
GS  
f = 1 MHz  
C
OSS  
C
RSS  
Reverse Transfer Capacitance  
Gate Resistance  
R
0.1  
1.1  
2.1  
W
G
2

STTFS010N10MCL  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted) (continued)  
J
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
SWITCHING CHARACTERISTICS  
t
Turn
*
On Delay Time  
Rise Time  
Turn
*
Off Delay Time  
Fall Time  
V
V
= 50 V, I
 
= 15 A
,
 
9
3
19  
10  
45  
10  
30  
ns  
d(ON)  
DD  
D
= 10
V
, R  
= 6
W  
GS  
GEN  
t
rd(ON)  
t
28  
5
d(OFF)  
t
f
Q
Q
T
o
tal Gate Charge  
T
o
tal Gate Charge  
Gate to Source Charge  
Gate to Drain “Miller” Charge  
Output Charge  
V
= 0V to 10 V  
= 0V to 4.5 V  
22  
10  
4
nC  
g
g
GS  
V
GS  
Q
V
I
= 50 V  
gs  
gd  
DD  
D
= 15 A  
Q
3
Q
V
DD  
= 50
V
, V
 
= 0 V  
41  
19  
nC  
V
oss  
GS  
Q
T
o
tal Gate Charge Sync  
V
DS  
= 0
V
, V
 
= 0
t
o 10 V  
GS  
sync  
DRAIN
−
SOURCE DIODE CHARACTERISTICS  
V
SD  
Source to Drain Diode Forward  
Voltage  
V
V
= 0
V
, I
 
= 2 A  
0.7  
0.8  
22  
35  
17  
79  
1.2  
1.3  
36  
GS  
S
= 0
V
, I
 
=
1
5 A  
GS  
S
t
rr  
Reverse Recovery Time  
Reverse Recovery Charge  
Reverse Recovery Time  
Reverse Recovery Charge  
I =
 
8 A, di/dt = 300 A/
m
s  
F
ns  
nC  
ns  
Q
56  
rr  
t
rr  
I =
 
8 A, di/dt = 1000 A/
m
s  
F
30  
Q
126  
nC  
rr  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
NOTES:  
2
1. R  
is determined with the device mounted on a 1 in
 
pad 2 oz copper pad on a 1.5
×
1.5 in. board of FR
−
4 material. R  
is determined  
CA  
q
q
JA  
by the user’s board design.  
a) 53
°
C/W when mounted on  
b) 125
°
C/W when mounted on  
a minimum pad of 2 oz copper.  
2
a 1 in
 
pad of 2 oz copper.  
2. Pulse
 
T
e
st: Pulse Width < 300
m
s, Duty cycle < 2.0%.  
3. E
 
of 73 mJ is based on starting T
 
= 25
_
C; L = 3 mH, I
 
= 7 A, V
 
= 100
V
, V
 
=
1
0
V
.
1
00% test at L = 0.5 mH, I
 
= 13 A.  
AS  
J
AS  
DD  
GS  
AS  
4. Pulsed
 
I

SOA graph for more details.  
D
5. Computed
 
continuous current limited to Max Junction
T
e
mperature only, actual continuous current will be limited by thermal  
& electro
−
mechanical application board design.  
3
 

STTFS010N10MCL  
TYPICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted)  
J
150  
120  
90  
60  
30  
0
4
V

GS

= 10 V  
V

GS

= 8 V  
V

GS

= 3 V  
V

GS

= 6 V  
V

GS

= 3.5 V  
3
2
1
0
V

GS

= 4.5 V  
V

GS

= 6 V  
V

GS

= 4.5 V  
V

GS

= 3.5 V  
V

GS

= 10 V  
V

GS

= 8 V  
V

GS

= 3 V  
PULSE DURATION = 80
m
s  
DUTY CYCLE = 0.5% MAX  
PULSE DURATION = 80
m
s  
DUTY CYCLE = 0.5% MAX  
0
1
2
3
4
5
0
30  
60  
90  
120  
150  
I

D

,
DRAIN CURRENT (A)  
V

DS

,
DRAIN TO SOURCE VOLTAGE (V)  
Figure 1. On Region Characteristics  
Figure 2. Normalized On
−
Resistance  
vs. Drain Current and Gate Voltage  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
80  
PULSE DURATION = 80
m
s  
DUTY CYCLE = 0.5% MAX  
I

D

= 15 A  
V

GS

= 10 V  
I

D

= 15 A  
60  
40  
20  
0
T

J

= 125

o  

C
T

J

= 25

o  

C
−
75
−
50
−
25  
0
25 50 75
 
100 125 150  
2
3
4
5
6
7
8
9
10  
T

J

,
JUNCTION TEMPERATURE

o

(
C
)  
V

GS

,
GATE TO SOURCE VOLTAGE (V)  
Figure 3. Normalized On Resistance  
vs. Junction Temperature  
Figure 4. On-Resistance  
vs. Gate to Source Voltage  
150  
100  
150  
120  
90  
60  
30  
0
PULSE DURATION = 80
m
s  
DUTY CYCLE = 0.5% MAX  
V

GS

= 0 V  
V

DS

= 5 V  
10  
1
T

J

= 150

o  

C
T

J

= 25

o

C  
0.1  
T

J

= 150

o  

C
0.01  
T

J

= 25

o  

C
T

J

=
−
55

o

C  
T

J

=
−
55

o

C  
0.001  
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1
2
3
4
5
6
7
V

GS

, GATE TO SOURCE VOLTAGE (V)  
V

SD

, BODY DIODE FORWARD VOLTAGE (V)  
Figure 5. Transfer Characteristics  
Figure 6. Source to Drain Diode  
Forward Voltage vs. Source Current  
4

STTFS010N10MCL  
TYPICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted)  
J
10  
8
10000  
I

D

= 15 A  
C

iss  

1000  
100  
10  
V

DD

= 25 V  
C

oss  

6
V

DD

= 50 V  
4
C

rss  

V

DD

= 75 V  
2
f = 1 MHz  

GS

= 0 V  
V
0
1
0
5
10  
15  
20  
25  
0.1  
1
10  
100  
V

DS

, DRAIN TO SOURCE VOLTAGE (V)  
Q

g

, GATE CHARGE (nC)  
Figure 7. Gate Charge Characteristics  
Figure 8. Capacitance vs. Drain  
to Source Voltage  
100  
10  
1
60  
45  
30  
15  
0
R

q
JC

= 2.4

o

C/W  
V

GS

= 10 V  
T

J

= 25

o

C  
V

GS

= 4.5 V  
T

J

= 100

o  

C
T

J

= 125

o  

C
0.001 0.01  
0.1  
1
10  
100  
25  
50  
75  
100  
125  
150  
T

C

,
CASE TEMPERATURE

o

(
C
)  
t

AV

, TIME IN AVALANCHE (ms)  
Figure 9. Unclamped Inductive  
Switching Capability  
Figure 10. Maximum Continuous Drain  
Current vs. Case Temperature  
500  
100  
10000  
1000  
100  
SINGLE PULSE  

q
JC

= 2.
4

o

C/W  
R
T

C

= 2
5

o

C  
10
m
s  
10  
1
THIS AREA IS  
LIMITED BY r

DS(on)  

100
m
s  
SINGLE PULSE  
T

J

= MAX RATED  
R

q
JC

= 2.
4

o

C/W  

C

= 2
5

o

C  
1 ms  
CURVE BENT TO  
MEASURED DATA  
10 ms  
T
100 ms/DC  
0.1  
10  
10

−
5  

10

−
4  

10

−
3  

t, PULSE WIDTH (sec)  
10

−
2  

10

−
1  

1
0.1  
1
10  
100  
700  
V

DS

, DRAIN to SOURCE VOLTAGE (V)  
Figure 11. Forward Bias Safe Operating Area  
Figure 12. Single Pulse Maximum  
Power Dissipation  
5

STTFS010N10MCL  
TYPICAL CHARACTERISTICS
(continued)  
2
1
DUTY CYCLE
−
DESCENDING ORDER  
D = 0.5  
0.2  
0.1  
P
DM  
0.1  
0.01  
0.05  
0.02  
0.01  
t
1
t
2
NOTES:  
SINGLE PULSE  
Z
R
(t) = r(t) x R  
o
q
JC  
q
JC  
= 2.4
 
C/W  
q
JC  
Peak T
 
= P  
x Z
 
(t) + T  
J
DM  
q
JC
C  
Duty Cycle, D = t
 
/ t  
1
2
0.001  
10

−
5  

10

−
4  

10

−
3  

10

−
2  

10

−
1  

1
t, RECTANGULAR PULSE DURATION (sec)  
Figure 13. Junction
−
to
−
Case Transient Thermal Response Curve  
6

STTFS010N10MCL  
PACKAGE DIMENSIONS  
WDFN8 3.3×3.3, 0.65P  
CASE 511DY  
ISSUE A  
0.20 C  
2X  
B
D
0.10  
D2  
C A B  
8
A
e/2  
L1  
M
8
5
5
G
E3  
E2  
E
E1  
0.10  
C A B  
L
K
2X  
0.20 C  
G1  
PIN 1  
AREA  
1
4
4
1
b
(8X)  
e
0.10  
0.05  
C A B  
C
BOTTOM VIEW  
TOP VIEW  
SIDE VIEW  
NOTES:  
1. CONTROLLING
 
DIMENSION: MILLIMETERS  
2. DIMENSIONS
 
D1 & E1 DO NOT INCLUDE MOLD FLASH  
PROTRUSIONS NOR GATE BURRS.  
D1  
A
(4X)  
c
Ө
0.10 C  
A1  
(8X)  
MILLIMETERS  
DIM  
0.10 C  
MIN NOM
 
MAX  
C
A
A1  
b
0.70 0.75 0.80  
0.00 0.05  
0.23 0.33 0.43  
0.15 0.20 0.25  
3.20 3.30 3.40  
2.95 3.13 3.30  
SEATING PLANE  
−
END VIEW  
c
3.46  
2.38  
D
D1  
D2  
E
E1  
E2  
E3  
e
1.98  
2.20 2.40  
8
5
3.20 3.30 3.40  
2.80 3.00 3.15  
1.40 1.60 1.80  
0.15 0.25 0.40  
0.65 BSC  
0.78 (4X)  
0.75  
2.51  
4.10  
G
G1  
K
L
L1  
M
0.30 0.43 0.55  
0.25 0.35 0.45  
0.55 0.75 0.95  
0.35 0.52 0.65  
0.06 0.15 0.30  
0.57  
1.00  
1.35  
0
1.50 1.60  
12  
0.60 (3X)  
0.65  
−
Ө
1
4
0.43 (8X)  
RECOMMENDED LAND PATTERN  
7

STTFS010N10MCL  
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States  
and/or other countries.  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent  
coverage may be accessed at

. ON Semiconductor reserves the right to make changes without further notice to any products herein.  
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,  
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer  
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not  
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification  
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized  
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and  
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such  
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This  
literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
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STTFS010N10MCL/D