PIP-PSP06N40

PSA06N40  

PSP06N40  

400V N-ch Planar MOSFET  

General Features  

BV

DSS  

400V  

R

DS(ON),Typ.  

I

D  

‹

‹

‹

‹

RoHS Compliant  

0.78Ω  

6.0A  

R

DS(ON),typ.

=0.78 Ω@V

GS

=10V  

Low Gate Charge Minimize Switching Loss  

Fast Recovery Body Diode  

Applications  

‹

‹

‹

Adaptor  

Charger  

SMPS Standby Power  

Ordering Information  

Part Number  

PSP06N40  

PSA06N40  

Package  

Brand  

TO-220  

TO-220F  

Absolute Maximum Ratings  

T

C

=25  

unless otherwise specified  

Symbol  

V

DSS  

V

GSS  

I

D  

Parameter  

PSA06N40 PSP06N40  

Unit  

Drain-to-Source Voltage  

Gate-to-Source Voltage  

Continuous Drain Current  

Pulsed Drain Current at V

GS

=10V  

Single Pulse Avalanche Energy  

Power Dissipation  

400  

±30  

6.0  

24  

V

A

I

DM  

E

AS  

200  

mJ  

W

25  

75  

P

D  

0.2  

0.60  

Derating Factor above 25  

W/  

Maximum Temperature for Soldering  

Leads at 0.063in (1.6mm) from Case for 10  

seconds, Package Body for 10 seconds  

T

L  

T

PAK  

300  

260  

T

J

& T

STG  

Operating and Storage Temperature Range  

-55 to 150  

Caution: Stresses greater than those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device.  

Thermal Characteristics  

Symbol  

Parameter  

PSA06N40  

PSP06N40  

Unit  

R

θJC  

Thermal Resistance, Junction-to-Case  

5.0  

1.67  

/W  

R

θJA  

Thermal Resistance, Junction-to-Ambient  

100  

62  

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI

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Page 1 / 9  

Rev. C .2019  

PSA06N40  

PSP06N40  

Electrical Characteristics  

OFF Characteristics  

T

J

=25  

unless otherwise specified  

Symbol  

Parameter  

Min. Typ. Max. Unit  

Test Conditions  

BV

DSS  

Drain-to-Source Breakdown Voltage  

400  

—  

—  

V

V

GS

=0V, I

D

=250uA  

—  

—  

—  

—  

—  

—  

—  

—  

1

V

DS

=400V, V

GS

=0V  

I

DSS  

Drain-to-Source Leakage Current  

Gate-to-Source Leakage Current  

uA  

V

DS

=320V, V

GS

=0V,  

T

J

=125  

100  

+0.1  

-0.1  

V

GS

=+30V, V

DS

=0V  

V

GS

=-30V, V

DS

=0V  

I

GSS  

uA  

ON Characteristics  

Symbol  

T

J

=25  

unless otherwise specified  

Parameter  

Min. Typ. Max. Unit  

Test Conditions  

Static Drain-to-Source  

On-Resistance  

R

DS(ON)  

V

GS(TH)  

gfs  

—  

2.0  

—  

0.78  

—  

1.0  

4.0  

—  

Ω

V

S

V

GS

=10V, I

D

=3.0A  

V

DS

=V

GS

, I

D

=250uA  

VDS=15V,ID=3.0A  

Gate Threshold Voltage  

Forward Transconductance  

5.0  

Dynamic Characteristics  

Essentially independent of operating temperature  

Symbol  

Parameter  

Min. Typ. Max. Unit  

Test Conditions  

C

iss  

Input Capacitance  

—  

—  

—  

—  

—  

—  

500  

8.0  

65  

—  

—  

—  

—  

—  

—  

V

GS

=0V,  

V

DS

=25V,  

f=1.0MH

Z  

C

rss  

C

oss  

Q

g  

Reverse Transfer Capacitance  

Output Capacitance  

pF  

nC  

Total Gate Charge  

14.5  

3.0  

6.5  

V

DD

=200V,  

I

D

=6A, V

GS

=0 to 10V  

Q

gs  

Q

gd  

Gate-to-Source Charge  

Gate-to-Drain (Miller) Charge  

Resistive Switching Characteristics  

Essentially independent of operating temperature  

Symbol  

Parameter  

Min. Typ. Max. Unit  

Test Conditions  

td

(ON)  

Turn-on Delay Time  

—  

—  

—  

—  

8

—  

—  

—  

—  

V

DD

=200V,  

I

D

=6A,  

V

GS

=10V  

Rg=9.1 Ω  

t

rise  

td

(OFF)  

fall  

Rise Time  

10  

25  

15  

ns  

Turn-Off Delay Time  

Fall Time  

t

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI

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Rev. C .2019  

PSA06N40  

PSP06N40  

Source-Drain Body Diode Characteristics  

T

J

=25  

unless otherwise specified  

Symbol  

Parameter  

Continuous Source Current

[2]  

Pulsed Source Current

[2]  

Min  

—  

Typ. Max. Unit  

Test Conditions  

I

SD  

—  

—  

6.0  

24  

Integral pn-diode  

in MOSFET  

A

I

SM  

—  

V

SD  

Diode Forward Voltage  

Reverse Recovery Time  

Reverse Recovery Charge  

—  

—  

—  

—  

1.5  

—  

V

I

S

=6A, V

GS

=0V  

t

rr  

300  

850  

ns  

nC  

V

GS

=0V  

I =6A,

 

di/dt=100A/µs  

F

Q

rr  

—  

Note:  

[1] T

J

=+25 to

 

+150  

[2] Pulse width≤380ꢀs; duty cycle≤2%.  

©2019 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP  

Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI

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Rev. C .2019  

PSA06N40  

PSP06N40  

Typical Characteristics  

Figure 1.

 

Maximun Forward Bias Safe  

Figure 2.

 

Maximun Power Dissipation  

Operating Area  

vs Case

 

T

e

mperature  

Figure 3.

 

Maximum Continuous Drain Current  

vs Case

T

e

mperature  

Figure 4.

 

Typical Output Characteristics  

Figure 5.

 

Maximum Effective Thermal Impendance , Junction to Case  

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI

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Rev. C .2019  

PSA06N40  

PSP06N40  

Typical Characteristics

(Cont.)  

Figure 6.

 

MaximunPeak Current Capability  

Figure 7.

 

Typical Transfer Characteristics  

Figure .8

 

Typical Drain to Source ON Resistance vs  

Gate Voltage and Drain Current  

Figure 10.

 

Typical Drian to Source on Resistance  

vs Junction

T

e

mperature  

Figure 9.

 

Typical Drain to Source ON  

Resistance vs

 

Drain Current  

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI

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Rev. C .2019  

PSA06N40  

PSP06N40  

Typical Characteristics

(Cont.)  

Figure 11.

 

Typical Theshold Voltage vs Junction  

T

e

mperature  

Figure 1.2

 

Typical Breakdown Voltage  

vs Junction

 

T

e

mperature  

Figure 13.

 

Typical Capacitance vs Drain to  

Source Voltage  

Figure 14.

 

Typical Gate Charge vs Gate to  

Source Voltage  

Figure 15.

 

Typical Body Diode Transfer  

Characteristics  

Figure 16.

 

Unclamped Inductive Switching  

Capability  

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PSA06N40  

PSP06N40  

Test Circuits and

Waveforms  

Fig. 1.1 Peak Diode Recovery dv/dt Test Circuit  

Fig. 1.2 Peak Diode Recovery dv/dt Waveforms  

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Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI

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Rev. C .2019  

PSA06N40  

PSP06N40  

Test Circuits and

Waveforms

(Cont.)  

©2019 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP  

Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI

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PSA06N40  

PSP06N40  

Disclaimers:  

Perfect Intelligent Power Semiconductor Co., Ltd (PIP) reserves the right to make changes without notice in order to improve  

reliability, function or design and to discontinue any product or service without notice. Customers should obtain the latest  

relevant information before orders and should verify that such information is current and complete. All products are sold subject  

to PIP’s terms and conditions supplied at the time of order acknowledgement.  

Perfect Intelligent Power Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at the time  

of sale, Testing, reliability and quality control are used to the extent PIP deems necessary to support this warrantee. Except where  

agreed upon by contractual agreement, testing of all parameters of each product is not necessarily performed.  

Perfect Intelligent Power Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit  

designs described herein. Customers are responsible for their products and applications using PIP’s components. To minimize  

risk, customers must provide adequate design and operating safeguards.  

Perfect Intelligent Power Semiconductor Co., Ltd does not warrant or convey any license either expressed or implied under its  

patent rights, nor the rights of others. Reproduction of information in PIP’s data sheets or data books is permissible only if  

reproduction is without modification or alteration. Reproduction of this information with any alteration is an unfair and deceptive  

business practice. Perfect Intelligent Power Semiconductor Co., Ltd is not responsible or liable for such altered documentation.  

Resale of PIP’s products with statements different from or beyond the parameters stated by Perfect Intelligent Power  

Semiconductor Co., Ltd for that product or service voids all express or implied warrantees for the associated PIP’s product or  

service and is unfair and deceptive business practice. Perfect Intelligent Power Semiconductor Co., Ltd is not responsible or liable  

for any such statements.  

Life Support

Policy:  

Perfect Intelligent Power Semiconductor Co., Ltd’s products are not authorized for use as critical components in life support  

devices or systems without the expressed written approval of Perfect Intelligent Power Semiconductor Co., Ltd.  

As used herein:  

1. Life support devices or systems are devices or systems which:  

a. are intended for surgical implant into the human body,  

b. support or sustain life,  

c. whose failure to perform when properly used in accordance with instructions  

for used provided in the labeling, can be reasonably expected to result in significant  

injury to the user.  

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably  

expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.  

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