PIP-SPTA60R130E
| Part # | PIP-SPTA60R130E |
| Download | PIP-SPTA60R130E |
SPTA60R130E
600V N-ch Multi-Epi Super-Junction MOSFET
BV
DSS
R
DS(ON),typ.
0.11Ω
I
D
General Features
@
TjMAX
‹
‹
‹
‹
‹
Multi-Epi Process
650V
25A
Proprietary New Super-Junction
T
e
chnology
R
DS(ON),typ.
=0.11Ω@V
GS
=10V
Low Gate Charge Minimize Switching Loss
Fast Recovery Body Diode
Applications
‹
‹
‹
Adaptor
Charger
SMPS Standby Power
G
D
S
TO-220F
Package No to Scale
Ordering Information
Part Number
Package
Brand
SPTA60R130E
TO-220F
Absolute Maximum Ratings
T
C
=25
unless otherwise specified
Value
Symbol
Parameter
Drain-to-Source Voltage
Unit
SPTA60R130E
V
DSS
V
GSS
600
±20
±30
25
15
75
Gate source voltage (static)
V
A
Gate source voltage (dynamic) AC (f>1Hz)
Continuous Drain Current @ T
C
= 25ºC
Continuous Drain Current @ T
C
= 100ºC
Pulsed Drain Current at V
GS
=10V
[1]
Reverse diode dv/dt
I
D
I
DM
dv/dt
d
iF
/dt
15
50
V/ns
A/us
Maximum diode commutation speed
E
AS
P
D
Single Pulse Avalanche Energy
[2]
898
35
mJ
W
Power Dissipation
T
J
& T
STG
Operating and Storage Temperature Range
-55 to 150
Caution: Stresses greater than those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device.
Thermal Characteristics
Max. Value
Symbol
Parameter
Unit
SPTA60R130E
R
θJC
R
θJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
3.57
/W
100
©2019 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP
Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI
P
.
Page 1 / 6
Rev. D .2019
SPTA60R130E
Electrical Characteristics
OFF Characteristics
T
J
=25
unless otherwise specified
Symbol
Parameter
Min. Typ. Max. Unit
Test Conditions
BV
DSS
Drain-to-Source Breakdown Voltage
600
—
—
V
V
GS
=0V, I
D
=250uA
I
DSS
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
—
—
—
—
—
—
1
uA
V
DS
=600V, V
GS
=0V
V
GS
=+30V, V
DS
=0V
V
GS
=-30V, V
DS
=0V
+100
-100
I
GSS
nA
ON Characteristics
Symbol
T
J
=25
unless otherwise specified
Parameter
Min. Typ. Max. Unit
Test Conditions
Static Drain-to-Source
On-Resistance
[3]
R
DS(ON)
V
GS(TH)
gfs
—
2.5
—
0.11 0.15
Ω
V
S
V
GS
=10V, I
D
=10.0A
V
DS
=V
GS
, I
D
=250uA
Gate Threshold Voltage
—
4.5
—
Forward Transconductance
[3]
10.5
V
DS
=10V,I =5.0A
D
Dynamic Characteristics
Essentially independent of operating temperature
Symbol
Parameter
Min. Typ. Max. Unit
Test Conditions
V
GS
=0V,
V
DS
=50V,
f=10KH
Z
C
iss
Input Capacitance
—
—
—
—
—
—
—
1966
208
5.8
48
—
—
—
—
—
—
—
pF
Ω
C
oss
Output Capacitance
R
G
Gate resistance (Intrinsic)
Total Gate Charge
f = 1.0MHz Open Drain
Q
g
Q
gs
Gate-to-Source Charge
Gate-to-Drain (Miller) Charge
Gate plateau voltage
8.5
8.5
6.3
nC
V
V
DD
=400V,
I
D
=11.3A, V
GS
=0 to 13V
Q
gd
V
plateau
Resistive Switching Characteristics
Essentially independent of operating temperature
Symbol
Parameter
Min. Typ. Max. Unit
Test Conditions
td
(ON)
Turn-on Delay Time
—
—
—
—
38
28
67
21
—
—
—
—
V
DD
=400V,
I
D
=11.3A,
V
GS
=10V
Rg=1.7Ω
t
rise
td
(OFF)
fall
Rise Time
pF
Turn-Off Delay Time
Fall Time
t
©2019 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP
Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI
P
.
Page 2 / 6
Rev. D .2019
SPTA60R130E
Source-Drain Body Diode Characteristics
T
J
=25
unless otherwise specified
Symbol
Parameter
Continuous Source Current
[2]
Pulsed Source Current
[2]
Min
—
Typ. Max. Unit
Test Conditions
Maximum Ratings
I
S
=3.8A, V
GS
=0V
I
SD
—
—
25
75
A
I
SM
—
V
SD
Diode Forward Voltage
—
—
—
—
—
1.2
—
V
ns
uC
A
t
rr
Reverse Recovery Time
Reverse Recovery Charge
PeakReverseRecoveryCurrent
293
3.9
V
R
=400V,V
GS
=0V
Q
rr
—
I
F
=3.2A, di/dt =100A/μs
I
rrm
26.7
—
Note:
[1] Repetitive Rating: Pulse width limited by maximum junction temperature
[2] L = 10mH, VDD= 80
V
, Starting T = 25°C
[3] Pulse
T
est: Pulse width
380us, Duty Cycle
2%
J
©2019 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP
Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI
P
.
Page 3 / 6
Rev. D .2019
SPTA60R130E
Test Circuits and
Waveforms
Fig. 1.1 Peak Diode Recovery dv/dt Test Circuit
Fig. 1.2 Peak Diode Recovery dv/dt Waveforms
©2019 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP
Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI
P
.
Page 4 / 6
Rev. D .2019
SPTA60R130E
Test Circuits and
Waveforms
(Cont.)
©2019 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP
Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI
P
.
Page 5 / 6
Rev. D .2019
SPTA60R130E
Disclaimers:
Perfect Intelligent Power Semiconductor Co., Ltd (PIP) reserves the right to make changes without notice in order to improve
reliability, function or design and to discontinue any product or service without notice. Customers should obtain the latest
relevant information before orders and should verify that such information is current and complete. All products are sold subject
to PIP’s terms and conditions supplied at the time of order acknowledgement.
Perfect Intelligent Power Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at the time
of sale, Testing, reliability and quality control are used to the extent PIP deems necessary to support this warrantee. Except where
agreed upon by contractual agreement, testing of all parameters of each product is not necessarily performed.
Perfect Intelligent Power Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit
designs described herein. Customers are responsible for their products and applications using PIP’s components. To minimize
risk, customers must provide adequate design and operating safeguards.
Perfect Intelligent Power Semiconductor Co., Ltd does not warrant or convey any license either expressed or implied under its
patent rights, nor the rights of others. Reproduction of information in PIP’s data sheets or data books is permissible only if
reproduction is without modification or alteration. Reproduction of this information with any alteration is an unfair and deceptive
business practice. Perfect Intelligent Power Semiconductor Co., Ltd is not responsible or liable for such altered documentation.
Resale of PIP’s products with statements different from or beyond the parameters stated by Perfect Intelligent Power
Semiconductor Co., Ltd for that product or service voids all express or implied warrantees for the associated PIP’s product or
service and is unfair and deceptive business practice. Perfect Intelligent Power Semiconductor Co., Ltd is not responsible or liable
for any such statements.
Life Support
Policy:
Perfect Intelligent Power Semiconductor Co., Ltd’s products are not authorized for use as critical components in life support
devices or systems without the expressed written approval of Perfect Intelligent Power Semiconductor Co., Ltd.
As used herein:
1. Life support devices or systems are devices or systems which:
a. are intended for surgical implant into the human body,
b. support or sustain life,
c. whose failure to perform when properly used in accordance with instructions
for used provided in the labeling, can be reasonably expected to result in significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
©2019 Perfect Intelligent Power Semiconductor Co., Ltd. All rights reserved. Information and data in this document are owned by PIP
Semiconductors and may not be edited, reproduced, or redistributed in any way without written consent from PI
P
.
Page 6 / 6
Rev. D .2019
