TC58BVG0S3HTA00 Chipset

TC58BVG0S3HTA00（MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS/1 GBIT (128M x 8 BIT) CMOS NAND E²PROM)

Introduction

The TC58BVG0S3HTA00 is a 3.3V 1Gbit (1,107,296,256 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E²PROM). It is organized as (2048 + 64) bytes x 64 pages x 1024 blocks, with a 2112-byte static register facilitating data transfer between the register and the memory cell array in 2112-byte increments. Erase operation occurs in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes x 64 pages).

This serial-type memory device utilizes I/O pins for address, data input/output, and command inputs. Erase and Program operations are automatically executed, making it suitable for applications like solid-state file storage, voice recording, and high-density non-volatile memory data storage in systems like still cameras.

The TC58BVG0S3HTA00 includes on-chip ECC logic, capable of internally correcting 8-bit read errors for each 528 bytes.

Features

Organization:x8

• Memory cell array:2112 x 64Kx 8
• Register:2112x 8
• Page size: 2112 bytes
• Block size: (128K + 4K) bytes

Modes

• Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, ECC Status Read

Mode control

• Serial input/output
• Command control

Number of valid blocks

• Min 1004 blocks
• Max 1024 blocks

Power supply

• Vcc= 2.7V to 3.6V

Access time

• Cell array to register:40 μS typ.
• Read Cycle Time:25 ns min (CL=50pF)

Program/Erase time

• Auto Page Program:330 μs/page typ.
• Auto Block Erase:2.5 ms/block typ.

Operating current

• Read (25 ns cycle):30 mA max
• Program (avg.):30 mA max
• Erase (avg.):30 mA max
• Standby:50 μA max

Package

• TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)

8bit ECC for each 528Bytes is implemented on a chip.

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