Qorvo-UJ3C120080K3S
| Part # | Qorvo-UJ3C120080K3S |
Download  | Qorvo-UJ3C120080K3S |
1200V-80m
W
SiC FET
Rev. F, November 2022
DATASHEET
Description
This SiC FET device is based on a unique ‘cascode’ circuit
configuration, in which a normally-on SiC JFET is co-packaged with a Si
MOSFET to produce a normally-off SiC FET device. The device’s
standard gate-drive characteristics allows for a true “drop-in
replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si superjunction
devices. Available in the TO-247-3L package, this device exhibits ultra-
low gate charge and exceptional reverse recovery characteristics,
making it ideal for switching inductive loads, and any application
requiring standard gate drive.
UJ3C120080K3S
CASE
CASE
D (2)
Features
w
Typical on-resistance R
DS(on),typ
of 80m
W
w
Maximum operating temperature of 175°C
w
Excellent reverse recovery
G (1)
w
Low gate charge
w
Low intrinsic capacitance
1
2
3
w
ESD protected: HBM class 2 and CDM class C3
S (3)
Typical applications
Part Number
Package
Marking
w
EV charging
w
PV inverters
UJ3C120080K3S
TO-247-3L
UJ3C120080K3S
w
Switch mode power supplies
w
Power factor correction modules
w
Motor drives
w
Induction heating
Datasheet: UJ3C120080K3S
Rev. F, November 2022
1
Maximum Ratings
Parameter
Test Conditions
Symbol
V
DS
V
GS
Value
1200
-25 to +25
33
Units
V
V
Drain-source voltage
Gate-source voltage
DC
T
C
= 25°C
A
Continuous drain current
1
I
D
T
C
= 100°C
T
C
= 25°C
L=15mH, I
AS
=2.8A
T
C
= 25°C
24
77
58.5
254.2
175
A
A
mJ
W
°C
°C
Pulsed drain current
2
I
DM
E
AS
P
tot
T
J,max
T
J
, T
STG
Single pulsed avalanche energy
3
Power dissipation
Maximum junction temperature
Operating and storage temperature
-55 to 175
Max. lead temperature for soldering,
1/8” from case for 5 seconds
T
L
250
°C
1. Limited
by T
J,max
2. Pulse
width t
p
limited by T
J,max
3. Starting
T
J
= 25°C
Thermal Characteristics
Value
Typ
Parameter
Symbol
R
q
JC
Test Conditions
Units
Min
Max
Thermal resistance, junction-to-case
0.45
0.59
°C/W
Datasheet: UJ3C120080K3S
Rev. F, November 2022
2
Electrical Characteristics
(T
J
= +25°C unless otherwise specified)
Typical Performance – Static
Value
Typ
Parameter
Symbol
BV
DS
Test Conditions
Units
V
Min
Max
75
V
GS
=0V, I
D
=1mA
Drain-source breakdown voltage
1200
V
DS
=1200V,
V
GS
=0V, T
J
=25°C
10
50
6
I
DSS
Total drain leakage current
Total gate leakage current
m
A
m
A
V
DS
=1200V,
V
GS
=0V, T
J
=175°C
V
DS
=0V, T
J
=25°C,
V
GS
=-20V / +20V
I
GSS
20
V
GS
=12V, I
D
=20A,
T
J
=25°C
80
100
V
GS
=12V, I
D
=20A,
T
J
=125°C
V
GS
=12V, I
D
=20A,
T
J
=175°C
R
DS(on)
Drain-source on-resistance
m
W
130
172
V
DS
=5V, I
D
=10mA
f=1MHz, open drain
Gate threshold voltage
Gate resistance
V
G(th)
R
G
4
5
6
V
4.5
W
Typical Performance – Reverse Diode
Value
Typ
Parameter
Symbol
Test Conditions
Units
Min
Max
33
Diode continuous forward current
1
Diode pulse current
2
T
C
=25°C
T
C
=25°C
I
S
A
A
I
S,pulse
77
V
GS
=0V, I
S
=10A,
T
J
=25°C
1.5
2
2
V
FSD
Forward voltage
V
V
GS
=0V, I
S
=10A,
T
J
=175°C
V
DS
=800V, I
S
=20A,
V
GS
=0V, R
G_EXT
=10
W
di/dt=2200A/
m
s,
T
J
=150°C
Reverse recovery charge
Reverse recovery time
Q
rr
t
rr
180
30
nC
ns
Datasheet: UJ3C120080K3S
Rev. F, November 2022
3
Typical Performance – Dynamic
Value
Typ
Parameter
Symbol
Test Conditions
Units
pF
Min
Max
Input capacitance
C
iss
C
oss
C
rss
1500
100
2.1
V
DS
=100V, V
GS
=0V
f=100kHz
Output capacitance
Reverse transfer capacitance
V
DS
=0V to 800V,
V
GS
=0V
Effective output capacitance, energy
related
C
oss(er)
C
oss(tr)
59
pF
V
DS
=0V to 800V,
V
GS
=0V
Effective output capacitance, time
related
136
pF
C
OSS
stored energy
V
DS
=800V, V
GS
=0V
E
oss
Q
G
19
51
11
19
22
m
J
Total gate charge
Gate-drain charge
Gate-source charge
Turn-on delay time
V
DS
=800V, I
D
=20A,
V
GS
= -5V to15V
Q
GD
Q
GS
t
d(on)
nC
ns
V
DS
=800V, I
D
=20A, Gate
Driver =-5V to +15V,
Turn-on R
G,EXT
=1
W
,
Turn-off R
G,EXT
=20
W
Inductive Load,
Rise time
t
r
t
d(off)
t
f
14
61
Turn-off delay time
Fall time
14
Turn-on energy
Turn-off energy
Total switching energy
E
ON
E
OFF
E
TOTAL
260
108
368
FWD: UJ2D1215T
T
J
=150°C
m
J
Datasheet: UJ3C120080K3S
Rev. F, November 2022
4
Typical Performance Diagrams
60
50
40
30
20
10
0
60
50
40
30
20
10
0
Vgs = 15V
Vgs = 8V
Vgs = 15V
Vgs = 8V
Vgs = 7V
Vgs = 6.5V
Vgs = 6V
Vgs = 7.5V
Vgs = 7V
Vgs = 6.5V
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Drain-Source Voltage, V
DS
(V)
Drain-Source Voltage, V
DS
(V)
Figure 1. Typical output characteristics at T
J
= – 55°C,
Figure 2. Typical output characteristics at T
J
= 25°C,
tp < 250
m
s
tp < 250
m
s
60
2.5
2.0
1.5
1.0
0.5
0.0
Vgs = 15V
Vgs = 8V
Vgs = 7V
Vgs = 6V
Vgs = 5.5V
Vgs = 5V
50
40
30
20
10
0
-75 -50 -25
0
25 50 75
100 125 150 175
0
1
2
3
4
5
6
7
8
9
10
Junction Temperature, T
J
(°C)
Drain-Source Voltage, V
DS
(V)
Figure 3. Typical output characteristics at T
J
= 175°C,
tp < 250
m
s
Figure 4. Normalized on-resistance vs. temperature
at V
GS
= 12V and I
D
= 20A
Datasheet: UJ3C120080K3S
Rev. F, November 2022
5
300
250
200
150
100
50
60
50
40
30
20
10
0
Tj = -55°C
Tj = 25°C
Tj = 175°C
Tj = 175°C
Tj = 25°C
Tj = – 55°C
0
0
10
20
30
40
50
60
0
1
2
3
4
5
6
7
8
9
10
Drain Current, I
D
(A)
Gate-Source Voltage, V
GS
(V)
Figure 5. Typical drain-source on-resistances at V
GS
12V
=
Figure 6. Typical transfer characteristics at V
DS
= 5V
6
5
4
3
2
1
0
20
15
10
5
0
-5
0
10
20
30
40
50
60
-100
-50
0
50
100
150
200
Junction Temperature, T
J
(°C)
Gate Charge, Q
G
(nC)
Figure 7. Threshold voltage vs. junction temperature
at V
DS
= 5V and I
D
= 10mA
Figure 8. Typical gate charge at V
DS
= 800V and I
D
=
20A
Datasheet: UJ3C120080K3S
Rev. F, November 2022
6
0
-5
0
-5
Vgs = – 5V
Vgs = 0V
Vgs = 5V
Vgs = 8V
Vgs = -5V
Vgs = 0V
Vgs = 5V
Vgs = 8V
-10
-15
-20
-25
-30
-10
-15
-20
-25
-30
-4
-3
-2
-1
0
-4
-3
-2
-1
0
Drain-Source Voltage, V
DS
(V)
Drain-Source Voltage, V
DS
(V)
Figure 9. 3rd quadrant characteristics at T
J
= -55°C
Figure 10. 3rd quadrant characteristics at T
J
= 25°C
0
-5
40
30
20
10
0
-10
-15
Vgs = – 5V
Vgs = 0V
Vgs = 5V
Vgs = 8V
-20
-25
-30
-4
-3
-2
-1
0
0
200
400
600
800 1000
1200
Drain-Source Voltage, V
DS
(V)
Drain-Source Voltage, V
DS
(V)
Figure 11. 3rd quadrant characteristics at T
J
= 175°C
Figure 12. Typical stored energy in C
OSS
at V
GS
= 0V
Datasheet: UJ3C120080K3S
Rev. F, November 2022
7
10,000
1,000
100
10
35
30
25
20
15
10
5
C
iss
C
oss
C
rss
1
0
0
200 400 600 800
1000 1200
Drain-Source Voltage, V
DS
(V)
-75 -50 -25
0
25 50 75
100 125 150 175
Case Temperature, T
C
(°C)
Figure 13. Typical capacitances at f = 100kHz and V
GS
= 0V
Figure 14. DC drain current derating
300
250
200
150
100
50
1
0.1
D = 0.5
D = 0.3
D = 0.1
D = 0.05
D = 0.02
D = 0.01
Single Pulse
0.01
0
0.001
-75 -50 -25
0
25 50 75
100 125 150 175
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01
Pulse Time, t
p
(s)
Case Temperature, T
C
(°C)
Figure 15. Total power dissipation
Figure 16. Maximum transient thermal impedance
Datasheet: UJ3C120080K3S
Rev. F, November 2022
8
100
10
1
900
800
700
600
500
400
300
200
100
0
V
DS
= 800V, V
GS
= -5V/15V
R
G_ON
= 1
W
, R
G_OFF
= 20
W
FWD: UJ2D1215T
T
J
= 150°C
1
m
s
10
m
s
Etot
Eon
Eoff
100
m
s
1ms
DC
10ms
0.1
0
5
10
15
20
25
30
35
1
10
100
1000
Drain-Source Voltage, V
DS
(V)
Drain Current, I
D
(A)
Figure 17. Safe operation area at T
C
= 25°C, D = 0,
Parameter t
p
Figure 18. Clamped inductive
switching energy vs.
drain current at T
J
= 150°C
500
400
300
300
250
200
150
200
100
0
V
DS
= 800V, V
GS
= -5V/15V
I
D
= 20A, T
J
= 150°C
FWD:UJ2D1215T
100
50
0
V
DS
= 800V, V
GS
= -5V/15V
I
D
= 20A, T
J
= 150°C
FWD: UJ2D1215T
0
20
40
60
80
100
0
5
10
15
20
Total External R
G
,
RG,EXT_ON
(
W
)
Total External R
G
,
RG,EXT_OFF
(
W
)
Figure 19. Clamped inductive
switching turn-on
energy vs. R
G,EXT_ON
Figure 20. Clamped inductive
switching turn-off
energy vs. R
G,EXT_OFF
Datasheet: UJ3C120080K3S
Rev. F, November 2022
9
500
400
300
200
100
0
V
GS
= -5V/15V, R
G_ON
= 1
W
,
R
G_OFF
= 20
W
FWD: UJ2D1215T
Etot
Eon
Eoff
0
25
50
75 100
125 150 175
Junction Temperature, T
J
(°C)
Figure 21. Clamped inductive switching energy vs.
junction temperature at V
DS
= 800V and I
D
= 20A
Applications Information
SiC FETs are enhancement-mode power switches formed by a high-voltage SiC depletion-mode JFET and a low-voltage silicon MOSFET
connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This
combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low
on-resistance (R
DS(on)
), output capacitance (C
oss
), gate charge (Q
G
), and reverse recovery charge (Q
rr
) leading to low conduction and switching
losses. The SiC FETs also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode.
Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high
dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum
A snubber circuit with a small R
(G)
, or gate resistor, provides better EMI suppression with higher efficiency compared to using a high R
(G)
value.
There is no extra gate delay time when using the snubber circuitry, and a small R
(G)
will better control both the turn-off V
(DS)
peak spike and
ringing duration, while a high R
(G)
will damp the peak spike but result in a longer delay time. In addition, the total switching loss when using a
snubber circuit is less than using high R
(G)
, while greatly reducing E
(OFF)
from mid-to-full load range with only a small increase in E
(ON)
. Efficiency
will therefore improve with higher load current. For more information on how a snubber circuit will improve overall system performance, visit
Datasheet: UJ3C120080K3S
Rev. F, November 2022
10
Important notice
The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein
and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is
subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo
products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent
rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such
information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN,
AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED
BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing,
Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other
applications where a failure would reasonably be expected to cause severe personal injury or death.
Datasheet: UJ3C120080K3S
Rev. F, November 2022
11
