RENESAS-F1956NBGI8
| Part # | RENESAS-F1956NBGI8 |
Download  | RENESAS-F1956NBGI8 |
F1956
Datasheet
7-Bit 0.25dB Wideband Digital Step Attenuator
1 to 6000 MHz
D
ESCRIPTION
F
EATURES
This document describes the specification for the
F1956 Digital Step Attenuator.
The F1956 is part of
Renesas’
Glitch-Free
TM
family of DSAs optimized for the
demanding requirements of Base Station (BTS) radio
cards and numerous other non-BTS applications.
This
device is offered in compact 5 x 5 mm 32-pin package
with 50
Ω
input and output impedance for ease of
integration into the radio or RF system.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Serial and 7-bit Parallel Interface
31.75dB Range
0.25dB steps
Glitch-Free
TM
: low transient overshoot
500ns settling time
Ultra linear > 64dBm IIP3
Low Insertion Loss < 1.7dB at 4GHz
Attenuation error < ±0.2dB at 4GHz
Bi-directional RF use
C
OMPETITIVE
A
DVANTAGE
3.3V or 5V Supply
1.8V or 3.3V control logic
Low Current Consumption: 350
μ
A typical
-40°C to +105°C operating temperature
5 x 5 mm thin 32-QFN package
The F1956 offers very high reliability due to its
construction from a monolithic silicon die in a QFN
package. The
insertion loss is very low with minimal
distortion. Additionally
the device is designed to have
extremely accurate attenuations levels.
These
accurate attenuation level improves system SNR
and/or ACLR by ensuring system gain is as close to
targeted level as possible.
Also, the very fast settling
time in parallel mode is ideal for fast switching
systems. Finally,
the device is
Glitch-Free
TM
with less
than 2dB of ringing across the attenuation range in
stark contrast to competing DSAs that glitch as much
as 10dB during MSB state changes.
F
UNCTIONAL
B
LOCK
D
IAGRAM
RF
1
RF
2
Lowest insertion loss for best SNR
Glitch-Free
TM
technology to protect PA or
ADC during transitions between attenuation
states.
Bias
Decoder
SPI
Extremely accurate attenuation levels
Ultra low distortion
V
MODE
LE
D[6:0] A[2:0]
CLK DATA
MSL1 and 2000V HBM ESD
Part# Details
O
RDERING
I
NFORMATION
Freq Range
Part#
IL
Resolution /
Range (dB)
Control
Pinout
Tape &
Reel
(MHz)
(dB)
PE43702
PE43701
Parallel &
Serial
F1950 150
– 4000
0.25 / 31.75
1.3
F1956NBGI8
Serial
Only
F1951 100
– 4000
0.50 / 31.5
F1952 100
– 4000
0.50 / 15.5
F1953 400
– 4000
0.50 / 31.5
1.2
0.9
1.3
HMC305
HMC305
Green
Serial
Only
Parallel &
Serial
PE4302
DAT-31R5
PE43705,
1.4 PE43712,
RFSA3715
Parallel &
Serial
F1956 1
– 6000
0.25 / 31.75
Parallel &
Serial
PE4312
1.6
F1912 1
– 4000
0.50 / 31.5
PE4302
© 2021 Renesas Electronics Corporation
1
February 23, 2021
F1956 Datasheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Parameter
Symbol
Min
Max
+5.5
Units
VDD to GND
V
DD
-0.3
V
Min (V
DD
0.3, 3.9)
+
D[6:0], DATA, CLK, LE, A0, A1, A2, V
MODE
VCNTL
V
RF
-0.3
-0.3
V
V
RF1, RF2
+0.3
Maximum Input Power applied
to RF1 or RF2 (>100 MHz)
P
RF
+34
dBm
Operating Case Temperature
Continuous Power Dissipation
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (soldering, 10s)
105
1.5
°C
W
TJ
max
T
ST
+150
+150
+260
°C
°C
°C
-65
T
LEAD
Electrostatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
1500
(Class 1C)
V
ESDHBM
V
ESDCDM
V
V
500
(Class C2)
ESD Voltage – CDM (Per JESD22-C101F)
Stresses above those listed above may cause permanent damage to the device. Functional operation of the device at
these or any other conditions above those indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD C
AUTION
This product features proprietary protection circuitry. However, it may be damaged if subjected to high energy ESD.
Please use proper ESD precautions when handling to avoid damage or loss of performance
.
P
ACKAGE
T
HERMAL AND
M
OISTURE
C
HARACTERISTICS
θ
JA
(Junction – Ambient)
40°C/W
4°C/W
θ
JC
(Junction – Case) [The Case is defined as the exposed paddle]
Moisture Sensitivity Rating (Per J-STD-020)
MSL1
© 2021 Renesas Electronics Corporation
2
February 23, 2021
F1956 Datasheet
F1956 R
ECOMMENDED
O
PERATING
C
ONDITIONS
Parameter
Supply Voltage(s)
Symbol
V
DD
Conditions
Min
3.00
-40
1
Typ
Max
Units
V
5.25
+105
6000
Operating Temperature Range
Frequency Range
T
CASE
F
RF
Case Temperature
°C
MHz
See
Figure 1
RF CW Input Power
P
CW
RF1 or RF2
dBm
RF1 Port, V
DD
= 3.3V,
T
CASE
= 85
°
C,
F
RF
> 500MHz,
WCDMA, 3GPP,
Downlink, 64 DPCH,
Chip rate =3.84MSPS,
Avg. Pin = +22dBm
RF Peak Input Power
P
peak
1%
28.9
30.7
32.3
33.2
0.1%
dBm
0.01%
0.001%
Single-Ended
Single-Ended
RF Source Impedance
RF Load Impedance
Z
RFI
50
50
Ω
Ω
Z
RFO
32
28
24
20
16
12
8
4
0
0.01
0.10
1.00
10.00
100.00
1000.00
Frequenc
y
(
MHz)
Figure 1. Maximum Operating RF input power vs Input Frequency
© 2021 Renesas Electronics Corporation
3
February 23, 2021
F1956 Datasheet
F1956 S
PECIFICATION
Specifications apply at V
DD
= +3.3V, T
CASE
= +25°C, F
RF
= 2GHz, 0.25dB steps unless otherwise noted.
Minimum
Attenuation D[6:0] = [0000000], Maximum Attenuation D[6:0] = [1111111], EVKit losses are de-embedded unless
otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
CLK, LE, DATA, D[6:0],
A0, A1, A2, V
MODE
Logic Input High
V
IH
3.0V
≤ V
DD
≤ 3.6
V
1.17
2
V
DD
3.6
V
V
3.6V < V
DD
1.17
1
CLK, LE, DATA, D[6:0],
A0, A1, A2, V
MODE
Logic Input Low
V
IL
0.63
Logic Current
I
IH,
I
IL
I
DD
Individual Pins
-40
+20
800
μA
μA
dB
Supply Current
Attenuation Range
350
31.75
0.25
0.50
1.00
ATT
RNG
No missing codes
F
RF
≤
4.5GHz
F
RF
≤
6.5GHz
F
RF
≤
8.5GHz
Minimum Gain Step
DSA Settling time
LSB
dB
Max to Min Attenuation to
settle to within 0.5dB of final
value
0.9
1.8
τ
SET
µ
s
Min to Max Attenuation to
settle to within 0.5dB of final
value
Measured at RF ports with
2.5ns rise time, 0 to 3.3V
control pulse
Video Feedthrough
RF1, RF2 ports
VID
FT
10
mV
pp
dBm
Maximum spurious level on
any RF port
4
Spur
MAX
Spur Freq ~ 2.2MHz
-140
Serial Clock Speed
F
CLK
A
SPI 3 wire bus
SPI 3 wire bus
SPI 3 wire bus
25
MHz
ns
Parallel to Serial Setup
Serial Data Hold Time
100
10
B
ns
SPI 3 wire bus
LE Delay
C
Time from final serial clock
rising edge
10
ns
Maximum Switching Rate
SW
RATE
25
kHz
Specification Notes:
Note 1:
Note 2:
Note 3.
Items in min/max columns in
bold italics
are guaranteed by Test.
Items in min/max columns that are not bold/italics are guaranteed by Design Characterization.
The input 0.1dB compression point is used as a linearity figure of merit.
The recommended maximum input power is specified as the
lesser of the two values from RF CW Power (Figure 1) and the RF Average Power (Recommended Operating Conditions Table).
Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2MHz.
Note 4:
© 2021 Renesas Electronics Corporation
4
February 23, 2021
F1956 Datasheet
F1956 S
PECIFICATION
(
CONTINUED
)
Specifications apply at V
DD
= +3.3V, T
CASE
= +25°C, F
RF
= 2GHz, 0.25dB steps unless otherwise noted.
Minimum
Attenuation D[6:0] = [0000000], Maximum Attenuation D[6:0] = [1111111], EVKit losses are de-embedded unless
otherwise noted.
Parameter
Symbol
Conditions
1MHz < F
RF
≤ 2
GHz
2GHz < F
RF
≤ 3
GHz
3GHz < F
RF
≤ 4
GHz
4GHz < F
RF
≤ 5
GHz
5GHz < F
RF
≤ 6
GHz
F
RF
= 1GHz
Min
Typ
1.3
1.3
1.6
2.1
2.6
12
Max
1.8
1.9
Units
Insertion Loss
IL
2.2
dB
2.6
3.0
F
RF
= 2GHz
25
Relative Phase
(Amin vs. Amax)
ΦΔ
deg
F
RF
= 4GHz
55
F
RF
= 6GHz
90
Step Error
(Differential Non-Linearity)
Max error between adjacent
steps
DNL
INL
0.10
0.1
0.19
+0.5
+0.5
dB
dB
Max Error for state 19.75dB,
FRF = 2GHz
-0.4
-0.8
Absolute Attenuation Error
(Integral Non-Linearity)
Max Error, over all states
F
RF
= 2GHz
1MHz < F
RF
≤ 2
GHz
2GHz < F
RF
≤ 4
GHz
4GHz < F
RF
≤ 6
GHz
1MHz < F
RF
≤ 2
GHz
2GHz < F
RF
≤ 4
GHz
4GHz < F
RF
≤ 6
GHz
20
20
14
18
16
11
15
15
7
Input Return Loss
Output Return Loss
S
11
dB
dB
14
12
7
S
22
P
IN
= +10dBm per tone
50MHz Tone Separation
Attn =
0.00dB
Attn = 15.75dB
Attn = 31.75dB
64
64
64
dBm
Attn = 0.00dB
P
IN
= +22dBm per tone
1MHz Tone Separation
Input IP3
IIP3
F
RF
= 0.7GHz
F
RF
= 1.8GHz
60
60
60
60
63.4
63.4
64.1
63.3
34.5
dBm
dBm
F
RF
= 2.2GHz
F
RF
= 2.6GHz
Input 0.1dB Compression
3
P
0.1dB
F
RF
= 2GHz, Attn = 10dB
Specification Notes:
Note 1:
Note 2:
Note 3.
Items in min/max columns in
bold italics
are guaranteed by Test.
Items in min/max columns that are not bold/italics are guaranteed by Design Characterization.
The input 0.1dB compression point is used as a linearity figure of merit.
The recommended maximum input power is specified as the
lesser of the two values from RF CW Power (Figure 1) and the RF Average Power (Recommended Operating Conditions Table).
Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2MHz.
Note 4:
© 2021 Renesas Electronics Corporation
5
February 23, 2021
F1956 Datasheet
P
ROGRAMMING
O
PTIONS
F1956 can be programmed using either the parallel or serial interface; selectable via V
MODE
(pin 3).
Serial
mode is selected by floating V
MODE
or pulling V
MODE
to a logic high and parallel mode is selected by setting
V
MODE
to logic low.
S
ERIAL
C
ONTROL
M
ODE
F1956 Serial mode is selected by floating V
MODE
(pin 3) or pulling it to logic high.
The serial interface is a
16-bit shift register made up of two words.
The first 8-bit word is the Attenuation word, which controls the
DSA state.
The second word is the address word, which uses only 3 of 8-bits that must match the hard wired
A0-A2 programming in order to change the DSA state.
If no external connections are made to A0 – A2 then
internally they will default to 000 due to internal pull down resistors.
If these 3 external preset address bits
are not matched with the SPI loaded address bits then the current attenuator state will remain unchanged.
This allows up to 8 serial-controlled devices to be used on a single board, which share a common DATA, CLK
and LE
.
When serial programming is used, all the parallel control input pins 26 – 32 can be left open or grounded.
If a
pin is grounded then an additional 25µA will be drawn from the voltage supply per pin.
Set to either Logic High or Low
Set to Logic Low
MSB (Last In)
Q15 Q14 Q13 Q12 Q11 Q10
LSB (First In)
Q9
A1
Q8
A0
Q7
D7
Q6
D6
Q5
D5
Q4
D4
Q3
D3
Q2
D2
Q1
D1
Q0
D0
A7
A6
A5
A4
A3
A2
8-Bit Address Word
8-Bit Attenuation Word
Figure 2. Two 8-bit words are comprised of 16bit serial in, parallel out shift register
Table 1. Truth Table for the Serial Address Word
A7
(MSB)
Address
Setting
A6
A5
A4
A3
A2
A1
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
000
001
010
011
100
101
110
111
© 2021 Renesas Electronics Corporation
6
February 23, 2021
F1956 Datasheet
Table 2. Truth Table for the Serial Control Word
D0
(LSB)
Attenuation
D7
D6
D5
D4
D3
D2
D1
(dB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0.25
0.5
1
2
4
8
16
31.75
S
ERIAL
M
ODE
D
EFAULT
C
ONDITION
When the device is first powered up it will default to the
Maximum Attenuation
setting as described below:
Note that for the F1956 in all cases logic high (1) has the attenuation stepped IN, while logic low (0) has the
attenuation stepped OUT.
MSB (Last In)
LSB (First In)
Q15 Q14 Q13 Q12 Q11 Q10
Q9
A1
0
Q8
A0
0
Q7
D7
0
Q6
D6
1
Q5
D5
1
Q4
D4
1
Q3
D3
1
Q2
D2
1
Q1
D1
1
Q0
D0
1
A7
X
A6
X
A5
X
A4
X
A3
X
A2
0
8-Bit Address Word
8-Bit Attenuation Word
Figure 3. Default register settings set for max attenuation and 000 Address Word
R
EGISTER
T
IMING
D
IAGRAM
: (N
OTE THE
T
IMING
S
PEC
I
NTERVALS IN
B
LUE
)
With serial control, the F1956 can be programmed via the serial port on the rising edge of Latch Enable (LE)
which loads the last 8 DATA line bits [formatted LSB (D0) first] resident in the SHIFT register followed by the
Address Word into the ACTIVE register.
© 2021 Renesas Electronics Corporation
7
February 23, 2021
F1956 Datasheet
Reinsert
Figure 4. Serial Timing Diagram
Note – When Latch enable is high, the shift register is disabled and DATA is NOT continuously clocked into the
shift register which minimizes noise.
It is recommended that Latch enable be left high when the device is not
being programmed.
Table 3. Serial Mode Timing Table
Interval
Symbol
Min
Spec
Max
Spec
Description
Units
Parallel to Serial Setup Time – From rising edge
of Vmode to rising edge of CLK for D5
100
10
ns
ns
t
ps
t
p
Clock high pulse width
LE Setup Time – From the rising edge of CLK
pulse for D0 to LE rising edge minus half the
clock period.
10
ns
t
cls
LE pulse width
30
10
ns
ns
t
lew
t
dst
Data Setup Time – From the starting edge of
Data bit to rising edge of CLK
Data Hold Time – From rising edge of CLK to
falling edge of the Data bit.
10
ns
t
dht
P
ARALLEL
C
ONTROL
M
ODE
For the F1956 the user has the option of running in one of two parallel modes.
Direct Parallel Mode or
Latched Parallel Mode.
Direct Parallel Mode:
Direct Parallel Mode is selected when V
MODE
is a logic low and LE is a logic high.
In this mode the device will
immediately react to any voltage changes to the parallel control pins [pins 26 – 32].
Use direct parallel mode
for the fastest settling time.
© 2021 Renesas Electronics Corporation
8
February 23, 2021
F1956 Datasheet
Latched Parallel Mode:
Latched Parallel Mode is selected when V
MODE
is logic low and LE is toggled from logic low to high.
To utilize
Latched Parallel Mode:
•
Set V
MODE
is logic low.
•
Set LE to logic low.
•
Adjust pins [26, 27, 28, 29, 30, 31, 32] to the desired attenuation setting. (Note the device will not
react to these pins while LE is a logic low).
•
Pull LE to a logic high.
The device will then transition to the attenuation settings reflected by pins
D6 – D0.
•
IF LE is pulled to a logic low then the attenuator will not change state.
Latched Parallel Mode implies a default state for when the device is first powered up with V
MODE
set for logic
low and LE logic low.
In this case the default setting is MAXIMUM Attenuation.
Table 4. Truth Table for the Parallel Control Word
Attenuation
D6
D5
D4
D3
D2
D1
D0
(dB)
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0.25
0.5
1
2
4
8
16
31.75
Figure 5. Latched Parallel Mode Timing Diagram
© 2021 Renesas Electronics Corporation
9
February 23, 2021
F1956 Datasheet
Table 5. Latched Parallel Mode Timing
Interval
Symbol
Min
Max
Spec
Description
Units
Spec
100
10
Serial to Parallel Mode Setup Time
Parallel Data
Hold Time
ns
ns
ns
ns
t
sps
t
pdh
t
le
t
pds
LE minimum pulse width
Parallel Data Setup Time
10
10
T
YPICAL
O
PERATING
C
ONDITIONS
(TOC)
Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.
1. V
DD
= +3.30V
2. T
CASE
= +25°C
3. 50
MHz Tone Space
4. Serial
Control
5. P
IN
= 0dBm
6. RF1
is the input port
7. Attenuation
Setting = 0dB
8. EVKit
losses (traces and connectors) are fully de-embedded
© 2021 Renesas Electronics Corporation
10
February 23, 2021
F1956 Datasheet
T
YPICAL
O
PERATING
C
ONDITIONS
(1)
Insertion Loss vs Frequency
Insertion Loss vs Attenuation
0
0
-5
3.0 GHz,
-40 C
3.0 GHz,
+25 C
3.0 GHz, +105 C
-1
-2
-10
-15
-20
-25
-30
-35
-3
-40 C
-4
+25 C
+105 C
-5
0
1
2
3
4
5
6
7
7
7
8
8
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Input Return Loss vs Frequency [All States]
Input Return Loss vs Attenuation
0
-5
0
0.02 GHz
3.50 GHz
1.00 GHz
4.00 GHz
1.50 GHz
4.50 GHz
2.00 GHz
5.00 GHz
2.50 GHz
5.50 GHz
3.00 GHz
6.00 GHz
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
6
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Output Return Loss vs Frequency [All States]
Output Return Loss vs Attenuation
0
-5
0
0.02 GHz
3.50 GHz
1.00 GHz
4.00 GHz
1.50 GHz
4.50 GHz
2.00 GHz
5.00 GHz
2.50 GHz
5.50 GHz
3.00 GHz
6.00 GHz
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
6
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
© 2021 Renesas Electronics Corporation
11
February 23, 2021
F1956 Datasheet
T
YPICAL
O
PERATING
C
ONDITIONS
(2)
Worst Case Absolute Accuracy (LSB = 0.25dB)
Absolute Accuracy (LSB = 0.25dB)
1.0
0.5
0.6
0.4
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-0.5
-1.0
-40 C
Min
+25 C
Min
+105 C
Min
-40 C
Max
+25 C
Max
+105 C
Max
-1.5
-2.0
0.02 GHz
3.00 GHz
1.00 GHz
3.50 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
2.50 GHz
-1.6
-1.8
0
1
2
3
4
5
6
7
7
7
8
8
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Worst Case Absolute Accuracy (LSB = 0.50dB)
Absolute Accuracy (LSB = 0.50dB)
1.0
0.5
0.6
0.4
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-0.5
-1.0
-40 C
Min
+25 C
Min
+105 C
Min
-40 C
Max
+25 C
Max
+105 C
Max
-1.5
-2.0
0.02 GHz
3.50 GHz
1.00 GHz
4.00 GHz
1.50 GHz
4.50 GHz
2.00 GHz
5.00 GHz
2.50 GHz
5.50 GHz
3.00 GHz
6.00 GHz
-1.6
-1.8
0
1
2
3
4
5
6
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Worst Case Absolute Accuracy (LSB = 1.00dB)
Absolute Accuracy (LSB = 1.00dB)
1.0
0.5
0.6
0.4
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-0.5
-1.0
-40 C
Min
+25 C
Min
+105 C
Min
-40 C
Max
+25 C
Max
+105 C
Max
-1.5
-2.0
0.02 GHz
3.50 GHz
1.00 GHz
4.00 GHz
1.50 GHz
4.50 GHz
2.00 GHz
5.00 GHz
2.50 GHz
5.50 GHz
3.00 GHz
6.00 GHz
-1.6
-1.8
0
1
2
3
4
5
6
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
© 2021 Renesas Electronics Corporation
12
February 23, 2021
F1956 Datasheet
T
YPICAL
O
PERATING
C
ONDITIONS
(3)
Worst Case Step Accuracy (LSB = 0.25dB)
Step Accuracy (LSB = 0.25dB)
0.4
0.3
0.5
0.02 GHz
3.00 GHz
1.00 GHz
3.50 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
2.50 GHz
0.4
0.3
0.2
0.1
0.0
0.2
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.7
-0.8
-0.9
-1.0
-40 C
Min
+25 C
Min
+105 C
Min
-40 C
Max
+25 C
Max
+105 C
Max
0
1
2
3
4
5
6
7
7
7
8
8
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Worst Case Step Accuracy (LSB = 0.50dB)
Step Accuracy (LSB = 0.50dB)
0.4
0.3
0.5
0.50 GHz
3.50 GHz
1.00 GHz
4.00 GHz
1.50 GHz
4.50 GHz
2.00 GHz
5.00 GHz
2.50 GHz
5.50 GHz
3.00 GHz
6.00 GHz
0.4
0.3
0.2
0.1
0.0
0.2
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.7
-0.8
-0.9
-1.0
-40 C
Min
+25 C
Min
+105 C
Min
-40 C
Max
+25 C
Max
+105 C
Max
0
1
2
3
4
5
6
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Worst Case Step Accuracy (LSB = 1.00dB)
Step Accuracy (LSB = 1.00dB)
0.4
0.3
0.5
0.02 GHz
3.50 GHz
1.00 GHz
4.00 GHz
1.50 GHz
4.50 GHz
2.00 GHz
5.00 GHz
2.50 GHz
5.50 GHz
3.00 GHz
6.00 GHz
0.4
0.3
0.2
0.1
0.0
0.2
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.7
-0.8
-0.9
-1.0
-40 C
Min
+25 C
Min
+105 C
Min
-40 C
Max
+25 C
Max
+105 C
Max
0
1
2
3
4
5
6
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
© 2021 Renesas Electronics Corporation
13
February 23, 2021
F1956 Datasheet
T
YPICAL
O
PERATING
C
ONDITIONS
(4)
Relative Insertion Phase vs Frequency [All States]
Relative Insertion Phase vs Attenuation
110
100
90
80
70
60
50
40
30
20
10
0
110
0.50 GHz
3.50 GHz
1.00 GHz
4.00 GHz
1.50 GHz
4.50 GHz
2.00 GHz
5.00 GHz
2.50 GHz
5.50 GHz
3.00 GHz
6.00 GHz
100
90
80
70
60
50
40
30
20
10
0
-10
-10
0
1
2
3
4
5
6
7
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Frequency (GHz)
Input Compression (at 2GHz, Attn = 0dB)
Input Compression (at 2GHz, Attn = 16dB)
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.3
-0.4
-0.5
-40 C
-40 C
+25 C
+105 C
+25 C
+105 C
18
20
22
24
26
28
30
32
34
18
20
22
24
26
28
30
32
34
Input Power (dBm)
Input Power (dBm)
Input Compression (at 2GHz, Attn = 4dB)
Input Compression (at 2GHz, Attn = 31.75dB)
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.3
-0.4
-0.5
-40 C
-40 C
+25 C
+105 C
+25 C
+105 C
18
20
22
24
26
28
30
32
34
18
20
22
24
26
28
30
32
34
Input Power (dBm)
Input Power (dBm)
© 2021 Renesas Electronics Corporation
14
February 23, 2021
F1956 Datasheet
T
YPICAL
O
PERATING
C
ONDITIONS
(5)
Input Compression (+25
°
C, 4GHz)
Input Compression (+25
°
C, 6GHz)
0.5
0.5
6 GHz 0 dB
4 GHz 0 dB
0.4
0.4
6 GHz 4 dB
4 GHz 4 dB
6 GHz 8 dB
0.3
4 GHz 8 dB
0.3
6 GHz 16 dB
0.2
4 GHz 16 dB
0.2
0.1
0.0
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
24
25
26
27
28
29
30
31
32
33
34
24
25
26
27
28
29
30
31
32
33
34
Input Power (dBm)
Input Power (dBm)
Input IP3 vs Attenuation [2GHz]
Input IP3 vs Attenuation [3.92GHz]
80
75
70
65
60
55
80
75
70
65
60
55
50
45
40
50
-40 C /
Pin = 10 dBm/Tone
-40 C /
Pin = 15 dBm/Tone
+25 C /
Pin = 15 dBm/Tone
+105 C /
Pin = 15 dBm/Tone
+25 C /
Pin = 10 dBm/Tone
45
+105 C /
Pin = 10 dBm/Tone
40
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Attenuation (dB)
Input IP3 vs Frequency [Attn = 0dB, Pin = +22dBm]
80
75
70
65
60
55
50
IIP3-HS
45
IIP3-LS
40
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Frequency (GHz)
© 2021 Renesas Electronics Corporation
15
February 23, 2021
F1956 Datasheet
P
ACKAGE
O
UTLINE
D
RAWINGS
Th
e
package outline drawings
are located at the end of this document. The package information is the most current
data available and is subject to change without revision of this document.
P
IN
D
IAGRAM
TOP View
(looking through the top of the package)
NC
VDD
1
2
24
23
22
21
20
19
18
17
CLK
LE
3
4
5
6
V_MODE
A0
A1
F1956
Exposed pad
(GND)
A2
GND
NC
GND
GND
RF2
GND
RF1
7
8
GND
© 2021 Renesas Electronics Corporation
16
February 23, 2021
F1956 Datasheet
P
IN
D
ESCRIPTION
Pin
1
Name
DNC
Function
This pin must be left open.
2
VDD
Main Supply.
Use 3.3V or 5V. Bypass capacitor as close to pin as possible.
Logic low for parallel mode. Logic high or NC for serial mode.
Address bit A0 connection.
1
3
V
MODE
A0
2
4
5
GND
Connect directly to paddle ground or as close as possible to pin with thru
via. This pin is not internally connected
6
7
GND
RF1
3
GND
RF2
3
GND
NC
Connect directly to paddle ground or as close as possible to pin with thru
via.
Device RF input or output (bi-directional). AC couple to this pin unless 0V
DC.
8 – 17
18
Connect each pin directly to paddle ground or as close as possible to pin
with thru vias.
Device RF input or output (bi-directional). AC couple to this pin unless 0V
DC.
19
Connect directly to paddle ground or as close as possible to pin with thru
via.
20
No internal connection. These pins can be left unconnected, voltage applied,
or connected to ground (recommended).
21
22
23
24
25
26
27
28
29
30
31
32
EP
A2
2
A1
2
LE
1
CLK
1
DATA
1
D6
1
D5
1
D4
1
D3
1
D2
1
Address bit A2 connection.
Address bit A1 connection.
Serial interface latch enable input.
Serial interface clock input.
Serial interface data input.
Parallel control bit, 16dB. Ground pin if not used.
Parallel control bit, 8dB. Ground pin if not used.
Parallel control bit, 4dB. Ground pin if not used.
Parallel control bit, 2dB. Ground pin if not used.
Parallel control bit, 1dB. Ground pin if not used.
Parallel control bit, 0.5dB. Ground pin if not used.
Parallel control bit, 0.25dB. Ground pin if not used.
Connect to Ground with multiple vias for good thermal and RF performance.
D1
1
D0
1
Exposed
Paddle
© 2021 Renesas Electronics Corporation
17
February 23, 2021
F1956 Datasheet
E
V
K
IT
P
ICTURE
© 2021 Renesas Electronics Corporation
18
February 23, 2021
F1956 Datasheet
EVK
IT
/ A
PPLICATIONS
C
IRCUIT
2
2
2
1
A T A D
D 6
N D
G
N D
G
N D
G
N D
G
N D
G
N D
G
N D
G
N D
G
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
1 6
1 5
1 4
1 3
1 2
1 1
1 0
D 5
D 4
D 3
D 2
D 1
1 2
1 1
1
2
3
4
5
6
7
8
9
D 0
9
1 0
2
2
2
2
© 2021 Renesas Electronics Corporation
19
February 23, 2021
F1956 Datasheet
EVK
IT
BOM (R
EV
2)
Item #
Part Reference
QTY
DESCRIPTION
Mfr. Part #
Mfr.
C1 – C11, C14,
C15, C16
14
100pF ±5%, 50V, C0G Ceramic Capacitor (0402)
GRM1555C1H101J
MURATA
1
C18, C20, C22
3
1000pF ±5%, 50V, C0G Ceramic Capacitor
(0402)
GRM1555C1H102J
MURATA
2
3
4
5
6
7
C17, C19, C21
R17
3
1
10nF ±5%, 50V, X7R Ceramic Capacitor (0603)
0Ω Resistors
(0402)
GRM188R71H103J
ERJ-2GE0R00X
ERJ-2RKF1000X
ERJ-2RKF6981X
ERJ-2RKF1002X
961102-6404-AR
MURATA
PANASONIC
PANASONIC
PANASONIC
PANASONIC
3M
R1 – R14
R15
14
1
100Ω ±1%, 1/10
W, Resistor (0402)
6.98kΩ ±5%, 1/10
W, Resistor (0402)
10kΩ ±1%, 1/10
W, Resistor (0402)
CONN HEADER VERT SGL 2 X 1 POS GOLD
R16
1
J3, J7, J9,
J10, J11
5
8
9
J5
J1
1
1
6
CONN HEADER VERT SGL 4 X 1 POS GOLD
CONN HEADER VERT SGL 12 X 1 POS GOLD
961104-6404-AR
961112-6404-AR
142-0701-851
3M
3M
10
J2, J4, J6, J8,
J12, J13
Edge Launch SMA
(0.375 inch pitch ground, tab)
Emerson Johnson
11
12
13
14
SW1
U1
1
1
1
SWITCH 10 POSITION DIP SWITCH
DSA
KAT1110E
F1956
E-Switch
Renesas
Renesas
Printed Circuit Board
F1955 EVKit Rev 02
T
OP
M
ARKINGS
Part Number
IDT
F1956NBGI
ZA1515G
ASM
Test
Step
Date Code [YYWW]
(Week 15 of 2015)
© 2021 Renesas Electronics Corporation
20
February 23, 2021
F1956 Datasheet
A
PPLICATIONS
I
NFORMATION
Power Supplies
A common V
DD
power supply should be used for all pins requiring DC power. All supply pins should be
bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure
and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should
have a slew rate smaller than 1V/20µs. In addition, all control pins should remain at 0V (±0.3V) while the
supply voltage ramps or while it returns to zero.
Digital Pin Voltage and Resistance Values
The following table provides open-circuit DC voltage referenced to ground and resistance values for each of
the control pins listed.
Open Circuit DC
Pin
3
Name
V
MODE
Internal Connection
Voltage
100
kΩ pull
-up resistor to
internally regulated 2.5V
2.5V
4, 21, 22
A0, A2, A1
0V
100
kΩ resistor to GND
100
kΩ pull
-up resistor to
internally regulated 2.5V
100
kΩ pull
-up resistor to
internally regulated 2.5V
23, 24, 25
LE, CLK, DATA
2.5V
2.5V
26 – 32
D6 – D0
© 2021 Renesas Electronics Corporation
21
February 23, 2021
F1956 Datasheet
R
EVISION
H
ISTORY
Date
Description of Change
May 22, 2015
Initial release.
Datasheet format update.
Added Maximum Average Power Rating
Maximum operating frequency changed to 6 GHz.
Added curves showing performance at higher frequencies.
Rebranded to Renesas.
Sep 29, 2015
Apr 01, 2016
Feb 23, 2021
© 2021 Renesas Electronics Corporation
22
February 23, 2021
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILIT
Y
,
F
ITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products.
Y
o
u are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safet
y
, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual propert
y
.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas’ products are provided only subject
to Renesas’
T
e
rms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar
2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24
T
o
yosu,
Koto-ku,
T
o
kyo 135-0061, Japan
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property
of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.
