RENESAS-F1958NBGK
| Part # | RENESAS-F1958NBGK |
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7-Bit 0.25dB Digital Step Attenuator
1MHz to 6GHz
F1958
Datasheet
Description
Features
The F1958 is part of IDT’s
Glitch-Free
TM
family of DSAs optimized
for the demanding requirements of Base Station (BTS) radio cards
and numerous other applications. This device is offered in a
compact 4mm x 4mm 24-
pin package with 50Ω input and output
impedance for ease of integration into the radio or RF system.
.
.
.
Serial and 7-bit parallel interface
31.75dB range
0.25dB steps
.
Glitch-Free
TM
: low transient overshoot
.
.
.
.
.
.
.
.
500ns settling time for 0.25dB steps
Ultra linear > 63dBm IIP3
The F1958 offers very high reliability due to its construction from a
monolithic silicon die in a QFN package. The insertion loss is very
low with minimal distortion. Additionally, the device is designed to
have extremely accurate attenuation levels. These accurate
attenuation levels improve system SNR and/or ACLR by ensuring
system gain is as close to the targeted level as possible. In addition,
the very fast settling time in parallel mode is ideal for fast switching
systems. Finally, the device uses our
Glitch-Free
TM
technology in
contrast to competing DSAs.
Low insertion loss < 1.7dB at 4GHz
Attenuation error < ±0.2dB at 4GHz
Bi-directional RF use
3.3V or 5V supply
-40°C to +105°C operating temperature
4mm x 4mm Thin QFN 24-pin package
Block Diagram
Figure 1.
Block Diagram
Competitive Advantage
.
Lowest insertion loss for best SNR
.
Glitch-Free
TM
technology to protect power amplifiers or ADC
during transitions between attenuation states
Glitch-Free
TM
.
.
.
Extremely accurate attenuation levels
Ultra-low distortion
MSL1 and 2000 V HBM ESD
RF2
RF1
Typical Applications
SPI
Decoder
Bias
.
.
.
.
.
.
3G/4G/4G+ Base Station Systems
Distributed Antenna Systems, DAS
Remote Radio Heads
Active Antenna Systems, AAS Broadband Satellite Equipment
NFC Infrastructure
Military Communication Equipment
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November 13, 2019
Pin Assignments
Figure 2.
Pin Assignments for 4mm x 4mm x 0.75mm TQFN Package – Top View
1
2
3
4
5
6
18
17
16
15
14
13
D
A
T
A
CLK
LE
D0
V
DD
Decoder
SPI
B
I
A
S
V
MODE
GND
RF1
GND
RF2
GND
GND
EPAD
Pin Descriptions
Table 1.
Pin Descriptions
Number
Name
Description
Parallel control pin – 0.25dB. Pull high for attenuation.
Power supply input. Bypass to ground with capacitors as close as possible to pin.
1
2
D0
V
DD
Parallel or serial programming mode pin. Leave open or logic LOW for parallel mode. Logic HIGH for
serial mode.
3
V
MODE
GND
RF1
4, 6 – 13, 15
5
Internally grounded. These pins must be grounded as close to the device as possible.
RF Port 1. Can be used as either the input or output RF (bi-directional). Port must be at 0V DC. An
external AC coupling capacitor
must
be used if there is a DC voltage present.
RF Port 2. Can be used as either the input or output RF (bi-directional). Port must be at 0V DC. An
external AC coupling capacitor
must
be used if there is a DC voltage present.
14
RF2
16
17
18
19
20
21
22
23
24
LE
CLK
DATA
D6
Serial latch enable.
Serial clock input.
Serial data input.
D5
D4
D3
D2
D1
Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board
(PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground
planes. These multiple ground vias are also required to achieve the specified RF performance.
– EPAD
[a]
There is a 500kΩ pull
-down resistor to ground.
2
November 13, 2019
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.
Functional operation of the F1958 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 2.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Power Supply Voltage
V
DD
-0.3
5.8
V
Lower of
(V
DD
+0.25, 5.8)
V
MODE
, DATA, CLK, LE, D[6:0]
V
CTRL
-0.3
-0.3
V
RF1, RF2
V
RF
0.3
V
dBm
°C
Maximum RF Input Power to RF1 or RF2 (> 100 MHz)
Junction Temperature
P
MAX
T
JMAX
T
STOR
T
LEAD
+34
+150
+150
+260
Storage Temperature Range
Lead Temperature (soldering, 10s)
-65
°C
°C
Electrostatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
2000
(Class 2)
V
ESDHMB
V
ESDCDM
V
V
Electrostatic Discharge – CDM
(JEDEC 22-C101F)
1000
(Class C3)
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November 13, 2019
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Power Supply Voltage
Operating Temperature Range
RF Frequency Range
V
DD
T
EP
3.0
-40
5.5
+105
V
Exposed paddle
°C
f
RF
0.001
6
GHz
dBm
Maximum Input Power
P
MAX
RF1 or RF2
RF1 Port,
V
DD
= 3.3V, T
EP
= 85
°
C,
f
RF
> 500MHz, WCDMA,
3GPP, Downlink, 64 DPCH,
Chip rate =3.84MSPS,
Avg. P
IN
= +22dBm
RF Peak Input Power
P
PEAK
1 %
28.9
30.7
32.3
33.2
0.1 %
0.01 %
0.001 %
dBm
RF1 Port Impedance
RF2 Port Impedance
Z
1
Z
2
50
50
Ω
Ω
Figure 3.
Maximum Operating CW Input Power vs. Input Frequency
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November 13, 2019
Electrical Characteristics – Part 1
Table 4.
Electrical Characteristics
Specifications apply at V
DD
= 3.3V, T
EP
= 25°C, f
RF
= 2GHz, LSB = 0.25dB steps and Evaluation Board (EVKit) trace and connector losses are
de-embedded, unless otherwise noted. Minimum attenuation D[6:0] = [0000000], Maximum attenuation D[6:0] = [1111111].
Parameter
Logic Input HIGH
Symbol
Condition
All logic pins
Minimum
Typical
Maximum
Units
0
V
IH
V
IL
5.5
1
V
V
Logic Input LOW
Logic Current
All logic pins
I
IH
, I
IL
µA
-15
+15
400
V
DD
= 3.3V
250
310
DC Current
I
DD
µA
dB
V
DD
= 5.5V
Attenuation Range
No missing codes
f
RF
< 4.0GHz
f
RF
< 6.0GHz
f
RF
< 8.0GHz
31.75
0.25
0.50
1.00
Minimum Gain Step for
Monotonicity
LSB
dB
Max to min attenuation to
settle to within 0.5dB of final
value
1.2
2.0
t
SET
µs
Min to max attenuation to
settle to within 0.5dB of final
value
Measured with 10ns rise time,
0V to 3.3V control pulse
Maximum Video Feed-Through
VID
FT
10
mV
pp
dBm
Maximum Spurious Level on any
Unused RF ports terminated
into 50Ω
SPUR
MAX
-118
Serial Clock Speed
f
CLK
t
PS
t
H
MHz
ns
10
Parallel to Serial Setup
Serial Data Hold Time
100
10
ns
Time from final serial clock
rising edge
LE Delay
10
ns
Maximum Switch Rate
SW
RATE
25
kHz
[a] Specifications
in the minimum/maximum columns that are shown in
bold italics
are guaranteed by test. Specifications in
these columns that are not shown in bold italics are guaranteed by design characterization.
[b] Speeds
are measured after SPI programming is completed (data latched with LE = LOW to HIGH transition).
[c] Spurious
due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2MHz.
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November 13, 2019
Electrical Characteristics – Part 2
Table 5.
Electrical Characteristics
Specifications apply at V
DD
= 3.3V, T
EP
= 25°C, f
RF
= 2GHz, LSB = 0.25dB steps and Evaluation Board (EVKit) trace and connector losses are
de-embedded, unless otherwise noted. Minimum attenuation D[6:0] = [0000000], Maximum attenuation D[6:0] = [1111111].
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
1.2
[a]
1.5
1MHz ≤ f
RF
≤ 1GHz
1GHz < f
RF
≤ 2GHz
2GHz < f
RF
≤ 3GHz
3GHz < f
RF
≤ 4GHz
4GHz < f
RF
≤ 5GHz
5GHz < f
RF
≤ 6GHz
f
RF
= 1GHz
1.1
1.3
1.5
1.6
1.9
2.6
12
1.7
Insertion Loss
IL
dB
2.2
2.6
3.0
f
RF
= 2GHz
25
Relative Phase Between the
Minimum and Maximum Attenuation
Φ
∆
deg
f
RF
= 4GHz
50
f
RF
= 6GHz
70
Maximum error between any
two adjacent attenuation
levels
Step Error
DNL
INL
0.15
0.28
dB
dB
Max. error for state 19.75dB,
f
RF
= 2000MHz
-0.5
+0.5
Absolute Attenuation Error
Max. error, over all states
f
RF
= 2000MHz
-0.25
+0.08
-0.8
+0.5
1MHz ≤ f
RF
≤ 2GHz
2GHz < f
RF
≤ 4GHz
4GHz < f
RF
≤ 6GHz
1MHz ≤ f
RF
≤ 2GHz
2GHz < f
RF
≤ 4GHz
4GHz < f
RF
≤ 6GHz
20
17
13
20
16
12
RF1 Port Return Loss
RF2 Port Return Loss
RL
1
RL
2
dB
dB
[a] Specifications
in the minimum/maximum columns that are shown in
bold italics
are guaranteed by test. Specifications in
these columns that are not shown in bold italics are guaranteed by design characterization.
6
November 13, 2019
Electrical Characteristics – Part 3
Table 6.
Electrical Characteristics
Specifications apply at V
DD
= 3.3V, T
EP
= 25°C, f
RF
= 2GHz, LSB = 0.25dB steps and Evaluation Board (EVKit) trace and connector losses are
de-embedded, unless otherwise noted. Minimum attenuation D[6:0] = [0000000], Maximum attenuation D[6:0] = [1111111].
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
P
IN
= +19dBm per tone
50MHz tone separation
Attn = 0.00dB
Attn = 15.75dB
Attn = 31.75dB
64
64
64
dBm
Input IP3
IIP3
P
IN
= +16dBm per tone
1MHz tone separation
f
RF
= 0.7GHz
f
RF
= 1.8GHz
f
RF
= 2.2GHz
f
RF
= 2.6GHz
60
63.3
63.7
63.4
63.7
35
dBm
dBm
60
60
IP
0.1dB
[a] Specifications
in the minimum/maximum columns that are shown in
bold italics
are guaranteed by test. Specifications in
these columns that are not shown in bold italics are guaranteed by design characterization.
[b] The
input 0.1dB compression point is a linearity figure of merit. Refer to the Recommended Operating Conditions section and
Figure 3
for the maximum operating power levels.
7
November 13, 2019
Thermal Characteristics
Table 7.
Package Thermal Characteristics
Parameter
Symbol
Value
Units
Junction to Ambient Thermal Resistance
θ
JA
42
°C/W
Junction to Case Thermal Resistance
(case is defined as the exposed paddle)
θ
JC-BOT
8
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL 1
Typical Operating Conditions (TOC)
.
.
.
.
.
.
.
.
.
V
DD
= 3.3V
Z
L
= Z
S
= 50Ω
T
EP
= 25°C
f
RF
= 2.0GHz
Attenuation setting = 0 dB = D[6:0] =[0000000]
P
in
= +16dBm / tone
50MHz tone spacing
All temperatures are referenced to the exposed paddle
Evaluation Kit traces and connector losses are de-embedded
8
November 13, 2019
Typical Performance Characteristics
Figure 4.
Insertion Loss vs Frequency
Figure 5.
Insertion Loss vs Attenuator Setting
0
-5
0
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
0.02 GHz
2.50 GHz
5.00 GHz
0.50 GHz
3.00 GHz
5.50 GHz
1.00 GHz
3.50 GHz
6.00 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
0
1
2
3
4
5
6
7
8
8
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
Figure 6.
Input Return Loss vs Frequency
[All States]
Figure 7.
Input Return Loss vs Attenuator
Setting
0
0
0.02 GHz
2.50 GHz
5.00 GHz
0.50 GHz
3.00 GHz
5.50 GHz
1.00 GHz
3.50 GHz
6.00 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
-5
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
6
7
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
Figure 8.
Output Return Loss vs Frequency
[All States]
Figure 9.
Output Return Loss vs Attenuator
Setting
0
0
0.02 GHz
2.50 GHz
5.00 GHz
0.50 GHz
3.00 GHz
5.50 GHz
1.00 GHz
3.50 GHz
6.00 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
-5
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
4
5
6
7
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
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November 13, 2019
Figure 10.
Worst Case Absolute Accuracy vs
Frequency [LSB = 0.25dB]
Figure 11.
Absolute Accuracy vs Attenuator
Setting [LSB = 0.25dB]
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-40 C /
Min
+25 C /
Min
+105 C /
Min
-40 C /
Max
+25 C /
Max
+105 C /
Max
0.02 GHz
2.50 GHz
0.50 GHz
3.00 GHz
1.00 GHz
3.50 GHz
1.50 GHz
4.00 GHz
2.00 GHz
-1.6
-1.8
0
1
2
3
4
5
6
7
8
8
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
Figure 12.
Worst Case Absolute Accuracy vs
Frequency [LSB = 0.50dB]
Figure 13.
Absolute Accuracy vs Attenuator
Setting [LSB = 0.50dB]
0.6
0.4
0.6
0.02 GHz
2.50 GHz
5.00 GHz
0.50 GHz
3.00 GHz
5.50 GHz
1.00 GHz
3.50 GHz
6.00 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-40 C /
Min
+25 C /
Min
+105 C /
Min
-40 C /
Max
+25 C /
Max
+105 C /
Max
-1.6
-1.8
0
1
2
3
4
5
6
7
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
Figure 14.
Worst Case Absolute Accuracy vs
Frequency [LSB = 1.00dB]
Figure 15.
Absolute Accuracy vs Attenuator
Setting [LSB = 1.00dB]
0.6
0.4
0.6
0.02 GHz
2.50 GHz
5.00 GHz
0.50 GHz
3.00 GHz
5.50 GHz
1.00 GHz
3.50 GHz
6.00 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-40 C /
Min
+25 C /
Min
+105 C /
Min
-40 C /
Max
+25 C /
Max
+105 C /
Max
-1.6
-1.8
0
1
2
3
4
5
6
7
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
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November 13, 2019
Figure 16.
Worst Case Step Accuracy vs
Frequency [LSB = 0.25dB]
Figure 17.
Step Accuracy vs Attenuator Setting
[LSB = 0.25dB]
0.5
0.5
0.4
0.02 GHz
2.50 GHz
0.50 GHz
3.00 GHz
1.00 GHz
3.50 GHz
1.50 GHz
4.00 GHz
2.00 GHz
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-0.4
-0.5
-40 C /
Min
+25 C /
Min
+105 C /
Min
-40 C /
Max
+25 C /
Max
+105 C /
Max
-0.4
-0.5
0
1
2
3
4
5
6
7
7
7
8
8
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
Figure 18.
Worst Case Step Accuracy vs
Frequency [LSB = 0.50dB]
Figure 19.
Step Accuracy vs Attenuator Setting
[LSB = 0.50dB]
0.5
0.4
0.5
0.02 GHz
2.50 GHz
5.00 GHz
0.50 GHz
3.00 GHz
5.50 GHz
1.00 GHz
3.50 GHz
6.00 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-0.4
-0.5
-40 C /
Min
+25 C /
Min
+105 C /
Min
-40 C /
Max
+25 C /
Max
+105 C /
Max
-0.4
-0.5
0
1
2
3
4
5
6
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
Figure 20.
Worst Case Step Accuracy vs
Frequency [LSB = 1.00dB]
Figure 21.
Step Accuracy vs Attenuator Setting
[LSB = 1.00dB]
0.5
0.4
0.5
0.02 GHz
2.50 GHz
5.00 GHz
0.50 GHz
3.00 GHz
5.50 GHz
1.00 GHz
3.50 GHz
6.00 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-0.4
-0.5
-40 C /
Min
+25 C /
Min
+105 C /
Min
-40 C /
Max
+25 C /
Max
+105 C /
Max
-0.4
-0.5
0
1
2
3
4
5
6
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
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November 13, 2019
Figure 22.
Relative Insertion Phase vs
Frequency [All States]
Figure 23.
Relative Insertion Phase vs
Attenuator Setting
90
80
70
60
50
40
30
20
10
90
80
70
60
50
40
30
20
10
0
0.02 GHz
2.50 GHz
5.00 GHz
0.50 GHz
3.00 GHz
5.50 GHz
1.00 GHz
3.50 GHz
6.00 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
0
Positive phase means the device is electrically shorter.
Positive phase means the device is electrically shorter.
-10
-10
0
1
2
3
4
5
6
7
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
Figure 24.
Attenuation vs Frequency
[All States]
Figure 25.
Attenuation vs Attenuator Setting
0
-2
0
-2
-4
-4
-6
-6
-8
-8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
0.02 GHz
2.50 GHz
5.00 GHz
0.50 GHz
3.00 GHz
5.50 GHz
1.00 GHz
3.50 GHz
6.00 GHz
1.50 GHz
4.00 GHz
2.00 GHz
4.50 GHz
0
1
2
3
4
5
6
7
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation Setting (dB)
Figure 26.
Insertion Loss vs Frequency [0dB]
Figure 27.
Evaluation Board Insertion Loss
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
3.00 V /
-40 C
3.00 V /
+25 C
3.00 V / +105 C
3.30 V /
-40 C
3.30 V /
+25 C
3.30 V / +105 C
5.00 V /
-40 C
5.00 V /
+25 C
5.00 V / +105 C
5.25 V /
-40 C
5.25 V /
+25 C
5.25 V / +105 C
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-1.6
-1.8
-2.0
-40 C
+25 C
+105 C
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Frequency (GHz)
Frequency (GHz)
12
November 13, 2019
Figure 28.
Input IP3 vs Frequency [0dB]
Figure 29.
Input IP3 vs Attenuation [2GHz]
75
70
65
60
55
50
75
70
65
60
55
50
-40 C
/ RF1
+25 C
/ RF1
+105 C
/ RF1
-40 C
/ RF2
+25 C
/ RF2
+105 C
/ RF2
0
1
2
3
4
5
6
7
8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (GHz)
Attenuation (dB)
Figure 30.
Compression vs Input Power [2GHz]
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
0.00 dB
2.00 dB
0.25 dB
4.00 dB
0.50 dB
6.00 dB
1.00 dB
10.00 dB
30.00 dB
-0.5
-0.6
-0.7
-0.8
12.00 dB
31.75 dB
18.00 dB
24.00 dB
16
18
20
22
24
26
28
30
32
34
36
Input Power (dBm)
Figure 31.
Typical Switching Time for a 0.25dB
Attenuation Transition
Figure 32.
Switching Time between Maximum
and Minimum Attenuation
-5.00
0
5.50 dB to 5.75 dB
5.75 dB to 5.50 dB
-5.25
-2
0.00 to 31.75 dB
31.75 to 0.00 dB
-4
-6
-8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-5.50
-5.75
-6.00
-6.25
-6.50
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Time (µs)
Time (µs)
13
November 13, 2019
Programming
The F1958 can be programmed using either the parallel or the serial mode, which is selectable via V
MODE
(pin 3). The serial mode is selected
by pulling V
MODE
to a logic HIGH, and the parallel mode is selected by floating V
MODE
or setting it to logic LOW.
Serial Mode
F1958 Serial Mode is selected by pulling V
MODE
to a logic HIGH. The serial interface uses a 8-bit word with only 7 bits used. The serial word is
shifted in LSB (D0) first. When serial programming is used, all the parallel control input pins (1, 19 – 24) must be grounded.
Table 8.
7-Bit SPI Word Sequence
Data Bit
Symbol
D7
D6
D5
D4
D3
D2
D1
D0
Not Used
Attenuation 16 dB Control Bit
Attenuation 8 dB Control Bit
Attenuation 4 dB Control Bit
Attenuation 2 dB Control Bit
Attenuation 1 dB Control Bit
Attenuation 0.5 dB Control Bit
Attenuation 0.25 dB Control Bit
Table 9.
Truth Table for Serial Control Word
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
Attenuation (dB)
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0.25
0.5
1
2
4
8
16
31.75
In the Serial Mode, the F1958 is programmed via the serial port on the rising edge of Latch Enable (LE). It is required that LE be kept logic
LOW until all data bits are clocked into the shift register. The F1958 will change attenuation state after the data word is latched into the active
14
November 13, 2019
Figure 33.
Serial Register Timing Diagram
Table 10.
SPI Timing Diagram Values for the Serial Mode
Parameter
Symbol
Test Condition
Min
Typical
Max
25
Units
MHz
ns
ns
ns
ns
ns
ns
ns
CLK Frequency
f
C
t
CH
t
CL
t
S
t
P
t
H
t
CLS
t
LS
t
L
CLK HIGH Duration Time
CLK LOW Duration Time
DATA to CLK Setup Time
CLK to Data Hold Time
Final CLK Rising Edge to LE Rising Edge
LE to CLK Setup Time
LE Trigger Pulse Width
[a] (t
CH
+ t
CL
) ≥ 1/f
C
.
20
20
10
40
10
10
10
10
10
ns
ns
t
LC
[b] Once
all desired data has been clocked in, LE must transition from LOW to HIGH after the minimum setup time t
LC
and before
any further CLK signals.
Serial Mode Default Startup Condition
When the device is first powered up, it will default to the maximum attenuation of 31.75dB independent of the V
MODE
and parallel pin [D6:D0]
conditions.
Table 11.
Default Setting Truth Table for Serial Control Word
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
Attenuation (dB)
31.75
X
1
1
1
1
1
1
1
15
November 13, 2019
Parallel Control Mode
For the F1958, the user has the option of running in one of two parallel modes. Direct Parallel Mode or Latched Parallel Mode.
Direct Parallel Mode
Direct Parallel Mode is selected when V
MODE
is floating or a logic LOW and LE is a logic HIGH. In this mode, the device will immediately react
to any voltage changes on the parallel control pins (1, 19 – 24). Use Direct Parallel Mode for the fastest settling time. The serial pins, CLK and
DATA, can be either grounded or left opened in the Parallel Mode.
Latched Parallel Mode
Latched Parallel Mode is selected when V
MODE
is floating or a logic LOW and LE is toggled from logic LOW to HIGH. To utilize Latched Parallel
Mode:
.
.
.
.
.
Set V
MODE
to logic LOW or leave floating.
Set LE to logic LOW.
Adjust pins (1, 19 – 24) to the desired attenuation setting. (Note the device will not react to these pins while LE is a logic LOW).
Set LE to a logic HIGH. The device will then transition to the attenuation settings reflected by pins D6 – D0.
If LE is set to a logic LOW then the attenuator will not change state.
The truth table for the Parallel Mode is identical for bits D6 to D0 as shown in the Serial Mode truth table; se
e Table 9.
Figure 34.
Latch Parallel Timing Diagram
Table 12.
Latched Parallel Timing Diagram Values
Parameter
Serial to Parallel Mode Setup Time
Parallel Data Hold Time
Symbol
t
SPS
t
PDH
Min
100
10
Max
Units
ns
ns
LE Minimum Pulse Width
Parallel Data Setup Time
t
LE
t
PDS
10
10
ns
ns
16
November 13, 2019
Evaluation Kit Picture
Figure 35.
Top View
SW1 Switch for parallel control
VLOGIC
V
MODE
V
DD
J6 Parallel
Control Pins
RF1
RF2
J10 Serial Control Pins
V
DD
Figure 36.
Bottom View
17
November 13, 2019
Evaluation Kit / Applications Circuit
Figure 37.
Electrical Schematic
J9
VLOGIC
C9
C10
J7
HEADER
1×2
SW1
Logic LOW Switch to ‘ – ‘ position
Logic HIGH Switch to ‘ + ‘ position
1
J8
1
2
8 Pin DP Switch
VDD
R9
R10
HEADER 1×2
J6
1
2
D0
D1
D2
D3
D4
D5
D6
3
4
5
6
7
VMODE
VDD
GND
8
9
10
10 Pin Header
VDD
R2
R3
R1
R4
R5
R6
R7
R8
C2
C3
C5
C1
C4
C6
C7
C8
J10
R11
R12
R13
2
4
6
7
1
3
5
7
HEADER 4
C11
C12
C13
U1
D0
J1
J2
1
2
3
4
5
6
18
Thru Cal
DATA
17
16
15
14
13
VDD
VDD
CLK
LE
VMODE
GND
RF1
GND
RF2
GND
J3
J4
J5
RF1
RF2
1
2
HEADER 1×2
GND
J11
R14
VDD
VDD
25
PAD
C14
C15
18
November 13, 2019
Table 13.
Bill of Material (BOM)
Part Reference
QTY
Description
Manufacturer Part #
Manufacturer
C1 – C8, C11 – C13
11
2
100pF ±5%, 50V, C0G Ceramic Capacitor (0402)
1000pF ±5%, 50V, C0G Ceramic Capacitor (0402)
10nF ±5%, 50V, X7R Ceramic Capacitor (0603)
0Ω Resistors (0402)
GRM1555C1H101J
GRM1555C1H102J
GRM188R71H103J
ERJ-2GE0R00X
ERJ-2RKF1000X
ERJ-2RKF1002X
961102-6404-AR
67997-108HLF
MURATA
MURATA
MURATA
PANASONIC
PANASONIC
PANASONIC
3M
C9, C15
C10, C14
2
R14
1
R1 – R8, R11 – R13
11
1
100Ω ±1%, 1/10W, Resistor (0402)
10kΩ ±1%, 1/10W, Resistor (0402)
CONN HEADER VERT SGL 2 X 1 POS GOLD
CONN HEADER VERT SGL 4 X 2 POS GOLD
CONN HEADER VERT SGL 10 X 1 POS GOLD
Edge Launch SMA (0.375 inch pitch ground, tab)
SWITCH 8 POSITION DIP SWITCH
DSA
R9
J5, J7, J8
J10
3
1
Amphenol FCI
3M
J6
1
961110-6404-AR
142-0701-851
J1 – J4, J11
SW1
5
Emerson Johnson
E-Switch
1
KAT1108E
U1
1
F1958NBGK
IDT
1
Printed Circuit Board
F1958 EVKit Rev 01
IDT
J9, R10
Do Not Populate (DNP)
19
November 13, 2019
Evaluation Kit Operation
Power Supply Setup
Set up a power supply in the voltage range of 3.0V to 5.5V with the power supply output disabled. The voltage can be applied via one of the
.
.
.
J11 connector
J5 header connection (note the polarity of the GND pin on this connector)
Pin 9 (V
DD
) and pin 10 (GND) on the J6 header connection
Figure 38.
Power Supply Connections
V
DD
V
DD
Parallel Logic Control Setup
The Evaluation Board has the ability to control the F1958 in the Parallel Mode. For external control, apply logic voltages to the J6 header pins
1 through 7 (see
Figure 39)
. For manual control, switches 1 through 7 on SW1 can be set. The switch is a three-position switch. The bottom
position, “-” will ground the pin. The center position “O” will leave the pin open circuited. Setting the switch to the top position “+” will apply a
voltage that is supplied to the switch.
The logic voltage can be applied in one of three ways:
.
.
.
Apply a voltage through a SMA connector (J9). This connector is not supplied.
Apply a voltage on pin 2 of the J7 header connector.
Short out the two header connectors, J7 and J8, so a resistor divider will generate the correct logic voltage from the power supply on the
Evaluation Board. The logic voltage will be V
DD
.
20
November 13, 2019
Figure 39.
Parallel Logic Voltage Connections
SW1 Switch for parallel control
VLOGIC
V
MODE
V
DD
J6 Parallel
Control Pins
Serial Logic Control Setup
The Evaluation Board has the ability to control the F1958 in the Serial Mode. Connect the serial controller to the J10 header connection as
Figure 40.
Serial Logic Connections
J10 Serial Control Pins
V
DD
Power-On Procedure
Set up the voltage supplies and Evaluation Board as described in the “Power Supply Setup” section and either the “Parallel Logic Control Setup”
or “Serial Logic Control Setup” sections above.
.
.
Enable the power supply.
Power-Off Procedure
.
Set the logic control pins to a logic LOW.
.
Disable the power supply.
21
November 13, 2019
Application Information
Digital Pin Voltage and Resistance Values
Table 14
provides the open-circuit DC voltage referenced to ground and resistance values for each of the control pins listed.
Table 14.
Digital Pin Voltages and Resistance
Open Circuit
DC Voltage
Pin
Name
Internal Connection
3, 16, 17, 18
1, 19 – 24
V
MODE
, LE, CLK, DATA
D0, D6 – D1
0V
0V
500kΩ pull
-down resistor to GND
500kΩ
pull-down resistor to GND
Power Supplies
A common power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize
noise and fast transients. Supply noise can degrade the noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply
voltage changes or transients should have a slew rate smaller than 1V/20µs. In addition, all control pins should remain at 0V (+/-0.3V) while
the supply voltage ramps or while it returns to zero.
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to pins for the SPI (16, 17, 18), parallel (1, 19-24) and V
MODE
pin (3) as shown
below. Note the recommended resistor and capacitor values do not necessarily match the EVKit BOM for the case of poor control signal integrity.
For multiple devices driven by a single control line, the component values will need to be adjusted accordingly so as not to load down the control
line.
Figure 41. Control Pin Interface for Signal Integrity
5 kohm
5 kohm
D4
D3
2 pF
2 pF
5 kohm
5 kohm
D5
D2
2 pF
2 pF
5 kohm
5 kohm
D1
D6
2 pF
2 pF
5 kohm
D
A
T
A
2 pF
5 kohm
5 kohm
D0
1
2
3
4
5
6
18
17
16
15
14
13
2 pF
5 kohm
5 kohm
Decoder
SPI
B
I
A
S
CLK
LE
2 pF
2 pF
V
MODE
2 pF
EPAD
22
November 13, 2019
Package Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Temperature
F1958NBGK
F1958NBGK8
F1958EVB
4mm x 4mm x 0.75mm 24 pin QFN
4mm x 4mm x 0.75mm 24 pin QFN
Evaluation Board
1
1
Tray
Reel
-40°C to +105°C
-40°C to +105°C
Evaluation Solution including the Evaluation Board, Controller Board, and cable. The Evaluation Software is
F1958EVS
Marking Diagram
1. Line 1 and 2 are the part number.
2. Line 3 “Z” is for die version.
3. Line 3 “yyww” = 1716 has two digits for the year and week that the part was assembled.
4. Line 3 “NG” denotes Assembly Lot number.
F1958
NBGK
Z1716AAG
23
November 13, 2019
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,
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o
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