RENESAS-HSP50306SC-27
| Part # | RENESAS-HSP50306SC-27 |
Download  | RENESAS-HSP50306SC-27 |
®
H
S
P50306
Digital QPSK Demodulator
July 2004
Features
D
e
s cr
i
p
tion
• 25.6MHz
or 26.97MHz Clock Rates
The HSP50306 is a 6-bit QPSK demodulator chip designed
for use in high signal to noise environments which have some
multipath distortion. The part recovers 2.048 MBPS data from
samples of a QPSK modulated 10.7MHz or 2.1MHz carrier.
The chip coherently demodulates the waveform, recovers
symbol timing, adaptively equalizes the signal to remove
multipath distortion, differentially decodes and multiplexes the
data decisions. 8-A lock signal is provided to indicate when
the tracking loops are locked and the data decisions are valid.
To optimize performance, a gain error feedback signal is
provided which can be filtered and used to close an I.F. AGC
loop around the A/D converter.
• Single
Chip QPSK Demodulator with 10kHz Tracking
Loop
• Square
Root of Raised Cosine (
α
= 0.4) Matched
Filtering
• 2.048
MBPS Reconstructed Output Data Stream
• Bit
Synchronization with 3kHz Loop Bandwidth
• Internal
Equalization for Multipath Distortion
• 6-Bit
Real Input: Digitized 10.7MHz or 2.1MHz IF
• Level
Detection for External IF AGC Loop
• 0.1s
Acquisition Time
The QPSK demodulator derives all timing from CLKIN. The
chip divides this clock by 2 to provide the sample clock for the
external A/D converter. The -27 version operates at a clock
input of 26.97MHz and demodulates a 10.7MHz QPSK signal
to recover the 2048 KSPS data. The -25 version operates at a
clock input of 25.6MHz and demodulates a 2.1MHz QPSK
signal to recover the 2048 KSPS data. Variation from these
CLKIN frequencies will progressively degrade the receive
data rate, the receive IF, acquisition sweep rate, acquisition
sweep range and loop bandwidths as the deviation increases
from normal CLKIN. Details on the maximum allowable devia-
tion are found in the Input Characteristics section. The
HSP50306 processes 6-bit offset binary data. 4-bit data pro-
vides adequate performance for many applications.
-9
• 10
BER
• <116mA
on +5.0V Supply
A
p
p
l
i
c
at
i
o
ns
• Cable
Data Link Receivers
• Cable
Control Channel Receivers
Ordering
I
n
f
o
rmation
TEMP.
PKG.
DWG. #
PART NUMBER
RANGE (°C)
PACKAGE
HSP50306SC-27
0 to 70
16 Ld SOIC
M16.3
Block Diagram
I
4 TAP
ADAPTIVE
EQUALIZER
Q
6
DIN0-5
I
DIFF.
DECODE/
MUX
DATAOUT
COS SIN
NCO
Q
BIT PHASE
DETECTOR
LEVEL
AGCOUT
DETECT
LOCK
CARRIER
PHASE
DETECT
ADCLK
CLKIN
RESET
TEST
LOCK
DETECT
TIMING
GENERATOR
BIT SYNC
LOOP FILTER
CLKOUT
CARRIER
LOOP FILTER
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
FN4162.3
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corp. 1998, Copyright Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
H
S
P50306
P
i
n
out
16 LEAD SOIC
TOP VIEW
AGCOUT
CLKOUT
DATAOUT
LOCK
1
2
3
4
5
6
7
8
16 V
CC
15 ADCLK
14
13
DIN0
DIN1
RESET
TEST
12 DIN2
11
10
9
DIN3
DIN4
DIN5
CLKIN
GND
P
i
n D
e
s
cr
i
p
tion
NAME
SOIC PIN
TYPE
DESCRIPTION
V
16
8
–
–
I
I
+5V Power Supply
Ground
CC
GND
CLKIN
7
Clock input. This is the processing clock for the part. All timing is derived from this clock.
DIN (5:0)
9-14
I.F. input samples from the A/D converter. These bits interpreted as offset binary format. DIN5 is the
MSB. If fewer than 6 bits are used, the bits from the A/D should be connected to the MSBs of the
input and the unused LSBs grounded.
ADCLK
15
1
O
O
This output clock is the clock for the A/D converter.
AGCOUT
This output indicates whether the magnitude of the input samples are above or below the expected
level. This output is provided as an error detector for an external AGC loop. The output is low when
the input is greater than nominal, and high when the input is lower than nominal.
DATAOUT
CLKOUT
LOCK
3
2
4
5
6
O
O
O
I
This is the recovered data.
This is the recovered clock.
This signal indicates that the carrier tracking loop is locked and data on the DOUT pin should be valid.
This input is provided to for initialization and test. Active low.
This input is provided for test. Pull high for normal operation.
RESET
TEST
I
2
H
S
P50306
The Block Diagram of the QPSK Demodulator is shown on
rectifying the I.F. input samples and comparing them against
page 1. To demodulate the data, the I.F. samples are multi-
a threshold. The error signal is low if the signal magnitude is
plied by sine and cosine samples from a numerically con-
above the upper threshold, high if the magnitude is below the
trolled oscillator. The digital mixer outputs are then low pass
lower limit.
filtered to remove mixer products. The filtered data is then
Figure 1 shows the circuit of a typical demodulator application.
equalized by a 4 tap equalizer (1 precursor, one reference
The typical Bit Error Rate (BER) performance is shown in
tap, and a 2 tap Decision Feedback Equalizer (DFE) to
Figure 2 for both 4-bit and 6-bit quantized inputs. The
remove distortion caused by multipath. The output of the
theoretical QPSK BER Performance Curve is provided for
equalizer is differentially decoded and multiplexed into the
reference. Note
that the BER performance shown in Figure 2
output data stream. The carrier tracking loop providing the
includes a multipath distortion element at the input, in addition
L.O. for the digital mixer is a second order digital Costas loop
to the desired signal. This multipath distortion is
with a tracking bandwidth of ~10kHz. A sweep circuit
representative of receive signal distortions found in cable data
searches the carrier uncertainty using a triangle sweep algo-
links.
rithm during acquisition. A lock detector controls the sweep
Table 1 details the BER, Acquisition and Delay Performance
and indicates when valid data is available. The recovered
Specifications of the HSP50306 QPSK demodulator chip,
data rate clock is generated by another numerically controlled
based on an input that complies with the specifications
oscillator. The timing recovery loop is a first order decision
detailed in Table 2.
directed digital phase locked with a loop bandwidth of
~
3kHz.
The Level Detect circuitry generates the AGC error signal by
A
p
p
l
i
c
at
i
o
n Examp
l
e
(25.6MHz)
26.97MHz
HSP50306
OSC
CLKIN
DIN0-5
CLKOUT
CA3304/6
A/D
2.048 MBPS
OUTPUT
I.F. FILTER
DIGITIZED
10.7MHz (2.1MHz)
IF INPUT
6
DATA/CLK
DATAOUT
ADCLK
LOCK
TEST
AGCOUT
V+
RESET
FIGURE 1.
APPLICATIONS CIRCUIT EXAMPLE
0.01
0.001
0.0001
0.00001
1E-06
1E-07
1E-08
1E-09
1E-10
1E-11
1E-12
4-BIT DATA
THEORETICAL
6-BIT DATA
11
12
13
14
15
16
17
/N
18
19
20
21
22
23
E
S
O
NOTE: Simulation
performed using alpha = 0.4 Root Raised Cosine Transmit Filtering, Multipath -10dBc at 72° at 1.6
µ
s.
FIGURE 2.
TYPICAL BIT ERROR RATE PERFORMANCE
3
H
S
P50306
TABLE 1.
PERFORMANCE SPECIFICATIONS
PERFORMANCE
SPECIFICATION
–
9
BER
Better than 1.0 x 10
with specified input signal characteristics. (See Figure 1.)
Acquisition Time
Acquisition within 0.1s from applying an input signal with the specified characteristics.
Carrier Loop Bandwidth
Bit Sync Loop Bandwidth
Throughput Delay
10kHz
3kHz
Less than 6 output bit times.
TABLE 2.
INPUT SIGNAL CHARACTERISTICS
(NOTE 1)
PARAMETER
Carrier Frequency
Bit Rate
SPECIFICATION
6
10.7 x 10
±
40kHz.
6
2.048 x 10
±
0.01%.
Modulation Format
QPSK w/differential encoding specified as:
00:
0° phase change
10: +90°
phase change
01: -90°
phase change
11: 180°
phase change
(Note 2)
Filtering
Square root of raised cosine matched filtering (
α
= 0.4).
Set input p-p signal to full scale on the A/D converter.
6 bits, offset binary.
Input RMS Signal Level
Input Data Format
Input Clock Frequency
SINAD
26.97MHz
±
0.015% (Note 3) for -27; 25.6MHz
±
0.015% for -25.
>25.5dB SNR (thermal (AWGN)), >28dB (adjacent channel interference).
Total energy in multipath distortion -10dBc
Multipath Distortion
>95% of multipath energy within 2
µ
s from main path. If the multipath changes rapidly, the bit error rate
may exceed the above specification until the equalizer has readjusted.
NOTES:
1. All
frequencies are relative to the input clock frequency. For example, the bit rate is actually ~0.075936 * f
in this document are only valid for a 26.97MHz or 25.6MHz clock.
. The frequencies provided
CLK
2. Each
pair of input bits is encoded into a phase change relative to the previous symbol. In the HSP50306, the symbol to symbol phase
change is decoded into the transmitted bit pair which is multiplexed into the output data stream.
3. While
the device is static CMOS and can be clocked down to close to DC, the specified range indicates the accuracy needed to maintain
the data rate inside the bit sync tracking loop bandwidth assuming 50ppm tx and 100ppm rx crystal accuracies.
4
H
S
P50306
Two V
e
rs
ions :
Different Applications
DEMOD INPUT IF
RECEIVE IF
The -27 and -25 versions of the HSP50306 Digital QPSK
Demodulator are not simply different speed grades of the
same device, but are designs which have proportionally
scaled clocks and bandwidths for different applications.
NOTE: While thes
e parts are pin for pin compatible, in
mos t
app
l
i
c
at
i
o
ns they cannot be us
ed as
f
u
nct
i
o
nal
equ
i
valent s
ubs titutes
for each other.
Key differences
are:
DC 2.79
10.7
F
16.27
24.19
29.76
CLK
F
S
FIGURE 3.
SAMPLED SPECTRUM FOR THE -27 VERSIONS
(f =
26.97MHz)
CLK
• The
-27 version of the HSP50306 has an input IF of
10.7MHz with an input clock of 26. 97MHz.
DEMOD INPUT IF
RECEIVE IF
• The
-25 version of the HSP50306 has an input IF of
2.1MHz with an input clock of 25. 6MHz.
DC 2.1
10.7 F
14.9
23.5
27.7
F
CLK
S
In both the -27 and -25 designs, the sample rate clock for the
input IF signal is half of the CLK frequency.
NOTE: Sample
FIGURE 4.
SAMPLED SPECTRUM FOR THE -25 VERSIONS
(f =
25.6MHz)
rate clock is des
ignated by f
= f
/2.
Aside from input
S
CLK
CLK
IF and input clock, all other performance parameters of the
two parts are identical for their respective IF inputs.
TABLE 3.
DIFFERENTIAL ENCODING REQUIRED FOR THE -27
AND -25 DEMODULATORS RECEIVING 10.7MHz IF
10.7
M
Hz I
n
put
I
F A
p
p
l
i
c
at
i
o
ns
PHASE CHANGE
REQUIRED FOR -27
DEMODULATION
PHASE CHANGE
REQUIRED FOR -25
DEMODULATION
Both the -27 and -25 parts can be used in 10.7MHz IF Applica-
tions. Figures 3 and 4 show the frequency spectrum for the
sampled 10.7MHz IF input signals for both the -27 and -25 ver-
sions, respectively. In the 10.7MHz IF Application, the -25 ver-
sion offers tighter filtering capability than the -27 version
because the lower IF allows use of low pass filtering. Also, the
lower IF of the -25 version has inherently lower internal pro-
cessing spectral spurs than the -27 version. Note that the
receive IF for the HSP50306SC-27 is the input IF to the demod-
ulator. For the HSP50306SC-25, the receive IF is 10.7MHz, but
the processing is done on the spectral image at 2.1MHz. Exam-
ine the spectral inversion between the 10.7MHz Receive IF and
the 2.1MHz demodulator input in Figure 4.
The transmit differ-
ential encoder must take into account this spectral rever-
sal.
The required encoding is shown in Table 3. This part was
designed to be paired with the HSP50307 Burst Modulator, and
can be operated from the same 25.6MHz reference clock.
INPUT
BITS
o
o
00
01
10
11
0
0
o
o
-90
90
o
o
90
-90
o
o
180
180
5
H
S
P50306
Absolute Maximum Ratings
T
= 25°C
Thermal Information
A
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
+
6.0V
Thermal Resistance (Typical, Note 4)
θ
JA
(°C/W)
Input, Output or I/O Voltage . . . . . . . . . . .
GND -0.5V to V
+0.5V
CC
Typical Derating Factor
. . . . . . . . . . . .4mA/MHz Increase in I
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
CCOP
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300°C
(SOIC – Lead Tips Only)
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class 1
Operating Conditions
Operating Voltage Rang
e
. . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 70°C
C
A
UTION:
S
t
r
e
sses abo
v
e those
l
i
s
t
e
d
i
n “A
b
so
l
u
te M
a
x
imum Rat
i
n
gs”
may cause permanent damage to the dev
i
c
e. Th
i
s is a
s
t
r
e
ss on
l
y r
a
t
ing
a
nd operat
i
o
n
of the
dev
i
c
e at these or any other cond
i
ti
o
ns above those
i
n
d
i
c
ated
i
n t
h
e operat
i
o
nal sect
i
o
ns of th
i
s
s
pec
i
fi
c
at
i
o
n
i
s
n
ot
i
m
p
l
i
e
d.
NOTE:
4.
θ
is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
PARAMETER
V
= 5.0V
±
5%, T
= 0°C to 70°C
CC A
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Power Supply Current
I
V
= Max, CLK = 28.6MHz
–
114
mA
CCOP
CC
(Notes 5, 6)
Standby Power Supply Current
Input Leakage Current
I
V
V
V
V
V
V
= Max, Outputs Not Loaded
–
-10
3.7
–
500
10
–
µ
A
µ
A
V
CCSB
CC
CC
CC
CC
CC
CC
I
= Max, Input = 0V or V
CC
I
CMOS Output High (ADCLK, AGCOUT)
CMOS Output Low (ADCLK, AGCOUT)
Logical One Input Voltage
Logical Zero Input Voltage
Logical One Output Voltage
Logical Zero Output Voltage
Input Capacitance
V
= Min, I
= -400
µ
A
OH
OHC
V
= Min, I
= 2mA
OL
0.4
–
V
OLC
V
= Max
= Min
2.0
–
V
IH
V
0.8
–
V
IL
V
I
I
= -400
µ
A, V
= Min
2.4
–
V
OH
OH
OL
CC
V
= 2mA, V
= Min
0.4
10
10
V
OL
CC
C
CLK = 1MHz
All measurements referenced to GND.
T =
25°C, (Note 7)
A
–
pF
pF
IN
Output Capacitance
C
–
OUT
NOTES:
5. Power
supply current is proportional to frequency. Typical rating is 4mA/MHz.
6. Output
load per test circuit and C
= 40pF.
L
7. Not
tested, but characterized at initial design and at major process/design changes.
6
H
S
P50306
AC Electrical Specifications
27MHz Clock Rate, V
= 5.0V
±
5%, T
= 0°C to 70°C (Note 8)
CC
A
PARAMETER
SYMBOL
NOTES
MIN
36
12
12
15
1
MAX
UNITS
ns
CLK Period
t
–
–
CP
CLK High
t
ns
CH
CLK Low
t
–
ns
CL
RS
RH
Setup RESET to CLK
t
–
ns
Hold Time RESET to CLK
Setup Time DIN0-5 to ADCLK
Hold Time DIN0-5 to ADCLK
CLK to DATAOUT, LOCK, AGCOUT
Output Rise, Fall Time
t
–
ns
t
9
9
15
2
–
ns
DS
t
–
ns
DH
t
–
25
8
12
ns
PD
t
t
10
10
–
ns
RF
TC
Output Rise, Fall Time (CMOS Outputs)
–
ns
NOTES:
8. AC
Testing is performed as follows:
Input levels 0.0V to 3.0V. Timing reference levels = 1.5V. Output load circuit with C
= 40pF. Output
L
transition measured at V
_1.5V and V
_1.5V.
OH OL
9. The
set up and hold times for DIN (5:0) are with respect to the rising edge of ADCLKOUT. These parameters are guaranteed by design
and characterization but not tested. An A/D converter with a clock to data out specification of 55ns and a data hold from clock specification
of 2ns will meet these requirements at an oscillator clock frequency of 26.97MHz. Intersil
recommends the CA3304 or CA3306 A/D con-
verters for use with the HSP50306.
10. Controlled
via design or process parameters and not directly tested. Characterized upon initial design and at major process or design
changes.
AC T
e
s
t
L
o
ad C
i
rcuit
S
DUT
1
C
L
(NOTE)
I
2.5V
I
OL
±
OH
EQUIVALENT CIRCUIT
SWITCH S1 OPEN FOR I
AND I
CCOP
CCSB
NOTE: Test
head capacitance
7
H
S
P50306
W
a
ve
f
o
rms
t
CP
t
t
CH
CL
CLKIN
t
PD
ADCLK
t
t
RH
RS
RESET
t
t
DH
DS
DIN0-5
t
PD
CLKOUT
DATAOUT,
LOCK,
AGCOUT
FIGURE 5.
t
t
RF
t
t
TC
RF
TC
DATAOUT,
LOCK,
CLKOUT
AGCOUT,
ADCLK
3.2V
2.0V
0.8V
0.8V
FIGURE 6.
OUTPUT RISE AND FALL TIMES
FIGURE 7.
OUTPUT RISE AND FALL TIMES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
8
