Shikues-SKQ50N03BD
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SKQ50N03BD
N-Channel Enhancement Mode Field Effect Transistor
Product Summary
●
V
DS
30V
●
I
D
50A
●
R
DS(ON)
( at V
GS
=10V)
●
R
DS(ON)
( at V
GS
=4.5V)
●
100% UIS Tested
●
100%
▽
V
DS
Tested
＜
6.0 mohm
＜
8.0 mohm
General Description
●
Trench Power LV MOSFET technology
●
Excellent package for heat dissipation
●
High density cell design for low R
DS(ON)
Applications
●
High current load applications
●
Load switching
●
Hard switched and high frequency circuits
●
Uninterruptible power supply
●
Marking
:
Q50N03B
Absolute Maximum Ratings
(T
A
=25
℃
unless otherwise noted)
Parameter
Symbol
Limit
Unit
Drain-source Voltage
Gate-source Voltage
V
DS
V
GS
30
±
20
50
V
V
T
C
=25
℃
Drain Current
I
D
A
T
C
=100
℃
35
Pulsed Drain Current
A
Total Power Dissipation
Single Pulse Avalanche Energy
B
I
DM
190
30
A
W
T
C
=25
℃
P
D
T
C
=100
℃
15
W
E
AS
225
5
mJ
℃
/
W
℃
Thermal Resistance Junction-to-Case
C
Junction and Storage Temperature Range
R
θ
JC
T
J
,T
STG
-55
～
+175
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SKQ50N03BD
Electrical Characteristics
(T
J
=25
℃
unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Static Parameter
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-Body Leakage Current
Gate Threshold Voltage
BV
DSS
V
GS
= 0V, I
D
=250
μA
V
DS
=30V,V
GS
=0V
V
GS
=
±
20V, V
DS
=0V
V
DS
= V
GS
, I
D
=250
μA
V
GS
= 10V, I
D
=15A
V
GS
= 4.5V, I
D
=15A
I
S
=20A,V
GS
=0V
30
V
I
DSS
1
±
100
2.5
μA
nA
V
I
GSS
V
GS(th)
1.0
1.5
4.9
6.3
6.0
Static Drain-Source On-Resistance
R
DS(ON)
m
Ω
8.0
Diode Forward Voltage
Maximum Body-Diode Continuous Current
Dynamic Parameters
Input Capacitance
V
SD
1.2
V
A
I
S
50
C
iss
C
oss
C
rss
2150
435
Output Capacitance
V
DS
=15V,V
GS
=0V,f=1MHZ
pF
nC
ns
Reverse Transfer Capacitance
Switching Parameters
T
o
tal Gate Charge
252
Q
g
Q
gs
Q
gd
Q
rr
t
rr
52.8
12.3
10.8
28
Gate-Source Charge
Gate-Drain Charge
V
GS
=10V,V
DS
=15V,I
D
=20A
I
F
=25A, di/dt=100A/us
Reverse Recovery Chrage
Reverse Recovery Time
Turn-on Delay Time
27
t
D(on)
9
Turn-on Rise Time
t
r
15.5
29
V
GS
=10V, V
DD
=20V, I
D
=4A,R
L
=1
Ω
R
GEN
=3
Ω
Turn-off Delay Time
t
D(off)
Turn-off fall Time
t
f
9
A. Pulse
Test: Pulse Width
≤
300us,Duty cycle
≤
2%.
B. T
j
=25
℃
, V
DS
=30V V
DD
=25V V
GS
=10V L=1mH.
R
C.
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder
R
R
mounting surface of the drain pins.
θ
JC
is guaranteed by design, while
θ
JA
is determined by the board design. The maximum rating presented
here is based on mounting on a 1 in 2
pad of 2oz copper.
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SKQ50N03BD
Typical Performance Characteristics
Figure1. Output
Characteristics
Figure2. Transfer
Characteristics
Figure3. Capacitance
Characteristics
Figure4. Gate Charge
Figure5. Drain-Source on Resistance
Figure6. Drain-Source on Resistance
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SKQ50N03BD
Figure7. Safe Operation Area
Figure8. Switching wave
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SKQ50N03BD
DFN3.3X3.3 Package
information
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