SKYWORKS-SILICON-LABS-EFR32BG13P632F512IM48-D

EFR32BG13 Blue Gecko

Bluetooth

® Low  

Energy SoC Family Data Sheet  

The Blue Gecko Bluetooth Low Energy family of SoCs is part of  

the Wireless Gecko portfolio. Blue Gecko SoCs are ideal for ena-  

KEY FEATURES  

bling energy-friendly Bluetooth 5 networking for IoT devices.  

• 32-bit

 

ARM® Cortex®-M4 core with 40  

MHz maximum operating frequency  

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup  

times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-  

tures.  

• 512

 

kB of flash and 64 kB of RAM  

• Pin-compatible

 

across EFR32BG families  

(exceptions apply for 5V-tolerant pins)  

• 12-channel

 

Peripheral Reflex System  

enabling autonomous interaction of MCU  

peripherals  

Blue Gecko applications include:  

• IoT

 

Sensors and End Devices  

• Health

 

and Wellness  

• Autonomous

 

Hardware Crypto Accelerator  

and True Random Number Generator  

• Home

 

and Building Automation  

• Accessories  

• Precision

 

Low Frequency Oscillator meets  

BLE Sleep Clock accuracy requirements  

• Human

 

Interface Devices  

• Metering  

• Integrated

 

PA with up to 19 dBm (2.4  

GHz) or 20 dBm (Sub-GHz) tx power  

• Integrated

 

balun for 2.4 GHz  

• Commercial

 

and Retail Lighting and Sensing  

• Robust

 

peripheral set and up to 31 GPIO  

Core / Memory  

Clock Management  

Energy Management  

Other  

H-F Crystal  

Oscillator  

H-F  

RC Oscillator  

Voltage  

Regulator  

CRYPTO  

CRC  

Voltage Monitor  

Power-On Reset  

ARM Cortex

TM

M4 processor  

with DSP extensions, FPU and MPU  

Flash Program  

Memory  

Auxiliary H-F RC  

Oscillator  

Precision L-F  

RC Oscillator  

DC-DC  

Converter  

L-F Crystal  

Oscillator  

L-F RC  

Oscillator  

True Random  

Number Generator  

LDMA  

Controller  

Brown-Out  

Detector  

ETM  

Debug Interface  

RAM Memory  

Ultra L-F RC  

Oscillator  

SMU  

32-bit bus  

Peripheral Reflex System  

Radio Transceiver  

Serial  

I/O Ports  

Timers and Triggers  

Analog I/F  

Interfaces  

Sub GHz  

DEMOD  

ADC  

I

External  

Interrupts  

USART  

Timer/Counter  

Protocol Timer  

LNA  

RF Frontend  

Analog  

Comparator  

IFADC  

AGC  

PGA  

PA  

Low Energy  

UART

TM  

General  

Purpose I/O  

Low Energy  

Timer  

Low Energy  

Sensor Interface  

Q

IDAC  

To Sub GHz  

receive I/Q  

mixers and PA  

Capacitive  

Touch  

I

2

C  

Pin Reset  

Pulse Counter  

Watchdog Timer  

Cryotimer  

2.4 GHz  

LNA  

I

Frequency  

Synthesizer  

MOD  

VDAC  

Real Time  

Counter and  

Calendar  

RF Frontend  

BALUN  

Pin Wakeup  

Op-Amp  

PA  

To 2.4 GHz receive  

I/Q mixers and PA  

To Sub GHz  

and 2.4 GHz PA  

Q

Lowest power mode with peripheral operational:  

EM0—Active EM1—Sleep  

EM2—Deep Sleep  

EM3—Stop  

EM4—Hibernate  

EM4—Shutoff  

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Copyright © 2022 by Silicon Laboratories  

Rev. 1.7  

EFR32BG13 Blue Gecko

Bluetooth

® Low Energy SoC Family Data Sheet  

Feature List  

1. Feature

 

List  

The EFR32BG13 highlighted features are listed below.  

•

Low Power Wireless System-on-Chip  

•

Wide selection of MCU peripherals  

High Performance 32-bit 40 MHz ARM Cortex

®

-M4 with  

DSP instruction and floating-point unit for efficient signal  

processing  

•

•

• 12-bit

 

1 Msps SAR Analog to Digital Converter (ADC)  

• 2

 

× Analog Comparator (ACMP)  

• 2

 

× Digital to Analog Converter (VDAC)  

• 3

 

× Operational Amplifier (Opamp)  

• Embedded

 

Trace Macrocell (ETM) for advanced debugging  

• 512

 

kB flash program memory  

• Digital

 

to Analog Current Converter (IDAC)  

• Low-Energy

 

Sensor Interface (LESENSE)  

• Multi-channel

 

Capacitive Sense Interface (CSEN)  

• 64

 

kB RAM data memory  

• 2.4

 

GHz and Sub-GHz radio operation  

• Transmit

 

power:  

• Up

 

to 31 pins connected to analog channels (APORT)  

shared between analog peripherals  

• 2.4

 

GHz radio: Up to 19 dBm  

• Sub-GHz

 

radio: Up to 20 dBm  

• Up

 

to 31 General Purpose I/O pins with output state re-  

tention and asynchronous interrupts  

•

Low Energy Consumption  

• 8

 

Channel DMA Controller  

• 9.5

 

mA RX current at 1 Mbps, GFSK, 2.4 GHz  

• 8.4

 

mA RX current at 38.4 kbps, GFSK, 169 MHz  

• 8.5

 

mA TX current at 0 dBm output power at 2.4 GHz  

• 35.3

 

mA TX current at 14 dBm output power at 868 MHz  

• 69

 

μA/MHz in Active Mode (EM0)  

• 12

 

Channel Peripheral Reflex System (PRS)  

• 2

 

× 16-bit Timer/Counter  

• 3

 

or 4 Compare/Capture/PWM channels  

• 1

 

× 32-bit Timer/Counter  

• 3

 

Compare/Capture/PWM channels  

• Precision

 

Low Frequency RC Oscillator (PLFRCO)  

• 32-bit

 

Real Time Counter and Calendar  

• 16-bit

 

Low Energy Timer for waveform generation  

• 1.3

 

μA EM2 DeepSleep current (16 kB RAM retention and  

RTCC running from LFRCO)  

•

High Receiver Performance  

• -103.3

 

dBm sensitivity at 125 kbit/s GFSK, 2.4 GHz  

• -94.8

 

dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz  

• -91.5

 

dBm sensitivity at 2 Mbit/s GFSK, 2.4 GHz  

• -102.7

 

dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz  

• -126.2

 

dBm sensitivity at 600 bps, GFSK, 915 MHz  

• -120.6

 

dBm sensitivity at 2.4 kbps, GFSK, 868 MHz  

• -107.4

 

dBm sensitivity at 4.8 kbps, OOK, 433 MHz  

• -112.2

 

dBm sensitivity at 38.4 kbps, GFSK, 169 MHz  

•

Supported Modulation Formats  

• 32-bit

 

Ultra Low Energy Timer/Counter for periodic  

wake-up from any Energy Mode  

• 16-bit

 

Pulse Counter with asynchronous operation  

• 2

 

× Watchdog Timer with dedicated RC oscillator  

• 3

 

× Universal Synchronous/Asynchronous Receiver/  

Transmitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I

2

S)  

Low Energy UART (LEUART

™

)  

2 × I

2

C interface with SMBus support and address rec-  

ognition in EM3 Stop  

•

•

• 2/4

 

(G)FSK with fully configurable shaping  

• BPSK

 

/ DBPSK TX  

•

Wide Operating Range  

• 1.8

 

V to 3.8 V single power supply  

• OOK

 

/ ASK  

• Integrated

 

DC-DC, down to 1.8 V output with up to 200 mA  

load current for system  

• Shaped

 

OQPSK / (G)MSK  

• Configurable

 

DSSS and FEC  

• Standard

 

(-40 °C to 85 °C) and Extended (-40 °C to 125 °C)  

temperature grades available  

•

Supported Protocols  

Bluetooth

®

Low Energy (Bluetooth 5)  

•

•

Support for Internet Security  

• General

 

Purpose CRC  

• Proprietary

 

Protocols  

• Wireless

 

M-Bus  

• True

 

Random Number Generator  

• Selected

 

IEEE 802.15.4g SUN-FSK PHYs  

• Low

 

Power Wide Area Networks  

•

Suitable for Systems Targeting Compliance With:  

• FCC

 

Part 90.210 Mask D, FCC part 15.247, 15.231, 15.249  

• ETSI

 

Category I Operation, EN 300 220, EN 300 328  

• ARIB

 

T-108, T-96  

• 2

 

× Hardware Cryptographic Acceleration for AES 128/256,  

SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC  

•

QFN32 5×5 mm Package  

•

QFN48 7×7 mm Package  

• China

 

regulatory  

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| Building a more connected world.  

Rev. 1.7

 

| 2  

EFR32BG13 Blue Gecko

Bluetooth

® Low Energy SoC Family Data Sheet  

Ordering Information  

2. Ordering

 

Information  

Table 2.1.

 

Ordering Information  

Frequency Band  

@ Max TX Power  

2.4 GHz @ 19 dBm  

Sub-GHz @ 20 dBm  

2.4 GHz @ 19 dBm  

Protocol  

Stack  

Flash RAM  

Ordering Code  

(kB)  

(kB)  

GPIO Package Temp

 

Range  

EFR32BG13P733F512GM48-D  

Bluetooth LE  

Proprietary  

Bluetooth LE  

Proprietary  

Bluetooth LE  

Proprietary  

Bluetooth LE  

Proprietary  

Bluetooth LE  

Proprietary  

Bluetooth LE  

Proprietary  

Bluetooth LE  

Proprietary  

Bluetooth LE  

Proprietary  

Bluetooth LE  

Proprietary  

512  

64  

28  

31  

16  

31  

31  

16  

16  

31  

16  

QFN48  

QFN48  

QFN32  

QFN48  

QFN48  

QFN32  

QFN32  

QFN48  

QFN32  

-40 to +85°C  

-40 to +85°C  

-40 to +85°C  

-40 to +85°C  

-40 to +125°C  

-40 to +85°C  

-40 to +125°C  

-40 to +85°C  

-40 to +85°C  

EFR32BG13P732F512GM48-D  

EFR32BG13P732F512GM32-D  

EFR32BG13P632F512GM48-D  

EFR32BG13P632F512IM48-D  

EFR32BG13P632F512GM32-D  

EFR32BG13P632F512IM32-D  

EFR32BG13P532F512GM48-D  

EFR32BG13P532F512GM32-D  

512  

512  

512  

512  

512  

512  

512  

512  

64  

64  

64  

64  

64  

64  

64  

64  

2.4 GHz @ 19 dBm  

2.4 GHz @ 10 dBm  

2.4 GHz @ 10 dBm  

2.4 GHz @ 10 dBm  

2.4 GHz @ 10 dBm  

2.4 GHz @ 0 dBm  

2.4 GHz @ 0 dBm  

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| 3  

EFR32BG13 Blue Gecko

Bluetooth

® Low Energy SoC Family Data Sheet  

Ordering Information  

EFR32 X G 1 3 P 132 F 512 G

 

M 48

–

A R  

Tape and Reel (Optional)  

Revision  

Pin Count  

Package – M (QFN), L (BGA)  

Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)  

Flash Memory Size in kB  

Memory Type (Flash)  

Feature Set Code – r2r1r0  

r2: Reserved  

r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)  

r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)  

Performance Grade – P (Performance), B (Basic), V (Value)  

Device Configuration  

Series  

Gecko  

Family – M (Mighty), B (Blue), F (Flex)  

Wireless Gecko 32-bit  

Figure 2.1.

 

Ordering Code Key  

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Table of Contents  

1. Feature

 

List .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

2  

2. Ordering

 

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

3  

3. System

 

Overview .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.1 Introduction .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.2 Radio .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.2.1 Antenna

 

Interface .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .

 

9  

3.2.2 Fractional-N

 

Frequency Synthesizer

 

. . . . . . . . . . . . . . . . . . . . .

 

9  

3.2.3 Receiver

 

Architecture .

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

9  

3.2.4 Transmitter

 

Architecture . . . . . . . . . . . . . . . . . . . . . . . . .

 

9  

3.2.5 Wake

 

on Radio

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .10  

3.2.6 Flexible

 

Frame Handling

 

. . . . . . . . . . . . . . . . . . . . . . . . .10  

3.2.7 Packet

 

and State Trace

 

. . . . . . . . . . . . . . . . . . . . . . . . .10  

3.2.8 Data

 

Bufferin

g

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10  

3.2.9 Radio

 

Controller (RAC).

 

. . . . . . . . . . . . . . . . . . . . . . . . .10  

3.2.10 Random

 

Number Generator

 

. . . . . . . . . . . . . . . . . . . . . . .10  

3.3 Power

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  

3.3.1 Energy

 

Management Unit (EMU)

 

. . . . . . . . . . . . . . . . . . . . . .11  

3.3.2 DC-DC

 

Converter .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .11  

3.3.3 Power

 

Domains .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .11  

3.4 General

 

Purpose Input/Output (GPIO)

 

. . . . . . . . . . . . . . . . . . . . . .11  

3.5 Clocking .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  

3.5.1 Clock

 

Management Unit (CMU) .

 

. . . . . . . . . . . . . . . . . . . . . .12  

3.5.2 Internal

 

and External Oscillators.

 

. . . . . . . . . . . . . . . . . . . . . .12  

3.6 Counters/Timers

 

and PWM .

 

. . . . . . . . . . . . . . . . . . . . . . . . .12  

3.6.1 Timer/Counter

 

(TIMER) .

 

. . . . . . . . . . . . . . . . . . . . . . . .12  

3.6.2 Wide

 

Timer/Counter (WTIMER) .

 

. . . . . . . . . . . . . . . . . . . . . .12  

3.6.3 Real

 

Time Counter and Calendar (RTCC)

 

. . . . . . . . . . . . . . . . . . .12  

3.6.4 Low

 

Energy Timer (LETIMER)

 

. . . . . . . . . . . . . . . . . . . . . . .13  

3.6.5 Ultra

 

Low Power Wake-up Timer (CRYOTIMER)

 

. . . . . . . . . . . . . . . . .13  

3.6.6 Pulse

 

Counter (PCNT) .

 

. . . . . . . . . . . . . . . . . . . . . . . . .13  

3.6.7 Watchdog

 

Timer (WDOG

)

.

 

. . . . . . . . . . . . . . . . . . . . . . .

.

13  

3.7 Communications

 

and Other Digital Peripherals

 

. . . . . . . . . . . . . . . . . . .13  

3.7.1 Universal

 

Synchronous/Asynchronous Receiver/Transmitter (USART) .

 

. . . . . . . . .13  

3.7.2 Low

 

Energy Universal Asynchronous Receiver/Transmitter (LEUART) .

 

. . . . . . . . .13  

2

3.7.3 Inter-Integrated

 

Circuit Interface (I

 

C) .

 

. . . . . . . . . . . . . . . . . . . .13  

3.7.4 Peripheral

 

Reflex System (PRS)

 

. . . . . . . . . . . . . . . . . . . . . .13  

3.7.5 Low

 

Energy Sensor Interface (LESENSE)

 

. . . . . . . . . . . . . . . . . . .14  

3.8 Security

 

Features .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .14  

3.8.1 General

 

Purpose Cyclic Redundancy Check (GPCRC)

 

. . . . . . . . . . . . . . .14  

3.8.2 Crypto

 

Accelerator (CRYPTO)

 

. . . . . . . . . . . . . . . . . . . . . . .14  

3.8.3 True

 

Random Number Generator (TRNG)

 

. . . . . . . . . . . . . . . . . . .14  

3.8.4 Security

 

Management Unit (SMU)

 

. . . . . . . . . . . . . . . . . . . . . .14  

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3.9 Analo

g

.

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14  

3.9.1 Analog

 

Port (APORT)

 

. . . . . . . . . . . . . . . . . . . . . . . . . .14  

3.9.2 Analog

 

Comparator (ACMP) .

 

. . . . . . . . . . . . . . . . . . . . . . .14  

3.9.3 Analog

 

to Digital Converter (ADC)

 

. . . . . . . . . . . . . . . . . . . . . .15  

3.9.4 Capacitive

 

Sense (CSEN

)

.

 

. . . . . . . . . . . . . . . . . . . . . . .

.

15  

3.9.5 Digital

 

to Analog Current Converter (IDAC)

 

. . . . . . . . . . . . . . . . . . .15  

3.9.6 Digital

 

to Analog Converter (VDAC)

 

. . . . . . . . . . . . . . . . . . . . .15  

3.9.7 Operational

 

Amplifiers .

 

. . . . . . . . . . . . . . . . . . . . . . . . .15  

3.10 Reset

 

Management Unit (RMU) .

 

. . . . . . . . . . . . . . . . . . . . . . .15  

3.11 Core

 

and Memory

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .15  

3.11.1 Processor

 

Core .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .15  

3.11.2 Memory

 

System Controller (MSC)

 

. . . . . . . . . . . . . . . . . . . . .16  

3.11.3 Linked

 

Direct Memory Access Controller (LDMA)

 

. . . . . . . . . . . . . . . .16  

3.12 Memory

 

Map .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .17  

3.13 Configuration

 

Summary . . . . . . . . . . . . . . . . . . . . . . . . . .19  

4. Electrical

 

Specifications .

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

20  

4.1 Electrical

 

Characteristics .

 

. . . . . . . . . . . . . . . . . . . . . . . . .20  

4.1.1 Absolute

 

Maximum Ratings

 

. . . . . . . . . . . . . . . . . . . . . . . .21  

4.1.2 Operating

 

Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .23  

4.1.3 Thermal

 

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .25  

4.1.4 DC-DC

 

Converter .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .26  

4.1.5 Current

 

Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .28  

4.1.6 Wake

 

Up Times

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .38  

4.1.7 Brown

 

Out Detector (BOD)

 

. . . . . . . . . . . . . . . . . . . . . . . .39  

4.1.8 Frequency

 

Synthesize

r

. . . . . . . . . . . . . . . . . . . . . . . . .

.

40  

4.1.9 2.4

 

GHz RF Transceiver Characteristics .

 

. . . . . . . . . . . . . . . . . . .41  

4.1.10 Sub-GHz

 

RF Transceiver Characteristics

 

. . . . . . . . . . . . . . . . . . .57  

4.1.11 Modem.

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82  

4.1.12 Oscillators

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .83  

4.1.13 Flash

 

Memory Characteristics

 

. . . . . . . . . . . . . . . . . . . . . . .88  

4.1.14 General-Purpose

 

I/O (GPIO)

 

. . . . . . . . . . . . . . . . . . . . . . .89  

4.1.15 Voltage

 

Monitor (VMON

)

.

 

. . . . . . . . . . . . . . . . . . . . . . .

.

91  

4.1.16 Analog

 

to Digital Converter (ADC)

 

. . . . . . . . . . . . . . . . . . . . .92  

4.1.17 Analog

 

Comparator (ACMP)

 

. . . . . . . . . . . . . . . . . . . . . . .94  

4.1.18 Digital

 

to Analog Converter (VDAC)

 

. . . . . . . . . . . . . . . . . . . . .96  

4.1.19 Current

 

Digital to Analog Converter (IDAC)

 

. . . . . . . . . . . . . . . . . .99  

4.1.20 Capacitive

 

Sense (CSEN)  

4.1.21 Operational

 

Amplifier (OPAMP)  

. . . . . . . . . . . . . . . . . . . . . .

.

1

01  

. . . . . . . . . . . . . . . . . . . .

1

.

 

03  

4.1.22 Pulse

 

Counter (PCNT)  

. . . . . . . . . . . . . . . . . . . . . . .

1

.

 

06  

4.1.23 Analog

 

Port (APORT) .

 

. . . . . . . . . . . . . . . . . . . . . . . .

 

106  

4.1.24 I2C

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

107  

4.1.25 USART

 

SPI .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .

.

1

10  

4.2 Typical

 

Performance Curves  

. . . . . . . . . . . . . . . . . . . . . . .

.

1

11  

4.2.1 Supply

 

Current  

4.2.2 DC-DC

 

Converter  

4.2.3 2.4

 

GHz Radio  

. . . . . . . . . . . . . . . . . . . . . . . . . .

1

.

 

12  

. . . . . . . . . . . . . . . . . . . . . . . . .

1

.

1

8  

. . . . . . . . . . . . . . . . . . . . . . . . . .

 

1

.20  

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5. Typical

 

Connection Diagrams

 

. . . . . . . . . . . . . . . . . . . . . . . .122  

5.1 Power

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

122  

5.2 RF

 

Matching Networks  

. . . . . . . . . . . . . . . . . . . . . . . . . .124  

5.3 Other

 

Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

125  

6. Pin

 

Definitions .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

126  

6.1 QFN48

 

2.4 GHz and Sub-GHz Device Pinout.

 

. . . . . . . . . . . . . . . . . .

 

126  

6.2 QFN48

 

2.4 GHz Device Pinout  

6.3 QFN32

 

2.4 GHz Device Pinout  

6.4 GPIO

 

Functionality Table  

. . . . . . . . . . . . . . . . . . . . . .

 

1

.

2

8  

. . . . . . . . . . . . . . . . . . . . . .

 

1

.

3

0  

. . . . . . . . . . . . . . . . . . . . . . . .

1

.

 

32  

6.5 Alternate

 

Functionality Overview

 

. . . . . . . . . . . . . . . . . . . . . . .

 

159  

6.6 Analog

 

Port (APORT) Client Maps

 

. . . . . . . . . . . . . . . . . . . . .

.

171  

7. QFN48

 

Package Specifications.

 

. . . . . . . . . . . . . . . . . . . . . . .

 

180  

7.1 QFN48

 

Package Dimensions

 

. . . . . . . . . . . . . . . . . . . . . . .

.

1

80  

7.2 QFN48

 

PCB Land Pattern

 

. . . . . . . . . . . . . . . . . . . . . . . . .182  

7.3 QFN48

 

Package Marking  

. . . . . . . . . . . . . . . . . . . . . . . .

.

184  

8. RQFN32

 

Package Specifications

 

. . . . . . . . . . . . . . . . . . . . . .

.

1

85  

8.1 RQFN32

 

Package Dimensions  

8.2 RQFN32

 

PCB Land Pattern  

. . . . . . . . . . . . . . . . . . . . . .

 

1

.

8

5  

. . . . . . . . . . . . . . . . . . . . . . .

 

1

.87  

8.3 RQFN32

 

Package Marking

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

189  

9. Revision

 

History .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .190  

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EFR32BG13 Blue Gecko

Bluetooth

® Low Energy SoC Family Data Sheet  

System Overview  

3. System

 

Overview  

3.1 Introduction  

The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for  

any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a  

short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG13 Reference  

Manual.  

A block diagram of the EFR32BG13 family is shown in

Figure 3.1 Detailed EFR32BG13 Block Diagram on page 8

. The diagram  

shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult  

Ordering Information

.  

Radio Transceiver  

Port I/O Configuration  

Digital Peripherals  

IOVDD  

Sub-GHz RF  

SUBGRF_IP  

SUBGRF_IN  

SUBGRF_OP  

SUBGRF_ON  

I

DEMOD  

IFADC  

AGC  

LNA  

LETIMER  

PA  

Port A  

Drivers  

PGA  

Q

PAn  

TIMER  

CRYOTIMER  

PCNT  

2.4 GHz RF  

I

Frequency  

LNA  

Synthesizer  

Port B  

Drivers  

PBn  

PCn  

PDn  

PFn  

2G4RF_IOP  

2G4RF_ION  

To RF  

MOD  

BALUN  

PA  

Frontend  

Circuits  

RTC / RTCC  

USART  

Q

Port  

Mapper  

Port C  

Drivers  

LEUART  

I2C  

Reset  

Management  

Unit  

ARM Cortex-M4 Core  

RESETn  

Port D  

Serial Wire  

and ETM  

Debug /  

512 KB ISP Flash  

Program Memory  

CRYPTO  

CRC  

Drivers  

Debug Signals  

(shared w/GPIO)  

Brown Out /  

Power-On  

Reset  

A

H

B

A

P

B

64 KB RAM  

Memory Protection Unit  

Floating Point Unit  

DMA Controller  

Programming  

Port F  

Drivers  

LESENSE  

Energy Management  

Analog Peripherals  

PAVDD  

RFVDD  

IOVDD  

AVDD  

IDAC  

Voltage  

Monitor  

–

+

Watchdog  

Timer  

VDAC  

DVDD  

bypass  

Op-Amp  

VDD  

Internal  

Reference  

Clock Management  

ULFRCO  

VREGVDD  

VREGSW  

DC-DC  

Converter  

Voltage  

Regulator  

AUXHFRCO  

PLFRCO  

12-bit ADC  

DECOUPLE  

Temp  

LFRCO  

Sense  

LFXTAL_P  

LFXTAL_N  

HFXTAL_P  

HFXTAL_N  

LFXO  

Capacitive  

Touch  

HFRCO  

+

–

HFXO  

Analog Comparator  

Figure 3.1.

 

Detailed EFR32BG13 Block Diagram  

3.2 Radio  

The Blue Gecko family features a radio transceiver supporting Bluetooth Low Energy

®

and proprietary short range wireless protocols.  

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System Overview  

3.2.1 Antenna

 

Interface  

The EFR32BG13 family includes devices which support both single-band and dual-band RF communication over separate physical RF  

interfaces.  

The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The  

2G4RF_ION pin should be grounded externally.  

The sub-GHz antenna interface consists of a differential transmit interface (pins SUBGRF_OP and SUBGRF_ON) and a differential re-  

ceive interface (pinsSUBGRF_IP and SUBGRF_IN).  

The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching  

Networks section.  

3.2.2 Fractional-N

 

Frequency Synthesizer  

The EFR32BG13 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is  

used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly  

generate the modulated RF carrier.  

The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with  

low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to  

optimize system energy consumption.  

3.2.3 Receiver

 

Architecture  

The EFR32BG13 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion  

mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital  

converter (IFADC).  

The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-  

ing flexibility with respect to known interferers at the image frequency.  

The Automatic Gain Control (AGC) block adjusts the receiver gain to optimize performance and avoid saturation for excellent selectivity  

and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz radio  

can be calibrated on-demand by the user for the desired frequency band.  

Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-  

ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and  

compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by  

block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS) for 2.4 GHz and sub-GHz bands.  

A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-  

nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received  

frame and the dynamic RSSI measurement can be monitored throughout reception.  

The EFR32BG13 features integrated support for antenna diversity to mitigate the problem of frequency-selective fading due to multi-  

path propagation and improve link budget. Support for antenna diversity is available for specific PHY configurations in 2.4 GHz and  

sub-GHz bands. Internal configurable hardware controls an external switch for automatic switching between antennae during RF re-  

ceive detection operations.  

Note:

Due to the shorter preamble of 802.15.4 and BLE packets, RX diversity is not supported.  

3.2.4 Transmitter

 

Architecture  

The EFR32BG13 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls  

phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping  

filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-  

ing.  

Carrier Sense Multiple Access – Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by  

the EFR32BG13. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-  

tween devices that otherwise lack synchronized RF channel access.  

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System Overview  

3.2.5 Wake

 

on Radio  

The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-  

ing a subsystem of the EFR32BG13 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-  

als.  

3.2.6 Flexible

 

Frame Handling  

EFR32BG13 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.  

The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-  

tor:  

• Highly

 

adjustable preamble length  

• Up

 

to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts  

• Frame

 

disassembly and address matching (filtering) to accept or reject frames  

• Automatic

 

ACK frame assembly and transmission  

• Fully

 

flexible CRC generation and verification:  

• Multiple

 

CRC values can be embedded in a single frame  

• 8,

 

16, 24 or 32-bit CRC value  

• Configurable

 

CRC bit and byte ordering  

• Selectable

 

bit-ordering (least significant or most significant bit first)  

• Optional

 

data whitening  

• Optional

 

Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding  

• Half

 

rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing  

• Optional

 

symbol interleaving, typically used in combination with FEC  

• Symbol

 

coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware  

• UART

 

encoding over air, with start and stop bit insertion / removal  

• Test

 

mode support, such as modulated or unmodulated carrier output  

• Received

 

frame timestamping  

3.2.7 Packet

 

and State Trace  

The EFR32BG13 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.  

It features:  

• Non-intrusive

 

trace of transmit data, receive data and state information  

• Data

 

observability on a single-pin UART data output, or on a two-pin SPI data output  

• Configurable

 

data output bitrate / baudrate  

• Multiplexed

 

transmitted data, received data and state / meta information in a single serial data stream  

3.2.8 Data

 

Buffering  

The EFR32BG13 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64  

bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.  

3.2.9 Radio

 

Controller (RAC)  

The Radio Controller controls the top level state of the radio subsystem in the EFR32BG13. It performs the following tasks:  

• Precisely-timed

 

control of enabling and disabling of the receiver and transmitter circuitry  

• Run-time

 

calibration of receiver, transmitter and frequency synthesizer  

• Detailed

 

frame transmission timing, including optional LBT or CSMA-CA  

3.2.10 Random

 

Number Generator  

The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.  

The data is suitable for use in cryptographic applications.  

Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-  

ber generator algorithms such as Fortuna.  

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System Overview  

3.3 Power  

The EFR32BG13 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only  

a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator  

can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-  

tor.  

The EFR32BG13 device family includes support for internal supply voltage scaling, as well as two different power domains groups for  

peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.  

AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will  

operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.  

Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB  

components, supplying up to a total of 200 mA.  

3.3.1 Energy

 

Management Unit (EMU)  

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and  

features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM  

blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi-  

ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has  

fallen below a chosen threshold.  

3.3.2 DC-DC

 

Converter  

The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2  

and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation  

of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,  

short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low  

for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance  

switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-  

sients.  

3.3.3 Power

 

Domains  

The EFR32BG13 has two peripheral power domains for operation in EM2 and EM3. If all of the peripherals in a peripheral power do-  

main are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall cur-  

rent consumption of the device.  

Table 3.1.

 

Peripheral Power Subdomains  

Peripheral Power Domain 1  

Peripheral Power Domain 2  

ACMP0  

PCNT0  

ADC0  

ACMP1  

CSEN  

VDAC0  

LEUART0  

I2C0  

LETIMER0  

LESENSE  

APORT  

–

I2C1  

IDAC  

3.4 General

 

Purpose Input/Output (GPIO)  

EFR32BG13 has up to 31 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or  

input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO  

pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to  

several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-  

als. The GPIO subsystem supports asynchronous external pin interrupts.  

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System Overview  

3.5 Clocking  

3.5.1 Clock

 

Management Unit (CMU)  

The Clock Management Unit controls oscillators and clocks in the EFR32BG13. Individual enabling and disabling of clocks to all periph-  

erals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows  

software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscilla-  

tors.  

3.5.2 Internal

 

and External Oscillators  

The EFR32BG13 supports two crystal oscillators and fully integrates five RC oscillators, listed below.  

• A

 

high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-  

ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can  

also be applied to the HFXO input for improved accuracy over temperature.  

• A

 

32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.  

• An

 

integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The  

HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.  

• An

 

integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial  

Wire Viewer port with a wide frequency range.  

• An

 

integrated low frequency precision 32.768 kHz RC oscillator (PLFRCO) can be used as a timing reference in low energy modes,  

with 500 ppm accuracy.  

• An

 

integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-  

tal accuracy is not required.  

• An

 

integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-  

sumption in low energy modes.  

3.6 Counters/Timers

 

and PWM  

3.6.1 Timer/Counter

 

(TIMER)  

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the  

PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one  

of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output  

reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width  

modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional  

dead-time insertion available in timer unit TIMER_0 only.  

3.6.2 Wide

 

Timer/Counter (WTIMER)  

WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM  

outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to  

4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a  

buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh-  

old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by  

the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.  

3.6.3 Real

 

Time Counter and Calendar (RTCC)  

The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a  

Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-  

tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving  

frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy  

and convenient data storage in all energy modes down to EM4H.  

A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli-  

cation software.  

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3.6.4 Low

 

Energy Timer (LETIMER)  

The unique LETIMER is a 16-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This  

allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed  

while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-  

forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-  

figured to start counting on compare matches from the RTCC.  

3.6.5 Ultra

 

Low Power Wake-up Timer (CRYOTIMER)  

The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal  

oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events  

and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-  

rupt periods, facilitating flexible ultra-low energy operation.  

3.6.6 Pulse

 

Counter (PCNT)  

The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The  

clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from  

among any of the internal oscillators, except the AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep,  

EM2 Deep Sleep, and EM3 Stop.  

3.6.7 Watchdog

 

Timer (WDOG)  

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed  

monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can  

also monitor autonomous systems driven by PRS.  

3.7 Communications

 

and Other Digital Peripherals  

3.7.1 Universal

 

Synchronous/Asynchronous Receiver/Transmitter (USART)  

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous  

UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-  

porting:  

• ISO7816

 

SmartCards  

• IrDA  

I

2

S  

•

3.7.2 Low

 

Energy Universal Asynchronous Receiver/Transmitter (LEUART)  

The unique LEUART

TM

provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow  

UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication  

possible with a minimum of software intervention and energy consumption.  

3.7.3 Inter-Integrated

 

Circuit Interface (I

2

C)  

The I

2

C interface enables communication between the MCU and a serial I

2

C bus. It is capable of acting as both a master and a slave  

and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates  

from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system.  

The interface provided to software by the I

2

C peripheral allows precise timing control of the transmission process and highly automated  

transfers. Automatic recognition of slave addresses is provided in active and low energy modes.  

3.7.4 Peripheral

 

Reflex System (PRS)  

The Peripheral Reflex System provides a communication network between different peripherals without software involvement. Peripher-  

als producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals, which in  

turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied  

by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.  

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3.7.5 Low

 

Energy Sensor Interface (LESENSE)  

The Low Energy Sensor Interface LESENSE

TM

is a highly configurable sensor interface with support for up to 16 individually configura-  

ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and  

measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a  

programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is  

available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy  

budget.  

3.8 Security

 

Features  

3.8.1 General

 

Purpose Cyclic Redundancy Check (GPCRC)  

The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The suppor-  

ted 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the  

needs of the application.  

3.8.2 Crypto

 

Accelerator (CRYPTO)  

The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-  

port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2

m

), SHA-1 and SHA-2 (SHA-224 and  

SHA-256).  

Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.  

Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.  

The CRYPTO1 block is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on  

data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention.  

CRYPTO also provides trigger signals for DMA read and write operations.  

3.8.3 True

 

Random Number Generator (TRNG)  

The TRNG is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with NIST800-22  

and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key generation).  

3.8.4 Security

 

Management Unit (SMU)  

The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the  

Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to  

the peripheral’s register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and  

can optionally generate an interrupt.  

3.9 Analog  

3.9.1 Analog

 

Port (APORT)  

The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins.  

Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are  

grouped by X/Y pairs.  

3.9.2 Analog

 

Comparator (ACMP)  

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-  

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption  

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The  

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the  

programmable threshold.  

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3.9.3 Analog

 

to Digital Converter (ADC)  

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output  

sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.  

The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of  

sources, including pins configurable as either single-ended or differential.  

3.9.4 Capacitive

 

Sense (CSEN)  

The CSEN peripheral is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a  

switches and sliders. The CSEN peripheral uses a charge ramping measurement technique, which provides robust sensing even in  

adverse conditions including radiated noise and moisture. The peripheral can be configured to take measurements on a single port pin  

or scan through multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the  

combined capacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an aver-  

aging filter, as well as digital threshold comparators to reduce software overhead.  

3.9.5 Digital

 

to Analog Current Converter (IDAC)  

The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC  

input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of  

various step sizes.  

3.9.6 Digital

 

to Analog Converter (VDAC)  

The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500  

ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-  

ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications  

such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low  

frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any  

CPU intervention. The VDAC is available in all energy modes down to and including EM3.  

3.9.7 Operational

 

Amplifiers  

The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and  

are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple  

common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to  

rail output. They can be used in conjunction with the VDAC peripheral or in stand-alone configurations. The opamps save energy, PCB  

space, and cost as compared with standalone opamps because they are integrated on-chip.  

3.10 Reset

 

Management Unit (RMU)  

The RMU is responsible for handling reset of the EFR32BG13. A wide range of reset sources are available, including several power  

supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.  

3.11 Core

 

and Memory  

3.11.1 Processor

 

Core  

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:  

• ARM

 

Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz  

• Memory

 

Protection Unit (MPU) supporting up to 8 memory segments  

• Up

 

to 512 kB flash program memory  

• Up

 

to 64 kB RAM data memory  

• Configuration

 

and event handling of all peripherals  

• 2-pin

 

Serial-Wire debug interface  

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3.11.2 Memory

 

System Controller (MSC)  

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable  

from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code  

is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a  

read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-  

ergy modes EM0 Active and EM1 Sleep.  

3.11.3 Linked

 

Direct Memory Access Controller (LDMA)  

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This  

reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-  

phisticated operations to be implemented.  

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3.12 Memory

 

Map  

The EFR32BG13 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.  

Figure 3.2.

 

EFR32BG13 Memory Map — Core Peripherals and Code Space  

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Figure 3.3.

 

EFR32BG13 Memory Map — Peripherals  

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3.13 Configuration

 

Summary  

The features of the EFR32BG13 are a subset of the feature set described in the device reference manual. The table below describes  

device specific implementation of the features. Remaining peripherals support full configuration.  

Table 3.2.

 

Configuration Summary  

Peripheral  

Configuration  

IrDA  

Pin Connections  

USART0  

US0_TX, US0_RX, US0_CLK, US0_CS  

SmartCard  

I

2

S  

USART1  

USART2  

US1_TX, US1_RX, US1_CLK, US1_CS  

US2_TX, US2_RX, US2_CLK, US2_CS  

SmartCard  

IrDA  

SmartCard  

with DTI  

–

TIMER0  

TIMER1  

WTIMER0  

TIM0_CC[2:0], TIM0_CDTI[2:0]  

TIM1_CC[3:0]  

with DTI  

WTIM0_CC[2:0], WTIM0_CDTI[2:0]  

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4. Electrical

 

Specifications  

4.1 Electrical

 

Characteristics  

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:  

• Typical

 

values are based on T

AMB

=25 °C and V

DD

= 3.3 V, by production test and/or technology characterization.  

• Radio

 

performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-  

er-specific external RF impedance-matching networks for interfacing to a 50 Ω source or load.  

• Minimum

 

and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,  

unless stated otherwise.  

Refer to

4.1.2.1 General Operating Conditions

for more details about operational supply and temperature limits.  

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4.1.1 Absolute

 

Maximum Ratings  

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of  

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure  

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-  

bility data, see the Quality and Reliability Monitor Report at

.  

Table 4.1.

 

Absolute Maximum Ratings  

Parameter  

Symbol  

T

STG  

Test Condition  

Min  

-50  

-0.3  

—

Typ  

—

Max  

150  

3.8  

1

Unit  

°C  

Storage temperature range  

Voltage on any supply pin  

V

DDMAX  

V

DDRAMPMAX  

—

V

Voltage ramp rate on any  

supply pin  

—

V / µs  

5V tolerant GPIO pins

1 2 3  

Standard GPIO pins  

DC voltage on any GPIO pin

 

V

DIGPIN  

-0.3  

—

Min of 5.25  

and IOVDD  

+2  

V

-0.3  

-0.3  

—

—

—

—

IOVDD+0.3  

V

V

Voltage on HFXO pins  

V

HFXOPIN  

1.4  

10  

Input RF level on pins  

2G4RF_IOP and  

2G4RF_ION  

P

RFMAX2G4  

dBm  

Voltage differential between

 

V

MAXDIFF2G4  

RF pins (2G4RF_IOP –  

2G4RF_ION)  

-50  

—

—

50  

mV  

V

Absolute voltage on RF pins

 

V

MAX2G4  

2G4RF_IOP and  

-0.3  

3.8  

2G4RF_ION  

Absolute voltage on Sub-  

GHz RF pins  

V

MAXSUBG  

Pins SUBGRF_OP and  

SUBGRF_ON  

-0.3  

-0.3  

—

—

—

—

—

3.8  

0.3  

V

V

Pins SUBGRF_IP and  

SUBGRF_IN,  

Total current into VDD power

 

I

VDDMAX  

lines  

Source  

200  

200  

mA  

mA  

Total current into VSS  

ground lines  

I

VSSMAX  

Sink  

—

Current per I/O pin  

I

IOMAX  

Sink  

—

—

—

—

—

—

—

—

50  

50  

mA  

mA  

mA  

mA  

°C  

Source  

Current for all I/O pins  

Junction temperature  

I

IOALLMAX  

Sink  

—

200  

200  

105  

125  

Source  

—

T

J  

-G grade devices  

-I grade devices  

-40  

-40  

°C  

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Parameter  

Note:  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

1. When a GPIO pin is routed to the analog block through the APORT, the maximum voltage = IOVDD.  

2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source  

below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the  

maximum IO current specifications.  

3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.  

Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.  

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4.1.2 Operating

 

Conditions  

When assigning supply sources, the following requirements must be observed:  

• VREGVDD

 

must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies.  

• VREGVDD

 

= AVDD  

• DVDD

 

≤ AVDD  

• IOVDD

 

≤ AVDD  

• RFVDD

 

≤ AVDD  

• PAVDD

 

≤ AVDD  

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4.1.2.1 General

 

Operating Conditions  

Table 4.2.

 

General Operating Conditions  

Parameter  

Symbol  

Test Condition  

Min  

-40  

-40  

1.8  

Typ  

25  

Max  

85  

Unit  

°C  

°C  

V

Operating ambient tempera-

 

T

A  

ture range

1  

-G temperature grade  

-I temperature grade  

25  

125  

3.8  

AVDD supply voltage

2  

V

AVDD  

3.3  

VREGVDD operating supply

 

V

VREGVDD  

voltage

2 3  

DCDC in regulation  

2.4  

1.8  

1.8  

3.3  

3.3  

3.3  

3.8  

3.8  

3.8  

V

V

V

DCDC in bypass, 50mA load  

DCDC not in use. DVDD external-  

ly shorted to VREGVDD  

VREGVDD current  

I

VREGVDD  

DCDC in bypass, T ≤ 85 °C  

DCDC in bypass, T > 85 °C  

—

—

—

—

—

200  

100  

mA  

mA  

V

RFVDD operating supply  

voltage  

V

RFVDD  

1.62  

V

VREGVDD  

DVDD operating supply volt-

 

V

DVDD  

age  

1.62  

1.62  

1.62  

0.75  

—

—

V

VREGVDD  

V

VREGVDD  

V

VREGVDD  

2.75  

V

V

PAVDD operating supply  

voltage  

V

PAVDD  

All IOVDD pins

4  

IOVDD operating supply volt-

 

V

IOVDD  

age  

—

V

DECOUPLE output capaci-  

tor

5 6  

C

DECOUPLE  

1.0  

µF  

Difference between AVDD  

dV

DD  

—

—

0.1  

V

and VREGVDD, ABS(AVDD-  

VREGVDD)

2  

HFCORECLK frequency  

f

CORE  

VSCALE2, MODE = WS1  

VSCALE2, MODE = WS0  

VSCALE0, MODE = WS2  

VSCALE0, MODE = WS1  

VSCALE0, MODE = WS0  

VSCALE2  

—

—

—

—

—

—

—

—

—

—

—

—

—

—

40  

25  

20  

14  

7

MHz  

MHz  

MHz  

MHz  

MHz  

MHz  

MHz  

HFCLK frequency  

f

HFCLK  

40  

20  

VSCALE0  

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Parameter  

Note:  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

1. The maximum limit on T

A

may be lower due to device self-heating, which depends on the power dissipation of the specific appli-  

cation. T

A

(max) = T

J

(max) – (THETA

JA

x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal  

Characteristics table for T

J

and THETA

JA  

.

2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.  

3. The minimum voltage required in bypass mode is calculated using R

BYP

from the DCDC specification table. Requirements for  

other loads can be calculated as V

DVDD_min

+I

LOAD

* R

BYP_max  

.

4. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.  

5. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-  

ue stays within the specified bounds across temperature and DC bias.  

6. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transi-  

tion, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70  

mA (with a 2.7 µF capacitor).  

4.1.3 Thermal

 

Characteristics  

Table 4.3.

 

Thermal Characteristics  

Parameter  

Symbol  

Test Condition  

Min  

—

—

—

—

—

—

—

—

—

Typ  

75.7  

61.5  

55.4  

30.2  

26.3  

24.9  

30.1  

24.9  

23.9  

Max  

—

—

—

—

—

—

—

—

—

Unit  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

Thermal resistance, QFN48

 

THETA

JA_QFN48

2-Layer PCB, Air velocity = 0 m/s  

Package  

2-Layer PCB, Air velocity = 1 m/s  

2-Layer PCB, Air velocity = 2 m/s  

4-Layer PCB, Air velocity = 0 m/s  

4-Layer PCB, Air velocity = 1 m/s  

4-Layer PCB, Air velocity = 2 m/s  

Thermal resistance, QFN32

 

THETA

JA_QFN32

4-Layer PCB, Air velocity = 0 m/s  

Package  

4-Layer PCB, Air velocity = 1 m/s  

4-Layer PCB, Air velocity = 2 m/s  

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4.1.4 DC-DC

 

Converter  

Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3  

V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.  

Table 4.4.

 

DC-DC Converter  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Input voltage range  

V

DCDC_I  

Bypass mode, I

DCDC_LOAD

= 50  

mA  

1.8  

—

V

VREGVDD_  

V

MAX  

Low noise (LN) mode, 1.8 V out-  

put, I

DCDC_LOAD

= 100 mA, or  

Low power (LP) mode, 1.8 V out-  

put, I

DCDC_LOAD

= 10 mA  

2.4  

—

V

VREGVDD_  

V

MAX  

Low noise (LN) mode, 1.8 V out-  

put, I

DCDC_LOAD

= 200 mA  

2.6  

1.8  

—

—

V

VREGVDD_  

V

V

MAX  

Output voltage programma-

 

V

DCDC_O  

ble range

1  

V

VREGVDD  

Regulation DC accuracy  

ACC

DC  

Low Noise (LN) mode, 1.8 V tar-  

get output  

1.7  

—

—

1.9  

2.2  

V

V

Regulation window

2  

WIN

REG  

Low Power (LP) mode,  

LPCMPBIASEMxx

3

= 0, 1.8 V tar-  

get output, I

DCDC_LOAD

≤ 75 µA  

1.63  

Low Power (LP) mode,  

1.63  

—

2.1  

V

LPCMPBIASEMxx

3

= 3, 1.8 V tar-  

get output, I

DCDC_LOAD

≤ 10 mA  

Steady-state output ripple  

V

R  

Radio disabled  

—

—

3

—

mVpp  

mV  

CCM Mode (LNFORCECCM

3

=  

1), Load changes between 0 mA  

and 100 mA  

Output voltage under/over-  

shoot  

V

OV  

25  

60  

DCM Mode (LNFORCECCM

3

=  

0), Load changes between 0 mA  

and 10 mA  

—

45  

90  

mV  

Overshoot during LP to LN  

CCM/DCM mode transitions com-  

pared to DC level in LN mode  

—

—

200  

40  

—

—

mV  

mV  

Undershoot during BYP/LP to LN  

CCM (LNFORCECCM

3

= 1) mode  

transitions compared to DC level  

in LN mode  

Undershoot during BYP/LP to LN  

—

100  

—

mV  

DCM (LNFORCECCM

3

= 0) mode  

transitions compared to DC level  

in LN mode  

DC line regulation  

DC load regulation  

V

REG  

Input changes between  

V

VREGVDD_MAX

and 2.4 V  

—

—

0.1  

0.1  

—

—

%

%

I

REG  

Load changes between 0 mA and  

100 mA in CCM mode  

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Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Max load current  

I

LOAD_MAX  

Low noise (LN) mode, Heavy  

Drive

4

, T ≤ 85 °C  

—

—

200  

mA  

Low noise (LN) mode, Heavy  

Drive

4

, T > 85 °C  

—

—

—

—

—

1

—

—

—

—

—

4.7  

100  

100  

50  

mA  

mA  

mA  

µA  

Low noise (LN) mode, Medium  

Drive

4  

Low noise (LN) mode, Light  

Drive

4  

Low power (LP) mode,  

LPCMPBIASEMxx

3

= 0  

75  

Low power (LP) mode,  

LPCMPBIASEMxx

3

= 3  

10  

mA  

µF  

DCDC nominal output ca-  

pacitor

5  

C

DCDC  

25% tolerance  

4.7  

DCDC nominal output induc-

 

L

DCDC  

tor  

20% tolerance  

4.7  

—

4.7  

1.2  

4.7  

2.5  

µH  

Ω

Resistance in Bypass mode

 

R

BYP  

Note:  

1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, V

VREGVDD  

.

2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.  

3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the  

EMU_DCDCLOEM01CFG register, depending on the energy mode.  

4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-  

um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.  

5. Output voltage under/over-shoot and regulation are specified with C

DCDC

4.7 µF. Different settings for DCDCLNCOMPCTRL  

must be used if C

DCDC

is lower than 4.7 µF. See Application Note AN0948 for details.  

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4.1.5 Current

 

Consumption  

4.1.5.1 Current

 

Consumption 3.3 V without DC-DC Converter  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C. DCDC is off.  

Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.  

Table 4.5.

 

Current Consumption 3.3 V without DC-DC Converter  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

mode with all peripherals dis-  

abled  

38.4 MHz crystal, CPU running  

while loop from flash

1  

—

128  

—

µA/MHz  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

—

—

—

97  

98  

—

107  

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

119  

100  

246  

86  

26 MHz HFRCO, CPU running  

while loop from flash  

109  

430  

—

1 MHz HFRCO, CPU running  

while loop from flash  

Current consumption in EM0

 

I

ACTIVE_VS  

mode with all peripherals dis-  

abled and voltage scaling  

enabled  

19 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

209  

76  

—

38.4 MHz crystal

1  

38 MHz HFRCO  

26 MHz HFRCO  

1 MHz HFRCO  

19 MHz HFRCO  

1 MHz HFRCO  

Current consumption in EM1

 

I

EM1  

mode with all peripherals dis-  

abled  

—

—

—

—

—

—

47  

49  

51  

55  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

195  

43  

374  

—

Current consumption in EM1

 

I

EM1_VS  

mode with all peripherals dis-  

abled and voltage scaling  

enabled  

167  

—

Current consumption in EM2

 

I

EM2_VS  

mode, with voltage scaling  

enabled  

Full 64 kB RAM retention and  

RTCC running from LFXO  

—

—

—

—

1.9  

2.2  

2.8  

1.9  

—

—

µA  

µA  

µA  

µA  

Full 64 kB RAM retention and  

RTCC running from LFRCO  

Full 64 kB RAM retention and  

PRORTCC running from PLFRCO  

—

1 bank (16 kB) RAM retention and  

RTCC running from LFRCO

2  

3.3  

1 bank (16 kB) RAM retention and  

PRORTCC running from PLFRCO  

—

—

2.6  

—

µA  

µA  

Current consumption in EM3

 

I

EM3_VS  

mode, with voltage scaling  

enabled  

Full 64 kB RAM retention and  

CRYOTIMER running from ULFR-  

CO  

1.53  

3.0  

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Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in  

EM4H mode, with voltage  

scaling enabled  

I

EM4H_VS  

128 byte RAM retention, RTCC  

running from LFXO  

—

0.93  

—

µA  

128 byte RAM retention, CRYO-  

TIMER running from ULFRCO  

—

0.45  

—

µA  

128 byte RAM retention, no RTCC  

No RAM retention, no RTCC  

—

—

0.44  

0.04  

0.9  

µA  

µA  

Current consumption in  

EM4S mode  

I

EM4S  

0.085  

Note:  

1. CMU_HFXOCTRL_LOWPOWER=0.  

2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1  

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4.1.5.2 Current

 

Consumption 3.3 V using DC-DC Converter  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC  

output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.  

Table 4.6.

 

Current Consumption 3.3 V using DC-DC Converter  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE_DCM  

mode with all peripherals dis-  

abled, DCDC in Low Noise  

DCM mode

1  

38.4 MHz crystal, CPU running  

while loop from flash

2  

—

87  

—

µA/MHz  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

—

69  

70  

—

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

82  

26 MHz HFRCO, CPU running  

while loop from flash  

76  

1 MHz HFRCO, CPU running  

while loop from flash  

615  

97  

Current consumption in EM0

 

I

ACTIVE_CCM  

mode with all peripherals dis-  

abled, DCDC in Low Noise  

CCM mode

3  

38.4 MHz crystal, CPU running  

while loop from flash

2  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

—

—

80  

81  

—

—

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

92  

26 MHz HFRCO, CPU running  

while loop from flash  

94  

1 MHz HFRCO, CPU running  

while loop from flash  

1145  

101  

1124  

Current consumption in EM0

 

I

ACTIVE_CCM_VS

19 MHz HFRCO, CPU running  

mode with all peripherals dis-  

abled and voltage scaling  

enabled, DCDC in Low  

Noise CCM mode

3  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

38.4 MHz crystal

2  

38 MHz HFRCO  

26 MHz HFRCO  

1 MHz HFRCO  

19 MHz HFRCO  

1 MHz HFRCO  

Current consumption in EM1

 

I

EM1_DCM  

mode with all peripherals dis-  

abled, DCDC in Low Noise  

—

56  

—

µA/MHz  

—

—

—

—

—

39  

46  

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

DCM mode

1  

588  

50  

Current consumption in EM1

 

I

EM1_DCM_VS  

mode with all peripherals dis-  

abled and voltage scaling  

572  

enabled, DCDC in Low  

Noise DCM mode

1  

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Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM2

 

I

EM2_VS  

mode, with voltage scaling  

enabled, DCDC in LP mode

4  

Full 64 kB RAM retention and  

RTCC running from LFXO  

—

1.4  

—

µA  

Full 64 kB RAM retention and  

RTCC running from LFRCO  

—

—

—

1.5  

2.0  

1.3  

—

—

—

µA  

µA  

µA  

Full 64 kB RAM retention and  

PRORTCC running from PLFRCO  

1 bank RAM retention and RTCC  

running from LFRCO

5  

1 bank RAM retention and  

PRORTCC running from PLFRCO  

—

—

1.9  

—

—

µA  

µA  

Current consumption in EM3

 

I

EM3_VS  

mode, with voltage scaling  

enabled  

Full 64 kB RAM retention and  

CRYOTIMER running from ULFR-  

CO  

1.14  

Current consumption in  

EM4H mode, with voltage  

scaling enabled  

I

EM4H_VS  

128 byte RAM retention, RTCC  

running from LFXO  

—

—

0.75  

0.44  

—

—

µA  

µA  

128 byte RAM retention, CRYO-  

TIMER running from ULFRCO  

128 byte RAM retention, no RTCC  

No RAM retention, no RTCC  

—

—

0.42  

0.07  

—

—

µA  

µA  

Current consumption in  

EM4S mode  

I

EM4S  

Note:  

1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.  

2. CMU_HFXOCTRL_LOWPOWER=0.  

3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.  

4. DCDC Low Power Mode = Medium Drive, LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIMSEL=1, ANASW=DVDD.  

5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1  

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4.1.5.3 Current

 

Consumption 1.8 V without DC-DC Converter  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.8 V. T = 25 °C. DCDC is off.  

Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.  

Table 4.7.

 

Current Consumption 1.8 V without DC-DC Converter  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

mode with all peripherals dis-  

abled  

38.4 MHz crystal, CPU running  

while loop from flash

1  

—

128  

—

µA/MHz  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

—

—

—

97  

98  

—

—

—

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

119  

100  

243  

86  

26 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

Current consumption in EM0

 

I

ACTIVE_VS  

mode with all peripherals dis-  

abled and voltage scaling  

enabled  

19 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

206  

76  

38.4 MHz crystal

1  

38 MHz HFRCO  

26 MHz HFRCO  

1 MHz HFRCO  

19 MHz HFRCO  

1 MHz HFRCO  

Current consumption in EM1

 

I

EM1  

mode with all peripherals dis-  

abled  

—

—

—

—

—

47  

48  

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

191  

43  

Current consumption in EM1

 

I

EM1_VS  

mode with all peripherals dis-  

abled and voltage scaling  

enabled  

163  

Current consumption in EM2

 

I

EM2_VS  

mode, with voltage scaling  

enabled  

Full 64 kB RAM retention and  

RTCC running from LFXO  

—

—

—

—

1.8  

2.0  

2.7  

1.6  

—

—

—

—

µA  

µA  

µA  

µA  

Full 64 kB RAM retention and  

RTCC running from LFRCO  

Full 64 kB RAM retention and  

PRORTCC running from PLFRCO  

1 bank (16 kB) RAM retention and  

RTCC running from LFRCO

2  

1 bank (16 kB) RAM retention and  

PRORTCC running from PLFRCO  

—

—

2.5  

—

—

µA  

µA  

Current consumption in EM3

 

I

EM3_VS  

mode, with voltage scaling  

enabled  

Full 64 kB RAM retention and  

CRYOTIMER running from ULFR-  

CO  

1.43  

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Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in  

EM4H mode, with voltage  

scaling enabled  

I

EM4H_VS  

128 byte RAM retention, RTCC  

running from LFXO  

—

0.83  

—

µA  

128 byte RAM retention, CRYO-  

TIMER running from ULFRCO  

—

0.37  

—

µA  

128 byte RAM retention, no RTCC  

no RAM retention, no RTCC  

—

—

0.36  

0.05  

—

—

µA  

µA  

Current consumption in  

EM4S mode  

I

EM4S  

Note:  

1. CMU_HFXOCTRL_LOWPOWER=0.  

2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1  

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Electrical Specifications  

4.1.5.4 Current

 

Consumption Using Radio 3.3 V with DC-DC  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V. T = 25  

°C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.  

Table 4.8.

 

Current Consumption Using Radio 3.3 V with DC-DC  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in re-  

ceive mode, active packet  

reception (MCU in EM1 @  

38.4 MHz, peripheral clocks  

disabled), T ≤ 85 °C  

I

RX_ACTIVE  

500 kbit/s, 2GFSK, F = 915 MHz,  

Radio clock prescaled by 4  

—

9.3  

10.2  

mA  

38.4 kbit/s, 2GFSK, F = 868 MHz,  

Radio clock prescaled by 4  

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

8.6  

8.6  

8.6  

8.6  

8.4  

9.2  

9.3  

9.5  

10.6  

10.3  

—

10.2  

10.2  

10.2  

10.2  

10.2  

—

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

38.4 kbit/s, 2GFSK, F = 490 MHz,  

Radio clock prescaled by 4  

50 kbit/s, 2GFSK, F = 433 MHz,  

Radio clock prescaled by 4  

38.4 kbit/s, 2GFSK, F = 315 MHz,  

Radio clock prescaled by 4  

38.4 kbit/s, 2GFSK, F = 169 MHz,  

Radio clock prescaled by 4  

125 kbit/s, 2GFSK, F = 2.4 GHz,  

Radio clock prescaled by 4  

500 kbit/s, 2GFSK, F = 2.4 GHz,  

Radio clock prescaled by 4  

—

1 Mbit/s, 2GFSK, F = 2.4 GHz,  

Radio clock prescaled by 4  

—

2 Mbit/s, 2GFSK, F = 2.4 GHz,  

Radio clock prescaled by 4  

—

802.15.4 receiving frame, F = 2.4  

GHz, Radio clock prescaled by 3  

—

Current consumption in re-  

ceive mode, active packet  

reception (MCU in EM1 @  

38.4 MHz, peripheral clocks  

disabled), T > 85 °C  

I

RX_ACTIVE_HT  

500 kbit/s, 2GFSK, F = 915 MHz,  

Radio clock prescaled by 4  

13  

38.4 kbit/s, 2GFSK, F = 868 MHz,  

Radio clock prescaled by 4  

—

13  

38.4 kbit/s, 2GFSK, F = 490 MHz,  

Radio clock prescaled by 4  

—

13  

50 kbit/s, 2GFSK, F = 433 MHz,  

Radio clock prescaled by 4  

—

13  

38.4 kbit/s, 2GFSK, F = 315 MHz,  

Radio clock prescaled by 4  

—

13  

38.4 kbit/s, 2GFSK, F = 169 MHz,  

Radio clock prescaled by 4  

—

13  

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Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in re-  

ceive mode, listening for  

packet (MCU in EM1 @ 38.4  

MHz, peripheral clocks disa-  

bled), T ≤ 85 °C  

I

RX_LISTEN  

500 kbit/s, 2GFSK, F = 915 MHz,  

No radio clock prescaling  

—

10.2  

11  

mA  

38.4 kbit/s, 2GFSK, F = 868 MHz,  

No radio clock prescaling  

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

9.5  

9.5  

9.5  

9.4  

9.3  

10.4  

10.4  

10.5  

11.3  

11.9  

—

11  

11  

11  

11  

11  

—

—

—

—

—

14  

14  

14  

14  

14  

14  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

38.4 kbit/s, 2GFSK, F = 490 MHz,  

No radio clock prescaling  

50 kbit/s, 2GFSK, F = 433 MHz,  

No radio clock prescaling  

38.4 kbit/s, 2GFSK, F = 315 MHz,  

No radio clock prescaling  

38.4 kbit/s, 2GFSK, F = 169 MHz,  

No radio clock prescaling  

125 kbit/s, 2GFSK, F = 2.4 GHz,  

No radio clock prescaling  

500 kbit/s, 2GFSK, F = 2.4 GHz,  

No radio clock prescaling  

1 Mbit/s, 2GFSK, F = 2.4 GHz, No  

radio clock prescaling  

2 Mbit/s, 2GFSK, F = 2.4 GHz, No  

radio clock prescaling  

802.15.4, F = 2.4 GHz, No radio  

clock prescaling  

Current consumption in re-  

ceive mode, listening for  

packet (MCU in EM1 @ 38.4  

MHz, peripheral clocks disa-  

bled), T > 85 °C  

I

RX_LISTEN_HT  

500 kbit/s, 2GFSK, F = 915 MHz,  

No radio clock prescaling  

38.4 kbit/s, 2GFSK, F = 868 MHz,  

No radio clock prescaling  

—

38.4 kbit/s, 2GFSK, F = 490 MHz,  

No radio clock prescaling  

—

50 kbit/s, 2GFSK, F = 433 MHz,  

No radio clock prescaling  

—

38.4 kbit/s, 2GFSK, F = 315 MHz,  

No radio clock prescaling  

—

38.4 kbit/s, 2GFSK, F = 169 MHz,  

No radio clock prescaling  

—

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Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in  

transmit mode (MCU in EM1  

@ 38.4 MHz, peripheral  

clocks disabled), T ≤ 85 °C  

I

TX  

F = 915 MHz, CW, 20 dBm  

match, External PA supply = 3.3V  

—

90.2  

134.3  

mA  

F = 915 MHz, CW, 14 dBm  

match, External PA supply con-  

nected to DCDC output  

—

36  

42.5  

mA  

F = 868 MHz, CW, 20 dBm  

match, External PA supply = 3.3V  

—

—

79.7  

35.3  

106.7  

41  

mA  

mA  

F = 868 MHz, CW, 14 dBm  

match, External PA supply con-  

nected to DCDC output  

F = 490 MHz, CW, 20 dBm  

match, External PA supply = 3.3V  

—

—

93.8  

20.3  

125.4  

24  

mA  

mA  

F = 433 MHz, CW, 10 dBm  

match, External PA supply con-  

nected to DC-DC output  

F = 433 MHz, CW, 14 dBm  

match, External PA supply con-  

nected to DCDC output  

—

—

34  

41.5  

42  

mA  

mA  

F = 315 MHz, CW, 14 dBm  

match, External PA supply con-  

nected to DCDC output  

33.5  

F = 169 MHz, CW, 20 dBm  

match, External PA supply = 3.3V  

—

—

—

—

—

—

—

88.6  

8.5  

116.7  

—

mA  

mA  

mA  

mA  

mA  

mA  

mA  

F = 2.4 GHz, CW, 0 dBm output  

power, Radio clock prescaled by 3  

F = 2.4 GHz, CW, 0 dBm output  

power, Radio clock prescaled by 1  

9.5  

—

F = 2.4 GHz, CW, 3 dBm output  

power  

16.5  

26.0  

34.0  

86.0  

—

F = 2.4 GHz, CW, 8 dBm output  

power  

—

F = 2.4 GHz, CW, 10.5 dBm out-  

put power  

—

F = 2.4 GHz, CW, 16.5 dBm out-  

put power, PAVDD connected di-  

rectly to external 3.3V supply  

—

F = 2.4 GHz, CW, 19.5 dBm out-  

put power, PAVDD connected di-  

rectly to external 3.3V supply  

—

131.0  

—

mA  

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Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in  

transmit mode (MCU in EM1  

@ 38.4 MHz, peripheral  

clocks disabled), T > 85 °C  

I

TX_HT  

F = 915 MHz, CW, 20 dBm  

match, External PA supply = 3.3V  

—

—

134.3  

mA  

F = 915 MHz, CW, 14 dBm  

match, External PA supply con-  

nected to DCDC output  

—

—

42.5  

mA  

F = 868 MHz, CW, 20 dBm  

match, External PA supply = 3.3V  

—

—

—

—

109.8  

41.3  

mA  

mA  

F = 868 MHz, CW, 14 dBm  

match, External PA supply con-  

nected to DCDC output  

F = 490 MHz, CW, 20 dBm  

match, External PA supply = 3.3V  

—

—

—

—

130.8  

24.4  

mA  

mA  

F = 433 MHz, CW, 10 dBm  

match, External PA supply con-  

nected to DC-DC output  

F = 433 MHz, CW, 14 dBm  

match, External PA supply con-  

nected to DCDC output  

—

—

—

—

—

—

41.5  

42  

mA  

mA  

mA  

F = 315 MHz, CW, 14 dBm  

match, External PA supply con-  

nected to DCDC output  

F = 169 MHz, CW, 20 dBm  

122.8  

match, External PA supply = 3.3V  

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| 37  

EFR32BG13 Blue Gecko

Bluetooth

® Low Energy SoC Family Data Sheet  

Electrical Specifications  

4.1.6 Wake

 

Up Times  

Table 4.9.

 

Wake Up Times  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Wake up time from EM1  

t

EM1_WU  

—

3

—

AHB  

Clocks  

Wake up from EM2  

Wake up from EM3  

t

EM2_WU  

Code execution from flash  

Code execution from RAM  

Code execution from flash  

Code execution from RAM  

Executing from flash  

—

—

—

—

—

10.9  

3.8  

—

—

—

—

—

µs  

µs  

µs  

µs  

µs  

t

EM3_WU  

10.9  

3.8  

Wake up from EM4H

1  

Wake up from EM4S

1  

t

EM4H_WU  

t

EM4S_WU  

t

RESET  

90  

Executing from flash  

—

300  

—

µs  

Time from release of reset  

source to first instruction ex-  

ecution  

Soft Pin Reset released  

Any other reset released  

—

—

51  

—

—

µs  

µs  

358  

Power mode scaling time  

t

SCALE  

VSCALE0 to VSCALE2, HFCLK =  

19 MHz

2 3  

—

—

31.8  

4.3  

—

—

µs  

µs  

VSCALE2 to VSCALE0, HFCLK =  

19 MHz

4  

Note:  

1. Time from wake up request until first instruction is executed. Wakeup results in device reset.  

2. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 µs + 28 HFCLKs.  

3. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,  

peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70 mA  

(with a 2.7 µF capacitor).  

4. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 µs + 29 HFCLKs.  

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Rev. 1.7

 

| 38  

EFR32BG13 Blue Gecko

Bluetooth

® Low Energy SoC Family Data Sheet  

Electrical Specifications  

4.1.7 Brown

 

Out Detector (BOD)  

Table 4.10.

 

Brown Out Detector (BOD)  

Parameter  

Symbol  

Test Condition  

Min  

—

Typ  

—

Max  

1.62  

—

Unit  

V

DVDD BOD threshold  

V

DVDDBOD  

DVDD rising  

DVDD falling (EM0/EM1)  

DVDD falling (EM2/EM3)  

1.35  

1.3  

—

—

V

—

—

V

DVDD BOD hysteresis  

DVDD BOD response time  

AVDD BOD threshold  

V

DVDDBOD_HYST  

18  

2.4  

—

—

mV  

µs  

V

t

DVDDBOD_DELAY

Supply drops at 0.1V/µs rate  

—

—

V

AVDDBOD  

AVDD rising