SKYWORKS-SILICON-LABS-EFR32BG1P332F256GJ43-C0

EFR32BG1 Blue Gecko

Bluetooth

® Smart  

SoC CSP Family Data Sheet  

The Blue Gecko Bluetooth Smart family of SoCs is part of the  

KEY FEATURES  

Wireless Gecko portfolio. Blue Gecko SoCs are ideal for enabling  

energy-friendly Bluetooth Smart networking for IoT devices.  

• 32-bit

 

ARM® Cortex®-M4 core with 40  

MHz maximum operating frequency  

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup  

times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-  

tures.  

• Scalable

 

Memory and Radio configuration  

options available in footprint-compatible  

CSP packaging  

• 12-channel

 

Peripheral Reflex System  

enabling autonomous interaction of MCU  

peripherals  

Blue Gecko applications include:  

• IoT

 

Sensors and End Devices  

• Health

 

and Wellness  

• Autonomous

 

Hardware Crypto Accelerator  

and Random Number Generator  

• Home

 

and Building Automation  

• Accessories  

• Integrated

 

2.4 GHz balun and PA with up  

to 19.5 dBm transmit power  

• Integrated

 

DC-DC with RF noise mitigation  

• Human

 

Interface Devices  

• Metering  

• Also

 

Available: Certified modules with  

compatible tools and software  

• Commercial

 

and Retail Lighting and Sensing  

Core / Memory  

Clock Management  

Energy Management  

Other  

High Frequency  

Crystal  

Oscillator  

High Frequency  

RC Oscillator  

Voltage  

CRYPTO  

Voltage Monitor  

Regulator  

ARM Cortex

TM

M4 processor  

Memory  

with DSP extensions and FPU  

Protection Unit  

Auxiliary High  

Frequency RC  

Oscillator  

Low Frequency  

RC Oscillator  

DC-DC  

Power-On Reset  

Converter  

CRC  

Low Frequency  

Crystal  

Oscillator  

Ultra Low  

Frequency RC  

Oscillator  

Flash Program  

RAM Memory  

Memory  

Brown-Out  

Detector  

Debug Interface  

DMA Controller  

32-bit bus  

Peripheral Reflex System  

Radio Transceiver  

Serial  

I/O Ports  

Timers and Triggers  

Analog I/F  

Interfaces  

External  

Interrupts  

RFSENSE  

BALUN  

DEMOD  

USART  

Timer/Counter  

Protocol Timer  

ADC  

Low Energy  

UART

TM  

General  

Purpose I/O  

Low Energy  

Timer  

Analog  

Comparator  

IFADC  

AGC  

PGA  

I

Watchdog Timer  

LNA  

RF Frontend  

Real Time  

Counter and  

Calendar  

I

2

C  

Pin Reset  

Pulse Counter  

IDAC  

PA  

Frequency  

Synthesizer  

Q

MOD  

Pin Wakeup  

Cryotimer  

Lowest power mode with peripheral operational:  

EM0—Active EM1—Sleep  

EM2—Deep Sleep  

EM3—Stop  

EM4—Hibernate  

EM4—Shutoff  

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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon  

Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).  

Preliminary Rev.

 

1.1  

EFR32BG1 Blue Gecko

Bluetooth

® Smart SoC CSP Family Data Sheet  

Feature List  

1. Feature

 

List  

The EFR32BG1 highlighted features are listed below.  

•

Low Power Wireless System-on-Chip

.  

•

Wide selection of MCU peripherals  

High Performance 32-bit 40 MHz ARM Cortex

®

-M4 with  

DSP instruction and floating-point unit for efficient signal  

processing  

•

• 12-bit

 

1 Msps SAR Analog to Digital Converter (ADC)  

• 2×

 

Analog Comparator (ACMP)  

• Digital

 

to Analog Current Converter (IDAC)  

• Up

 

to 256 kB flash program memory  

• Up

 

to 32 kB RAM data memory  

• 2.4

 

GHz radio operation  

• Up

 

to 19 pins connected to analog channels (APORT)  

shared between Analog Comparators, ADC, and IDAC  

• Up

 

to 19 General Purpose I/O pins with output state reten-  

tion and asynchronous interrupts  

• TX

 

power up to 19.5 dBm  

• 8

 

Channel DMA Controller  

•

Low Energy Consumption  

• 12

 

Channel Peripheral Reflex System (PRS)  

• 2×16-bit

 

Timer/Counter  

• 8.7

 

mA RX current at 2.4 GHz  

• 8.2

 

mA TX current @ 0 dBm output power at 2.4 GHz  

• 63

 

μA/MHz in Active Mode (EM0)  

• 3

 

+ 4 Compare/Capture/PWM channels  

• 32-bit

 

Real Time Counter and Calendar  

• 16-bit

 

Low Energy Timer for waveform generation  

• 2.5

 

μA EM2 DeepSleep current (full RAM retention and  

RTCC running from LFXO)  

• 0.58

 

μA EM4H Hibernate Mode (128 byte RAM retention)  

• 32-bit

 

Ultra Low Energy Timer/Counter for periodic wake-up  

from any Energy Mode  

• Wake

 

on Radio with signal strength detection, preamble  

pattern detection, frame detection and timeout  

• 16-bit

 

Pulse Counter with asynchronous operation  

• Watchdog

 

Timer with dedicated RC oscillator @ 50nA  

• 2×Universal

 

Synchronous/Asynchronous Receiver/Trans-  

mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I

2

S)  

•

High Receiver Performance  

• -91

 

dBm sensitivity @ 1 Mbit/s GFSK (2.4GHz)  

•

Supported Modulation Format  

• GFSK  

Low Energy UART (LEUART

™

)  

I

2

C interface with SMBus support and address recognition  

in EM3 Stop  

•

•

• 2-FSK

 

/ 4-FSK with fully configurable shaping (EFR32BG1P  

OPNs)  

• Shaped

 

OQPSK / (G)MSK (EFR32BG1P OPNs)  

• Configurable

 

DSSS and FEC (EFR32BG1P OPNs)  

•

Supported Protocol:  

•

Wide Operating Range  

• 1.85

 

V to 3.8 V single power supply  

• Integrated

 

DC-DC, down to 1.8 V output with up to 200 mA  

load current for system  

Bluetooth

®

Smart  

•

• -40

 

°C to 85 °C  

• Proprietary

 

Protocols (EFR32BG1P OPNs)  

•

Support for Internet Security  

• General

 

Purpose CRC  

•

43-pin CSP 3.3×3.14 mm Package  

• Random

 

Number Generation  

• Hardware

 

Cryptographic Acceleration for AES 128/256,  

SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC  

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Preliminary Rev. 1.1

 

| 1  

EFR32BG1 Blue Gecko

Bluetooth

® Smart SoC CSP Family Data Sheet  

Ordering Information  

2. Ordering

 

Information  

Ordering Code  

Protocol Stack  

Frequency Band  

@ Max TX Power  

2.4 GHz @ 19.5 dBm  

Flash  

(kB)  

RAM (kB)  

EFR32BG1P332F256GJ43-C0  

• Bluetooth

 

Smart  

• Proprietary  

256  

32  

EFR32BG1B232F256GJ43-C0  

EFR32BG1V132F256GJ43-C0  

Bluetooth Smart  

Bluetooth Smart  

2.4 GHz @ 10.5 dBm  

2.4 GHz @ 0 dBm  

256  

256  

32  

16  

EFR32 X G 1 P 132 F 256 G

 

M 32

–

C0 R  

Tape and Reel (Optional)  

Revision  

Pin Count  

Package – M (QFN), J (CSP)  

Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)  

Flash Memory Size in kB  

Memory Type (Flash)  

Feature Set Code – r2r1r0  

r2: Reserved  

r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)  

r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)  

Performance Grade – P (Performance), B (Basic), V (Value)  

Series  

Gecko  

Family – M (Mighty), B (Blue), F (Flex)  

Wireless Gecko 32-bit  

Figure 2.1.

 

OPN Decoder  

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EFR32BG1 Blue Gecko

Bluetooth

® Smart SoC CSP Family Data Sheet  

System Overview  

3. System

 

Overview  

3.1 Introduction  

The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for  

any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a  

short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32 Reference Manual.  

A block diagram of the EFR32BG1 family is shown in

Figure 3.1 Detailed EFR32BG1 Block Diagram on page 3

. The diagram shows  

a superset of features available on the family, which vary by OPN. For more information about specific device features, consult

Order-  

ing Information

.  

Port I/O Configuration  

Radio Transciever  

DEMOD  

Digital Peripherals  

RFSENSE  

BALUN  

RF Frontend  

PGA  

IFADC  

AGC  

LETIMER  

I

IOVDD  

LNA  

TIMER  

2G4RF_IOP  

2G4RF_ION  

PA  

Frequency  

Synthesizer  

Q

CRYOTIMER  

PCNT  

MOD  

Port A  

Drivers  

PAn  

RTC / RTCC  

USART  

Port  

Mapper  

Energy Management  

ARM Cortex-M4 Core  

Port B  

PAVDD  

RFVDD  

PBn  

PCn  

PDn  

PFn  

Drivers  

Up to 256 KB ISP Flash  

Program Memory  

LEUART  

I2C  

IOVDD  

AVDD  

Up to 32 KB RAM  

Memory Protection Unit  

Floating Point Unit  

DMA Controller  

Voltage  

Monitor  

CRYPTO  

CRC  

Port C  

Drivers  

A

H

B

A

P

B

DVDD  

bypass  

Port D  

Drivers  

VREGVDD  

VREGSW  

Analog Peripherals  

DC-DC  

Converter  

Voltage  

Regulator  

Serial Wire Debug /  

Programming  

Internal  

Reference  

IDAC  

DECOUPLE  

Watchdog  

Timer  

Port F  

Drivers  

VDD  

VREF  

VSS  

VREGVSS  

RFVSS  

Brown Out /  

Power-On  

Reset  

Clock Management  

VDD  

12-bit ADC  

PAVSS  

ULFRCO  

AUXHFRCO  

LFRCO  

Reset  

Management  

Unit  

RESETn  

Temp  

Sensor  

HFRCO  

LFXO  

LFXTAL_P / N  

+

–

HFXTAL_P  

HFXTAL_N  

HFXO  

Analog Comparator  

Figure 3.1.

 

Detailed EFR32BG1 Block Diagram  

3.2 Radio  

The Blue Gecko family features a radio transceiver supporting Bluetooth Smart

®

and proprietary short range wireless protocols.  

3.2.1 Antenna

 

Interface  

The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The  

2G4RF_ION pin should be grounded externally.  

The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching  

Networks section.  

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EFR32BG1 Blue Gecko

Bluetooth

® Smart SoC CSP Family Data Sheet  

System Overview  

3.2.2 Fractional-N

 

Frequency Synthesizer  

The EFR32BG1 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is  

used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly  

generate the modulated RF carrier.  

The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with  

low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to  

optimize system energy consumption.  

3.2.3 Receiver

 

Architecture  

The EFR32BG1 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion mix-  

er, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital  

converter (IFADC).  

The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-  

ing flexibility with respect to known interferers at the image frequency.  

The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-  

tivity and blocking performance. Devices are production-calibrated to improve image rejection performance.  

Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-  

ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and  

compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by  

block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).  

A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-  

nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received  

frame and the dynamic RSSI measurement can be monitored throughout reception.  

3.2.4 Transmitter

 

Architecture  

The EFR32BG1 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls  

phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping  

filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-  

ing.  

Carrier Sense Multiple Access – Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by  

the EFR32BG1. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-  

tween devices that otherwise lack synchronized RF channel access.  

3.2.5 Wake

 

on Radio  

The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-  

ing a subsystem of the EFR32BG1 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripherals.  

3.2.6 RFSENSE  

The RFSENSE module generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing  

true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.  

RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-  

sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by  

enabling normal RF reception.  

Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using  

available timer peripherals.  

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EFR32BG1 Blue Gecko

Bluetooth

® Smart SoC CSP Family Data Sheet  

System Overview  

3.2.7 Flexible

 

Frame Handling  

EFR32BG1 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.  

The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-  

tor:  

• Highly

 

adjustable preamble length  

• Up

 

to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts  

• Frame

 

disassembly and address matching (filtering) to accept or reject frames  

• Automatic

 

ACK frame assembly and transmission  

• Fully

 

flexible CRC generation and verification:  

• Multiple

 

CRC values can be embedded in a single frame  

• 8,

 

16, 24 or 32-bit CRC value  

• Configurable

 

CRC bit and byte ordering  

• Selectable

 

bit-ordering (least significant or most significant bit first)  

• Optional

 

data whitening  

• Optional

 

Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding  

• Half

 

rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing  

• Optional

 

symbol interleaving, typically used in combination with FEC  

• Symbol

 

coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware  

• UART

 

encoding over air, with start and stop bit insertion / removal  

• Test

 

mode support, such as modulated or unmodulated carrier output  

• Received

 

frame timestamping  

3.2.8 Packet

 

and State Trace  

The EFR32BG1 Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It  

features:  

• Non-intrusive

 

trace of transmit data, receive data and state information  

• Data

 

observability on a single-pin UART data output, or on a two-pin SPI data output  

• Configurable

 

data output bitrate / baudrate  

• Multiplexed

 

transmitted data, received data and state / meta information in a single serial data stream  

3.2.9 Data

 

Buffering  

The EFR32BG1 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64  

bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.  

3.2.10 Radio

 

Controller (RAC)  

The Radio Controller controls the top level state of the radio subsystem in the EFR32BG1. It performs the following tasks:  

• Precisely-timed

 

control of enabling and disabling of the receiver and transmitter circuitry  

• Run-time

 

calibration of receiver, transmitter and frequency synthesizer  

• Detailed

 

frame transmission timing, including optional LBT or CSMA-CA  

3.2.11 Random

 

Number Generator  

The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.  

The data is suitable for use in cryptographic applications.  

Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-  

ber generator algorithms such as Fortuna.  

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EFR32BG1 Blue Gecko

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System Overview  

3.3 Power  

The EFR32BG1 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a  

single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator can  

be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor.  

AVDD and VREGVDD need to be 1.85 V or higher for the MCU to operate across all conditions; however the rest of the system will  

operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.  

Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB  

components, supplying up to a total of 200 mA.  

3.3.1 Energy

 

Management Unit (EMU)  

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and  

features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM  

blocks, and it contains control registers for the dc-dc regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple  

supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen  

below a chosen threshold.  

3.3.2 DC-DC

 

Converter  

The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2  

and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation  

of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,  

short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low  

for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance  

switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-  

sients.  

3.4 General

 

Purpose Input/Output (GPIO)  

EFR32BG1 has up to 19 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input.  

More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin.  

The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to sev-  

eral GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals.  

The GPIO subsystem supports asynchronous external pin interrupts.  

3.5 Clocking  

3.5.1 Clock

 

Management Unit (CMU)  

The Clock Management Unit controls oscillators and clocks in the EFR32BG1. Individual enabling and disabling of clocks to all periph-  

eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility  

allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and  

oscillators.  

3.5.2 Internal

 

and External Oscillators  

The EFR32BG1 supports two crystal oscillators and fully integrates four RC oscillators, listed below.  

• A

 

high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-  

ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can  

also be applied to the HFXO input for improved accuracy over temperature.  

• A

 

32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.  

• An

 

integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The  

HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.  

• An

 

integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial  

Wire debug port with a wide frequency range.  

• An

 

integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-  

tal accuracy is not required.  

• An

 

integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-  

sumption in low energy modes.  

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EFR32BG1 Blue Gecko

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System Overview  

3.6 Counters/Timers

 

and PWM  

3.6.1 Timer/Counter

 

(TIMER)  

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the  

PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one  

of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output  

reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width  

modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional  

dead-time insertion available in timer unit TIMER_0 only.  

3.6.2 Real

 

Time Counter and Calendar (RTCC)  

The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a  

Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-  

tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving  

frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy  

and convenient data storage in all energy modes.  

3.6.3 Low

 

Energy Timer (LETIMER)  

The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This  

allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed  

while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-  

forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-  

figured to start counting on compare matches from the RTCC.  

3.6.4 Ultra

 

Low Power Wake-up Timer (CRYOTIMER)  

The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal  

oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events  

and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-  

rupt periods, facilitating flexible ultra-low energy operation.  

3.6.5 Pulse

 

Counter (PCNT)  

The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The  

clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from  

among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2  

Deep Sleep, and EM3 Stop.  

3.6.6 Watchdog

 

Timer (WDOG)  

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed  

monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can  

also monitor autonomous systems driven by PRS.  

3.7 Communications

 

and Other Digital Peripherals  

3.7.1 Universal

 

Synchronous/Asynchronous Receiver/Transmitter (USART)  

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous  

UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-  

porting:  

• ISO7816

 

SmartCards  

• IrDA  

I

2

S  

•

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EFR32BG1 Blue Gecko

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System Overview  

3.7.2 Low

 

Energy Universal Asynchronous Receiver/Transmitter (LEUART)  

The unique LEUART

TM

provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow  

UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication  

possible with a minimum of software intervention and energy consumption.  

3.7.3 Inter-Integrated

 

Circuit Interface (I

2

C)  

The I

2

C module provides an interface between the MCU and a serial I

2

C bus. It is capable of acting as both a master and a slave and  

supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10  

kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The  

interface provided to software by the I

2

C module allows precise timing control of the transmission process and highly automated trans-  

fers. Automatic recognition of slave addresses is provided in active and low energy modes.  

3.7.4 Peripheral

 

Reflex System (PRS)  

The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.  

Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-  

erals which in turn perform actions in response. Edge triggers and other functionality can be applied by the PRS. The PRS allows pe-  

ripheral to act autonomously without waking the MCU core, saving power.  

3.8 Security

 

Features  

3.8.1 GPCRC

 

(General Purpose Cyclic Redundancy Check)  

The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-  

ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the  

needs of the application.  

3.8.2 Crypto

 

Accelerator (CRYPTO)  

The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-  

port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2

m

), SHA-1 and SHA-2 (SHA-224 and  

SHA-256).  

Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.  

Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.  

The CRYPTO is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data  

buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger sig-  

nals for DMA read and write operations.  

3.9 Analog  

3.9.1 Analog

 

Port (APORT)  

The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog modules on a flexible selection of pins.  

Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are  

grouped by X/Y pairs.  

3.9.2 Analog

 

Comparator (ACMP)  

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-  

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption  

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The  

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the  

programmable threshold.  

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3.9.3 Analog

 

to Digital Converter (ADC)  

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output  

sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.  

The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of  

sources, including pins configurable as either single-ended or differential.  

3.9.4 Digital

 

to Analog Current Converter (IDAC)  

The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin  

or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with  

several ranges consisting of various step sizes.  

3.10 Reset

 

Management Unit (RMU)  

The RMU is responsible for handling reset of the EFR32BG1. A wide range of reset sources are available, including several power  

supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.  

3.11 Core

 

and Memory  

3.11.1 Processor

 

Core  

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:  

• ARM

 

Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz  

• Memory

 

Protection Unit (MPU) supporting up to 8 memory segments  

• Up

 

to 256 kB flash program memory  

• Up

 

to 32 kB RAM data memory  

• Configuration

 

and event handling of all modules  

• 2-pin

 

Serial-Wire debug interface  

3.11.2 Memory

 

System Controller (MSC)  

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable  

from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code  

is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a  

read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-  

ergy modes EM0 Active and EM1 Sleep.  

3.11.3 Linked

 

Direct Memory Access Controller (LDMA)  

The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of  

software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and stag-  

ed, enabling sophisticated operations to be implemented.  

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3.12 Memory

 

Map  

The EFR32BG1 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.  

Figure 3.2.

 

EFR32BG1 Memory Map — Core Peripherals and Code Space  

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Figure 3.3.

 

EFR32BG1 Memory Map — Peripherals  

3.13 Configuration

 

Summary  

The features of the EFR32BG1 are a subset of the feature set described in the device reference manual. The table below describes  

device specific implementation of the features. Remaining modules support full configuration.  

Table 3.1.

 

Configuration Summary  

Module  

USART0  

USART1  

Configuration  

Pin Connections  

IrDA SmartCard  

US0_TX, US0_RX, US0_CLK, US0_CS  

US1_TX, US1_RX, US1_CLK, US1_CS  

IrDA I

2

S SmartCard  

with DTI.  

TIMER0  

TIMER1  

TIM0_CC[2:0], TIM0_CDTI[2:0]  

TIM1_CC[3:0]  

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4. Electrical

 

Specifications  

4.1 Electrical

 

Characteristics  

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:  

• Typical

 

values are based on T

AMB

=25 °C and V

DD

= 3.3 V, by production test and/or technology characterization.  

• Radio

 

performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-  

er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.  

• Minimum

 

and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,  

unless stated otherwise.  

Refer to

Table 4.2 General Operating Conditions on page 14

for more details about operational supply and temperature limits.  

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4.1.1 Absolute

 

Maximum Ratings  

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of  

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure  

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-  

bility data, see the Quality and Reliability Monitor Report at

.  

Table 4.1.

 

Absolute Maximum Ratings  

Parameter  

Symbol  

Test Condition  

Min  

-50  

0

Typ  

—

Max  

150  

3.8  

1

Unit  

°C  

Storage temperature range  

T

STG  

External main supply voltage

 

V

DDMAX  

—

V

External main supply voltage

 

V

DDRAMPMAX  

ramp rate  

—

—

V / μs  

Voltage on any 5V tolerant  

GPIO pin

1  

V

DIGPIN  

-0.3  

-0.3  

—

—

Min of 5.25  

and IOVDD  

+2  

V

V

Voltage on non-5V tolerant  

GPIO pins  

IOVDD+0.3  

Voltage on HFXO pins  

V

HFXOPIN  

-0.3  

—

—

—

1.4  

10  

V

Input RF level on pins  

2G4RF_IOP and  

2G4RF_ION  

P

RFMAX2G4  

dBm  

Voltage differential between

 

V

MAXDIFF2G4  

RF pins (2G4RF_IOP –  

2G4RF_ION)  

-50  

—

—

50  

mV  

V

Absolute Voltage on RF pins

 

V

MAX2G4  

2G4RF_IOP and  

-0.3  

3.3  

2G4RF_ION  

Total current into VDD power

 

I

VDDMAX  

lines (source)  

—

—

—

—

200  

200  

mA  

mA  

Total current into VSS  

ground lines (sink)  

I

VSSMAX  

Current per I/O pin (sink)  

I

IOMAX  

—

—

—

—

—

—

—

—

50  

50  

mA  

mA  

mA  

mA  

Current per I/O pin (source)  

Current for all I/O pins (sink)

 

I

IOALLMAX  

200  

200  

Current for all I/O pins  

(source)  

Voltage difference between  

AVDD and VREGVDD  

ΔV

DD  

—

—

—

0.3  

V

Junction Temperature  

T

J  

-40  

105  

°C  

Note:  

1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.  

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4.1.2 Operating

 

Conditions  

When assigning supply sources, the following requirements must be observed:  

• VREGVDD

 

must be the highest voltage in the system  

• VREGVDD

 

= AVDD  

• DVDD

 

≤ AVDD  

• IOVDD

 

≤ AVDD  

• RFVDD

 

≤ AVDD  

• PAVDD

 

≤ AVDD  

4.1.2.1 General

 

Operating Conditions  

Table 4.2.

 

General Operating Conditions  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Operating temperature range

 

T

OP  

-G temperature grade, Ambient  

Temperature  

-40  

25  

85  

°C  

AVDD Supply voltage

1  

V

AVDD  

1.85  

3.3  

3.8  

V

VREGVDD Operating supply

 

V

VREGVDD  

voltage

1 2  

DCDC in regulation  

2.4  

3.3  

3.3  

3.3  

3.8  

3.8  

3.8  

V

V

V

DCDC in bypass, 50mA load  

1.85  

1.85  

DCDC not in use. DVDD external-  

ly shorted to VREGVDD  

VREGVDD Current  

I

VREGVDD  

V

RFVDD  

DCDC in bypass  

—

—

—

200  

mA  

V

RFVDD Operating supply  

voltage  

1.62  

V

VREGVDD  

DVDD Operating supply volt-

 

V

DVDD  

age  

1.62  

1.62  

1.62  

—

—

—

—

—

V

VREGVDD  

V

VREGVDD  

V

VREGVDD  

0.1  

V

V

V

V

PAVDD Operating supply  

voltage  

V

PAVDD  

V

IOVDD  

dV

DD  

IOVDD Operating supply  

voltage  

Difference between AVDD  

and VREGVDD, ABS(AVDD-  

VREGVDD)  

0 wait-states (MODE = WS0)

3  

1 wait-states (MODE = WS1)

3  

HFCLK frequency  

f

CORE  

—

—

—

26  

40  

MHz  

MHz  

38.4  

Note:  

1. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.  

2. The minimum voltage required in bypass mode is calculated using R

BYP

from the DCDC specification table. Requirements for  

other loads can be calculated as V

DVDD_min

+I

LOAD

* R

BYP_max  

3. In MSC_READCTRL register  

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4.1.3 DC-DC

 

Converter  

Test conditions: L

DCDC

=4.7 µH (Murata LQH3NPN4R7MM0L), C

DCDC

=1.0 µF (Murata GRM188R71A105KA61D), V

DCDC_I

=3.3 V,  

V

DCDC_O

=1.8 V, I

DCDC_LOAD

=50 mA, Heavy Drive configuration, F

DCDC_LN

=7 MHz, unless otherwise indicated.  

Table 4.3.

 

DC-DC Converter  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Input voltage range  

V

DCDC_I  

Bypass mode, I

DCDC_LOAD

= 50  

mA  

1.85  

—

V

VREGVDD_  

V

MAX  

Low noise (LN) mode, 1.8 V out-  

put, I

DCDC_LOAD

= 100 mA, or  

Low power (LP) mode, 1.8 V out-  

put, I

DCDC_LOAD

= 10 mA  

2.4  

—

V

VREGVDD_  

V

MAX  

Low noise (LN) mode, 1.8 V out-  

put, I

DCDC_LOAD

= 200 mA  

2.6  

1.8  

—

—

V

VREGVDD_  

V

V

MAX  

Output voltage programma-

 

V

DCDC_O  

ble range

1  

V

VREGVDD  

Regulation DC Accuracy  

ACC

DC  

Low noise (LN) mode, 1.8 V target  

output  

1.7  

—

—

1.9  

2.2  

V

V

Regulation Window

2  

WIN

REG  

Low power (LP) mode,  

LPCMPBIAS

3

= 0, 1.8 V target  

output, I

DCDC_LOAD

≤ 75 μA  

1.63  

Low power (LP) mode,  

1.63  

—

2.1  

V

LPCMPBIAS

3

= 3, 1.8 V target  

output, I

DCDC_LOAD

≤ 10 mA  

Steady-state output ripple  

V

R  

Radio disabled.  

—

—

3

—

mVpp  

mV  

CCM Mode (LNFORCECCM

3

=  

1), Load changes between 0 mA  

and 100 mA  

Output voltage under/over-  

shoot  

V

OV  

—

150  

DCM Mode (LNFORCECCM

3

=  

0), Load changes between 0 mA  

and 10 mA  

—

—

150  

mV  

Overshoot during LP to LN  

CCM/DCM mode transitions com-  

pared to DC level in LN mode  

—

—

200  

50  

—

—

mV  

mV  

Undershoot during BYP/LP to LN  

CCM (LNFORCECCM

3

= 1) mode  

transitions compared to DC level  

in LN mode  

Undershoot during BYP/LP to LN  

—

125  

—

mV  

DCM (LNFORCECCM

3

= 0) mode  

transitions compared to DC level  

in LN mode  

DC line regulation  

DC load regulation  

V

REG  

Input changes between  

V

VREGVDD_MAX

and 2.4 V  

—

—

0.1  

0.1  

—

—

%

%

I

REG  

Load changes between 0 mA and  

100 mA in CCM mode  

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Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Max load current  

I

LOAD_MAX  

Low noise (LN) mode, Heavy  

Drive

4  

—

—

200  

mA  

Low noise (LN) mode, Medium  

Drive

4  

—

—

—

—

—

—

—

—

100  

50  

mA  

mA  

μA  

Low noise (LN) mode, Light  

Drive

4  

Low power (LP) mode,  

LPCMPBIAS

3

= 0  

75  

Low power (LP) mode,  

LPCMPBIAS

3

= 3  

10  

mA  

DCDC nominal output ca-  

pacitor  

C

DCDC  

25% tolerance  

1

1

1

μF  

μH  

Ω

DCDC nominal output induc-

 

L

DCDC  

tor  

20% tolerance  

4.7  

—

4.7  

1.2  

4.7  

2.5  

Resistance in Bypass mode

 

R

BYP  

Note:  

1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, V

VREGVDD  

2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits  

3. In EMU_DCDCMISCCTRL register  

4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-  

um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.  

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4.1.4 Current

 

Consumption  

4.1.4.1 Current

 

Consumption 3.3 V without DC-DC Converter  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T

OP

= 25 °C.  

EMU_PWRCFG_PWRCG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table repre-  

sent the worst conditions across supply voltage and process variation at T

OP

= 25 °C. See

Figure 5.1

 

EFR32BG1 Typical Application  

Circuit: Direct Supply Configuration without DC-DC converter on page 64

.  

Table 4.4.

 

Current Consumption 3.3V without DC/DC  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

Active mode with all periph-  

erals disabled  

38.4 MHz crystal, CPU running  

while loop from flash

1  

—

130  

—

μA/MHz  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

—

88  

100  

112  

102  

222  

65  

—

105  

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

26 MHz HFRCO, CPU running  

while loop from flash  

106  

350  

—

1 MHz HFRCO, CPU running  

while loop from flash  

38.4 MHz crystal

1  

38 MHz HFRCO  

26 MHz HFRCO  

1 MHz HFRCO  

Current consumption in EM1

 

I

EM1  

Sleep mode with all peripher-  

als disabled  

—

—

—

—

35  

37  

38  

41  

μA/MHz  

μA/MHz  

μA/MHz  

μA  

157  

3.3  

275  

—

Current consumption in EM2

 

I

EM2  

Deep Sleep mode.  

Full RAM retention and RTCC  

running from LFXO  

4 kB RAM retention and RTCC  

running from LFRCO  

—

—

—

—

3

6.3  

6

μA  

μA  

μA  

μA  

Current consumption in EM3

 

I

EM3  

Stop mode  

Full RAM retention and CRYO-  

TIMER running from ULFRCO  

2.8  

1.1  

0.65  

Current consumption in  

EM4H Hibernate mode  

I

EM4  

128 byte RAM retention, RTCC  

running from LFXO  

—

—

128 byte RAM retention, CRYO-  

TIMER running from ULFRCO  

128 byte RAM retention, no RTCC  

no RAM retention, no RTCC  

—

—

0.65  

0.04  

1.3  

μA  

μA  

Current consumption in  

EM4S Shutoff mode  

I

EM4S  

0.11  

Note:  

1. CMU_HFXOCTRL_LOWPOWER=0  

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4.1.4.2 Current

 

Consumption 3.3 V using DC-DC Converter  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC  

output. T

OP

= 25 °C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process  

variation at T

OP

= 25 °C. See

Figure 5.2

 

EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from  

VDCDC) on page 64

.  

Table 4.5.

 

Current Consumption 3.3V with DC-DC  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

Active mode with all periph-  

erals disabled, DCDC in Low  

Noise DCM mode

1

.  

38.4 MHz crystal, CPU running  

while loop from flash

2  

—

88  

—

μA/MHz  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

63  

71  

78  

76  

98  

—

—

—

—

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

26 MHz HFRCO, CPU running  

while loop from flash  

Current consumption in EM0  

Active mode with all periph-  

erals disabled, DCDC in Low  

Noise CCM mode

3

.  

38.4 MHz crystal, CPU running  

while loop from flash

2  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

75  

81  

88  

94  

49  

—

—

—

—

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

26 MHz HFRCO, CPU running  

while loop from flash  

38.4 MHz crystal

2  

38 MHz HFRCO  

26 MHz HFRCO  

Current consumption in EM1

 

I

EM1  

Sleep mode with all peripher-  

als disabled, DCDC in Low  

Noise DCM mode

1

.  

—

—

—

32  

38  

61  

—

—

—

μA/MHz  

μA/MHz  

μA/MHz  

38.4 MHz crystal

2  

38 MHz HFRCO  

26 MHz HFRCO  

Current consumption in EM1  

Sleep mode with all peripher-  

als disabled, DCDC in Low  

Noise CCM mode

3

.  

—

—

—

45  

58  

—

—

—

μA/MHz  

μA/MHz  

μA  

Current consumption in EM2

 

I

EM2  

Deep Sleep mode. DCDC in  

Low Power mode

4

.  

Full RAM retention and RTCC  

running from LFXO  

2.5  

4 kB RAM retention and RTCC  

running from LFRCO  

—

—

—

—

—

2.3  

2.1  

—

—

—

—

—

μA  

μA  

μA  

μA  

μA  

Current consumption in EM3

 

I

EM3  

Stop mode  

Full RAM retention and CRYO-  

TIMER running from ULFRCO  

Current consumption in  

EM4H Hibernate mode  

I

EM4  

128 byte RAM retention, RTCC  

running from LFXO  

0.86  

0.58  

0.58  

128 byte RAM retention, CRYO-  

TIMER running from ULFRCO  

128 byte RAM retention, no RTCC  

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Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in  

EM4S Shutoff mode  

I

EM4S  

no RAM retention, no RTCC  

—

0.04  

—

μA  

Note:  

1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD  

2. CMU_HFXOCTRL_LOWPOWER=0  

3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD  

4. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPBIAS=3, LPCILIMSEL=1, ANASW=DVDD  

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Electrical Specifications  

4.1.4.3 Current

 

Consumption 1.85 V without DC-DC Converter  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.85 V. T

OP

= 25 °C.  

EMU_PWRCFG_PWRCG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table repre-  

sent the worst conditions across supply voltage and process variation at T

OP

= 25 °C. See

Figure 5.1

 

EFR32BG1 Typical Application  

Circuit: Direct Supply Configuration without DC-DC converter on page 64

.  

Table 4.6.

 

Current Consumption 1.85V without DC/DC  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

Active mode with all periph-  

erals disabled  

38.4 MHz crystal, CPU running  

while loop from flash

1  

—

131  

—

μA/MHz  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

—

88  

100  

112  

102  

220  

65  

—

—

—

—

—

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

26 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

38.4 MHz crystal

1  

38 MHz HFRCO  

26 MHz HFRCO  

1 MHz HFRCO  

Current consumption in EM1

 

I

EM1  

Sleep mode with all peripher-  

als disabled  

—

—

—

—

35  

37  

—

—

—

—

μA/MHz  

μA/MHz  

μA/MHz  

μA  

154  

3.2  

Current consumption in EM2

 

I

EM2  

Deep Sleep mode  

Full RAM retention and RTCC  

running from LFXO  

4 kB RAM retention and RTCC  

running from LFRCO  

—

—

—

—

2.8  

2.7  

1

—

—

—

—

μA  

μA  

μA  

μA  

Current consumption in EM3

 

I

EM3  

Stop mode  

Full RAM retention and CRYO-  

TIMER running from ULFRCO  

Current consumption in  

EM4H Hibernate mode  

I

EM4  

128 byte RAM retention, RTCC  

running from LFXO  

128 byte RAM retention, CRYO-  

TIMER running from ULFRCO  

0.62  

128 byte RAM retention, no RTCC  

No RAM retention, no RTCC  

—

—

0.62  

0.02  

—

—

μA  

μA  

Current consumption in  

EM4S Shutoff mode  

I

EM4S  

Note:  

1. CMU_HFXOCTRL_LOWPOWER=0  

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4.1.4.4 Current

 

Consumption Using Radio  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. T

OP

= 25 °C.  

Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T

OP

= 25 °C.  

See

Figure 5.2

 

EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64

or  

Figure 5.1

 

EFR32BG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter on page 64

.  

Table 4.7.

 

Current Consumption Using Radio 3.3 V with DC-DC  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in re-  

ceive mode, active packet  

reception (MCU in EM1 @  

38.4 MHz, peripheral clocks  

disabled)  

I

RX  

1 Mbit/s, 2GFSK, F = 2.4 GHz,  

Radio clock prescaled by 4  

—

8.7  

—

mA  

Current consumption in  

transmit mode (MCU in EM1  

@ 38.4 MHz, peripheral  

clocks disabled)  

I

TX  

F = 2.4 GHz, CW, 0 dBm output  

power, Radio clock prescaled by 3  

—

—

—

—

—

8.2  

—

—

—

—

—

mA  

mA  

mA  

mA  

mA  

F = 2.4 GHz, CW, 3 dBm output  

power  

16.5  

23.3  

32.7  

83.9  

F = 2.4 GHz, CW, 8 dBm output  

power  

F = 2.4 GHz, CW, 10.5 dBm out-  

put power  

F = 2.4 GHz, CW, 16.5 dBm out-  

put power, PAVDD connected di-  

rectly to external 3.3V supply  

F = 2.4 GHz, CW, 19.5 dBm out-  

put power, PAVDD connected di-  

rectly to external 3.3V supply  

—

—

126.7  

51  

—

—

mA  

nA  

RFSENSE current consump-

 

I

RFSENSE  

tion  

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4.1.5 Wake

 

up times  

Table 4.8.

 

Wake up times  

Parameter  

Symbol  

Test Condition  

Min  

—

Typ  

10.7  

3

Max  

—

Unit  

μs  

Wake up from EM2 Deep  

Sleep  

t

EM2_WU  

Code execution from flash  

Code execution from RAM  

Executing from flash  

—

—

μs  

Wakeup time from EM1  

Sleep  

t

EM1_WU  

—

3

—

AHB  

Clocks  

Executing from RAM  

—

3

—

AHB  

Clocks  

Wake up from EM3 Stop  

t

EM3_WU  

Executing from flash  

Executing from RAM  

Executing from flash  

—

—

—

10.7  

3

—

—

—

μs  

μs  

μs  

Wake up from EM4H Hiber-

 

t

EM4H_WU  

nate

1  

60  

Wake up from EM4S Shut-  

off

1  

t

EM4S_WU  

—

290  

—

μs  

Note:  

1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.  

4.1.6 Brown

 

Out Detector  

Table 4.9.

 

Brown Out Detector  

Parameter  

Symbol  

Test Condition  

DVDD rising  

Min  

—

Typ  

—

Max  

1.62  

—

Unit  

V

DVDDBOD threshold  

V

DVDDBOD  

DVDD falling  

1.35  

—

—

V

DVDD BOD hysteresis  

DVDD response time  

AVDD BOD threshold  

V

DVDDBOD_HYST  

24  

2.4  

—

—

mV  

μs  

V

t

DVDDBOD_DELAY

Supply drops at 0.1V/μs rate  

—

—

V

AVDDBOD  

AVDD rising  

AVDD falling  

—

1.85  

—

1.62  

—

—

V

AVDD BOD hysteresis  

AVDD response time  

EM4 BOD threshold  

V

AVDDBOD_HYST  

21  

2.4  

—

—

mV  

μs  

V

t

AVDDBOD_DELAY

Supply drops at 0.1V/μs rate  

—

—

V

EM4DBOD  

AVDD rising  

AVDD falling  

—

1.7  

—

1.45  

—

—

V

EM4 BOD hysteresis  

EM4 response time  

V

EM4BOD_HYST  

46  

300  

—

mV  

μs  

t

EM4BOD_DELAY

Supply drops at 0.1V/μs rate  

—

—

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4.1.7 Frequency

 

Synthesizer Characteristics  

Table 4.10.

 

Frequency Synthesizer Characteristics  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

RF Synthesizer Frequency  

range  

F

RANGE_2400  

2.4 GHz frequency range  

2400  

—

2483.5  

MHz  

LO tuning frequency resolu-

 

F

RES_2400  

tion with 38.4 MHz crystal  

2400 – 2483.5 MHz  

—

—

—

—

73  

Hz  

Maximum frequency devia-  

tion with 38.4 MHz crystal  

ΔF

MAX_2400  

1677  

kHz  

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4.1.8 2.4

 

GHz RF Transceiver Characteristics  

4.1.8.1 RF

 

Transmitter General Characteristics for the 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T

OP

= 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Test circuit according to  

Figure 5.2

 

EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64

and

Fig-  

ure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65

.  

Table 4.11.

 

RF Transmitter General Characteristics for 2.4 GHz Band  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Maximum TX power

1  

POUT

MAX  

19.5 dBm-rated part numbers.  

PAVDD connected directly to ex-  

ternal 3.3V supply

2  

—

19.5  

—

dBm  

10.5 dBm-rated part numbers  

0 dBm-rated part numbers  

CW  

—

—

10.5  

0

—

—

—

—

—

dBm  

dBm  

dBm  

dB  

Minimum active TX Power  

Output power step size  

POUT

MIN  

-30  

1

POUT

STEP  

-5 dBm< Output power < 0 dBm  

—

—

0 dBm < output power <  

POUT

MAX  

0.5  

dB  

Output power variation vs  

supply at POUT

MAX  

POUT

VAR_V  

1.85 V < V

VREGVDD

< 3.3 V,  

PAVDD connected directly to ex-  

ternal supply, for output power >  

10.5 dBm.  

—

4.5  

3.8  

—

dB  

dB  

1.85 V < V

VREGVDD

< 3.3 V,  

PAVDD connected directly to ex-  

ternal supply, for output power =  

10.5 dBm.  

—

—

1.85 V < V

VREGVDD

< 3.3 V using  

DC-DC converter  

—

—

2.2  

1.5  

1.5  

0.4  

—

—

—

dB  

dB  

Output power variation vs  

temperature at POUT

MAX  

POUT

VAR_T  

From -40 to +85 °C, PAVDD con-  

nected to DC-DC output  

From -40 to +85 °C, PAVDD con-  

nected to external supply  

—

—

dB  

Output power variation vs RF

 

POUT

VAR_F  

frequency at POUT

MAX  

Over RF tuning frequency range  

—

—

dB  

RF tuning frequency range  

F

RANGE  

2400  

2483.5  

MHz  

Note:  

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-  

ered in this datasheet can be found in the Max TX Power column of

2. Ordering Information  

2. For Bluetooth, the Maximum TX power on Channel 2456 is limited to +15 dBm to comply with In-band Spurious emissions.  

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4.1.8.2 RF

 

Receiver General Characteristics for the 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T

OP

= 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.440 GHz. Test circuit according  

to

Figure 5.2

 

EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64

and  

Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65

.  

Table 4.12.

 

RF Receiver General Characteristics for 2.4 GHz Band  

Parameter  

Symbol  

F

RANGE  

SPUR

RX  

Test Condition  

Min  

2400  

—

Typ  

—

Max  

2483.5  

—

Unit  

MHz  

dBm  

dBm  

dBm  

RF tuning frequency range  

Receive mode maximum  

spurious emission  

30 MHz to 1 GHz  

1 GHz to 12 GHz  

-57  

—

-47  

—

Max spurious emissions dur-

 

SPUR

RX_FCC  

ing active receive mode, per  

FCC Part 15.109(a)  

216 MHz to 960 MHz, Conducted  

Measurement  

—

-55.2  

—

Above 960 MHz, Conducted  

Measurement  

—

—

-47.2  

-24  

—

—

dBm  

dBm  

Level above which  

RFSENSE will trigger

1  

RFSENSE

TRIG  

RFSENSE

THRES  

SENS

2GFSK  

CW at 2.45 GHz  

Level below which  

RFSENSE will not trigger

1  

—

-50  

—

dBm  

2 Mbps 2GFSK signal

2  

250 kbps 2GFSK signal  

1% PER Sensitivity  

—

—

-89.2  

-99.1  

—

—

dBm  

dBm  

0.1% BER Sensitivity  

Note:  

1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.  

2. Channel at 2420 MHz will have degraded sensitivity. Sensitivity could be as high as -83dBm on this channel.  

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4.1.8.3 RF

 

Transmitter Characteristics for Bluetooth Smart in the 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T

OP

= 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.44 GHz. Test circuit according to  

Figure 5.2

 

EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64

and

Fig-  

ure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65

.  

Table 4.13.

 

RF Transmitter Characteristics for Bluetooth Smart in the 2.4GHz Band  

Parameter  

Symbol  

TXBW  

Test Condition  

Min  

—

Typ  

740  

-6.5  

Max  

—

Unit  

Transmit 6dB bandwidth  

Power spectral density limit  

kHz  

PSD

LIMIT  

Per FCC part 15.247 at 10 dBm  

Per FCC part 15.247 at 20 dBm  

—

—

dBm/  

3kHz  

—

—

—

-2.6  

10  

—

—

—

dBm/  

3kHz  

Per ETSI 300.328 at 10 dBm/1  

MHz  

dBm  

Occupied channel bandwidth

 

OCP

ETSI328  

per ETSI EN300.328  

99% BW at highest and lowest  

channels in band  

1.1  

MHz  

In-band spurious emissions

 

SPUR

INB  

at 10 dBm, with allowed ex-  

ceptions

1  

At ±2 MHz  

At ±3 MHz  

—

—

-39.8  

-42.1  

—

—

dBm  

dBm  

In-band spurious emissions  

at 20 dBm, with allowed ex-  

ceptions

1 2  

At ±2 MHz  

At ±3 MHz  

—

—

—

—

-20  

-30  

dBm  

dBm  

Emissions of harmonics out-

 

SPUR

HRM_FCC

2nd,3rd, 5, 6, 8, 9,10 harmonics;  

—

-47  

—

dBm  

of-band, per FCC part  

15.247  

continuous transmission of modu-  

lated carrier  

Spurious emissions out-of-  

band, per FCC part 15.247,  

excluding harmonics cap-  

tured in SPUR

HARM,FCC

. Re-  

stricted Bands  

SPUR

OOB_FCC  

Above 2.483 GHz or below 2.4  

GHz; continuous transmission of  

modulated carrier

3  

—

-47  

—

dBm  

Spurious emissions out-of-  

band, per FCC part 15.247,  

excluding harmonics cap-  

Above 2.483 GHz or below 2.4  

GHz; continuous transmission of  

modulated carrier  

—

-26  

—

dBc  

tured in SPUR

HARM,FCC  

.

Non Restricted Bands  

Spurious emissions out-of-  

band; per ETSI 300.328  

SPUR

ETSI328  

[2400-BW to 2400] MHz, [2483.5  

to 2483.5+BW] MHz  

—

—

-16  

-26  

—

—

dBm  

dBm  

[2400-2BW to 2400-BW] MHz,  

[2483.5+BW to 2483.5+2BW]  

MHz per ETSI 300.328  

Spurious emissions per ETSI

 

SPUR

ETSI440  

EN300.440  

47-74 MHz,87.5-108 MHz,  

174-230 MHz, 470-862 MHz  

—

-60  

—

dBm  

25-1000 MHz  

1-12 GHz  

—

—

-42  

-36  

—

—

dBm  

dBm  

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Electrical Specifications  

Parameter  

Note:  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

1. Per Bluetooth Core_4.2, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a frequency  

which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.  

2. For 2456 MHz, a maximum output power of 15 dBm is used to achieve this value.  

3. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value.  

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4.1.8.4 RF

 

Receiver Characteristics for Bluetooth Smart in the 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T

OP

= 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.440 GHz. Test circuit according  

to

Figure 5.2

 

EFR32BG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64

and  

Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65

.  

Table 4.14.

 

RF Receiver Characteristics for Bluetooth Smart in the 2.4GHz Band  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Signal is reference signal

1

. Packet  

length is 20 bytes.  

Max usable receiver input  

level, 0.1% BER  

SAT  

—

10  

—

dBm  

Sensitivity, 0.1% BER

2  

Signal is reference signal

1

. Using  

DC-DC converter  

SENS  

—

—

-91  

—

—

dBm  

dBm  

With non-ideal signals as speci-  

fied in RF-PHY.TS.4.2.2, section  

4.6.1  

-90.2  

Signal to co-channel interfer-

 

C/I

CC  

er, 0.1% BER  

Desired signal 3 dB above refer-  

ence sensitivity  

—

—

8.3  

—

—

dB  

dB  

N+1 adjacent channel (1  

MHz) selectivity, 0.1% BER,  

with allowable exceptions.  

Desired is reference signal at  

-67 dBm  

C/I

1+  

Interferer is reference signal at +1  

MHz offset. Desired frequency  

2402 MHz ≤ Fc ≤ 2480 MHz  

-3.3  

N-1 adjacent channel (1  

MHz) selectivity, 0.1% BER,  

with allowable exceptions.  

Desired is reference signal at  

-67 dBm  

C/I

1-  

Interferer is reference signal at -1  

MHz offset. Desired frequency  

2402 MHz ≤ Fc ≤ 2480 MHz  

—

1.3  

—

dB  

Alternate (2 MHz) selectivity,

 

C/I

2  

0.1% BER, with allowable  

exceptions. Desired is refer-  

ence signal at -67 dBm  

Interferer is reference signal at ± 2  

MHz offset. Desired frequency  

2402 MHz ≤ Fc ≤ 2480 MHz  

—

—

-39.5  

-43.8  

—

—

dB  

dB  

Alternate (3 MHz) selectivity,

 

C/I

3  

0.1% BER, with allowable  

exceptions. Desired is refer-  

ence signal at -67 dBm  

Interferer is reference signal at ±3  

MHz offset. Desired frequency  

2404 MHz ≤ Fc ≤ 2480 MHz  

Selectivity to image frequen-

 

C/I

IM  

cy, 0.1% BER. Desired is ref-  

erence signal at -67 dBm  

Interferer is reference signal at im-  

age frequency with 1 MHz preci-  

sion  

—

—

-29  

—

—

dB  

dB  

Selectivity to image frequen-

 

C/I

IM+1  

cy +1 MHz, 0.1% BER. De-  

sired is reference signal at  

-67 dBm  

Interferer is reference signal at im-  

age frequency +1 MHz with 1  

MHz precision  

-43.6  

Blocking, 0.1% BER, Desired

 

BLOCK

OOB  

is reference signal at -67  

dBm. Interferer is CW in  

OOB range.  

Interferer frequency 30 MHz ≤ f ≤  

2000 MHz  

—

—

—

—

-27  

-32  

-32  

-27  

—

—

—

—

dBm  

dBm  

dBm  

dBm  

Interferer frequency 2003 MHz ≤ f  

≤ 2399 MHz  

Interferer frequency 2484 MHz ≤ f  

≤ 2997 MHz  

Interferer frequency 3 GHz ≤ f ≤  

12.75 GHz  

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Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Intermodulation performance

 

IM  

Per Core_4.1, Vol 6, Part A, Sec-  

tion 4.4 with n = 3  

—

-25.8  

—

dBm  

Upper limit of input power  

range over which RSSI reso-  

lution is maintained  

RSSI

MAX  

4

—

—

—

—

-101  

0.5  

dBm  

dBm  

dB  

Lower limit of input power  

range over which RSSI reso-  

lution is maintained  

RSSI

MIN  

RSSI

RES  

—

—

RSSI resolution  

Over RSSI

MIN

to RSSI

MAX  

Note:  

1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;  

interferer data = PRBS15; frequency accuracy better than 1 ppm  

2. Receive sensitivity on Bluetooth Smart channel 26 is -86 dBm  

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4.1.8.5 RF

 

Transmitter Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD  

and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz. Test circuit according to

Figure  

5.2 EFR32BG1

 

Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64

and

Figure  

5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65

.  

Table 4.15.

 

RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4GHz Band  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Error vector magnitude (off-

 

EVM  

set EVM), per  

802.15.4-2011, not including  

2415 MHz channel

1  

Average across frequency. Signal  

is DSSS-OQPSK reference pack-  

et

2  

—

5.5  

—

% rms  

Power spectral density limit  

PSD

LIMIT  

Relative, at carrier ±3.5 MHz  

—

—

-26  

-36  

—

—

dBc  

Absolute, at carrier ±3.5 MHz

3  

Per FCC part 15.247  

dBm  

—

—

-4.2  

12  

—

—

dBm/  

3kHz  

Output power level which meets  

10dBm/MHz ETSI 300.328 speci-  

fication  

dBm  

Occupied channel bandwidth

 

OCP

ETSI328  

per ETSI EN300.328  

99% BW at highest and lowest  

channels in band  

—

—

2.25  

—

—

MHz  

dBm  

Spurious emissions of har-  

monics in restricted bands  

per FCC Part 15.205/15.209,  

Emissions taken at  

SPUR

HRM_FCC_

Continuous transmission of modu-  

-45.8  

lated carrier  

R

Pout_Max power level of  

19.5 dBm, PAVDD connec-  

ted to external 3.3 V supply,  

Test Frequency is 2450 MHz  

Spurious emissions of har-  

monics in harmonics in non-  

restricted bands per FCC  

Part 15.247/15.35, Emis-  

sions taken at Pout_Max  

power level of 19.5 dBm,  

PAVDD connected to exter-  

nal 3.3 V supply, Test Fre-  

quency is 2450 MHz  

SPUR

HRM_FCC_  

—

-26  

—

dBc  

NRR  

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Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Spurious emissions out-of-  

band in restricted bands  

(30-88 MHz), per FCC part  

15.205/15.209, Emissions  

taken at Pout_Max power  

level of 19.5 dBm, PAVDD  

connected to external 3.3 V  

supply, Test Frequency =  

2450 MHz  

SPUR

OOB_FCC_

Above 2.483 GHz or below 2.4  

—

-52  

—

dBm  

GHz; continuous transmission of  

R

modulated carrier

4  

Spurious emissions out-of-  

band in restricted bands  

(88-216 MHz), per FCC part  

15.205/15.209, Emissions  

taken at Pout_Max power  

level of 19.5 dBm, PAVDD  

connected to external 3.3 V  

supply, Test Frequency =  

2450 MHz  

—

—

—

—

-62  

-57  

-48  

-26  

—

—

—

—

dBm  

dBm  

dBm  

dBc  

Spurious emissions out-of-  

band in restricted bands  

(216-960 MHz), per FCC  

part 15.205/15.209, Emis-  

sions taken at Pout_Max  

power level of 19.5 dBm,  

PAVDD connected to exter-  

nal 3.3 V supply, Test Fre-  

quency = 2450 MHz  

Spurious emissions out-of-  

band in restricted bands  

(>960 MHz), per FCC part  

15.205/15.209, Emissions  

taken at Pout_Max power  

level of 19.5 dBm, PAVDD  

connected to external 3.3 V  

supply, Test Frequency =  

2450 MHz  

Spurious emissions out-of-  

band in non-restricted bands  

per FCC Part 15.247, Emis-  

sions taken at Pout_Max  

power level of 19.5 dBm,  

PAVDD connected to exter-  

nal 3.3 V supply, Test Fre-  

quency = 2450 MHz  

SPUR

OOB_FCC_

Above 2.483 GHz or below 2.4  

GHz; continuous transmission of  

NR  

modulated carrier  

Spurious emissions out-of-  

band; per ETSI 300.328

5  

SPUR

ETSI328  

[2400-BW to 2400], [2483.5 to  

2483.5+BW];  

—

—

-16  

-26  

—

—

dBm  

dBm  

[2400-2BW to 2400-BW],  

[2483.5+BW to 2483.5+2BW]; per  

ETSI 300.328  

Spurious emissions per ETSI

 

SPUR

ETSI440  

EN300.440

5  

47-74 MHz,87.5-108 MHz,  

174-230 MHz, 470-862 MHz  

—

—

—

-60  

-42  

-36  

—

—

—

dBm  

dBm  

dBm  

25-1000 MHz, excluding above  

frequencies  

1G-14G  

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Parameter  

Note:  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

1. Typical EVM for the 2415 MHz channel is 7.9%  

2. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with  

pseudo-random packet data content  

3. For 2415 MHz, a maximum duty cycle of 50% is used to achieve this value.  

4. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value.  

5. Specified at maximum power output level of 10 dBm  

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4.1.8.6 RF

 

Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD  

and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.445 GHz. Test circuit according to

Figure  

5.2 EFR32BG1

 

Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64

and

Figure  

5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65

.  

Table 4.16.

 

RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Signal is reference signal

1

. Packet  

length is 20 octets.  

Max usable receiver input  

level, 1% PER  

SAT  

—

10  

—

dBm  

Sensitivity, 1% PER

2  

SENS  

Signal is reference signal. Packet  

length is 20 octets. Using DC-DC  

converter.  

—

—

-101  

-101  

—

—

dBm  

dBm  

Signal is reference signal. Packet  

length is 20 octets. Without DC-  

DC converter.  

Co-channel interferer rejec-

 

CCR  

tion, 1% PER  

Desired signal 10 dB above sensi-  

tivity limit  

—

—

—

-2.6  

33.75  

52.2  

—

—

—

dB  

dB  

dB  

High-side adjacent channel  

rejection, 1% PER. Desired  

is reference signal at 3dB  

above reference sensitivity  

ACR

+1  

Interferer is reference signal at +1  

channel-spacing.  

Interferer is filtered reference sig-  

nal

4

at +1 channel-spacing.  

level

3  

Interferer is CW at +1 channel-  

spacing.

5  

—

58.6  

—

dB  

Low-side adjacent channel  

rejection, 1% PER. Desired  

is reference signal at 3dB  

above reference sensitivity  

ACR

-1  

ACR

2  

IR  

Interferer is reference signal at -1  

channel-spacing.  

—

—

35  

—

—

dB  

dB  

Interferer is filtered reference sig-  

nal

4

at -1 channel-spacing.  

54.7  

level

3  

Interferer is CW at -1 channel-  

spacing.  

—

—

—

60.1  

45.9  

56.8  

—

—

—

dB  

dB  

dB  

Alternate channel rejection,  

1% PER. Desired is refer-  

ence signal at 3dB above  

reference sensitivity level

3  

Interferer is reference signal at ±2  

channel-spacing  

Interferer is filtered reference sig-  

nal

4

at ±2 channel-spacing  

Interferer is CW at ±2 channel-  

spacing  

—

—

65.5  

40.8  

—

—

dB  

dB  

Interferer is CW in image band

5  

Image rejection, 1% PER,  

Desired is reference signal at  

3dB above reference sensi-  

tivity level

3  

Blocking rejection of all other

 

BLOCK  

channels. 1% PER, Desired  

is reference signal at 3dB  

above reference sensitivity  

level

3

. Interferer is reference  

signal.  

Interferer frequency < Desired fre-  

quency – 3 channel-spacing  

—

—

57.2  

57.9  

—

—

dB  

dB  

Interferer frequency > Desired fre-  

quency + 3 channel-spacing  

Blocking rejection of 802.11g

 

BLOCK

80211G  

signal centered at +12MHz  

or -13MHz  

Desired is reference signal at 6dB  

above reference sensitivity level

3  

—

51.6  

—

dB  

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Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Upper limit of input power  

range over which RSSI reso-  

lution is maintained  

RSSI

MAX  

5

—

—

dBm  

Lower limit of input power  

range over which RSSI reso-  

lution is maintained  

RSSI

MIN  

—

—

-98  

dBm  

RSSI resolution  

RSSI

RES  

RSSI

LIN  

over RSSI

MIN

to RSSI

MAX  

—

—

0.25  

±1  

—

—

dB  

dB  

RSSI accuracy in the linear  

region as defined by  

802.15.4-2003  

Note:  

1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-  

bols/s  

2. Receive sensitivity on 802.15.4 channel 14 is -98 dBm  

3. Reference sensitivity level is -85 dBm  

4. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-  

band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.  

5. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker  

tests place the Interferer center frequency at the Desired frequency ±5 MHz on the channel raster, whereas the image rejection  

test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.  

4.1.9 Modem

 

Features  

Table 4.17.

 

Modem Features  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Receive Bandwidth  

RX

Bandwidth  

Configurable range with 38.4 MHz  

crystal  

0.1  

—

2530  

kHz  

IF Frequency  

IF

Freq  

Configurable range with 38.4 MHz  

crystal. Selected steps available.  

150  

—

1371  

kHz  

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4.1.10 Oscillators  

4.1.10.1 LFXO  

Table 4.18.

 

LFXO  

Parameter  

Symbol  

Test Condition  

Min  

—

Typ  

32.768  

—

Max  

—

Unit  

kHz  

kΩ  

Crystal frequency  

f

LFXO  

Supported crystal equivalent

 

ESR

LFXO  

series resistance (ESR)  

—

70  

Supported range of crystal  

load capacitance

1  

C

LFXO_CL  

6

8

—

—

18  

40  

pF  

pF  

On-chip tuning cap range

2  

C

LFXO_T  

On each of LFXTAL_N and  

LFXTAL_P pins  

On-chip tuning cap step size

 

SS

LFXO  

—

—

0.25  

273  

—

—

pF  

nA  

ESR = 70 kΩ, C

L

= 7 pF, GAIN

4

=  

3, AGC

4

= 1  

Current consumption after  

startup

3  

I

LFXO