SKYWORKS-SILICON-LABS-EFR32BG21A010F512IM32-B

EFR32BG21 Blue Gecko Wireless SoC  

Family Data Sheet  

The Blue Gecko family of SoCs is part of the Wireless Gecko port-  

folio. Blue Gecko SoCs are ideal for enabling energy-friendly Blue-  

KEY FEATURES  

tooth 5 networking for IoT devices.  

• 32-bit

 

ARM® Cortex®-M33 core with 80  

MHz maximum operating frequency  

The single-die solution combines an 80 MHz ARM Cortex-M33 with a high performance  

2.4 GHz radio to provide an industry-leading, energy efficient wireless SoC for IoT con-  

nected applications.  

• Up

 

to 1024 kB of flash and 96 kB of RAM  

• 12-channel

 

Peripheral Reflex System  

enabling autonomous interaction of MCU  

peripherals  

Blue Gecko applications include:  

• Integrated

 

PA with up to 20 dBm (2.4  

GHz) TX power  

• Lighting  

• Robust

 

peripheral set and up to 20 GPIO  

in a 4×4 QFN package  

• Connected

 

Home  

• Gateways

 

and Digital Assistants  

• Building

 

Automation and Security  

Core / Memory  

Clock Management  

Energy  

Security  

Management  

Crypto Acceleration  

Secure Boot with  

Root of Trust and  

Secure Loader  

HF Crystal  

Oscillator  

HF  

Fast Startup  

RC Oscillator  

True Random  

Number Generator  

ARM Cortex

TM

M33 processor  

with DSP extensions,  

FPU and Trust Zone  

RC Oscillator  

Voltage  

Regulator  

Flash Program  

Memory  

DPA  

EM23 HF RC  

Oscillator  

Countermeasures  

EUI  

Brown-Out  

Detector  

Secure Debug  

Authentication  

LF Crystal  

Oscillator  

LF  

Ultra LF RC  

Oscillator  

LDMA  

Controller  

ETM  

Secure Debug  

RAM Memory  

Power-On Reset  

RC Oscillator  

Secure Element  

32-bit bus  

Peripheral Reflex System  

Radio Transceiver  

Serial  

I/O Ports  

Timers and Triggers  

Analog I/F  

Interfaces  

External  

Interrupts  

DEMOD  

RF Frontend  

USART  

I

2

C  

Timer/Counter  

Protocol Timer  

IADC  

I

LNA  

Q

General  

Purpose I/O  

Analog  

Comparator  

IFADC  

AGC  

PGA  

Watchdog Timer  

Low Energy Timer  

PA  

PA  

Real Time  

Capture Counter  

Pin Reset  

Frequency  

Synth  

Back-Up Real  

Time Counter  

MOD  

Pin Wakeup  

Lowest power mode with peripheral operational:  

EM0—Active  

EM1—Sleep  

EM2—Deep Sleep  

EM3—Stop  

EM4—Shutoff  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Feature List  

1. Feature

 

List  

The EFR32BG21 highlighted features are listed below.  

•

Low Power Wireless System-on-Chip  

•

Wide selection of MCU peripherals  

High Performance 32-bit 80 MHz ARM Cortex

®

-M33 with  

DSP instruction and floating-point unit for efficient signal  

processing  

•

• 12-bit

 

1 Msps SAR Analog to Digital Converter (ADC)  

• 2

 

× Analog Comparator (ACMP)  

• Up

 

to 20 General Purpose I/O pins with output state reten-  

tion and asynchronous interrupts  

• Up

 

to 1024 kB flash program memory  

• Up

 

to 96 kB RAM data memory  

• 8

 

Channel DMA Controller  

• 2.4

 

GHz radio operation  

• 12

 

Channel Peripheral Reflex System (PRS)  

• 2

 

× 16-bit Timer/Counter  

• TX

 

power up to 20 dBm  

•

Low Energy Consumption  

• 3

 

Compare/Capture/PWM channels  

• 1

 

× 32-bit Timer/Counter  

• 8.8

 

mA RX current at 2.4 GHz (1 Mbps GFSK)  

• 9.3

 

mA TX current @ 0 dBm output power at 2.4 GHz  

• 33.8

 

mA TX current @ 10 dBm output power at 2.4 GHz  

• 50.9

 

μA/MHz in Active Mode (EM0)  

• 5.0

 

μA EM2 DeepSleep current  

• 3

 

Compare/Capture/PWM channels  

• 32-bit

 

Real Time Counter  

• 24-bit

 

Low Energy Timer for waveform generation  

• 2

 

× Watchdog Timer  

• 3

 

× Universal Synchronous/Asynchronous Receiver/Trans-  

mitter (UART/SPI/SmartCard(ISO 7816)/IrDA/I

2

S)  

(96 kB RAM retention and RTC running from LFXO)  

• 4.5

 

μA EM2 DeepSleep current  

2 × I

2

C interface with SMBus support  

•

(16 kB RAM retention and RTC running from LFRCO)  

•

High Receiver Performance  

•

Wide Operating Range  

• 1.71

 

to 3.8 V single power supply  

• -40

 

to 125 °C ambient  

• -97.5

 

dBm sensitivity @ 1 Mbit/s GFSK  

• -94.4

 

dBm sensitivity @ 2 Mbit/s GFSK  

• -104.9

 

dBm sensitivity @ 125 kbps GFSK  

•

Supported Modulation Format  

• GFSK  

•

Security  

• Secure

 

Boot with Root of Trust and Secure Loader (RTSL)  

• Hardware

 

Cryptographic Acceleration with DPA counter-  

measures for AES128/256, SHA-1, SHA-2 (up to 256-bit),  

ECC (up to 256-bit), ECDSA, ECDH and J-Pake  

•

Protocol Support  

• True

 

Random Number Generator (TRNG) compliant with  

NIST SP800-90 and AIS-31  

• Bluetooth

 

Low Energy (Bluetooth 5)  

• ARM®

 

TrustZone®  

• Secure

 

Debug with lock/unlock  

•

QFN32 4×4 mm Package  

• 0.4

 

mm pitch  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Ordering Information  

2. Ordering

 

Information  

Table 2.1.

 

Ordering Information  

Max TX Power @ Fre-  

Flash RAM  

Pack-  

GPIO age  

Ordering Code  

Protocol Stack

 

quency Band  

(kB)  

(kB)  

Security  

EFR32BG21A010F1024IM32-B  

Bluetooth 5.1  

Bluetooth 5.1  

Bluetooth 5.1  

Bluetooth 5.1  

Bluetooth 5.1  

Bluetooth 5.1  

10 dBm @ 2.4 GHz  

10 dBm @ 2.4 GHz  

10 dBm @ 2.4 GHz  

20 dBm @ 2.4 GHz  

20 dBm @ 2.4 GHz  

20 dBm @ 2.4 GHz  

1024  

96  

Secure Ele-  

ment  

20  

20  

20  

20  

20  

20  

QFN32  

QFN32  

QFN32  

QFN32  

QFN32  

QFN32  

EFR32BG21A010F512IM32-B  

EFR32BG21A010F768IM32-B  

EFR32BG21A020F1024IM32-B  

EFR32BG21A020F512IM32-B  

EFR32BG21A020F768IM32-B  

512  

768  

1024  

512  

768  

64  

64  

96  

64  

64  

Secure Ele-  

ment  

Secure Ele-  

ment  

Secure Ele-  

ment  

Secure Ele-  

ment  

Secure Ele-  

ment  

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Table of Contents  

1. Feature

 

List .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

2  

2. Ordering

 

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

3  

3. System

 

Overview .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

6  

3.1 Introduction .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

6  

3.2 Radio .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

6  

3.2.1 Antenna

 

Interface .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .

 

6  

3.2.2 Fractional-N

 

Frequency Synthesizer

 

. . . . . . . . . . . . . . . . . . . . .

 

7  

3.2.3 Receiver

 

Architecture .

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

7  

3.2.4 Transmitter

 

Architecture . . . . . . . . . . . . . . . . . . . . . . . . .

 

7  

3.2.5 Packet

 

and State Trace

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

7  

3.2.6 Data

 

Bufferin

g

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

7  

3.2.7 Radio

 

Controller (RAC).

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

7  

3.3 General

 

Purpose Input/Output (GPIO)

 

. . . . . . . . . . . . . . . . . . . . . .

 

8  

3.4 Clocking .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.4.1 Clock

 

Management Unit (CMU) .

 

. . . . . . . . . . . . . . . . . . . . . .

 

8  

3.4.2 Internal

 

and External Oscillators.

 

. . . . . . . . . . . . . . . . . . . . . .

 

8  

3.5 Counters/Timers

 

and PWM .

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.5.1 Timer/Counter

 

(TIMER) .

 

. . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.5.2 Low

 

Energy Timer (LETIMER)

 

. . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.5.3 Real

 

Time Clock with Capture (RTCC)

 

. . . . . . . . . . . . . . . . . . . .

 

9  

3.5.4 Back-Up

 

Real Time Counter .

 

. . . . . . . . . . . . . . . . . . . . . . .

 

9  

3.5.5 Watchdog

 

Timer (WDOG

)

.

 

. . . . . . . . . . . . . . . . . . . . . . . .

 

9  

3.6 Communications

 

and Other Digital Peripherals

 

. . . . . . . . . . . . . . . . . . .

 

9  

3.6.1 Universal

 

Synchronous/Asynchronous Receiver/Transmitter (USART) .

 

. . . . . . . . .

 

9  

2

3.6.2 Inter-Integrated

 

Circuit Interface (I

 

C) .

 

. . . . . . . . . . . . . . . . . . . .

 

9  

3.6.3 Peripheral

 

Reflex System (PRS)

 

. . . . . . . . . . . . . . . . . . . . . .

 

9  

3.7 Security

 

Features .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

9  

3.7.1 Secure

 

Boot with Root of Trust and Secure Loader (RTSL)

 

. . . . . . . . . . . . .10  

3.7.2 Cryptographic

 

Accelerato

r

. . . . . . . . . . . . . . . . . . . . . . . . .10  

3.7.3 True

 

Random Number Generator

 

. . . . . . . . . . . . . . . . . . . . . .10  

3.7.4 Secure

 

Debug with Lock/Unlock.

 

. . . . . . . . . . . . . . . . . . . . . .10  

3.8 Analo

g

.

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10  

3.8.1 Analog

 

Comparator (ACMP) .

 

. . . . . . . . . . . . . . . . . . . . . . .10  

3.8.2 Analog

 

to Digital Converter (IADC) .

 

. . . . . . . . . . . . . . . . . . . . .11  

3.9 Reset

 

Management Unit (RMU)

 

. . . . . . . . . . . . . . . . . . . . . . . .11  

3.10 Core

 

and Memory

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .11  

3.10.1 Processor

 

Core .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .11  

3.10.2 Memory

 

System Controller (MSC)

 

. . . . . . . . . . . . . . . . . . . . .11  

3.10.3 Linked

 

Direct Memory Access Controller (LDMA)

 

. . . . . . . . . . . . . . . .11  

3.11 Memory

 

Map .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  

3.12 Configuration

 

Summary . . . . . . . . . . . . . . . . . . . . . . . . . .13  

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4. Electrical

 

Specifications .

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

14  

4.1 Electrical

 

Characteristics .

 

. . . . . . . . . . . . . . . . . . . . . . . . .14  

4.1.1 Absolute

 

Maximum Ratings

 

. . . . . . . . . . . . . . . . . . . . . . . .14  

4.1.2 General

 

Operating Conditions

 

. . . . . . . . . . . . . . . . . . . . . . .15  

4.1.3 Thermal

 

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .16  

4.1.4 Current

 

Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .17  

4.1.5 2.4

 

GHz RF Transceiver Characteristics .

 

. . . . . . . . . . . . . . . . . . .22  

4.1.6 Flash

 

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .35  

4.1.7 Wake

 

Up, Entry, and Exit times .

 

. . . . . . . . . . . . . . . . . . . . . .36  

4.1.8 Oscillators .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37  

4.1.9 GPIO

 

Pins (3V GPIO pins)

 

. . . . . . . . . . . . . . . . . . . . . . . .42  

4.1.10 Analog

 

to Digital Converter (ADC)

 

. . . . . . . . . . . . . . . . . . . . .43  

4.1.11 Analog

 

Comparator (ACMP)

 

. . . . . . . . . . . . . . . . . . . . . . .45  

4.1.12 Temperature

 

Sense . . . . . . . . . . . . . . . . . . . . . . . . . .46  

4.1.13 Brown

 

Out Detectors

 

. . . . . . . . . . . . . . . . . . . . . . . . . .47  

4.1.14 SPI

 

Electrical Specifications

 

. . . . . . . . . . . . . . . . . . . . . . .49  

4.1.15 I2C

 

Electrical Specifications.

 

. . . . . . . . . . . . . . . . . . . . . . .50  

4.2 Typical

 

Performance Curves

 

. . . . . . . . . . . . . . . . . . . . . . . . .52  

4.2.1 Supply

 

Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .53  

4.2.2 2.4

 

GHz Radio

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .55  

5. Typical

 

Connection Diagrams

 

. . . . . . . . . . . . . . . . . . . . . . . .

 

57  

5.1 Power

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57  

5.2 RF

 

Matching Networks

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .57  

5.2.1 2.4

 

GHz 0 dBm Matching Network .

 

. . . . . . . . . . . . . . . . . . . . .57  

5.2.2 2.4

 

GHz 10 dBm Matching Network

 

. . . . . . . . . . . . . . . . . . . . .58  

5.2.3 2.4

 

GHz 20 dBm Matching Network

 

. . . . . . . . . . . . . . . . . . . . .59  

5.3 Other

 

Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . .59  

6. Pin

 

Definitions .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  

6.1 QFN32

 

2.4GHz Device Pinout .

 

. . . . . . . . . . . . . . . . . . . . . . . .60  

6.2 Alternate

 

Function Table.

 

. . . . . . . . . . . . . . . . . . . . . . . . . .61  

6.3 Analog

 

Peripheral Connectivity

 

. . . . . . . . . . . . . . . . . . . . . . . .62  

6.4 Digital

 

Peripheral Connectivity .

 

. . . . . . . . . . . . . . . . . . . . . . . .63  

7. QFN32

 

Package Specifications.

 

. . . . . . . . . . . . . . . . . . . . . . .

 

66  

7.1 QFN32

 

Package Dimensions

 

. . . . . . . . . . . . . . . . . . . . . . . . .66  

7.2 QFN32

 

PCB Land Pattern

 

. . . . . . . . . . . . . . . . . . . . . . . . . .68  

7.3 QFN32

 

Package Marking

 

. . . . . . . . . . . . . . . . . . . . . . . . . .70  

8. Revision

 

History .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

71  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

System Overview  

3. System

 

Overview  

3.1 Introduction  

The EFR32 product family combines an energy-friendly MCU with a high performance radio transceiver. The devices are well suited for  

secure connected IoT multiprotocol devices requiring high performance and low energy consumption. This section gives a short intro-  

duction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG21 Reference Manual.  

A block diagram of the EFR32BG21 family is shown in

Figure 3.1 Detailed EFR32BG21 Block Diagram on page 6

. The diagram  

shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult  

Ordering Information

.  

Radio Transciever  

Port I/O Configuration  

Digital Peripherals  

IOVDD  

RF Frontend  

DEMOD  

IFADC  

AGC  

I

LNA  

Q

PGA  

RF2G4_IO1  

RF2G4_IO2  

LETIMER  

PA  

PA  

Port A  

Drivers  

PAn  

Frequency  

Synthesizer  

TIMER  

RTC  

MOD  

Port B  

PBn  

PCn  

PDn  

Drivers  

USART  

I2C  

Port  

Mapper  

Reset  

Management  

Unit  

Port C  

Drivers  

ARM Cortex-M33 Core  

RESETn  

Serial Wire  

and ETM  

Debug /  

Up to 1024 kB Flash  

Program Memory  

Debug Signals  

(shared w/GPIO)  

Brown Out /  

Power-On  

Reset  

Crypto  

Accelerator  

Port D  

Drivers  

Up to 96 KB RAM  

Trust Zone  

Programming  

A

H

B

A

P

B

TRNG  

CRC  

Floating Point Unit  

DMA Controller  

Energy Management  

PAVDD  

RFVDD  

IOVDD  

AVDD  

Analog Peripherals  

Watchdog  

Timer  

Internal  

Reference  

DVDD  

Clock Management  

ULFRCO  

Voltage  

Regulator  

VDD  

12-bit ADC  

FSRCO  

HFRCOEM2  

LFRCO  

LFXO  

DECOUPLE  

LFXTAL_I  

LFXTAL_O  

HFXTAL_I  

HFXTAL_O  

+

–

HFRCO  

HFXO  

Analog Comparator  

Figure 3.1.

 

Detailed EFR32BG21 Block Diagram  

3.2 Radio  

The EFR32BG21 Blue Gecko features a highly configurable radio transceiver supporting the Bluetooth Low Energy wireless protocol.  

3.2.1 Antenna

 

Interface  

The 2.4 GHz antenna interface consists of two single-ended pins (RF2G4_IO1 and RF2G4_IO2) that interface directly to two LNAs and  

two 10 dBm PAs. For devices that support 20 dBm, these pins also interface to the 20 dBm on-chip balun. Integrated switches select  

either RF2G4_IO1 or RF2G4_IO2 to be the active path.  

The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching  

Networks section.  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

System Overview  

3.2.2 Fractional-N

 

Frequency Synthesizer  

The EFR32BG21 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is  

used in receive mode to generate the LO frequency for the down-conversion mixer. It is also used in transmit mode to directly generate  

the modulated RF carrier.  

The fractional-N architecture provides excellent phase noise performance, frequency resolution better than 100 Hz, and low energy  

consumption. The synthesizer’s fast frequency settling allows for very short receiver and transmitter wake up times to reduce system  

energy consumption.  

3.2.3 Receiver

 

Architecture  

The EFR32BG21 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion  

mixer. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital converter (IFADC).  

The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-  

ing flexibility with respect to known interferers at the image frequency.  

The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-  

tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance.  

Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-  

ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and  

compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by  

block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).  

A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-  

nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received  

frame and the dynamic RSSI measurement can be monitored throughout reception.  

3.2.4 Transmitter

 

Architecture  

The EFR32BG21 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls  

phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping  

filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-  

ing.  

Carrier Sense Multiple Access – Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by  

the EFR32BG21. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-  

tween devices that otherwise lack synchronized RF channel access.  

3.2.5 Packet

 

and State Trace  

The EFR32BG21 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.  

It features:  

• Non-intrusive

 

trace of transmit data, receive data and state information  

• Data

 

observability on a single-pin UART data output, or on a two-pin SPI data output  

• Configurable

 

data output bitrate / baudrate  

• Multiplexed

 

transmitted data, received data and state / meta information in a single serial data stream  

3.2.6 Data

 

Buffering  

The EFR32BG21 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64  

bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.  

3.2.7 Radio

 

Controller (RAC)  

The Radio Controller controls the top level state of the radio subsystem in the EFR32BG21. It performs the following tasks:  

• Precisely-timed

 

control of enabling and disabling of the receiver and transmitter circuitry  

• Run-time

 

calibration of receiver, transmitter and frequency synthesizer  

• Detailed

 

frame transmission timing, including optional LBT or CSMA-CA  

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System Overview  

3.3 General

 

Purpose Input/Output (GPIO)  

EFR32BG21 has up to 20 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or  

input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO  

pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to  

several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-  

als. The GPIO subsystem supports asynchronous external pin interrupts.  

All of the pins on ports A and port B are EM2 capable. These pins may be used by Low-Energy peripherals in EM2/3 and may also be  

used as EM2/3 pin wake-ups. Pins on ports C and D are latched/retained in their current state when entering EM2 until EM2 exit upon  

which internal peripherals could once again drive those pads.  

A few GPIOs also have EM4 wake functionality. These pins are listed in

6.2 Alternate Function Table

.  

3.4 Clocking  

3.4.1 Clock

 

Management Unit (CMU)  

The Clock Management Unit controls oscillators and clocks in the EFR32BG21. Individual enabling and disabling of clocks to all periph-  

eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility  

allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and  

oscillators.  

3.4.2 Internal

 

and External Oscillators  

The EFR32BG21 supports two crystal oscillators and fully integrates five RC oscillators, listed below.  

• A

 

high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-  

ence for the MCU and RF synthesizer. The HFXO provides excellent RF clocking performance using a 38.4 MHz crystal. The HFXO  

can also support an external clock source such as a TCXO for applications that require an extremely accurate clock frequency over  

temperature.  

• A

 

32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.  

• An

 

integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The  

HFRCO employs fast start-up at minimal energy consumption combined with a wide frequency range, from 1 MHz to 80 MHz.  

• An

 

integrated high frequency RC oscillator (HFRCOEM2) runs down to EM2 and is available for timing the general-purpose ADC  

and the Serial Wire Viewer port with a wide frequency range.  

• An

 

integrated fast start-up RC oscillator (FSRCO) that runs at a fixed 20 MHz  

• An

 

integrated low frequency 32.768 kHz RC oscillator (LFRCO) for low power operation where high accuracy is not required.  

• An

 

integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-  

sumption in low energy modes.  

3.5 Counters/Timers

 

and PWM  

3.5.1 Timer/Counter

 

(TIMER)  

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the  

Peripheral Reflex System (PRS). The core of each TIMER is a 16-bit or 32-bit counter with up to 3 compare/capture channels. Each  

channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In  

compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER  

supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the  

compare registers. In addition some timers offer dead-time insertion.  

See

3.12 Configuration Summary

for information on the feature set of each timer.  

3.5.2 Low

 

Energy Timer (LETIMER)  

The unique LETIMER is a 24-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This  

allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed  

while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-  

forms with minimal software intervention. The LETIMER is connected to the Peripheral Reflex System (PRS), and can be configured to  

start counting on compare matches from other peripherals such as the RTCC.  

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System Overview  

3.5.3 Real

 

Time Clock with Capture (RTCC)  

The Real Time Clock with Capture (RTCC) is a 32-bit counter providing timekeeping down to EM3. The RTCC can be clocked by any of  

the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined intervals.  

A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli-  

cation software.  

3.5.4 Back-Up

 

Real Time Counter  

The Back-Up Real Time Counter (BURTC) is a 32-bit counter providing timekeeping in all energy modes, including EM4. The BURTC  

can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined inver-  

vals.  

3.5.5 Watchdog

 

Timer (WDOG)  

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed  

monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can  

also monitor autonomous systems driven by the Peripheral Reflex System (PRS).  

3.6 Communications

 

and Other Digital Peripherals  

3.6.1 Universal

 

Synchronous/Asynchronous Receiver/Transmitter (USART)  

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous  

UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-  

porting:  

• ISO7816

 

SmartCards  

• IrDA  

I

2

S  

•

3.6.2 Inter-Integrated

 

Circuit Interface (I

2

C)  

The I

2

C module provides an interface between the MCU and a serial I

2

C bus. It is capable of acting as both a master and a slave and  

supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10  

kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The  

interface provided to software by the I

2

C module allows precise timing control of the transmission process and highly automated trans-  

fers. Automatic recognition of slave addresses is provided in active and low energy modes. Note that not all instances of I

2

C are avalia-  

ble in all energy modes.  

3.6.3 Peripheral

 

Reflex System (PRS)  

The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.  

Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-  

erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)  

can be applied by the PRS to the signals. The PRS allows peripherals to act autonomously without waking the MCU core, saving pow-  

er.  

3.7 Security

 

Features  

A dedicated security CPU enables the Secure Element function. It isolates cryptographic functions and data from the host Cortex-M33  

core and provides the following security features:  

• Secure

 

Boot with Root of Trust and Secure Loader (RTSL)  

• Cryptographic

 

Accelerator  

• True

 

Random Number Generator (TRNG)  

• Secure

 

Debug with Lock/Unlock  

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System Overview  

3.7.1 Secure

 

Boot with Root of Trust and Secure Loader (RTSL)  

The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM).  

It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed and protects Over The Air updates.  

More information on this feature can be found in the Application Note

AN1218: Series 2 Secure Boot with RTSL

.  

3.7.2 Cryptographic

 

Accelerator  

The Cryptographic Accelerator is an autonomous hardware accelerator with Differential Power Analysis (DPA) countermeasures to pro-  

tect keys.  

It supports AES encryption and decryption with 128/192/256-bit keys, Elliptic Curve Cryptography(ECC) to support public key opera-  

tions and hashes.  

Supported block cipher modes of operation for AES include:  

• ECB

 

(Electronic Code Book)  

• CTR

 

(Counter Mode)  

• CBC

 

(Cipher Block Chaining)  

• CFB

 

(Cipher Feedback)  

• GCM

 

(Galois Counter Mode)  

• CBC-MAC

 

(Cipher Block Chaining Message Authentication Code)  

• GMAC

 

(Galois Message Authentication Code)  

• CCM

 

(Counter with CBC-MAC)  

The Cryptographic Accelerator accelerates Elliptical Curve Cryptography and supports the NIST (National Institute of Standards and  

Technology) recommended curves including P-192 and P-256 for ECDH(Elliptic Curve Diffie-Hellman) key derivation and ECDSA (El-  

liptic Curve Digital Signature Algorithm) sign and verify operations.  

Supported hashes include SHA-1, SHA2/224, and SHA-2/256.  

This implementation provides a fast and energy efficient solution to state of the art cryptographic needs.  

3.7.3 True

 

Random Number Generator  

The True Random Number Generator module is a non-deterministic random number generator that harvests entropy from a thermal  

energy source. It includes start-up health tests for the entropy source as required by NIST SP800-90B and AIS-31 as well as online  

health tests required for NIST SP800-90C.  

The TRNG is suitable for periodically generating entropy to seed an approved pseudo random number generator.  

3.7.4 Secure

 

Debug with Lock/Unlock  

For obvious security reasons, it is critical for a product to have its debug interface locked before being released in the field.  

In addition, the Secure Element also provides a secure debug unlock function that allows authenticated access based on public key  

cryptography. This functionality is particularly useful for supporting failure analysis while maintaining confidentiality of IP and sensitive  

end-user data.  

More information on this feature can be found in the Application Note

AN1190: EFR32xG21 Secure Debug

.  

3.8 Analog  

3.8.1 Analog

 

Comparator (ACMP)  

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-  

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption  

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The  

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the  

programmable threshold.  

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System Overview  

3.8.2 Analog

 

to Digital Converter (IADC)  

The IADC is a hybrid architecture combining techniques from both SAR and Delta-Sigma style converters. It has a resolution of up to 12  

bits at up to 1 Msps. Hardware oversampling reduces system-level noise over multiple front-end samples. The IADC includes integrated  

voltage references. Inputs are selectable from a wide range of sources, including pins configurable as either single-ended or differential.  

3.9 Reset

 

Management Unit (RMU)  

The RMU is responsible for handling reset of the EFR32BG21. A wide range of reset sources are available, including several power  

supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.  

3.10 Core

 

and Memory  

3.10.1 Processor

 

Core  

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:  

• ARM

 

Cortex-M33 RISC processor achieving 1.50 Dhrystone MIPS/MHz  

• ARM

 

TrustZone security technology  

• Embedded

 

Trace Macrocell (ETM) for real-time trace and debug  

• Up

 

to 1024 kB flash program memory  

• Up

 

to 96 kB RAM data memory  

• Configuration

 

and event handling of all modules  

• 2-pin

 

Serial-Wire debug interface  

3.10.2 Memory

 

System Controller (MSC)  

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable  

from both the Cortex-M and DMA. In addition to the main flash array where Program code is normally written the MSC also provides an  

Information block where additional information such as special user information or flash-lock bits are stored. There is also a read-only  

page in the information block containing system and device calibration data. Read and write operations are supported in energy modes  

EM0 Active and EM1 Sleep.  

3.10.3 Linked

 

Direct Memory Access Controller (LDMA)  

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This  

reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-  

phisticated operations to be implemented.  

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System Overview  

3.11 Memory

 

Map  

The EFR32BG21 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.  

Figure 3.2.

 

EFR32BG21 Memory Map — Core Peripherals and Code Space  

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System Overview  

3.12 Configuration

 

Summary  

The features of the EFR32BG21 are a subset of the feature set described in the device reference manual. The table below describes  

device specific implementation of the features. Remaining modules support full configuration.  

Table 3.1.

 

Configuration Summary  

Module  

TIMER0  

TIMER1  

TIMER2  

USART0  

USART1  

USART2  

I2C0  

Lowest Energy Mode  

Configuration  

EM1  

EM1  

EM1  

EM1  

EM1  

EM1  

EM2  

EM1  

32-bit, 3-channels, +DTI  

16-bit, 3-channels, +DTI  

16-bit, 3-channels, +DTI  

+IrDA, +I2S, +SmartCard  

+IrDA, +I2S, +SmartCard  

+IrDA, +I2S, +SmartCard  

I2C1  

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Electrical Specifications  

4. Electrical

 

Specifications  

4.1 Electrical

 

Characteristics  

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:  

• Typical

 

values are based on T

A

=25 °C and all supplies at 3.0 V, by production test and/or technology characterization.  

• Radio

 

performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-  

er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.  

• Minimum

 

and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,  

unless stated otherwise.  

4.1.1 Absolute

 

Maximum Ratings  

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of  

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure  

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-  

bility data, see the Quality and Reliability Monitor Report at

.  

Table 4.1.

 

Absolute Maximum Ratings  

Parameter  

Symbol  

T

STG  

Test Condition  

Min  

-50  

—

Typ  

—

Max  

+150  

+135  

3.8  

Unit  

°C  

Storage temperature range  

Junction temperature  

Voltage on any supply pin  

T

JMAX  

-I grade  

—

°C  

V

DDMAX  

V

DDRAMPMAX  

-0.3  

—

—

V

Voltage ramp rate on any  

supply pin  

—

1.0  

V / µs  

Voltage on HFXO pins  

V

HFXOPIN  

-0.3  

-0.3  

—

—

1.2  

V

V

DC voltage on any GPIO pin

 

V

DIGPIN  

V

IOVDD  

0.3  

+

Input RF level on pins  

RF2G4_IO1 and  

RF2G4_IO2  

P

RFMAX2G4  

—

—

+10  

dBm  

Absolute voltage on RF pins

 

V

MAX2G4  

RF2G4_IOx  

-0.3  

—

—

—

—

V

PAVDD  

V

Total current into VDD power

 

I

VDDMAX  

lines  

Source  

Sink  

200  

mA  

mA  

Total current into VSS  

ground lines  

I

VSSMAX  

—

200  

Current per I/O pin  

I

IOMAX  

Sink  

—

—

—

—

—

—

—

—

50  

50  

mA  

mA  

mA  

mA  

Source  

Sink  

Current for all I/O pins  

I

IOALLMAX  

200  

200  

Source  

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Electrical Specifications  

4.1.2 General

 

Operating Conditions  

This table specifies the general operating temperature range and supply voltage range for all supplies. The minimum and maximum  

values of all other tables are specifed over this operating range, unless otherwise noted.  

Table 4.2.

 

General Operating Conditions  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

-I temperature grade

1  

Operating ambient tempera-

 

T

A  

ture range  

-40  

—

+125  

° C  

DVDD supply voltage  

V

DVDD  

EM0/1  

1.71  

1.71  

3.0  

3.0  

3.8  

3.8  

V

V

EM2/3/4

2  

AVDD supply voltage  

V

AVDD  

1.71  

1.71  

3.0  

3.0  

3.8  

3.8  

V

V

IOVDDx operating supply  

voltage (All IOVDD pins)  

V

IOVDDx  

PAVDD operating supply  

voltage  

V

PAVDD  

1.71  

1.71  

0.75  

3.0  

3.0  

1.0  

3.8  

V

PAVDD  

2.75  

V

V

RFVDD operating supply  

voltage  

V

RFVDD  

DECOUPLE output capaci-  

tor

3  

C

DECOUPLE  

µF  

MODE = WS1, RAMWSEN = 1

4  

MODE = WS1, RAMWSEN = 0

4  

MODE = WS0, RAMWSEN = 0

4  

HCLK and Core frequency  

f

HCLK  

—

—

—

—

—

—

—

—

—

—

80  

50  

39  

50  

80  

MHz  

MHz  

MHz  

MHz  

MHz  

PCLK frequency  

f

PCLK  

EM01 Group A clock fre-  

quency  

f

EM01GRPACLK  

HCLK Radio frequency

5  

f

HCLKRADIO  

38  

38.4  

40  

MHz  

Note:  

1. The device may operate continuously at the maximum allowable ambient T

A

rating as long as the absolute maximum T

JMAX

is not  

exceeded. For an application with significant power dissipation, the allowable T

A

may be lower than the maximum T

A

rating. T

A

=  

T

JMAX

– (THETA

JA

x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for  

T

JMAX

and THETA

JA  

.

2. The DVDD supply is monitored by the DVDD BOD in EM0/1 and the LE DVDD BOD in EM2/3/4.  

3. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-  

ue stays within the specified bounds across temperature and DC bias.  

4. Flash wait states are set by the MODE field in the MSC_READCTRL register. RAM wait states are enabled by setting the RAMW-  

SEN bit in the SYSYCFG_DMEM0RAMCTRL register.  

5. The recommended radio crystal frequency is 38.4 MHz. Any crystal frequency other than 38.4 is expressly not supported. The  

minimum and maximum HCLKRADIO frequency in this table represent the design limits, which are much wider than the typical  

crystal tolerance.  

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Electrical Specifications  

4.1.3 Thermal

 

Characteristics  

Table 4.3.

 

Thermal Characteristics  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

2-Layer PCB, Natural Convection

1  

4-Layer PCB, Natural Convection

1  

2-Layer PCB, Natural Convection

1  

4-Layer PCB, Natural Convection

1  

Thermal Resistance Junction

 

THE-  

to Ambient QFN32 (4x4mm)

 

TA

JA_QFN32_4X4  

Package  

—

94.3  

—

°C/W  

—

—

—

35.4  

36.3  

23.5  

—

—

—

°C/W  

°C/W  

°C/W  

Thermal Resistance Junction

 

THE-  

to Case QFN32 (4x4mm)  

Package  

TA

JC_QFN32_4X4  

Note:  

1. Measured according to JEDEC standard JESD51-2A. Integrated Circuit Thermal Test Method Environmental Conditions – Natural  

Convection (Still Air).  

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Electrical Specifications  

4.1.4 Current

 

Consumption  

4.1.4.1 MCU

 

current consumption at 1.8V  

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = 1.8V. T

A

= 25 °C. Minimum and maximum  

values in this table represent the worst conditions across process variation at T

A

= 25 °C.  

Table 4.4.

 

MCU current consumption at 1.8V  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

mode with all peripherals dis-  

abled

1  

80 MHz HFRCO, CPU running  

Prime from flash  

—

50.9  

—

µA/MHz  

80 MHz HFRCO, CPU running  

while loop from flash  

—

—

—

—

—

—

—

45.5  

59.7  

63.6  

55.5  

59.1  

67.0  

360  

—

—

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

80 MHz HFRCO, CPU running  

CoreMark loop from flash  

38.4 MHz crystal, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

while loop from flash  

26 MHz HFRCO, CPU running  

while loop from flash  

16 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

Current consumption in EM1

 

I

EM1  

mode with all peripherals dis-  

80 MHz HFRCO  

38.4 MHz crystal  

38 MHz HFRCO  

26 MHz HFRCO  

16 MHz HFRCO  

1 MHz HFRCO  

—

—

—

—

—

—

—

28.7  

46.7  

38.7  

42.2  

50.0  

343  

5.0  

—

—

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA  

abled

1  

Current consumption in EM2

 

I

EM2  

mode  

Full RAM retention and RTC run-  

ning from LFXO  

Full RAM retention and RTC run-  

ning from LFRCO  

—

—

—

—

5.0  

4.5  

4.7  

4.2  

—

—

—

—

µA  

µA  

µA  

µA  

1 bank (16kB) RAM retention and  

RTC running from LFRCO  

Current consumption in EM3

 

I

EM3  

mode  

Full RAM retention and RTC run-  

ning from ULFRCO  

1 bank (16kB) RAM retention and  

RTC running from ULFRCO  

Current consumption in EM4

 

I

EM4  

mode  

No BURTC, no LF oscillator  

BURTC with LFXO  

—

—

—

0.14  

0.51  

107  

—

—

—

µA  

µA  

µA  

Current consumption during

 

I

RST  

reset  

Hard pin reset held  

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Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current Consumption per re-

 

I

RAM  

tained 16kB RAM bank in  

EM2  

—

0.10  

—

µA  

Note:  

1. The typical EM0/EM1 current measurement includes some current consumed by the security core for periodical housekeeping  

purposes. This does not include current consumed by user-triggered security operations, such as cryptographic calculations.  

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Electrical Specifications  

4.1.4.2 MCU

 

current consumption at 3.0V  

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = 3.0 V. T

A

= 25 °C. Minimum and maximum  

values in this table represent the worst conditions across process variation at T

A

= 25 °C.  

Table 4.5.

 

MCU current consumption at 3.0V  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

mode with all peripherals dis-  

abled

1  

80 MHz HFRCO, CPU running  

Prime from flash  

—

50.9  

—

µA/MHz  

80 MHz HFRCO, CPU running  

while loop from flash  

—

—

—

—

—

—

—

45.6  

59.8  

63.8  

55.6  

59.1  

67.1  

362  

55.5  

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

80 MHz HFRCO, CPU running  

CoreMark loop from flash  

38.4 MHz crystal, CPU running  

while loop from flash  

—

38 MHz HFRCO, CPU running  

while loop from flash  

75.1  

—

26 MHz HFRCO, CPU running  

while loop from flash  

16 MHz HFRCO, CPU running  

while loop from flash  

—

1 MHz HFRCO, CPU running  

while loop from flash  

1018  

Current consumption in EM1

 

I

EM1  

mode with all peripherals dis-  

80 MHz HFRCO  

38.4 MHz crystal  

38 MHz HFRCO  

26 MHz HFRCO  

16 MHz HFRCO  

1 MHz HFRCO  

—

—

—

—

—

—

—

28.7  

46.9  

38.7  

42.2  

50.2  

345  

5.1  

37.6  

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA  

abled

1  

57.5  

—

—

994  

—

Current consumption in EM2

 

I

EM2  

mode  

Full RAM retention and RTC run-  

ning from LFXO  

Full RAM retention and RTC run-  

ning from LFRCO  

—

—

—

—

5.0  

4.5  

4.8  

4.3  

—

10.5  

11.4  

—

µA  

µA  

µA  

µA  

1 bank (16 kB) RAM retention and  

RTC running from LFRCO  

Current consumption in EM3

 

I

EM3  

mode  

Full RAM retention and RTC run-  

ning from ULFRCO  

1 bank (16 kB) RAM retention and  

RTC running from ULFRCO  

Current consumption in EM4

 

I

EM4  

mode  

No BURTC, no LF oscillator  

BURTC with LFXO  

—

—

—

0.21  

0.61  

146  

0.5  

—

µA  

µA  

µA  

Current consumption during

 

I

RST  

reset  

Hard pin reset held  

—

Current consumption per re-

 

I

RAM  

tained 16kB RAM bank in  

EM2  

—

0.10  

—

µA  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Note:  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

1. The typical EM0/EM1 current measurement includes some current consumed by the security core for periodical housekeeping  

purposes. This does not include current consumed by user-triggered security operations, such as cryptographic calculations.  

4.1.4.3 Radio

 

current consumption at 1.8V  

RF current consumption measured with MCU in EM1, HCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indica-  

ted, typical conditions are: AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8V. Minimum and maximum values in this table represent  

the worst conditions across process variation at T

A

= 25 °C.  

Table 4.6.

 

Radio current consumption at 1.8V  

Parameter  

Symbol  

Test Condition  

Min  

—

—

—

—

—

—

—

—

—

Typ  

9.0  

9.1  

8.8  

9.4  

9.0  

9.0  

9.0  

9.8  

9.3  

Max  

—

—

—

—

—

—

—

—

—

Unit  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

Current consumption in re-  

ceive mode, active packet  

reception  

I

RX_ACTIVE  

125 kbit/s, 2GFSK, f = 2.4 GHz  

500 kbit/s, 2GFSK, f = 2.4 GHz  

1 Mbit/s, 2GFSK, f = 2.4 GHz  

2 Mbit/s, 2GFSK, f = 2.4 GHz  

125 kbit/s, 2GFSK, f = 2.4 GHz  

500 kbit/s, 2GFSK, f = 2.4 GHz  

1 Mbit/s, 2GFSK, f = 2.4 GHz  

2 Mbit/s, 2GFSK, f = 2.4 GHz  

Current consumption in re-  

ceive mode, listening for  

packet  

I

RX_LISTEN  

Current consumption in  

transmit mode  

I

TX  

f = 2.4 GHz, CW, 0 dBm PA, 0  

dBm output power  

f = 2.4 GHz, CW, 10 dBm PA, 0  

dBm output power  

—

—

16.6  

33.8  

—

—

mA  

mA  

f = 2.4 GHz, CW, 10 dBm PA, 10  

dBm output power  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

4.1.4.4 Radio

 

current consumption at 3.0V  

RF current consumption measured with MCU in EM1, HCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indica-  

ted, typical conditions are: AVDD = DVDD = IOVDD = RFVDD = PAVDD = 3.0V. Minimum and maximum values in this table represent  

the worst conditions across process variation at T

A

= 25 °C.  

Table 4.7.

 

Radio current consumption at 3.0V  

Parameter  

Symbol  

Test Condition  

Min  

—

—

—

—

—

—

—

—

—

Typ  

9.0  

9.1  

8.8  

9.4  

9.0  

9.0  

9.0  

9.8  

10.5  

Max  

—

—

—

—

—

—

—

—

—

Unit  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

Current consumption in re-  

ceive mode, active packet  

reception  

I

RX_ACTIVE  

125 kbit/s, 2GFSK, f = 2.4 GHz  

500 kbit/s, 2GFSK, f = 2.4 GHz  

1 Mbit/s, 2GFSK, f = 2.4 GHz  

2 Mbit/s, 2GFSK, f = 2.4 GHz  

125 kbit/s, 2GFSK, f = 2.4 GHz  

500 kbit/s, 2GFSK, f = 2.4 GHz  

1 Mbit/s, 2GFSK, f = 2.4 GHz  

2 Mbit/s, 2GFSK, f = 2.4 GHz  

Current consumption in re-  

ceive mode, listening for  

packet  

I

RX_LISTEN  

Current consumption in  

transmit mode  

I

TX  

f = 2.4 GHz, CW, 0 dBm PA, 0  

dBm output power  

f = 2.4 GHz, CW, 10 dBm PA, 0  

dBm output power  

—

—

—

16.7  

34.0  

60.8  

—

—

—

mA  

mA  

mA  

f = 2.4 GHz, CW, 10 dBm PA, 10  

dBm output power  

f = 2.4 GHz, CW, 20 dBm PA, 10  

dBm output power, PAVDD = 3.0  

V

f = 2.4 GHz, CW, 20 dBm PA, 20  

—

185  

—

mA  

dBm output power, PAVDD = 3.3  

V

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

4.1.5 2.4

 

GHz RF Transceiver Characteristics  

4.1.5.1 RF

 

Transmitter Characteristics  

4.1.5.1.1 RF

 

Transmitter General Characteristics for the 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T

A

= 25 °C, PAVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD. Crystal  

frequency=38.4 MHz. RF center frequency 2.45 GHz. Antenna port 2.  

Table 4.8.

 

RF Transmitter General Characteristics for the 2.4 GHz Band  

Parameter  

Symbol  

F

RANGE  

Test Condition  

Min  

2400  

—

Typ  

—

Max  

2483.5  

—

Unit  

MHz  

dBm  

RF tuning frequency range  

Maximum TX power

1  

Maximum TX power  

Maximum TX power  

Minimum active TX Power  

POUT

MAX  

20 dBm PA, PAVDD = 3.3V  

+20.2  

POUT

MAX10  

POUT

MAX0  

POUT

MIN  

10 dBm PA  

—

—

—

—

—

—

+10.5  

+0.4  

-20.5  

-19.3  

-23.5  

1.5  

—

—

—

—

—

—

dBm  

dBm  

dBm  

dBm  

dBm  

dB  

0 dBm PA  

20 dBm PA, PAVDD = 3.3 V  

10 dBm PA  

0 dBm PA  

Output power step size  

POUT

STEP  

0 dBm PA,-15 dBm < Output  

Power < -5 dBm  

0 dBm PA,-5 dBm < Output Pow-  

er < 0 dBm  

—

—

—

—

—

—

0.3  

1.5  

1.0  

0.7  

0.5  

0.8  

—

—

—

—

—

—

dB  

dB  

dB  

dB  

dB  

dB  

10 dBm PA, -5 dBm < Output  

power < 0 dBm  

10 dBm PA, 0 dBm < output pow-  

er < 10 dBm  

20 dBm PA, 0 dBm < Output Pow-  

er < 5 dBm  

20 dBm PA, 5 dBm < output pow-  

er < POUT

MAX  

Output power variation vs  

PAVDD supply voltage varia-  

tion, frequency = 2450MHz  

POUT

VAR_V  

20 dBm PA P

out

= POUT

MAX

out-  

put power with PAVDD voltage  

swept from 3.0V to 3.8V.  

10 dbm PA output power with  

PAVDD voltage swept from 1.8 V  

to 3.0 V  

—

—

—

0.1  

0.1  

1.5  

—

—

—

dB  

dB  

dB  

0 dBm PA output power with  

PAVDD voltage swept from 1.8 V  

to 3.0 V  

Output power variation vs  

temperature, Frequency =  

2450MHz  

POUT

VAR_T  

AVDD = 3.3V supply, 20 dBm PA  

at P

out

= POUT

MAX

, (-40 to +125  

°C)  

10 dBm PA at 10 dBm, (-40 to  

+125 °C)  

—

—

0.3  

2.1  

—

—

dB  

dB  

0 dBm PA at 0 dBm, (-40 to +125  

°C)  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Output power variation vs RF

 

POUT

VAR_F  

frequency  

20 dBm PA, POUT

MAX

, PAVDD =  

3.3 V.  

—

0.2  

—

dB  

10 dBm PA, 10 dBm  

0 dBm PA, 0 dBm  

—

—

—

0.2  

0.1  

-47  

—

—

—

dB  

dB  

Spurious emissions of har-  

monics in restricted bands  

per FCC Part 15.205/15.209  

SPUR

HRM_FCC_

Continuous transmission of CW  

dBm  

carrier. P

out

= POUT

MAX

. PAVDD  

= 3.3V. Test Frequency =  

2450MHz.  

R

Continuous transmission of CW  

carrier, P

out

= 10 dBm, Test Fre-  

quency = 2450 MHz.  

—

—

-47  

-26  

—

—

dBm  

dBc  

Spurious emissions of har-  

monics in non-restricted  

bands per FCC Part  

15.247/15.35  

SPUR

HRM_FCC_

Continuous transmission of CW  

carrier, P

out

= POUT

MAX

, PAVDD  

= 3.3V, Test Frequency =  

2450MHz.  

NRR  

Continuous transmission of CW  

carrier. P

out

= 10 dBm. Test Fre-  

quency = 2450 MHz.  

—

-26  

—

dBc  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Spurious emissions out-of-  

band (above 2.483 GHz or  

below 2.4 GHz) in restricted  

bands, per FCC part  

SPUR

OOB_FCC_

Restricted bands 30-88 MHz,  

—

-47  

—

dBm  

Continuous transmission of CW  

R

carrier, 20 dBm PA, P

out  

=

POUT

MAX

, PAVDD = 3.3V. Test  

Frequency = 2450MHz.  

15.205/15.209  

Restricted bands 88 – 216 MHz,  

Continuous transmission of CW  

—

—

—

-47  

-47  

-47  

—

—

—

dBm  

dBm  

dBm  

carrier, 20 dBm PA, P

out  

=

POUT

MAX

, PAVDD = 3.3V. Test  

Frequency = 2450MHz.  

Restricted bands 216 – 960 MHz,  

Continuous transmission of CW  

carrier, 20 dBm PA P

out  

=

POUT

MAX

, PAVDD = 3.3V. Test  

Frequency = 2450MHz.  

Restricted bands >960 MHz, Con-  

tinuous transmission of CW carri-  

er, 20 dBm PA, P

out

= POUT

MAX  

,

PAVDD = 3.3V, Test Frequency =  

2450MHz.  

Restricted bands 30-88 MHz,  

Continuous transmission of CW  

carrier, P

out

= 10 dBm, Test Fre-  

quency = 2450 MHz  

—

—

—

—

-47  

-47  

-47  

-47  

—

—

—

—

dBm  

dBm  

dBm  

dBm  

Restricted bands 88 – 216 MHz,  

Continuous transmission of CW  

carrier, P

out

= 10 dBm, Test Fre-  

quency = 2450 MHz  

Restricted bands 216 – 960 MHz,  

Continuous transmission of CW  

carrier, P

out

= 10 dBm, Test Fre-  

quency = 2450 MHz  

Restricted bands > 960 MHz,  

Continuous transmission of CW  

carrier, P

out

= 10 dBm, Test Fre-  

quency = 2450 MHz  

Spurious emissions per ETSI

 

SPUR

ETSI440  

EN300.440  

1G-14G, P

out

= 10 dBm, Test Fre-  

quency = 2450 MHz  

—

—

-36  

-56  

—

—

dBm  

dBm  

47-74 MHz,87.5-108 MHz,  

174-230 MHz, 470-862 MHz, P

out  

= 10 dBm, Test Frequency = 2450  

MHz  

25-1000 MHz, excluding above  

frequencies. P

out

= 10 dBm, Test  

Frequency = 2450 MHz  

—

—

-42  

-50  

—

—

dBm  

dBm  

1G-12.75 GHz, excluding bands  

listed above, P

out

= 10 dBm, Test  

Frequency = 2450MHz.  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Spurious emissions out-of-  

band in non-restricted bands  

per FCC Part 15.247  

SPUR

OOB_FCC_

Frequencies above 2.483 GHz or  

—

-26  

—

dBc  

below 2.4 GHz, continuous trans-  

NR  

mission CW carrier, 20 dBm PA,  

P

out

= POUT

MAX

, PAVDD = 3.3  

V,Test Frequency = 2450 MHz  

Frequencies above 2.483 GHz or  

below 2.4 GHz, continuous trans-  

mission CW carrier, P

out

= 10  

dBm, Test Frequency = 2450  

MHz  

—

-26  

—

dBc  

Spurious emissions out-of-  

band, per ETSI 300.328  

SPUR

ETSI328  

[2400-2BW to 2400-BW],  

[2483.5+BW to 2483.5+2BW],  

P

out

= 10 dBm, Test Frequency =  

2450 MHz  

—

—

-26  

-16  

—

—

dBm  

dB  

[2400-BW to 2400], [2483.5 to  

2483.5+BW] P

out

= 10 dBm, Test  

Frequency = 2450MHz.  

Note:  

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-  

ered in this data sheet can be found in the Max TX Power column of the Ordering Information Table.  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

4.1.5.1.2 RF

 

Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate  

Unless otherwise indicated, typical conditions are: T

A

= 25 °C, PAVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD. Crystal  

frequency=38.4 MHz. RF center frequency 2.45 GHz. Antenna port 2.  

Table 4.9.

 

RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate  

Parameter  

Symbol  

Test Condition  

Min  

—

Typ  

635.1  

672.9  

646.5  

+6.4  

Max  

—

Unit  

kHz  

kHz  

kHz  

Transmit 6 dB bandwidth  

TXBW  

PAVDD = 3.3 V, P

out

= POUT

MAX  

P

out

= 10 dBm  

—

—

P

out

= 0 dBm  

—

—

Power spectral density limit  

PSD

LIMIT  

PAVDD = 3.3 V, P

out

= POUT

MAX  

Per FCC part 15.247  

,

—

—

dBm/  

3kHz  

P

out

= 10 dBm, Per FCC part  

15.247 at 10 dBm  

—

—

—

—

—

—

—

—

—

—

—

-3.7  

-13.6  

+10.2  

1.1  

—

—

—

—

—

—

—

—

—

—

—

dBm/  

3kHz  

P

out

= 0 dBm, Per FCC part  

15.247 at 0 dBm  

dBm/  

3kHz  

Per ETSI 300.328 at 10 dBm/1  

MHz  

dBm  

MHz  

MHz  

dBm  

dBm  

dBm  

dBm  

dBm  

dBm  

Occupied channel bandwidth

 

OCP

ETSI328  

per ETSI EN300.328  

P

out

= 10 dBm 99% BW at highest  

and lowest channels in band  

P

out

= 0 dBm 99% BW at highest  

and lowest channels in band  

1.1  

In-band spurious emissions,

 

SPUR

INB  

with allowed exceptions

1  

PAVDD = 3.3 V, P

out

= POUT

MAX  

Inband spurs at ± 2 MHz  

,

-26.3  

-36.4  

-46.3  

-20  

P

out

= 10 dbm, Inband spurs at ±  

2 MHz  

P

out

= 0 dbm, Inband spurs at ± 2  

MHz  

PAVDD = 3.3 V, P

out

= POUT

MAX  

Inband spurs at ± 3 MHz  

P

out

= 10 dBm Inband spurs at ± 3  

MHz  

-41.9  

-51.5  

P

out

= 0dbm Inband spurs at ± 3  

MHz  

Note:  

1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a  

frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

4.1.5.1.3 RF

 

Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate  

Unless otherwise indicated, typical conditions are: T

A

= 25 °C, PAVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD. Crystal  

frequency=38.4 MHz. RF center frequency 2.45 GHz. Antenna port 2.  

Table 4.10.

 

RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate  

Parameter  

Symbol  

Test Condition  

Min  

—

Typ  

Max  

—

Unit  

kHz  

kHz  

kHz  

Transmit 6 dB bandwidth  

TXBW  

PAVDD = 3.3 V, P

out

= POUT

MAX  

P

out

= 10 dBm  

1238.6  

1182.5  

1249.7  

+3.7  

—

—

P

out

= 0 dBm  

—

—

Power spectral density limit  

PSD

LIMIT  

PAVDD = 3.3 V, P

out

= POUT

MAX  

Per FCC part 15.247  

,

—

—

dBm/  

3kHz  

P

out

= 10 dBm, Per FCC part  

15.247 at 10 dBm  

—

—

—

—

—

—

—

—

—

—

—

-6.4  

-16.2  

+9.0  

2.1  

—

—

—

—

—

—

—

—

—

—

—

dBm/  

3kHz  

P

out

= 0 dBm, Per FCC part  

15.247 at 0 dBm  

dBm/  

3kHz  

Per ETSI 300.328 at 10 dBm/1  

MHz  

dBm  

MHz  

MHz  

dBm  

dBm  

dBm  

dBm  

dBm  

dBm  

Occupied channel bandwidth

 

OCP

ETSI328  

per ETSI EN300.328  

P

out

= 10 dBm 99% BW at highest  

and lowest channels in band  

P

out

= 0 dBm 99% BW at highest  

and lowest channels in band  

2.1  

In-band spurious emissions,

 

SPUR

INB  

with allowed exceptions

1  

PAVDD = 3.3 V P

out

= POUT

MAX  

Inband spurs at ± 2 MHz  

,

-31.7  

-41.9  

-51.7  

-35.7  

-46.0  

-55.7  

P

out

= 10 dBm, Inband spurs at ±  

4 MHz  

P

out

= 0 dBm, Inband spurs at ± 4  

MHz  

PAVDD = 3.3 V P

out

= POUT

MAX  

Inband spurs at ± 6 MHz  

P

out

= 10 dBm Inband spurs at ± 6  

MHz  

P

out

= 0 dbm Inband spurs at ± 6  

MHz  

Note:  

1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a  

frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

4.1.5.1.4 RF

 

Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate  

Unless otherwise indicated, typical conditions are: T

A

= 25 °C, PAVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD. Crystal  

frequency=38.4 MHz. RF center frequency 2.45 GHz. Antenna port 2.  

Table 4.11.

 

RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate  

Parameter  

Symbol  

Test Condition  

Min  

—

Typ  

770.9  

760.1  

775.1  

+5.4  

Max  

—

Unit  

kHz  

kHz  

kHz  

Transmit 6 dB bandwidth  

TXBW  

PAVDD = 3.3 V, P

out

= POUT

MAX  

P

out

= 10 dBm  

—

—

P

out

= 0 dBm  

—

—

Power spectral density limit  

PSD

LIMIT  

PAVDD = 3.3 V, P

out

= POUT

MAX  

Per FCC part 15.247  

,

—

—

dBm/  

3kHz  

P

out

= 10 dBm, Per FCC part  

15.247 at 10 dBm  

—

—

—

—

—

—

—

—

—

—

-4.6  

-14.4  

+10.2  

1.1  

—

—

—

—

—

—

—

—

—

—

dBm/  

3kHz  

P

out

= 0 dBm, Per FCC part  

15.247 at 0 dBm  

dBm/  

3kHz  

Per ETSI 300.328 at 10 dBm/1  

MHz  

dBm  

MHz  

MHz  

dBm  

dBm  

dBm  

dBm  

dBm  

Occupied channel bandwidth

 

OCP

ETSI328  

per ETSI EN300.328  

P

out

= 10 dBm 99% BW at highest  

and lowest channels in band  

P

out

= 0 dBm 99% BW at highest  

and lowest channels in band  

1.1  

In-band spurious emissions,

 

SPUR

INB  

with allowed exceptions

1  

P

out

= 10 dbm, Inband spurs at ±  

2 MHz  

-38.3  

-47.6  

-20  

P

out

= 0 dbm, Inband spurs at ± 2  

MHz  

PAVDD = 3.3 V, P

out

= POUT

MAX  

Inband spurs at ± 3 MHz  

P

out

= 10 dBm Inband spurs at ± 3  

MHz  

-42.3  

-51.8  

P

out

= 0dbm Inband spurs at ± 3  

MHz  

Note:  

1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a  

frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

4.1.5.1.5 RF

 

Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate  

Unless otherwise indicated, typical conditions are: T

A

= 25 °C, PAVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD. Crystal  

frequency=38.4 MHz. RF center frequency 2.45 GHz. Antenna port 2.  

Table 4.12.

 

RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate  

Parameter  

Symbol  

Test Condition  

Min  

—

Typ  

Max  

—

Unit  

kHz  

kHz  

kHz  

Transmit 6 dB bandwidth  

TXBW  

PAVDD = 3.3 V, P

out

= POUT

MAX  

P

out

= 10 dBm  

609.7  

619.3  

617.4  

+14.6  

—

—

P

out

= 0 dBm  

—

—

Power spectral density limit  

PSD

LIMIT  

PAVDD = 3.3 V, P

out

= POUT

MAX  

Per FCC part 15.247  

,

—

—

dBm/  

3kHz  

P

out

= 10 dBm, Per FCC part  

15.247 at 10 dBm  

—

—

—

—

—

—

—

—

—

—

—

+4.5  

-5.3  

—

—

—

—

—

—

—

—

—

—

—

dBm/  

3kHz  

P

out

= 0 dBm, Per FCC part  

15.247 at 0 dBm  

dBm/  

3kHz  

Per ETSI 300.328 at 10 dBm/1  

MHz  

+10.1  

1.1  

dBm  

MHz  

MHz  

dBm  

dBm  

dBm  

dBm  

dBm  

dBm  

Occupied channel bandwidth

 

OCP

ETSI328  

per ETSI EN300.328  

P

out

= 10 dBm 99% BW at highest  

and lowest channels in band  

P

out

= 0 dBm 99% BW at highest  

and lowest channels in band  

1.1  

In-band spurious emissions,

 

SPUR

INB  

with allowed exceptions

1  

PAVDD = 3.3 V, P

out

= POUT

MAX  

Inband spurs at ± 2 MHz  

,

-27.7  

-38.5  

-47.8  

-20  

P

out

= 10 dbm, Inband spurs at ±  

2 MHz  

P

out

= 0 dbm, Inband spurs at ± 2  

MHz  

PAVDD = 3.3 V, P

out

= POUT

MAX  

Inband spurs at ± 3 MHz  

P

out

= 10 dBm Inband spurs at ± 3  

MHz  

-42.4  

-51.8  

P

out

= 0dbm Inband spurs at ± 3  

MHz  

Note:  

1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a  

frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

4.1.5.2 RF

 

Receiver Characteristics  

4.1.5.2.1 RF

 

Receiver General Characteristics for the 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T

A

= 25 °C, PAVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD. Crystal  

frequency=38.4 MHz. RF center frequency 2.45 GHz. Antenna port 2.  

Table 4.13.

 

RF Receiver General Characteristics for the 2.4 GHz Band  

Parameter  

Symbol  

F

RANGE  

SPUR

RX  

Test Condition  

Min  

2400  

—

Typ  

—

Max  

2483.5  

—

Unit  

MHz  

dBm  

dBm  

dBm  

RF tuning frequency range  

Receive mode maximum  

spurious emission  

30 MHz to 1 GHz  

1 GHz to 12 GHz  

-54.8  

-57.1  

-54.8  

—

—

Max spurious emissions dur-

 

SPUR

RX_FCC  

ing active receive mode, per  

FCC Part 15.109(a)  

216 MHz to 960 MHz, conducted  

measurement  

—

—

Above 960 MHz, conducted  

measurement.  

—

-77.3  

—

dBm  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

4.1.5.2.2 RF

 

Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate  

Unless otherwise indicated, typical conditions are: T

A

= 25 °C, PAVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD. Crystal  

frequency=38.4 MHz. RF center frequency 2.45 GHz. Antenna port 2.  

Table 4.14.

 

RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Max usable receiver input  

level  

SAT  

Signal is reference signal, packet  

length is 37 bytes

1  

—

10  

—

dBm  

Sensitivity  

SENS  

Signal is reference signal, 37 byte  

payload

1  

—

-97.5  

—

dBm  

With non-ideal signals

2 1  

(see notes)

1 3  

—

—

-97.1  

+6.6  

—

—

dBm  

dB  

Signal to co-channel interfer-

 

C/I

CC  

er  

N ± 1 Adjacent channel se-  

lectivity  

C/I

1  

C/I

2  

C/I

3  

Interferer is reference signal at +1  

MHz offset

1 4 3 5  

—

—

—

—

—

—

—

-8.3  

-8.7  

—

—

—

—

—

—

—

dB  

dB  

dB  

dB  

dB  

dB  

dB  

Interferer is reference signal at -1  

MHz offset

1 4 3 5  

N ± 2 Alternate channel se-  

lectivity  

Interferer is reference signal at +2  

MHz offset

1 4 3 5  

-42.1  

-48.9  

-42.4  

-54.8  

-42.1  

Interferer is reference signal at -2  

MHz offset

1 4 3 5  

N ± 3 Alternate channel se-  

lectivity  

Interferer is reference signal at +3  

MHz offset

1 4 3 5  

Interferer is reference signal at -3  

MHz offset

1 4 3 5  

Selectivity to image frequen-

 

C/I

IM  

cy  

Interferer is reference signal at im-  

age frequency with 1 MHz preci-  

sion

1 5  

Selectivity to image frequen-

 

C/I

IM_1  

cy ± 1 MHz  

Interferer is reference signal at im-  

age frequency +1 MHz with 1  

—

—

—

-42.4  

-8.3  

-23  

—

—

—

dB  

dB  

MHz precision

1 5  

Interferer is reference signal at im-  

age frequency -1 MHz with 1 MHz  

precision

1 5  

n = 3

6  

Intermodulation performance

 

IM  

dBm  

Note:  

1. 0.1% Bit Error Rate.  

2. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1  

3. Desired signal -67 dBm.  

4. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.  

5. With allowed exceptions.  

6. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

4.1.5.2.3 RF

 

Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate  

Unless otherwise indicated, typical conditions are: T

A

= 25 °C, PAVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD. Crystal  

frequency=38.4 MHz. RF center frequency 2.45 GHz. Antenna port 2.  

Table 4.15.

 

RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Max usable receiver input  

level  

SAT  

Signal is reference signal, packet  

length is 37 bytes

1  

—

10  

—

dBm  

Sensitivity  

SENS  

Signal is reference signal, 37 byte  

payload

1  

—

-94.4  

—

dBm  

With non-ideal signals

2 1  

(see notes)

1 3  

—

—

-94.3  

+6.0  

—

—

dBm  

dB  

Signal to co-channel interfer-

 

C/I

CC  

er  

N ± 1 Adjacent channel se-  

lectivity  

C/I

1  

C/I

2  

C/I

3  

Interferer is reference signal at +2  

MHz offset

1 4 3 5  

—

—

—

—

—

—

—

-8.0  

-8.8  

—

—

—

—

—

—

—

dB  

dB  

dB  

dB  

dB  

dB  

dB  

Interferer is reference signal at -2  

MHz offset

1 4 3 5  

N ± 2 Alternate channel se-  

lectivity  

Interferer is reference signal at +4  

MHz offset

1 4 3 5  

-42.2  

-50.3  

-54.4  

-55.4  

-8.0  

Interferer is reference signal at -4  

MHz offset

1 4 3 5  

N ± 3 Alternate channel se-  

lectivity  

Interferer is reference signal at +6  

MHz offset

1 4 3 5  

Interferer is reference signal at -6  

MHz offset

1 4 3 5  

Selectivity to image frequen-

 

C/I

IM  

cy  

Interferer is reference signal at im-  

age frequency with 1 MHz preci-  

sion

1 5  

Selectivity to image frequen-

 

C/I

IM_1  

cy ± 1 MHz  

Interferer is reference signal at im-  

age frequency +2 MHz with 1  

—

—

—

-42.2  

+6.0  

—

—

—

dB  

dB  

MHz precision

1 5  

Interferer is reference signal at im-  

age frequency -2 MHz with 1 MHz  

precision

1 5  

n = 3

6  

Intermodulation performance

 

IM  

-22.3  

dBm  

Note:  

1. 0.1% Bit Error Rate.  

2. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1  

3. Desired signal -67 dBm.  

4. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.  

5. With allowed exceptions.  

6. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4  

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EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet  

Electrical Specifications  

4.1.5.2.4 RF

 

Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate  

Unless otherwise indicated, typical conditions are: T

A

= 25 °C, PAVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD. Crystal  

frequency=38.4 MHz. RF center frequency 2.45 GHz. Antenna port 2.  

Table 4.16.

 

RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Max usable receiver input  

level  

SAT  

Signal is reference signal, packet  

length is 37 bytes

1  

—

10  

—

dBm  

Signal is reference signal

1  

With non-ideal signals

2 1  

(see notes)

1 3  

Sensitivity  

SENS  

—

—

—

-100.6  

-100.0  

+2.1  

—

—

—

dBm  

dBm  

dB  

Signal to co-channel interfer-

 

C/I

CC  

er  

N ± 1 Adjacent channel se-  

lectivity  

C/I

1  

C/I

2  

C/I

3  

Interferer is reference signal at +1  

MHz offset

1 4 3 5  

—

—

—

—

—

—

—

-9.0  

-9.5  

—

—

—

—

—

—

—

dB  

dB  

dB  

dB  

dB  

dB  

dB  

Interferer is reference signal at -1  

MHz offset

1 4 3 5  

N ± 2 Alternate channel se-  

lectivity  

Interferer is reference signal at +2  

MHz offset

1 4 3 5  

-44.4  

-51.9  

-44.3  

-58.3  

-44.4  

Interferer is reference signal at -2  

MHz offset

1 4 3 5  

N ± 3 Alternate channel se-  

lectivity  

Interferer is reference signal at +3  

MHz offset

1 4 3 5  

Interferer is reference signal at -3  

MHz offset

1 4 3 5  

Selectivity to image frequen-

 

C/I

IM  

cy  

Interferer is reference signal at im-  

age frequency with 1 MHz preci-  

sion

1 5  

Selectivity to image frequen-

 

C/I