SKYWORKS-SILICON-LABS-EFR32BG22C222F352GM40-CR

EFR32BG22 Wireless Gecko SoC Family  

Data Sheet  

The EFR32BG22 Wireless Gecko family of SoCs is part of the  

Wireless Gecko portfolio. EFR32BG22 Wireless Gecko SoCs are  

KEY FEATURES  

ideal for enabling energy-friendly Bluetooth 5.2 networking for IoT  

devices.  

• 32-bit

 

ARM® Cortex®-M33 core with 76.8  

MHz maximum operating frequency  

• Up

 

to 512 kB of flash and 32 kB of RAM  

The single-die solution combines a 76.8 MHz Cortex-M33 with a high performance 2.4  

GHz radio to provide an industry-leading, energy efficient wireless, SoC for IoT connec-  

ted applications.  

• Energy-efficient

 

radio core with low active  

and sleep currents  

• Bluetooth

 

5.2 Direction Finding  

• Integrated

 

PA with up to 6 dBm (2.4 GHz)  

TX power  

Wireless Gecko applications include:  

• Asset

 

Tags and Beacons  

• Secure

 

Boot with Root of Trust and  

Secure Loader (RTSL)  

• Consumer

 

Electronics Remote Controls  

• Portable

 

Medical  

• Bluetooth

 

Mesh Low Power Nodes  

• Sports,

 

Fitness, and Wellness devices  

• Connected

 

Home  

• Building

 

Automation and Security  

Core / Memory  

Clock Management  

Energy Management  

Security  

HF Crystal  

Oscillator  

HF  

ARM Cortex

TM

M33 processor  

with DSP extensions,  

FPU and TrustZone  

RC Oscillator  

Voltage  

Regulator  

DC-DC  

Converter  

Flash Program  

Memory  

Crypto Acceleration  

Fast Startup  

RC Oscillator  

Precision LF  

RC Oscillator  

Power-On  

Reset  

Brown-Out  

Detector  

True Random  

Number Generator  

LDMA  

Controller  

LF Crystal  

Oscillator  

Ultra LF RC  

Oscillator  

ETM  

Debug Interface  

RAM Memory  

32-bit bus  

Peripheral Reflex System  

Radio Subsystem  

Serial  

I/O Ports  

Timers and Triggers  

Analog I/F  

Interfaces  

ARM Cortex

TM  

M0+ Radio  

Controller  

RFSENSE  

w/ OOK Detect  

DEMOD  

IFADC  

AGC  

External  

Interrupts  

USART  

PDM  

Timer/Counter  

Protocol Timer  

ADC  

General  

Purpose I/O  

Temperature  

Sensor  

Watchdog Timer  

Low Energy Timer  

RX/TX Frontend  

with Integrated PA  

BUFC RAM  

FRC  

Real Time  

Capture Counter  

Back-Up Real  

Time Counter  

EUART  

I

2

C  

Pin Reset  

Frequency  

Synthesizer  

MOD  

CRC  

Pin Wakeup  

Lowest power mode with peripheral operational:  

EM0—Active  

EM1—Sleep  

EM2—Deep Sleep  

EM3—Stop  

EM4—Shutoff  

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Rev. 1.0  

EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Feature List  

1. Feature

 

List  

The EFR32BG22 highlighted features are listed below.  

•

Low Power Wireless System-on-Chip  

•

Wide selection of MCU peripherals  

High Performance 32-bit 76.8 MHz MHz ARM Cortex

®

-M33  

with DSP instruction and floating-point unit for efficient sig-  

nal processing  

•

• Analog

 

to Digital Converter (ADC)  

• 12-bit

 

@ 1 Msps  

• 16-bit

 

@ 76.9 ksps  

• Up

 

to 512 kB flash program memory  

• Up

 

to 32 kB RAM data memory  

• Up

 

to 26 General Purpose I/O pins with output state reten-  

tion and asynchronous interrupts  

• 2.4

 

GHz radio operation  

• 8

 

Channel DMA Controller  

•

Radio Performance  

• 12

 

Channel Peripheral Reflex System (PRS)  

• -106.7

 

dBm sensitivity @ 125 kbps GFSK  

• -98.9

 

dBm sensitivity @ 1 Mbit/s GFSK  

• -96.2

 

dBm sensitivity @ 2 Mbit/s GFSK  

• TX

 

power up to 6 dBm  

• 4

 

× 16-bit Timer/Counter with 3 Compare/Capture/PWM  

channels  

• 1

 

× 32-bit Timer/Counter with 3 Compare/Capture/PWM  

channels  

• 32-bit

 

Real Time Counter  

• 2.5

 

mA radio receive current  

• 24-bit

 

Low Energy Timer for waveform generation  

• 1

 

× Watchdog Timer  

• 3.4

 

mA radio transmit current @ 0 dBm output power  

• 7.5

 

mA radio transmit current @ 6 dBm output power  

•

Low System Energy Consumption  

• 3.6

 

mA RX current (1 Mbps GFSK)  

• 4.1

 

mA TX current @ 0 dBm output power  

• 8.2

 

mA TX current @ 6 dBm output power  

• 27

 

μA/MHz in Active Mode (EM0) at 76.8 MHz  

• 2

 

× Universal Synchronous/Asynchronous Receiver/Trans-  

mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I

2

S)  

• 1

 

× Enhanced Universal Asynchronous Receiver/Transmit-  

ter (EUART)  

2 × I

2

C interface with SMBus support  

•

• Digital

 

microphone interface (PDM)  

• 1.40

 

μA EM2 DeepSleep current (32 kB RAM retention and  

RTC running from LFXO)  

• Precision

 

Low-Frequency RC Oscillator to replace 32 kHz  

sleep crystal  

• 1.75

 

μA EM2 DeepSleep current (32 kB RAM retention and  

RTC running from Precision LFRCO)  

• RFSENSE

 

with selective OOK mode  

• Die

 

temperature sensor with +/-1.5 degree C accuracy after  

single-point calibration  

• 0.17

 

μA EM4 current  

•

Supported Modulation Format  

• 2

 

(G)FSK with fully configurable shaping  

• OQPSK

 

DSSS  

•

Wide Operating Range  

• 1.71

 

V to 3.8 V single power supply  

• -40

 

°C to 125 °C  

• (G)MSK  

•

Security Features  

•

Protocol Support  

• Secure

 

Boot with Root of Trust and Secure Loader (RTSL)  

• Bluetooth

 

Low Energy (Bluetooth 5.2)  

• Hardware

 

Cryptographic Acceleration for AES128/256,  

SHA-1, SHA-2 (up to 256-bit), ECC (up to 256-bit), ECDSA,  

and ECDH  

• Direction

 

finding using Angle-of-Arrival (AoA) and Angle-of-  

Departure (AoD)  

• Proprietary  

• True

 

Random Number Generator (TRNG) compliant with  

NIST SP800-90 and AIS-31  

ARM

®

TrustZone

®  

•

• Secure

 

Debug with lock/unlock  

•

Packages  

•

QFN40

5 mm × 5 mm × 0.85 mm  

•

QFN32

4 mm × 4 mm × 0.85 mm  

•

TQFN32

4 mm × 4 mm × 0.30 mm  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Ordering Information  

2. Ordering

 

Information  

Table 2.1.

 

Ordering Information  

Protocol  

Stack  

Max TX  

Power  

Max CPU  

Speed  

Flash RAM  

(kB) (kB)

 

GPIO Package

 

Temp Range  

Ordering Code  

LFRCO  

EFR32BG22C222F352GM32-C •

 

Bluetooth  

5.2  

6 dBm  

6 dBm  

6 dBm  

6 dBm  

76.8 MHz

 

Precision 352  

76.8 MHz

 

Precision 352  

76.8 MHz

 

Precision 352  

76.8 MHz

 

Precision 512  

32  

32  

32  

32  

18 QFN32  

26 QFN40  

18 TQFN32  

18 QFN32  

-40 to 85 °C  

-40 to 85 °C  

-40 to 85 °C  

-40 to 85 °C  

• Proprietary  

EFR32BG22C222F352GM40-C •

 

Bluetooth  

5.2  

• Proprietary  

EFR32BG22C222F352GN32-C •

 

Bluetooth  

5.2  

• Proprietary  

EFR32BG22C224F512GM32-C •

 

Bluetooth  

5.2  

• Direction  

finding  

• Proprietary  

EFR32BG22C224F512GM40-C •

 

Bluetooth  

5.2  

6 dBm  

6 dBm  

6 dBm  

6 dBm  

76.8 MHz

 

Precision 512  

76.8 MHz

 

Precision 512  

76.8 MHz

 

Precision 512  

76.8 MHz

 

Precision 512  

32  

32  

32  

32  

26 QFN40  

18 TQFN32  

18 QFN32  

26 QFN40  

-40 to 85 °C  

-40 to 85 °C  

-40 to 125 °C  

-40 to 125 °C  

• Direction  

finding  

• Proprietary  

EFR32BG22C224F512GN32-C •

 

Bluetooth  

5.2  

• Direction  

finding  

• Proprietary  

EFR32BG22C224F512IM32-C  

EFR32BG22C224F512IM40-C  

• Bluetooth  

5.2  

• Direction  

finding  

• Proprietary  

• Bluetooth  

5.2  

• Direction  

finding  

• Proprietary  

LE Long Range (125 kbps and 500 kbps) PHYs are only supported on part numbers which include AoA/AoD direction-finding capability.  

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Table of Contents  

1. Feature

 

List .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

2  

2. Ordering

 

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

3  

3. System

 

Overview .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

7  

3.1 Introduction .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

7  

3.2 Radio .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

7  

3.2.1 Antenna

 

Interface .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .

 

7  

3.2.2 Fractional-N

 

Frequency Synthesizer

 

. . . . . . . . . . . . . . . . . . . . .

 

8  

3.2.3 Receiver

 

Architecture .

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.2.4 Transmitter

 

Architecture . . . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.2.5 Packet

 

and State Trace

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.2.6 Data

 

Bufferin

g

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.2.7 Radio

 

Controller (RAC).

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

8  

3.2.8 RFSENSE

 

Interface .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .

 

9  

3.3 General

 

Purpose Input/Output (GPIO)

 

. . . . . . . . . . . . . . . . . . . . . .

 

9  

3.4 Clocking .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

9  

3.4.1 Clock

 

Management Unit (CMU) .

 

. . . . . . . . . . . . . . . . . . . . . .

 

9  

3.4.2 Internal

 

and External Oscillators.

 

. . . . . . . . . . . . . . . . . . . . . .

 

9  

3.5 Counters/Timers

 

and PWM .

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

9  

3.5.1 Timer/Counter

 

(TIMER) .

 

. . . . . . . . . . . . . . . . . . . . . . . .

 

9  

3.5.2 Low

 

Energy Timer (LETIMER)

 

. . . . . . . . . . . . . . . . . . . . . . .10  

3.5.3 Real

 

Time Clock with Capture (RTCC)

 

. . . . . . . . . . . . . . . . . . . .10  

3.5.4 Back-Up

 

Real Time Counter .

 

. . . . . . . . . . . . . . . . . . . . . . .10  

3.5.5 Watchdog

 

Timer (WDOG

)

.

 

. . . . . . . . . . . . . . . . . . . . . . .

.

10  

3.6 Communications

 

and Other Digital Peripherals

 

. . . . . . . . . . . . . . . . . . .10  

3.6.1 Universal

 

Synchronous/Asynchronous Receiver/Transmitter (USART) .

 

. . . . . . . . .10  

3.6.2 Enhanced

 

Universal Asynchronous Receiver/Transmitter (EUART) .

 

. . . . . . . . . .10  

2

3.6.3 Inter-Integrated

 

Circuit Interface (I

 

C) .

 

. . . . . . . . . . . . . . . . . . . .10  

3.6.4 Peripheral

 

Reflex System (PRS)

 

. . . . . . . . . . . . . . . . . . . . . .11  

3.6.5 Pulse

 

Density Modulation (PDM) Interface

 

. . . . . . . . . . . . . . . . . . .11  

3.7 Security

 

Features .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .11  

3.7.1 Secure

 

Boot with Root of Trust and Secure Loader (RTSL)

 

. . . . . . . . . . . . .11  

3.7.2 Cryptographic

 

Accelerato

r

. . . . . . . . . . . . . . . . . . . . . . . . .11  

3.7.3 True

 

Random Number Generator

 

. . . . . . . . . . . . . . . . . . . . . .11  

3.7.4 Secure

 

Debug with Lock/Unlock.

 

. . . . . . . . . . . . . . . . . . . . . .12  

3.8 Analo

g

.

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  

3.8.1 Analog

 

to Digital Converter (IADC) .

 

. . . . . . . . . . . . . . . . . . . . .12  

3.9 Power

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  

3.9.1 Energy

 

Management Unit (EMU)

 

. . . . . . . . . . . . . . . . . . . . . .13  

3.9.2 Voltage

 

Scaling .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .13  

3.9.3 DC-DC

 

Converter .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .13  

3.9.4 Power

 

Domains .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .13  

3.10 Reset

 

Management Unit (RMU) .

 

. . . . . . . . . . . . . . . . . . . . . . .14  

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3.11 Core

 

and Memory

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .14  

3.11.1 Processor

 

Core .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .14  

3.11.2 Memory

 

System Controller (MSC)

 

. . . . . . . . . . . . . . . . . . . . .14  

3.11.3 Linked

 

Direct Memory Access Controller (LDMA)

 

. . . . . . . . . . . . . . . .14  

3.12 Memory

 

Map .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .15  

3.13 Configuration

 

Summary . . . . . . . . . . . . . . . . . . . . . . . . . .16  

4. Electrical

 

Specifications .

 

. . . . . . . . . . . . . . . . . . . . . . . . .

 

17  

4.1 Electrical

 

Characteristics .

 

. . . . . . . . . . . . . . . . . . . . . . . . .17  

4.2 Absolute

 

Maximum Ratings.

 

. . . . . . . . . . . . . . . . . . . . . . . . .18  

4.3 General

 

Operating Conditions .

 

. . . . . . . . . . . . . . . . . . . . . . . .19  

4.4 DC-DC

 

Converter .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .21  

4.4.1 DC-DC

 

Operating Limits

 

. . . . . . . . . . . . . . . . . . . . . . . . .23  

4.5 Thermal

 

Characteristics .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .24  

4.6 Current

 

Consumptio

n

. . . . . . . . . . . . . . . . . . . . . . . . . . .

.

25  

4.6.1 MCU

 

current consumption using DC-DC at 3.0 V input

 

. . . . . . . . . . . . . . .25  

4.6.2 MCU

 

current consumption at 3.0 V .

 

. . . . . . . . . . . . . . . . . . . . .27  

4.6.3 MCU

 

current consumption at 1.8 V .

 

. . . . . . . . . . . . . . . . . . . . .29  

4.6.4 Radio

 

current consumption at 3.0V using DCDC

 

. . . . . . . . . . . . . . . . .31  

4.7 Flash

 

Characteristics .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .33  

4.8 Wake

 

Up, Entry, and Exit times

 

. . . . . . . . . . . . . . . . . . . . . . . .34  

4.9 RFSENSE

 

Low-energy Wake-on-RF

 

. . . . . . . . . . . . . . . . . . . . . .35  

4.10 2.4

 

GHz RF Transceiver Characteristics .

 

. . . . . . . . . . . . . . . . . . . .36  

4.10.1 RF

 

Transmitter Characteristic

s

.

 

. . . . . . . . . . . . . . . . . . . . .

.

36  

4.10.2 RF

 

Receiver Characteristics

 

. . . . . . . . . . . . . . . . . . . . . . .43  

4.11 Oscillators .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49  

4.11.1 High

 

Frequency Crystal Oscillator.

 

. . . . . . . . . . . . . . . . . . . . .49  

4.11.2 Low

 

Frequency Crystal Oscillator .

 

. . . . . . . . . . . . . . . . . . . . .50  

4.11.3 High

 

Frequency RC Oscillator (HFRCO)

 

. . . . . . . . . . . . . . . . . . .51  

4.11.4 Fast

 

Start_Up RC Oscillator (FSRCO)

 

. . . . . . . . . . . . . . . . . . . .52  

4.11.5 Precision

 

Low Frequency RC Oscillator (LFRCO)

 

. . . . . . . . . . . . . . . .53  

4.11.6 Ultra

 

Low Frequency RC Oscillator

 

. . . . . . . . . . . . . . . . . . . . .53  

4.12 GPIO

 

Pins (3V GPIO pins)

 

. . . . . . . . . . . . . . . . . . . . . . . . .54  

4.13 Analog

 

to Digital Converter (IADC) .

 

. . . . . . . . . . . . . . . . . . . . . .56  

4.14 Temperature

 

Sense .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .58  

4.15 Brown

 

Out Detectors

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .59  

4.15.1 DVDD

 

BOD .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .59  

4.15.2 LE

 

DVDD BOD

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . .59  

4.15.3 AVDD

 

and IOVDD BODs

 

. . . . . . . . . . . . . . . . . . . . . . . .60  

4.16 PDM

 

Timing Specifications

 

. . . . . . . . . . . . . . . . . . . . . . . . .61  

4.16.1 Pulse

 

Density Modulator (PDM), Common DBUS

 

. . . . . . . . . . . . . . . .61  

4.17 USART

 

SPI Master Timing

 

. . . . . . . . . . . . . . . . . . . . . . . . .62  

4.17.1 SPI

 

Master Timing, Voltage Scaling = VSCALE2.

 

. . . . . . . . . . . . . . . .63  

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4.17.2 SPI

 

Master Timing, Voltage Scaling = VSCALE1.

 

. . . . . . . . . . . . . . . .63  

4.18 USART

 

SPI Slave Timing .

 

. . . . . . . . . . . . . . . . . . . . . . . . .64  

4.18.1 SPI

 

Slave Timing, Voltage Scaling = VSCALE2

 

. . . . . . . . . . . . . . . . .64  

4.18.2 SPI

 

Slave Timing, Voltage Scaling = VSCALE1

 

. . . . . . . . . . . . . . . . .65  

4.19 I2C

 

Electrical Specifications

 

. . . . . . . . . . . . . . . . . . . . . . . . .66  

4.19.1 I2C

 

Standard-mode (Sm)

 

. . . . . . . . . . . . . . . . . . . . . . . .66  

4.19.2 I2C

 

Fast-mode (Fm)

 

. . . . . . . . . . . . . . . . . . . . . . . . . .67  

4.19.3 I2C

 

Fast-mode Plus (Fm+)

 

. . . . . . . . . . . . . . . . . . . . . . . .68  

4.20 Typical

 

Performance Curves .

 

. . . . . . . . . . . . . . . . . . . . . . . .68  

4.20.1 Supply

 

Current .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .69  

4.20.2 RF

 

Characteristics .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .71  

4.20.3 DC-DC

 

Converter .

 

. . . . . . . . . . . . . . . . . . . . . . . . . .72  

4.20.4 IADC

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72  

5. Typical

 

Connections  

. . . . . . . . . . . . . . . . . . . . . . . . . . .73  

5.1 Power

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73  

5.2 RF

 

Matching Networks

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .74  

5.2.1 2.4

 

GHz Matching Network

 

. . . . . . . . . . . . . . . . . . . . . . . .74  

5.3 Other

 

Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . .74  

6. Pin

 

Definitions .

 

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  

6.1 QFN32

 

Device Pinout

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .75  

6.2 QFN40

 

Device Pinout

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .77  

6.3 TQFN32

 

Device Pinout

 

. . . . . . . . . . . . . . . . . . . . . . . . . . .79  

6.4 Alternate

 

Function Table.

 

. . . . . . . . . . . . . . . . . . . . . . . . . .80  

6.5 Analog

 

Peripheral Connectivity

 

. . . . . . . . . . . . . . . . . . . . . . . .81  

6.6 Digital

 

Peripheral Connectivity .

 

. . . . . . . . . . . . . . . . . . . . . . . .82  

7. QFN32

 

Package Specifications.

 

. . . . . . . . . . . . . . . . . . . . . . .

 

85  

7.1 QFN32

 

Package Dimensions

 

. . . . . . . . . . . . . . . . . . . . . . . . .85  

7.2 QFN32

 

PCB Land Pattern

 

. . . . . . . . . . . . . . . . . . . . . . . . . .87  

7.3 QFN32

 

Package Marking

 

. . . . . . . . . . . . . . . . . . . . . . . . . .89  

8. TQFN32

 

Package Specifications

 

. . . . . . . . . . . . . . . . . . . . . . .

 

90  

8.1 TQFN32

 

Package Dimensions.

 

. . . . . . . . . . . . . . . . . . . . . . . .90  

8.2 TQFN32

 

PCB Land Pattern.

 

. . . . . . . . . . . . . . . . . . . . . . . . .92  

8.3 TQFN32

 

Package Marking .

 

. . . . . . . . . . . . . . . . . . . . . . . . .94  

9. QFN40

 

Package Specifications.

 

. . . . . . . . . . . . . . . . . . . . . . .

 

95  

9.1 QFN40

 

Package Dimensions

 

. . . . . . . . . . . . . . . . . . . . . . . . .95  

9.2 QFN40

 

PCB Land Pattern

 

. . . . . . . . . . . . . . . . . . . . . . . . . .97  

9.3 QFN40

 

Package Marking

 

. . . . . . . . . . . . . . . . . . . . . . . . . .98  

10. Revision

 

History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

 

99  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

System Overview  

3. System

 

Overview  

3.1 Introduction  

The EFR32 product family combines an energy-friendly MCU with a high performance radio transceiver. The devices are well suited for  

secure connected IoT multi-protocol devices requiring high performance and low energy consumption. This section gives a short intro-  

duction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG22 Reference Manual.  

A block diagram of the EFR32BG22 family is shown in

Figure 3.1 Detailed EFR32BG22 Block Diagram on page 7

. The diagram  

shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult  

Ordering Information

.  

Radio Subsystem  

Port I/O Configuration  

Digital Peripherals  

IOVDD  

RFSENSE  

ARM Cortex

TM

M0+  

Radio Controller  

DEMOD  

IFADC  

AGC  

w/ OOK Detect  

USART  

EUART  

I2C  

RX/TX Frontend  

with Integrated PA  

BUFC RAM  

FRC  

Port A  

Drivers  

RF2G4_IO  

PAn  

Frequency  

Synthesizer  

MOD  

Port B  

CRC  

PBn  

PCn  

PDn  

Drivers  

LETIMER  

DBUS  

Port  

Mappers  

TIMER  

RTCC  

Core and Memory  

Port C  

Drivers  

Reset Management Unit,  

Brown Out and POR  

RESETn  

ARM Cortex-M33 Core  

with Floating Point Unit  

PDM  

Serial Wire and ETM  

Debug / Programming  

with Debug Challenge I/F  

Port D  

Drivers  

Debug Signals  

(shared w/GPIO)  

Up to 512 KB ISP Flash  

Program Memory  

TRNG  

A

H

B

A

P

B

CRYPTOACC  

CRC  

32 KB RAM  

Trust Zone  

Energy Management  

PAVDD  

RFVDD  

IOVDD  

AVDD  

LDMA Controller  

Analog Peripherals  

Voltage  

Monitor  

Watchdog  

Timer  

Internal  

Reference  

Temperature  

Sensor  

DVDD  

bypass  

VREGVDD  

VREGSW  

DC-DC  

Converter  

Voltage  

Regulator  

Clock Management  

ULFRCO  

VDD  

12-bit ADC  

DECOUPLE  

FSRCO  

LFRCO  

LFXO  

LFXTAL_I  

LFXTAL_O  

HFXTAL_I  

HFXTAL_O  

HFRCO  

HFXO  

Figure 3.1.

 

Detailed EFR32BG22 Block Diagram  

3.2 Radio  

The EFR32BG22 Wireless Gecko features a highly configurable radio transceiver supporting the Bluetooth Low Energy wireless proto-  

col.  

3.2.1 Antenna

 

Interface  

The 2.4 GHz antenna interface consists of a single-ended pin (RF2G4_IO). The external components for the antenna interface in typi-  

cal applications are shown in the RF Matching Networks section.  

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System Overview  

3.2.2 Fractional-N

 

Frequency Synthesizer  

The EFR32BG22 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is  

used in receive mode to generate the LO frequency for the down-conversion mixer. It is also used in transmit mode to directly generate  

the modulated RF carrier.  

The fractional-N architecture provides excellent phase noise performance, frequency resolution better than 100 Hz, and low energy  

consumption. The synthesizer’s fast frequency settling allows for very short receiver and transmitter wake up times to reduce system  

energy consumption.  

3.2.3 Receiver

 

Architecture  

The EFR32BG22 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion  

mixer. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital converter (IFADC).  

The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-  

ing flexibility with respect to known interferers at the image frequency.  

The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-  

tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance.  

Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-  

ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and  

compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by  

block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).  

A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-  

nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received  

frame and the dynamic RSSI measurement can be monitored throughout reception.  

3.2.4 Transmitter

 

Architecture  

The EFR32BG22 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls  

phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping  

filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-  

ing.  

Carrier Sense Multiple Access – Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by  

the EFR32BG22. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-  

tween devices that otherwise lack synchronized RF channel access.  

3.2.5 Packet

 

and State Trace  

The EFR32BG22 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.  

It features:  

• Non-intrusive

 

trace of transmit data, receive data and state information  

• Data

 

observability on a single-pin UART data output, or on a two-pin SPI data output  

• Configurable

 

data output bitrate / baudrate  

• Multiplexed

 

transmitted data, received data and state / meta information in a single serial data stream  

3.2.6 Data

 

Buffering  

The EFR32BG22 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64  

bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.  

3.2.7 Radio

 

Controller (RAC)  

The Radio Controller controls the top level state of the radio subsystem in the EFR32BG22. It performs the following tasks:  

• Precisely-timed

 

control of enabling and disabling of the receiver and transmitter circuitry  

• Run-time

 

calibration of receiver, transmitter and frequency synthesizer  

• Detailed

 

frame transmission timing, including optional LBT or CSMA-CA  

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System Overview  

3.2.8 RFSENSE

 

Interface  

The RFSENSE block allows the device to remain in EM2, EM3 or EM4 and wake when RF energy above a specified threshold is detec-  

ted. When operated in selective mode, the RFSENSE block performs OOK preamble and sync word detection, preventing false wake-  

up events.  

3.3 General

 

Purpose Input/Output (GPIO)  

EFR32BG22 has up to 26 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or  

input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO  

pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to  

several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-  

als. The GPIO subsystem supports asynchronous external pin interrupts.  

All of the pins on ports A and port B are EM2 capable. These pins may be used by Low-Energy peripherals in EM2/3 and may also be  

used as EM2/3 pin wake-ups. Pins on ports C and D are latched/retained in their current state when entering EM2 until EM2 exit upon  

which internal peripherals could once again drive those pads.  

A few GPIOs also have EM4 wake functionality. These pins are listed in the Alternate Function Table.  

3.4 Clocking  

3.4.1 Clock

 

Management Unit (CMU)  

The Clock Management Unit controls oscillators and clocks in the EFR32BG22. Individual enabling and disabling of clocks to all periph-  

eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility  

allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and  

oscillators.  

3.4.2 Internal

 

and External Oscillators  

The EFR32BG22 supports two crystal oscillators and fully integrates four RC oscillators, listed below.  

• A

 

high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-  

ence for the MCU. The HFXO provides excellent RF clocking performance using a 38.4 MHz crystal. The HFXO can also support an  

external clock source such as a TCXO for applications that require an extremely accurate clock frequency over temperature.  

• A

 

32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.  

• An

 

integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The  

HFRCO employs fast start-up at minimal energy consumption combined with a wide frequency range, from 1 MHz to 76.8 MHz.  

• An

 

integrated fast start-up RC oscillator (FSRCO) that runs at a fixed 20 MHz  

• An

 

integrated low frequency 32.768 kHz RC oscillator (LFRCO) for low power operation without an external crystal. Precision mode  

enables periodic recalibration against the 38.4 MHz HFXO crystal to improve accuracy to +/- 500 ppm, suitable for BLE sleep inter-  

val timing.  

• An

 

integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-  

sumption in low energy modes.  

3.5 Counters/Timers

 

and PWM  

3.5.1 Timer/Counter

 

(TIMER)  

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the  

Peripheral Reflex System (PRS). The core of each TIMER is a 16-bit or 32-bit counter with up to 3 compare/capture channels. Each  

channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In  

compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER  

supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the  

compare registers. In addition some timers offer dead-time insertion.  

See

3.13 Configuration Summary

for information on the feature set of each timer.  

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System Overview  

3.5.2 Low

 

Energy Timer (LETIMER)  

The unique LETIMER is a 24-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This  

allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed  

while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-  

forms with minimal software intervention. The LETIMER is connected to the Peripheral Reflex System (PRS), and can be configured to  

start counting on compare matches from other peripherals such as the RTCC.  

3.5.3 Real

 

Time Clock with Capture (RTCC)  

The Real Time Clock with Capture (RTCC) is a 32-bit counter providing timekeeping down to EM3. The RTCC can be clocked by any of  

the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined intervals.  

A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli-  

cation software.  

3.5.4 Back-Up

 

Real Time Counter  

The Back-Up Real Time Counter (BURTC) is a 32-bit counter providing timekeeping in all energy modes, including EM4. The BURTC  

can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined inver-  

vals.  

3.5.5 Watchdog

 

Timer (WDOG)  

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed  

monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can  

also monitor autonomous systems driven by the Peripheral Reflex System (PRS).  

3.6 Communications

 

and Other Digital Peripherals  

3.6.1 Universal

 

Synchronous/Asynchronous Receiver/Transmitter (USART)  

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous  

UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-  

porting:  

• ISO7816

 

SmartCards  

• IrDA  

I

2

S  

•

3.6.2 Enhanced

 

Universal Asynchronous Receiver/Transmitter (EUART)  

The Enhanced Universal Asynchronous Receiver/Transmitter supports full duplex asynchronous UART communication with hardware  

flow control, RS-485 and IrDA support. In EM0 and EM1 the EUART provides a high-speed, buffered communication interface.  

When routed to GPIO ports A or B, the EUART may also be used in a low-energy mode and operate in EM2. A 32.768 kHz clock  

source allows full duplex UART communication up to 9600 baud.  

3.6.3 Inter-Integrated

 

Circuit Interface (I

2

C)  

The I

2

C module provides an interface between the MCU and a serial I

2

C bus. It is capable of acting as both a master and a slave and  

supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10  

kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The  

interface provided to software by the I

2

C module allows precise timing control of the transmission process and highly automated trans-  

fers. Automatic recognition of slave addresses is provided in active and low energy modes. Note that not all instances of I

2

C are avalia-  

ble in all energy modes.  

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System Overview  

3.6.4 Peripheral

 

Reflex System (PRS)  

The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.  

Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-  

erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)  

can be applied by the PRS to the signals. The PRS allows peripherals to act autonomously without waking the MCU core, saving  

power.  

3.6.5 Pulse

 

Density Modulation (PDM) Interface  

The PDM module provides a serial interface and decimation filter for Pulse Density Modulation (PDM) microphones, isolated Sigma-  

delta ADCs, digital sensors and other PDM or sigma delta bit stream peripherals. A programmable Cascaded Integrator Comb (CIC)  

filter is used to decimate the incoming bit streams. PDM supports stereo or mono input data and DMA transfer.  

3.7 Security

 

Features  

The following security features are available on the EFR32BG22:  

• Secure

 

Boot with Root of Trust and Secure Loader (RTSL)  

• Cryptographic

 

Accelerator  

• True

 

Random Number Generator (TRNG)  

• Secure

 

Debug with Lock/Unlock  

3.7.1 Secure

 

Boot with Root of Trust and Secure Loader (RTSL)  

The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM).  

It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed and protects Over The Air updates.  

More information on this feature can be found in the Application Note

AN1218: Series 2 Secure Boot with RTSL

.  

3.7.2 Cryptographic

 

Accelerator  

The Cryptographic Accelerator is an autonomous hardware accelerator which supports AES encryption and decryption with  

128/192/256-bit keys, Elliptic Curve Cryptography (ECC) to support public key operations and hashes.  

Supported block cipher modes of operation for AES include:  

• ECB

 

(Electronic Code Book)  

• CTR

 

(Counter Mode)  

• CBC

 

(Cipher Block Chaining)  

• CFB

 

(Cipher Feedback)  

• GCM

 

(Galois Counter Mode)  

• CBC-MAC

 

(Cipher Block Chaining Message Authentication Code)  

• GMAC

 

(Galois Message Authentication Code)  

• CCM

 

(Counter with CBC-MAC)  

The Cryptographic Accelerator accelerates Elliptical Curve Cryptography and supports the NIST (National Institute of Standards and  

Technology) recommended curves including P-192 and P-256 for ECDH(Elliptic Curve Diffie-Hellman) key derivation and ECDSA (El-  

liptic Curve Digital Signature Algorithm) sign and verify operations.  

Supported hashes include SHA-1, SHA2/224, and SHA-2/256.  

This implementation provides a fast and energy efficient solution to state of the art cryptographic needs.  

3.7.3 True

 

Random Number Generator  

The True Random Number Generator module is a non-deterministic random number generator that harvests entropy from a thermal  

energy source. It includes start-up health tests for the entropy source as required by NIST SP800-90B and AIS-31 as well as online  

health tests required for NIST SP800-90C.  

The TRNG is suitable for periodically generating entropy to seed an approved pseudo random number generator.  

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System Overview  

3.7.4 Secure

 

Debug with Lock/Unlock  

For obvious security reasons, it is critical for a product to have its debug interface locked before being released in the field.  

In addition, the EFR32BG22 also provides a secure debug unlock function that allows authenticated access based on public key cryp-  

tography. This functionality is particularly useful for supporting failure analysis while maintaining confidentiality of IP and sensitive end-  

user data.  

More information on this feature can be found in the Application Note

AN1190: EFR32xG2x Secure Debug

.  

3.8 Analog  

3.8.1 Analog

 

to Digital Converter (IADC)  

The IADC is a hybrid architecture combining techniques from both SAR and Delta-Sigma style converters. It has a resolution of 12 bits  

at 1 Msps and 16 bits at up to 76.9 ksps. Hardware oversampling reduces system-level noise over multiple front-end samples. The  

IADC includes integrated voltage reference options. Inputs are selectable from a wide range of sources, including pins configurable as  

either single-ended or differential.  

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System Overview  

3.9 Power  

The EFR32BG22 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only  

a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator  

can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-  

tor.  

The EFR32BG22 device family includes support for internal supply voltage scaling, as well as two different power domains groups for  

peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.  

3.9.1 Energy

 

Management Unit (EMU)  

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and  

features are available and the amount of current the device consumes. The EMU can also be used to implement system-wide voltage  

scaling and turn off the power to unused RAM blocks to optimize the energy consumption in the target application. The DC-DC regula-  

tor operation is tightly integrated with the EMU.  

3.9.2 Voltage

 

Scaling  

The EFR32BG22 supports supply voltage scaling for the LDO powering DECOUPLE, with independent selections for EM0 / EM1 and  

EM2 / EM3. Voltage scaling helps to optimize the energy efficiency of the system by operating at lower voltages when possible. The  

default EM0 / EM1 voltage scaling level is VSCALE2, which allows the core to operate in active mode at full speed. The intermediate  

level, VSCALE1, allows operation in EM0 and EM1 at up to 40 MHz. The lowest level, VSCALE0, can be used to conserve power in  

EM2 and EM3. The EMU will automatically switch the target voltage scaling level when transitioning between energy modes.  

3.9.3 DC-DC

 

Converter  

The DC-DC buck converter covers a wide range of load currents, provides high efficiency in energy modes EM0, EM1, EM2 and EM3,  

and can supply up to 60 mA for device and radio operation. RF noise mitigation allows operation of the DC-DC converter without signifi-  

cantly degrading sensitivity of radio components. An on-chip supply-monitor signals when the supply voltage is low to allow bypass of  

the regulator via programmable software interrupt. It employs soft switching at boot and DCDC regulating-to-bypass transitions to limit  

the max supply slew-rate and mitigate inrush current.  

3.9.4 Power

 

Domains  

The EFR32BG22 has three peripheral power domains for operation in EM2 and EM3, as well as the ability to selectively retain configu-  

rations for EM0/EM1 peripherals. A small set of peripherals always remain powered on in EM2 and EM3, including all peripherals which  

are available in EM4. If all of the peripherals in PD0B or PD0C are configured as unused, that power domain will be powered off in EM2  

or EM3, reducing the overall current consumption of the device. Likewise, if the application can tolerate the setup time to re-configure  

used EM0/EM1 peripherals on wake, register retention for these peripherals can be disabled to further reduce the EM2 or EM3 current.  

Table 3.1.

 

Peripheral Power Subdomains  

Always available in EM2/EM3  

Power Domain PD0B  

LETIMER0  

Power Domain PD0C  

RTCC  

LFRCO (Precision Mode)  

LFRCO (Non-precision mode)

1  

IADC0  

LFXO

1  

I2C0  

BURTC

1  

RFSENSE

1  

WDOG0  

EUART0  

PRS  

ULFRCO

1  

FSRCO  

DEBUG  

Note:  

1. Peripheral also available in EM4.  

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3.10 Reset

 

Management Unit (RMU)  

The RMU is responsible for handling reset of the EFR32BG22. A wide range of reset sources are available, including several power  

supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.  

3.11 Core

 

and Memory  

3.11.1 Processor

 

Core  

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:  

• ARM

 

Cortex-M33 RISC processor achieving 1.50 Dhrystone MIPS/MHz  

• ARM

 

TrustZone security technology  

• Embedded

 

Trace Macrocell (ETM) for real-time trace and debug  

• Up

 

to 512 kB flash program memory  

• Up

 

to 32 kB RAM data memory  

• Configuration

 

and event handling of all modules  

• 2-pin

 

Serial-Wire debug interface  

3.11.2 Memory

 

System Controller (MSC)  

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable  

from both the Cortex-M and DMA. In addition to the main flash array where Program code is normally written the MSC also provides an  

Information block where additional information such as special user information or flash-lock bits are stored. There is also a read-only  

page in the information block containing system and device calibration data. Read and write operations are supported in energy modes  

EM0 Active and EM1 Sleep.  

3.11.3 Linked

 

Direct Memory Access Controller (LDMA)  

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This  

reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-  

phisticated operations to be implemented.  

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3.12 Memory

 

Map  

The EFR32BG22 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.  

Figure 3.2.

 

EFR32BG22 Memory Map — Core Peripherals and Code Space  

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3.13 Configuration

 

Summary  

The features of the EFR32BG22 are a subset of the feature set described in the device reference manual. The table below describes  

device specific implementation of the features. Remaining modules support full configuration.  

Table 3.2.

 

Configuration Summary  

Module  

Lowest Energy Mode  

Configuration  

EM2

1  

EM1  

EM2  

I2C0  

I2C1  

IADC0  

EM2

1  

LETIMER0  

PDM  

EM1  

2-channel  

TIMER0  

TIMER1  

TIMER2  

TIMER3  

TIMER4  

EUART0  

EM1  

32-bit, 3-channels, +DTI  

16-bit, 3-channels, +DTI  

16-bit, 3-channels, +DTI  

16-bit, 3-channels, +DTI  

16-bit, 3-channels, +DTI  

EM1  

EM1  

EM1  

EM1  

EM1 – Full high-speed operation  

EM2

1

– Low-energy operation, 9600 Baud  

USART0  

USART1  

Note:  

EM1  

EM1  

+IrDA, +I2S, +SmartCard  

+IrDA, +I2S, +SmartCard  

1. EM2 and EM3 operation is only supported for digital peripheral I/O on Port A and Port B. All GPIO ports support digital peripheral  

operation in EM0 and EM1.  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4. Electrical

 

Specifications  

4.1 Electrical

 

Characteristics  

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:  

• Typical

 

values are based on T

A

=25 °C and all supplies at 3.0 V, by production test and/or technology characterization.  

• Radio

 

performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-  

er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.  

• Minimum

 

and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,  

unless stated otherwise.  

Power Supply Pin Dependencies  

Due to on-chip circuitry (e.g., diodes), some EFR32 power supply pins have a dependent relationship with one or more other power  

supply pins. These internal relationships between the external voltages applied to the various EFR32 supply pins are defined below.  

Exceeding the below constraints can result in damage to the device and/or increased current draw.  

• VREGVDD

 

& DVDD  

• In

 

systems using the DCDC converter, DVDD (the buck converter output) should be connected to the recommended L

DCDC

and  

C

DCDC

, and should not be driven by an off-chip regulator.  

• In

 

systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD=DVDD)  

• DVDD

 

≥ DECOUPLE  

• PAVDD

 

≥ RFVDD  

• AVDD,

 

IOVDD: No dependency with each other or any other supply pin  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.2 Absolute

 

Maximum Ratings  

Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of  

the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure  

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-  

bility data, see the Quality and Reliability Monitor Report at

.  

Table 4.1.

 

Absolute Maximum Ratings  

Parameter  

Symbol  

T

STG  

Test Condition  

Min  

-50  

Typ  

—

Max  

+150  

3.8  

Unit  

°C  

Storage temperature range  

Voltage on any supply pin

1  

Junction temperature  

V

DDMAX  

-0.3  

—

V

T

JMAX  

-G grade  

-I grade  

—

—

—

—

—

—

+105  

+125  

1.0  

°C  

°C  

Voltage ramp rate on any  

supply pin  

V

DDRAMPMAX  

V / µs  

Voltage on HFXO pins  

V

HFXOPIN  

-0.3  

-0.3  

—

—

1.4  

V

V

DC voltage on any GPIO pin

 

V

DIGPIN  

V

IOVDD  

0.3  

+

DC voltage on RESETn pin

2  

V

RESETn  

-0.3  

—

—

—

3.8  

V

Input RF level on RF pins  

RF2G4_IO  

P

RFMAX2G4  

+10  

dBm  

Absolute voltage on RF pin  

RF2G4_IO  

V

MAX2G4  

-0.3  

—

—

—

—

V

PAVDD  

0.3  

+

V

Total current into VDD power

 

I

VDDMAX  

lines  

Source  

Sink  

200  

mA  

mA  

Total current into VSS  

ground lines  

I

VSSMAX  

—

200  

Current per I/O pin  

Current for all I/O pins  

Note:  

I

IOMAX  

Sink  

—

—

—

—

—

—

—

—

50  

50  

mA  

mA  

mA  

mA  

Source  

Sink  

I

IOALLMAX  

200  

200  

Source  

1. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifica-  

tions for more details.  

2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at  

DVDD.  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.3 General

 

Operating Conditions  

Table 4.2.

 

General Operating Conditions  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

-G temperature grade

1  

Operating ambient tempera-

 

T

A  

ture range  

-40  

—

+85  

°C  

-I temperature grade

1  

EM0/1  

-40  

—

+125  

° C  

DVDD supply voltage  

V

DVDD  

1.71  

1.71  

3.0  

3.0  

3.8  

3.8  

V

V

EM2/3/4

2  

AVDD supply voltage  

V

AVDD  

1.71  

1.71  

3.0  

3.0  

3.8  

3.8  

V

V

IOVDDx operating supply  

voltage (All IOVDD pins)  

V

IOVDDx  

PAVDD operating supply  

voltage  

V

PAVDD  

1.71  

2.2  

3.0  

3.0  

3.8  

3.8  

V

V

DC-DC in regulation

3  

VREGVDD operating supply

 

V

VREGVDD  

voltage  

DC-DC in bypass 60 mA load  

1.8  

3.0  

3.0  

3.8  

3.8  

V

V

DC-DC not in use. DVDD exter-  

nally shorted to VREGVDD  

1.71  

RFVDD operating supply  

voltage  

V

RFVDD  

1.71  

1.0  

3.0  

—

V

PAVDD  

V

DECOUPLE output capaci-  

tor

4  

C

DECOUPLE  

1.0 µF ± 10% X8L capacitor used  

for performance characterization.  

2.75  

µF  

HCLK and SYSCLK frequen-

 

f

HCLK  

cy  

VSCALE2, MODE = WS1  

VSCALE2, MODE = WS0  

VSCALE1, MODE = WS0  

VSCALE2  

—

—

—

—

—

—

—

—

—

—

—

—

76.8  

40  

MHz  

MHz  

MHz  

MHz  

MHz  

MHz  

MHz  

MHz  

MHz  

MHz  

—

40  

PCLK frequency  

f

PCLK  

—

50  

VSCALE1  

—

40  

EM01 Group A clock fre-  

quency  

f

EM01GRPACLK  

f

EM01GRPBCLK  

f

RHCLK  

VSCALE2  

—

76.8  

40  

VSCALE1  

—

EM01 Group B clock fre-  

quency  

VSCALE2  

—

76.8  

40  

VSCALE1  

—

Radio HCLK frequency

5  

VSCALE2 or VSCALE1  

38.4  

—

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Note:  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

1. The device may operate continuously at the maximum allowable ambient T

A

rating as long as the absolute maximum T

JMAX

is not  

exceeded. For an application with significant power dissipation, the allowable T

A

may be lower than the maximum T

A

rating. T

A

=  

T

JMAX

– (THETA

JA

x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for  

T

JMAX

and THETA

JA  

.

2. The DVDD supply is monitored by the DVDD BOD in EM0/1 and the LE DVDD BOD in EM2/3/4.  

3. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifica-  

tions for more details.  

4. Murata GCM21BL81C105KA58L used for performance characterization. Actual capacitor values can be significantly de-rated  

from their specified nominal value by the rated tolerance, as well as the application’s AC voltage, DC bias, and temperature. The  

minimum capacitance counting all error sources should be no less than 0.6 µF.  

5. The recommended radio crystal frequency is 38.4 MHz. Any crystal frequency other than 38.4 MHz is expressly not supported.  

See HFXO specifications for more detail on crystal tolerance.  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.4 DC-DC

 

Converter  

Test conditions: L

DCDC

= 2.2 µH (Samsung CIG22H2R2MNE), C

DCDC

= 4.7 µF (Samsung CL10B475KQ8NQNC), V

VREGVDD

= 3.0 V,  

V

OUT

= 1.8 V, IPKVAL in EM0/1 modes is set to 150 mA, and in EM2/3 modes is set to 90 mA, unless otherwise indicated.  

Table 4.3.

 

DC-DC Converter  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Input voltage range at  

VREGVDD pin

1  

V

VREGVDD  

DCDC in regulation, I

LOAD

= 60  

mA, EM0/EM1 mode  

2.2  

3.0  

3.8*  

V

DCDC in regulation, I

LOAD

= 5  

1.8  

3.0  

3.8*  

V

mA, EM0/EM1 or EM2/EM3 mode  

Bypass mode  

1.8  

—

3.0  

1.8  

—

3.8  

—

V

V

Regulated output voltage  

Regulation DC accuracy  

V

OUT  

ACC

DC  

V

VREGVDD

≥ 2.2 V, Steady state in  

EM0/EM1 mode or EM2/EM3  

mode  

-2.5  

3.3  

%

Regulation total accuracy  

ACC

TOT  

With mode transitions between  

EM0/EM1 and EM2/EM3 modes  

-5  

—

7

%

Steady-state output ripple  

DC line regulation  

V

R  

I

LOAD

= 20 mA in EM0/EM1 mode  

—

—

14.3  

5.5  

—

—

mVpp  

mV/V  

V

REG  

I

LOAD

= 60 mA in EM0/EM1  

mode, V

VREGVDD

≥ 2.2 V  

DC load regulation  

Efficiency  

I

REG  

EFF  

Load current between 100 µA and  

60 mA in EM0/EM1 mode  

—

—

0.27  

91  

—

—

mV/mA  

%

Load current between 100 µA and  

60 mA in EM0/EM1 mode, or be-  

tween 10 µA and 5 mA in  

EM2/EM3 mode  

Output load current  

I

LOAD  

EM0/EM1 mode, DCDC in regula-  

tion  

—

—

—

—

60  

5

mA  

mA  

EM2/EM3 mode, DCDC in regula-  

tion  

Bypass mode  

—

—

—

60  

10  

mA  

µF  

Nominal output capacitor  

C

DCDC  

4.7 µF ± 10% X7R capacitor used  

for performance characterization

2  

4.7  

Nominal inductor  

L

DCDC  

C

IN  

± 20% tolerance  

—

C

DCDC  

—

2.2  

—

—

—

3

µH  

µF  

Ω

Nominal input capacitor  

Resistance in bypass mode

 

R

BYP  

Bypass switch from VREGVDD to  

DVDD, V

VREGVDD

= 1.8 V  

1.75  

Powertrain PFET switch from  

VREGVDD to VREGSW,  

V

VREGVDD

= 1.8 V  

—

0.86  

1.5  

Ω

Supply monitor threshold  

programming range  

V

CMP_RNG  

Programmable in 0.1 V steps  

Supply falling edge trip point  

2.0  

-5  

—

—

2.3  

5

V

Supply monitor threshold ac-

 

V

CMP_ACC  

curacy  

%

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Supply monitor threshold  

hysteresis  

V

CMP_HYST  

Positive hysteresis on the supply  

rising edge referred to the falling  

edge trip point  

—

4

—

%

Supply monitor response  

time  

t

CMP_DELAY  

Supply falling edge at -100 mV /  

µs  

—

0.6  

—

µs  

Note:  

1. The supported maximum V

VREGVDD

in regulation mode is a function of temperature and 10-year lifetime average load current.  

See more details in

4.4.1 DC-DC Operating Limits

.  

2. Samsung CL10B475KQ8NQNC used for performance characterization. Actual capacitor values can be significantly de-rated from  

their specified nominal value by the rated tolerance, as well as the application’s AC voltage, DC bias, and temperature. The mini-  

mum capacitance counting all error sources should be no less than 2.4 µF.  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.4.1 DC-DC

 

Operating Limits  

The maximum supported voltage on the VREGVDD supply pin is limited under certain conditions. Maximum input voltage is a function  

of temperature and the average load current over a 10-year lifetime.

Figure 4.1 Lifetime average load current limit vs. Maximum input  

voltage on page 23

shows the safe operating region under specific conditions. Exceeding this safe operating range may impact the  

reliability and performance of the DC-DC converter.  

The average load current for an application can typically be determined by examining the current profile during the time the device is  

powered. For example, an application that is continuously powered which spends 99% of the time asleep consuming 2 µA and 1% of  

the time active and consuming 10 mA has an average lifetime load current of about 102 µA.  

Tj

≤

125 °C  

60  

5

3.3  

Maximum V

VREGVDD

(V)  

3.8  

Figure 4.1.

 

Lifetime average load current limit vs. Maximum input voltage  

The minimum input voltage for the DC-DC in EM0/EM1 mode is a function of the maximum load current, and the peak current setting.  

Figure 4.2 Transient maximum load current vs. Minimum input voltage on page 23

shows the max load current vs. input voltage for  

different DC-DC peak inductor current settings.  

60  

36  

I

PEAK

= 150 mA  

I

PEAK

= 90 mA  

5

1.8  

2.2  

Minimum V

VREGVDD

(V)  

Figure 4.2.

 

Transient maximum load current vs. Minimum input voltage  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.5 Thermal

 

Characteristics  

Table 4.4.

 

Thermal Characteristics  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

4-Layer PCB, Natural Convection

1  

Thermal Resistance Junction

 

THE-  

to Ambient QFN32 (4x4mm)

 

TA

JA_QFN32_4X4  

Package  

—

35.4  

—

°C/W  

4-Layer PCB, Natural Convection

1  

4-Layer PCB, Natural Convection

1  

Thermal Resistance Junction

 

THE-  

—

—

40.2  

32.6  

—

—

°C/W  

°C/W  

to Ambient TQFN32  

(4x4mm) Package  

TA

JA_TQFN32_4X  

4

Thermal Resistance, Junc-  

tion to Ambient, QFN40  

(5x5mm) Package  

THE-  

TA

JA_QFN40_5X5  

Note:  

1. Measured according to JEDEC standard JESD51-2A. Integrated Circuit Thermal Test Method Environmental Conditions – Natural  

Convection (Still Air).  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.6 Current

 

Consumption  

4.6.1 MCU

 

current consumption using DC-DC at 3.0 V input  

Unless otherwise indicated, typical conditions are: VREGVDD = 3.0 V. AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V from DC-  

DC. Voltage scaling level = VSCALE1. T

A

= 25 °C. Minimum and maximum values in this table represent the worst conditions across  

process variation at T

A

= 25 °C.  

Table 4.5.

 

MCU current consumption using DC-DC at 3.0 V input  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

mode with all peripherals dis-  

abled  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal, CPU  

running Prime from flash,  

VSCALE2  

—

28  

—

µA/MHz  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal, CPU  

running while loop from flash,  

VSCALE2  

—

—

27  

37  

—

—

µA/MHz  

µA/MHz  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal, CPU  

running CoreMark loop from flash,  

VSCALE2  

38.4 MHz crystal, CPU running  

Prime from flash  

—

—

—

—

—

—

—

—

28  

26  

38  

22  

24  

27  

159  

17  

—

—

—

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

38.4 MHz crystal, CPU running  

while loop from flash  

38.4 MHz crystal, CPU running  

CoreMark loop from flash  

38 MHz HFRCO, CPU running  

while loop from flash  

26 MHz HFRCO, CPU running  

while loop from flash  

16 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

Current consumption in EM1

 

I

EM1  

mode with all peripherals dis-  

abled  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal,  

VSCALE2  

38.4 MHz crystal  

38 MHz HFRCO  

26 MHz HFRCO  

16 MHz HFRCO  

1 MHz HFRCO  

—

—

—

—

—

17  

13  

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

15  

18  

150  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM2

 

I

EM2_VS  

mode, VSCALE0  

Full RAM retention and RTC run-  

ning from LFXO  

—

1.40  

—

µA  

Full RAM retention and RTC run-  

ning from LFRCO  

—

—

1.40  

1.75  

—

—

µA  

µA  

Full RAM retention and RTC run-  

ning from LFRCO in precision  

mode  

24 kB RAM retention and RTC  

running from LFXO  

—

—

1.32  

1.66  

—

—

µA  

µA  

24 kB RAM retention and RTC  

running from LFRCO in precision  

mode  

8 kB RAM retention and RTC run-  

ning from LFXO  

—

—

—

1.21  

1.20  

1.03  

—

—

—

µA  

µA  

µA  

8 kB RAM retention and RTC run-  

ning from LFRCO  

8 kB RAM retention and RTC run-  

ning from LFXO, Radio RAM and  

CPU cache not retained  

Current consumption in EM3

 

I

EM3_VS  

mode, VSCALE0  

8 kB RAM retention and RTC run-  

ning from ULFRCO  

—

—

1.05  

0.37  

—

—

µA  

µA  

Additional current in EM2 or

 

I

PD0B_VS  

EM3 when any peripheral in  

PD0B is enabled

1  

Note:  

1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the  

peripherals in each power domain.  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.6.2 MCU

 

current consumption at 3.0 V  

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = VREGVDD = 3.0 V. DC-DC not used. Voltage  

scaling level = VSCALE1. T

A

= 25 °C. Minimum and maximum values in this table represent the worst conditions across process varia-  

tion at T

A

= 25 °C.  

Table 4.6.

 

MCU current consumption at 3.0 V  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

mode with all peripherals dis-  

abled  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal, CPU  

running Prime from flash,  

VSCALE2  

—

42  

—

µA/MHz  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal, CPU  

running while loop from flash,  

VSCALE2  

—

—

39  

54  

—

—

µA/MHz  

µA/MHz  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal, CPU  

running CoreMark loop from flash,  

VSCALE2  

38.4 MHz crystal, CPU running  

Prime from flash  

—

—

—

—

—

—

—

—

40  

39  

55  

33  

35  

40  

228  

24  

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

38.4 MHz crystal, CPU running  

while loop from flash  

38.4 MHz crystal, CPU running  

CoreMark loop from flash  

—

38 MHz HFRCO, CPU running  

while loop from flash  

50  

—

26 MHz HFRCO, CPU running  

while loop from flash  

16 MHz HFRCO, CPU running  

while loop from flash  

—

1 MHz HFRCO, CPU running  

while loop from flash  

830  

—

Current consumption in EM1

 

I

EM1  

mode with all peripherals dis-  

abled  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal,  

VSCALE2  

38.4 MHz crystal  

38 MHz HFRCO  

26 MHz HFRCO  

16 MHz HFRCO  

1 MHz HFRCO  

—

—

—

—

—

25  

19  

—

35  

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

21  

27  

—

215  

770  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM2

 

I

EM2_VS  

mode, VSCALE0  

Full RAM retention and RTC run-  

ning from LFXO  

—

1.94  

—

µA  

Full RAM retention and RTC run-  

ning from LFRCO  

—

—

—

1.95  

1.81  

2.34  

4.9  

—

µA  

µA  

µA  

24 kB RAM retention and RTC  

running from LFXO  

24 kB RAM retention and RTC  

running from LFRCO in precision  

mode  

—

8 kB RAM retention and RTC run-  

ning from LFXO  

—

—

—

1.64  

1.65  

1.39  

—

—

—

µA  

µA  

µA  

8 kB RAM retention and RTC run-  

ning from LFRCO  

8 kB RAM retention and RTC run-  

ning from LFXO, Radio RAM and  

CPU cache not retained  

Current consumption in EM3

 

I

EM3_VS  

mode, VSCALE0  

8 kB RAM retention and RTC run-  

ning from ULFRCO  

—

1.41  

3.7  

µA  

Current consumption in EM4

 

I

EM4  

mode  

No BURTC, no LF oscillator  

BURTC with LFXO  

—

—

—

0.17  

0.50  

234  

0.43  

—

µA  

µA  

µA  

Current consumption during

 

I

RST  

reset  

Hard pin reset held  

—

Additional current in EM2 or

 

I

PD0B_VS  

EM3 when any peripheral in  

PD0B is enabled

1  

—

0.56  

—

µA  

Note:  

1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the  

peripherals in each power domain.  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.6.3 MCU

 

current consumption at 1.8 V  

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = VREGVDD = 1.8 V. DC-DC not used. Voltage  

scaling level = VSCALE1. T

A

= 25 °C. Minimum and maximum values in this table represent the worst conditions across process varia-  

tion at T

A

= 25 °C.  

Table 4.7.

 

MCU current consumption at 1.8 V  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

mode with all peripherals dis-  

abled  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal, CPU  

running Prime from flash,  

VSCALE2  

—

42  

—

µA/MHz  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal, CPU  

running while loop from flash,  

VSCALE2  

—

—

39  

54  

—

—

µA/MHz  

µA/MHz  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal, CPU  

running CoreMark loop from flash,  

VSCALE2  

38.4 MHz crystal, CPU running  

Prime from flash  

—

—

—

—

—

—

—

—

41  

39  

55  

33  

35  

40  

227  

24  

—

—

—

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

38.4 MHz crystal, CPU running  

while loop from flash  

38.4 MHz crystal, CPU running  

CoreMark loop from flash  

38 MHz HFRCO, CPU running  

while loop from flash  

26 MHz HFRCO, CPU running  

while loop from flash  

16 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

Current consumption in EM1

 

I

EM1  

mode with all peripherals dis-  

abled  

76.8 MHz HFRCO w/ DPLL refer-  

enced to 38.4 MHz crystal,  

VSCALE2  

38.4 MHz crystal  

38 MHz HFRCO  

26 MHz HFRCO  

16 MHz HFRCO  

1 MHz HFRCO  

—

—

—

—

—

25  

19  

—

—

—

—

—

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

µA/MHz  

21  

27  

213  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM2

 

I

EM2_VS  

mode, VSCALE0  

Full RAM retention and RTC run-  

ning from LFXO  

—

1.87  

—

µA  

Full RAM retention and RTC run-  

ning from LFRCO  

—

—

—

1.86  

1.73  

2.26  

—

—

—

µA  

µA  

µA  

24 kB RAM retention and RTC  

running from LFXO  

24 kB RAM retention and RTC  

running from LFRCO in precision  

mode  

8 kB RAM retention and RTC run-  

ning from LFXO  

—

—

—

1.57  

1.56  

1.32  

—

—

—

µA  

µA  

µA  

8 kB RAM retention and RTC run-  

ning from LFRCO  

8 kB RAM retention and RTC run-  

ning from LFXO, Radio RAM and  

CPU cache not retained  

Current consumption in EM3

 

I

EM3_VS  

mode, VSCALE0  

8 kB RAM retention and RTC run-  

ning from ULFRCO  

—

1.34  

—

µA  

Current consumption in EM4

 

I

EM4  

mode  

No BURTC, no LF oscillator  

BURTC with LFXO  

—

—

—

0.13  

0.44  

190  

—

—

—

µA  

µA  

µA  

Current consumption during

 

I

RST  

reset  

Hard pin reset held  

Additional current in EM2 or

 

I

PD0B_VS  

EM3 when any peripheral in  

PD0B is enabled

1  

—

0.54  

—

µA  

Note:  

1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the  

peripherals in each power domain.  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.6.4 Radio

 

current consumption at 3.0V using DCDC  

RF current consumption measured with MCU in EM1, HCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indica-  

ted, typical conditions are: VREGVDD = 3.0V. AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V powered from DCDC. T

A

= 25 °C.  

Minimum and maximum values in this table represent the worst conditions across process variation at T

A

= 25 °C.  

Table 4.8.

 

Radio current consumption at 3.0V using DCDC  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

System current consumption

 

I

RX_ACTIVE  

in receive mode, active pack-  

et reception  

125 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1, EM1P (Radio clocks  

only)  

—

3.7  

—

mA  

125 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1  

—

—

—

4.0  

4.1  

3.8  

—

—

—

mA  

mA  

mA  

125 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE2  

500 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1, EM1P (Radio clocks  

only)  

500 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1  

—

—

—

4.0  

4.2  

3.6  

—

—

—

mA  

mA  

mA  

500 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE2  

1 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1, EM1P (Radio clocks  

only)  

1 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1  

—

—

—

3.8  

3.9  

4.0  

—

—

—

mA  

mA  

mA  

1 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE2  

2 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1, EM1P (Radio clocks  

only)  

2 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1  

—

—

4.2  

4.4  

—

—

mA  

mA  

2 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE2  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

System current consumption

 

I

RX_LISTEN  

in receive mode, listening for  

packet  

125 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1, EM1P (Radio clocks  

only)  

—

3.8  

—

mA  

125 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1  

—

—

—

4.0  

4.1  

3.8  

—

—

—

mA  

mA  

mA  

125 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE2  

500 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1, EM1P (Radio clocks  

only)  

500 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1  

—

—

—

4.0  

4.1  

3.6  

—

—

—

mA  

mA  

mA  

500 kbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE2  

1 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1, EM1P (Radio clocks  

only)  

1 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1  

—

—

—

3.8  

4.0  

4.1  

—

—

—

mA  

mA  

mA  

1 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE2  

2 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1, EM1P (Radio clocks  

only)  

2 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE1  

—

—

—

4.3  

4.5  

4.1  

—

—

—

mA  

mA  

mA  

2 Mbit/s, 2GFSK, f = 2.4 GHz,  

VSCALE2  

System current consumption

 

I

TX  

in transmit mode  

f = 2.4 GHz, CW, 0 dBm PA, 0  

dBm output power, VSCALE1,  

EM1P (Radio clocks only)  

f = 2.4 GHz, CW, 6 dBm PA, 6  

dBm output power, VSCALE1,  

EM1P (Radio clocks only)  

—

8.2  

—

mA  

f = 2.4 GHz, CW, 0 dBm PA, 0  

dBm output power, VSCALE1  

—

—

—

—

4.3  

8.4  

4.4  

8.5  

—

—

—

—

mA  

mA  

mA  

mA  

f = 2.4 GHz, CW, 6 dBm PA, 6  

dBm output power, VSCALE1  

f = 2.4 GHz, CW, 0 dBm PA, 0  

dBm output power, VSCALE2  

f = 2.4 GHz, CW, 6 dBm PA, 6  

dBm output power, VSCALE2  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.7 Flash

 

Characteristics  

Table 4.9.

 

Flash Characteristics  

Test Condition  

Parameter  

Symbol  

Min  

Typ  

Max  

Unit  

Flash Supply voltage during

 

V

FLASH  

write or erase  

1.71  

—

3.8  

V

Flash erase cycles before  

failure

1  

EC

FLASH  

T

A

≤ 125 °C  

T

A

≤ 125 °C  

10,000  

—

—

cycles  

Flash data retention

1  

Program Time  

RET

FLASH  

t

PROG  

10  

—

—

years  

one word (32-bits)  

42.1  

10.3  

11.4  

11.7  

—

44  

10.9  

12.9  

13  

45.6  

11.3  

14.4  

14.3  

1.45  

1.34  

1.28  

uSec  

uSec  

ms  

average per word over 128 words  

Page Erase Time  

Mass Erase Time  

Program Current  

Page Erase Current  

Mass Erase Current  

Note:  

t

PERASE  

t

MERASE  

I

PROG  

Erases all of User Code area  

ms  

—

mA  

I

PERASE  

I

MERASE  

Page Erase  

Mass Erase  

—

—

mA  

—

—

mA  

1. Flash data retention information is published in the Quarterly Quality and Reliability Report.  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.8 Wake

 

Up, Entry, and Exit times  

Unless otherwise specified, these times are measured using the HFRCO at 19 MHz.  

Table 4.10.

 

Wake Up, Entry, and Exit times  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

WakeupTime from EM1  

t

EM1_WU  

Code execution from flash  

—

3

—

AHB  

Clocks  

Code execution from RAM  

—

—

1.42  

—

—

µs  

µs  

WakeupTime from EM2  

t

EM2_WU  

Code execution from flash, No  

Voltage Scaling  

13.22  

Code execution from RAM, No  

Voltage Scaling  

—

5.15  

—

µs  

Voltage scaling up one level

1  

Voltage scaling up two levels

2  

—

—

—

37.89  

50.56  

13.21  

—

—

—

µs  

µs  

µs  

WakupTime from EM3  

t

EM3_WU  

Code execution from flash, No  

Voltage Scaling  

Code execution from RAM, No  

Voltage Scaling  

—

5.15  

—

µs  

Voltage scaling up one level

1  

—

—

37.90  

50.55  

—

—

µs  

µs  

Voltage scaling up two levels

2  

Code execution from flash  

Code execution from flash  

Code execution from flash  

Code execution from flash  

Code execution from flash  

Up from VSCALE1 to VSCALE2  

WakeupTime from EM4  

Entry time to EM1  

Entry time to EM2  

Entry time to EM3  

Entry time to EM4  

t

EM4_WU  

t

EM1_ENT  

t

EM2_ENT  

t

EM3_ENT  

t

EM4_ENT  

t

SCALE  

—

—

—

—

—

—

—

8.81  

1.29  

5.23  

5.23  

9.96  

32  

—

—

—

—

—

—

—

ms  

µs  

µs  

µs  

µs  

µs  

µs  

Voltage scaling in time in  

EM0

3  

Down from VSCALE2 to  

VSCALE1  

172  

Note:  

1. Voltage scaling one level is between VSCALE0 and VSCALE1 or between VSCALE1 and VSCALE2.  

2. Voltage scaling two levels is between VSCALE0 and VSCALE2.  

3. During voltage scaling in EM0, RAM is inaccessible and processor will be halted until complete.  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.9 RFSENSE

 

Low-energy Wake-on-RF  

Table 4.11.

 

RFSENSE Low-energy Wake-on-RF  

Parameter  

Symbol  

Test Condition  

Min  

—

Typ  

138  

131  

Max  

—

Unit  

nA  

Average current  

I

RFSENSE  

RF energy below wake threshold  

Selective mode, RF energy above  

threshold but no OOK sync detec-  

ted  

—

—

nA  

RF level above which  

THRES

TRIG  

Threshold set to -34 dBm  

Threshold set to -22 dBm  

Threshold set to -34 dBm  

Threshold set to -22 dBm  

-28  

-19  

—

—

—

—

—

—

—

dBm  

dBm  

dBm  

dBm  

RFSENSE will detect signal

1  

RF level below which  

RFSENSE will not detect sig-  

nal

1  

THRES

NOTRIG  

-40  

-26  

—

Sensitivity in selective OOK

 

SENS

OOK  

mode

1  

Sensitivity for > 90% probability of  

OOK detection

2

, threshold set to  

-34 dBm  

-28  

—

—

dBm  

Sensitivity for > 90% probability of  

-19  

—

—

dBm  

OOK detection

2

, threshold set to  

-22 dBm  

Note:  

1. Values collected with conducted measurements performed at the end of the matching network.  

2. Selective wake signal is 1 kHz OOK Manchester-coded, 8 bits of preamble, 32-bit sync word.  

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

4.10 2.4

 

GHz RF Transceiver Characteristics  

4.10.1 RF

 

Transmitter Characteristics  

4.10.1.1 RF

 

Transmitter General Characteristics for the 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T

A

= 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8  

V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.  

Table 4.12.

 

RF Transmitter General Characteristics for the 2.4 GHz Band  

Parameter  

Symbol  

Test Condition  

Min  

2400  

—

Typ  

—

Max  

2483.5  

—

Unit  

MHz  

mA  

RF tuning frequency range  

F

RANGE  

Radio-only current consump-

 

I

TX_RADIO  

tion while transmitting

1  

f = 2.4 GHz, CW, 0 dBm PA, 0  

dBm output power  

3.4  

f = 2.4 GHz, CW, 6 dBm PA, 6  

dBm output power  

—

—

7.5  

6

—

—

mA  

Maximum TX power

2  

6 dBm PA

3  

0 dBm PA  

6 dBm PA  

0 dBm PA  

POUT

MAX  

dBm  

—

—

—

—

0

—

—

—

—

dBm  

dBm  

dBm  

dB  

Minimum active TX power  

POUT

MIN  

-27  

-28  

0.04  

Output power variation vs  

supply voltage variation, fre-  

quency = 2450 MHz  

POUT

VAR_V  

6 dBm PA output power, using  

DCDC with VREGVDD swept  

from 1.8 to 3.0 V  

0 dBm PA output power, using  

DCDC with VREGVDD swept  

from 1.8 to 3.0 V  

—

0.03  

—

dB  

Output power variation vs  

temperature, Frequency =  

2450 MHz  

POUT

VAR_T  

6 dBm PA at 6 dBm, (-40 to +125  

°C)  

—

—

—

—

0.18  

1.4  

—

—

—

—

dB  

dB  

dB  

dB  

0 dBm PA at 0 dBm, (-40 to +125  

°C)  

6 dBm PA at 6 dBm, (-40 to +85  

°C)  

0.17  

1.0  

0 dBm PA at 0 dBm, (-40 to +85  

°C)  

Output power variation vs RF

 

POUT

VAR_F  

frequency  

6 dBm PA, 6 dBm  

0 dBm PA, 0 dBm  

—

—

—

0.20  

0.19  

-47  

—

—

—

dB  

dB  

Spurious emissions of har-  

monics in restricted bands  

per FCC Part 15.205/15.209  

SPUR

HRM_FCC_

Continuous transmission of CW  

dBm  

carrier, P

out

= POUT

MAX

, Test  

Frequency = 2450 MHz.  

R

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EFR32BG22 Wireless Gecko SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Spurious emissions out-of-  

band (above 2.483 GHz or  

below 2.4 GHz) in restricted  

bands, per FCC part  

SPUR

OOB_FCC_

Restricted bands 30-88 MHz,  

—

-47  

—

dBm  

Continuous transmission of CW  

R

carrier, P

out

= POUT

MAX

, Test  

Frequency = 2450 MHz  

15.205/15.209  

Restricted bands 88 – 216 MHz,  

Continuous transmission of CW  

carrier, P

out

= POUT

MAX

, Test  

Frequency = 2450 MHz  

—

—

—

—

-47  

-47  

-47  

-26  

—

—

—

—

dBm  

dBm  

dBm  

dBc  

Restricted bands 216 – 960 MHz,  

Continuous transmission of CW  

carrier, P

out

= POUT

MAX

, Test  

Frequency = 2450 MHz  

Restricted bands > 960 MHz,  

Continuous transmission of CW  

carrier, P

out

= POUT

MAX

, Test  

Frequency = 2450 MHz  

Spurious emissions out-of-  

band in non-restricted bands  

per FCC Part 15.247  

SPUR

OOB_FCC_

Frequencies above 2.483 GHz or  

below 2.4 GHz, continuous trans-  

NR  

mission CW carrier, P

out  

=

POUT

MAX

, Test Frequency =  

2450 MHz  

Spurious emissions per ETSI

 

SPUR

ETSI440  

EN300.440  

47-74 MHz,87.5-108 MHz,  

174-230 MHz, 470-862 MHz, P

out  

= POUT