SKYWORKS-SILICON-LABS-EFR32FG12P231F1024GM68-C

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EFR32FG12 Gecko Proprietary Protocol

SoC Family Data Sheet

The Gecko proprietary protocol family of SoCs is part of the Wire-

less Gecko portfolio. Gecko SoCs are ideal for enabling energy-

KEY FEATURES

friendly proprietary protocol networking for IoT devices.

• 32-bit

ARM® Cortex®-M4 core with 40

MHz maximum operating frequency

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup

times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-

tures.

• Up

to 1 MB of flash and 256 kB of RAM

• Pin-compatible

across EFR32FG families

(exceptions apply for 5V-tolerant pins)

• 12-channel

Peripheral Reflex System,

Low-Energy Sensor Interface & Multi-

channel Capacitive Sense Interface

Gecko applications include:

• Home

and Building Automation and Security

• Metering

• Autonomous

Hardware Crypto Accelerator

and True Random Number Generator

• Electronic

Shelf Labels

• Integrated

PA with up to 19 dBm (2.4

GHz) or 20 dBm (Sub-GHz) TX power

• Industrial

Automation

• Commercial

and Retail Lighting and Sensing

• Integrated

balun for 2.4 GHz

• Robust

peripheral set and up to 65 GPIO

Core / Memory

Clock Management

Energy Management

Other

CRYPTO

CRC

High Frequency

Crystal

Oscillator

High Frequency

RC Oscillator

Voltage

Voltage Monitor

Power-On Reset

Regulator

ARM Cortex

M4 processor

Memory

with DSP extensions and FPU

Protection Unit

Auxiliary High

Frequency RC

Oscillator

Low Frequency

RC Oscillator

DC-DC

Converter

True Random

Number Generator

Low Frequency

Crystal

Oscillator

Ultra Low

Frequency RC

Oscillator

Flash Program

RAM Memory

Memory

Debug Interface

with ETM

LDMA

Controller

Brown-Out

Detector

SMU

32-bit bus

Peripheral Reflex System

Radio Transceiver

Serial

I/O Ports

Timers and Triggers

Analog I/F

Interfaces

RFSENSE

Sub GHz

LNA

DEMOD

ADC

External

Interrupts

USART

Timer/Counter

Protocol Timer

RF Frontend

Analog

Comparator

IFADC

AGC

PGA

Low Energy

UART

General

Purpose I/O

Low Energy

Timer

Watchdog Timer

IDAC

To Sub GHz

receive I/Q

mixers and PA

Real Time

Counter and

Calendar

RFSENSE

BALUN

Capacitive Sense

Pin Reset

Pulse Counter

2.4 GHz

LNA

Frequency

Synthesizer

MOD

VDAC

RF Frontend

Low Energy

Sensor Interface

Pin Wakeup

Cryotimer

Op-Amp

To 2.4 GHz receive

I/Q mixers and PA

To Sub GHz

and 2.4 GHz PA

Lowest power mode with peripheral operational:

EM0—Active EM1—Sleep

EM2—Deep Sleep

EM3—Stop

EM4—Hibernate

EM4—Shutoff

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Feature List

1. Feature

List

The EFR32FG12 highlighted features are listed below.

•

Low Power Wireless System-on-Chip

•

Wide selection of MCU peripherals

High Performance 32-bit 40 MHz ARM Cortex

-M4 with

DSP instruction and floating-point unit for efficient signal

processing

•

• 12-bit

1 Msps SAR Analog to Digital Converter (ADC)

• 2

× Analog Comparator (ACMP)

• 2

× Digital to Analog Converter (VDAC)

• 3

× Operational Amplifier (Opamp)

• Embedded

Trace Macrocell (ETM) for advanced debugging

• Up

to 1024 kB flash program memory

• Up

to 256 kB RAM data memory

• Digital

to Analog Current Converter (IDAC)

• Low-Energy

Sensor Interface (LESENSE)

• Multi-channel

Capacitive Sense Interface (CSEN)

• 2.4

GHz and Sub-GHz radio operation

• Transmit

power:

• Up

to 54 pins connected to analog channels (APORT)

shared between analog peripherals

• 2.4

GHz radio: Up to 19 dBm

• Sub-GHz

radio: Up to 20 dBm

• Up

to 65 General Purpose I/O pins with output state reten-

tion and asynchronous interrupts

•

Low Energy Consumption

• 8

Channel DMA Controller

• 8.4

mA RX current at 38.4 kbps, GFSK, 169 MHz

• 10.0

mA RX current at 1 Mbps, GFSK, 2.4 GHz

• 11

mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz

• 8.5

mA TX current at 0 dBm output power at 2.4 GHz

• 35.3

mA TX current at 14 dBm output power at 868 MHz

• 70

μA/MHz in Active Mode (EM0)

• 12

Channel Peripheral Reflex System (PRS)

• 2

× 16-bit Timer/Counter

• 3

or 4 Compare/Capture/PWM channels

• 2

× 32-bit Timer/Counter

• 3

or 4 Compare/Capture/PWM channels

• 32-bit

Real Time Counter and Calendar

• 16-bit

Low Energy Timer for waveform generation

• 1.5

μA EM2 DeepSleep current (16 kB RAM retention and

RTCC running from LFRCO)

•

High Receiver Performance

• 32-bit

Ultra Low Energy Timer/Counter for periodic wake-up

from any Energy Mode

• -94.8

dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz

• -102.7

dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz

• -126.2

dBm sensitivity at 600 bps, GFSK, 915 MHz

• -120.6

dBm sensitivity at 2.4 kbps, GFSK, 868 MHz

• -107.4

dBm sensitivity at 4.8 kbps, OOK, 433 MHz

• -112.2

dBm sensitivity at 38.4 kbps, GFSK, 169 MHz

•

Supported Modulation Formats

• 2/4

(G)FSK with fully configurable shaping

• BPSK

/ DBPSK TX

• 3

× 16-bit Pulse Counter with asynchronous operation

• 2

× Watchdog Timer with dedicated RC oscillator

• 4

× Universal Synchronous/Asynchronous Receiver/Trans-

mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I

Low Energy UART (LEUART

™

)

2 × I

C interface with SMBus support and address recogni-

tion in EM3 Stop

•

Wide Operating Range

• 1.8

V to 3.8 V single power supply

• OOK

/ ASK

• Integrated

DC-DC, down to 1.8 V output with up to 200 mA

load current for system

• Shaped

OQPSK / (G)MSK

• Configurable

DSSS and FEC

• Standard

(-40 °C to 85 °C) and Extended (-40 °C to 125 °C)

temperature grades available

•

Supported Protocols

• Proprietary

Protocols

•

Support for Internet Security

• General

Purpose CRC

• Wireless

M-Bus

• Selected

IEEE 802.15.4g SUN-FSK PHYs

• Low

Power Wide Area Networks

• True

Random Number Generator

• 2

× Hardware Cryptographic Acceleration for AES 128/256,

SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC

•

Suitable for Systems Targeting Compliance With:

• FCC

Part 90.210 Mask D, FCC part 15.247, 15.231, 15.249

• ETSI

Category I Operation, EN 300 220, EN 300 328

• ARIB

T-108, T-96

•

QFN48 7×7 mm Package

•

QFN68 8×8 mm Package

•

BGA125 7×7 mm Package

• China

regulatory

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Ordering Information

2. Ordering

Information

Table 2.1.

Ordering Information

Frequency Band

@ Max TX Power

Protocol

Stack

Flash RAM

Ordering Code

(kB)

GPIO Package Temp

Range

EFR32FG12P433F1024GL125-C Proprietary

EFR32FG12P433F1024GM68-C Proprietary

EFR32FG12P433F1024GM48-C Proprietary

2.4 GHz @ 19 dBm

Sub-GHz @ 20 dBm

2.4 GHz @ 19 dBm

Sub-GHz @ 20 dBm

2.4 GHz @ 19 dBm

Sub-GHz @ 20 dBm

2.4 GHz @ 19 dBm

Sub-GHz @ 20 dBm

2.4 GHz @ 19 dBm

Sub-GHz @ 20 dBm

1024

256

BGA125

QFN68

QFN48

-40 to +85°C

1024

256

EFR32FG12P432F1024GL125-C Proprietary

EFR32FG12P432F1024GM48-C Proprietary

EFR32FG12P431F1024GL125-C Proprietary

EFR32FG12P431F1024GM68-C Proprietary

1024

512

256

128

256

128

BGA125

QFN48

BGA125

QFN68

QFN48

BGA125

QFN48

BGA125

QFN68

QFN48

-40 to +85°C

-40 to +125°C

-40 to +85°C

EFR32FG12P431F512GM68-C

EFR32FG12P431F1024GM48-C Proprietary

EFR32FG12P431F1024IM48-C Proprietary

Proprietary

1024

512

EFR32FG12P232F1024GL125-C Proprietary

EFR32FG12P232F1024GM48-C Proprietary

EFR32FG12P231F1024GL125-C Proprietary

EFR32FG12P231F1024GM68-C Proprietary

EFR32FG12P231F512GM68-C

Proprietary

EFR32FG12P231F1024GM48-C Proprietary

1024

128

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Ordering Information

EFR32 X G 1 2 P 132 F

1024 G

L 125

–

A R

Tape and Reel (Optional)

Revision

Pin Count

Package – M (QFN), L (BGA)

Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)

Flash Memory Size in kB

Memory Type (Flash)

Feature Set Code – r2r1r0

r2: Reserved

r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)

r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)

Performance Grade – P (Performance), B (Basic), V (Value)

Device Configuration

Series

Gecko

Family – M, B, F

Wireless Gecko 32-bit

Figure 2.1.

Ordering Code Key

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Table of Contents

1. Feature

List .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2. Ordering

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3. System

Overview .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Introduction .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Radio .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Antenna

Interface .

. . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Fractional-N

Frequency Synthesizer

. . . . . . . . . . . . . . . . . . . . .

3.2.3 Receiver

Architecture .

. . . . . . . . . . . . . . . . . . . . . . . . .

3.2.4 Transmitter

Architecture . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.5 Wake

on Radio

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.6 RFSENSE .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.2.7 Flexible

Frame Handling

. . . . . . . . . . . . . . . . . . . . . . . . .10

3.2.8 Packet

and State Trace

. . . . . . . . . . . . . . . . . . . . . . . . .10

3.2.9 Data

Bufferin

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.2.10 Radio

Controller (RAC)

. . . . . . . . . . . . . . . . . . . . . . . . .10

3.2.11 Random

Number Generator

. . . . . . . . . . . . . . . . . . . . . . .11

3.3 Power

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.3.1 Energy

Management Unit (EMU)

. . . . . . . . . . . . . . . . . . . . . .12

3.3.2 DC-DC

Converter .

. . . . . . . . . . . . . . . . . . . . . . . . . .12

3.3.3 Power

Domains .

. . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.4 General

Purpose Input/Output (GPIO)

. . . . . . . . . . . . . . . . . . . . . .13

3.5 Clocking .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.5.1 Clock

Management Unit (CMU) .

. . . . . . . . . . . . . . . . . . . . . .13

3.5.2 Internal

and External Oscillators.

. . . . . . . . . . . . . . . . . . . . . .13

3.6 Counters/Timers

and PWM .

. . . . . . . . . . . . . . . . . . . . . . . . .13

3.6.1 Timer/Counter

(TIMER) .

. . . . . . . . . . . . . . . . . . . . . . . .13

3.6.2 Wide

Timer/Counter (WTIMER) .

. . . . . . . . . . . . . . . . . . . . . .13

3.6.3 Real

Time Counter and Calendar (RTCC)

. . . . . . . . . . . . . . . . . . .13

3.6.4 Low

Energy Timer (LETIMER)

. . . . . . . . . . . . . . . . . . . . . . .14

3.6.5 Ultra

Low Power Wake-up Timer (CRYOTIMER)

. . . . . . . . . . . . . . . . .14

3.6.6 Pulse

Counter (PCNT) .

. . . . . . . . . . . . . . . . . . . . . . . . .14

3.6.7 Watchdog

Timer (WDOG

)

. . . . . . . . . . . . . . . . . . . . . . .

3.7 Communications

and Other Digital Peripherals

. . . . . . . . . . . . . . . . . . .14

3.7.1 Universal

Synchronous/Asynchronous Receiver/Transmitter (USART) .

. . . . . . . . .14

3.7.2 Low

Energy Universal Asynchronous Receiver/Transmitter (LEUART) .

. . . . . . . . .14

3.7.3 Inter-Integrated

Circuit Interface (I

C) .

. . . . . . . . . . . . . . . . . . . .14

3.7.4 Peripheral

Reflex System (PRS)

. . . . . . . . . . . . . . . . . . . . . .14

3.7.5 Low

Energy Sensor Interface (LESENSE)

. . . . . . . . . . . . . . . . . . .15

3.8 Security

Features .

. . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.8.1 General

Purpose Cyclic Redundancy Check (GPCRC)

. . . . . . . . . . . . . . .15

3.8.2 Crypto

Accelerator (CRYPTO)

. . . . . . . . . . . . . . . . . . . . . . .15

3.8.3 True

Random Number Generator (TRNG)

. . . . . . . . . . . . . . . . . . .15

3.8.4 Security

Management Unit (SMU)

. . . . . . . . . . . . . . . . . . . . . .15

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3.9 Analo

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.9.1 Analog

Port (APORT)

. . . . . . . . . . . . . . . . . . . . . . . . . .15

3.9.2 Analog

Comparator (ACMP) .

. . . . . . . . . . . . . . . . . . . . . . .15

3.9.3 Analog

to Digital Converter (ADC)

. . . . . . . . . . . . . . . . . . . . . .16

3.9.4 Capacitive

Sense (CSEN

)

. . . . . . . . . . . . . . . . . . . . . . .

3.9.5 Digital

to Analog Current Converter (IDAC)

. . . . . . . . . . . . . . . . . . .16

3.9.6 Digital

to Analog Converter (VDAC)

. . . . . . . . . . . . . . . . . . . . .16

3.9.7 Operational

Amplifiers .

. . . . . . . . . . . . . . . . . . . . . . . . .16

3.10 Reset

Management Unit (RMU) .

. . . . . . . . . . . . . . . . . . . . . . .16

3.11 Core

and Memory

. . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.11.1 Processor

Core .

. . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.11.2 Memory

System Controller (MSC)

. . . . . . . . . . . . . . . . . . . . .17

3.11.3 Linked

Direct Memory Access Controller (LDMA)

. . . . . . . . . . . . . . . .17

3.12 Memory

Map .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.13 Configuration

Summary . . . . . . . . . . . . . . . . . . . . . . . . . .20

4. Electrical

Specifications .

. . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Electrical

Characteristics .

. . . . . . . . . . . . . . . . . . . . . . . . .21

4.1.1 Absolute

Maximum Ratings

. . . . . . . . . . . . . . . . . . . . . . . .22

4.1.2 Operating

Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.1.3 Thermal

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .26

4.1.4 DC-DC

Converter .

. . . . . . . . . . . . . . . . . . . . . . . . . .27

4.1.5 Current

Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.1.6 Wake

Up Times

. . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.1.7 Brown

Out Detector (BOD)

. . . . . . . . . . . . . . . . . . . . . . . .40

4.1.8 Frequency

Synthesize

. . . . . . . . . . . . . . . . . . . . . . . . .

4.1.9 2.4

GHz RF Transceiver Characteristics .

. . . . . . . . . . . . . . . . . . .42

4.1.10 Sub-GHz

RF Transceiver Characteristics

. . . . . . . . . . . . . . . . . . .53

4.1.11 Modem.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.1.12 Oscillators

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.1.13 Flash

Memory Characteristics

. . . . . . . . . . . . . . . . . . . . . . .82

4.1.14 General-Purpose

I/O (GPIO)

. . . . . . . . . . . . . . . . . . . . . . .83

4.1.15 Voltage

Monitor (VMON

)

. . . . . . . . . . . . . . . . . . . . . . .

4.1.16 Analog

to Digital Converter (ADC)

. . . . . . . . . . . . . . . . . . . . .86

4.1.17 Analog

Comparator (ACMP)

. . . . . . . . . . . . . . . . . . . . . . .88

4.1.18 Digital

to Analog Converter (VDAC)

. . . . . . . . . . . . . . . . . . . . .91

4.1.19 Current

Digital to Analog Converter (IDAC)

. . . . . . . . . . . . . . . . . .94

4.1.20 Capacitive

Sense (CSEN)

. . . . . . . . . . . . . . . . . . . . . . . .96

4.1.21 Operational

Amplifier (OPAMP)

. . . . . . . . . . . . . . . . . . . . . .98

4.1.22 Pulse

Counter (PCNT)

. . . . . . . . . . . . . . . . . . . . . . .

4.1.23 Analog

Port (APORT) .

. . . . . . . . . . . . . . . . . . . . . . . .

101

4.1.24 I2C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

102

4.1.25 USART

SPI .

. . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Typical

Performance Curves

. . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Supply

Current

4.2.2 DC-DC

Converter

4.2.3 2.4

GHz Radio

. . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . .

.14

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5. Typical

Connection Diagrams

. . . . . . . . . . . . . . . . . . . . . . . .116

5.1 Power

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

116

5.2 RF

Matching Networks

. . . . . . . . . . . . . . . . . . . . . . . . . .118

5.3 Other

Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . .

119

6. Pin

Definitions .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

120

6.1 BGA125

2.4 GHz and Sub-GHz Device Pinout

. . . . . . . . . . . . . . . . . .120

6.2 BGA125

2.4 GHz Device Pinout

. . . . . . . . . . . . . . . . . . . . . .

6.3 BGA125

Sub-GHz Device Pinout .

. . . . . . . . . . . . . . . . . . . . . .

127

6.4 QFN68

2.4 GHz and Sub-GHz Device Pinout.

. . . . . . . . . . . . . . . . . .

130

6.5 QFN68

Sub-GHz Device Pinout

. . . . . . . . . . . . . . . . . . . . . . .133

6.6 QFN48

2.4 GHz and Sub-GHz Device Pinout.

. . . . . . . . . . . . . . . . . .

135

6.7 QFN48

2.4 GHz Device Pinout

6.8 QFN48

Sub-GHz Device Pinout

. . . . . . . . . . . . . . . . . . . . . . .139

6.9 GPIO

Functionality Table

. . . . . . . . . . . . . . . . . . . . . . . .

6.10 Alternate

Functionality Overview

. . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

6.11 Analog

Port (APORT) Client Maps

. . . . . . . . . . . . . . . . . . . . . .

199

7. BGA125

Package Specifications

. . . . . . . . . . . . . . . . . . . . . . .208

7.1 BGA125

Package Dimension

. . . . . . . . . . . . . . . . . . . . . . .

7.2 BGA125

PCB Land Pattern .

. . . . . . . . . . . . . . . . . . . . . . . .

210

7.3 BGA125

Package Marking

. . . . . . . . . . . . . . . . . . . . . . . . .

212

8. QFN48

Package Specifications.

. . . . . . . . . . . . . . . . . . . . . . .

213

8.1 QFN48

Package Dimensions

. . . . . . . . . . . . . . . . . . . . . . .

8.2 QFN48

PCB Land Pattern

. . . . . . . . . . . . . . . . . . . . . . . . .215

8.3 QFN48

Package Marking

. . . . . . . . . . . . . . . . . . . . . . . .

217

9. QFN68

Package Specifications.

. . . . . . . . . . . . . . . . . . . . . . .

218

9.1 QFN68

Package Dimensions

. . . . . . . . . . . . . . . . . . . . . . .

9.2 QFN68

PCB Land Pattern

. . . . . . . . . . . . . . . . . . . . . . . . .220

9.3 QFN68

Package Marking

. . . . . . . . . . . . . . . . . . . . . . . .

222

10. Revision

History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

223

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

System Overview

3. System

Overview

3.1 Introduction

The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for

any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a

short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG12 Wireless

Gecko Reference Manual.

A block diagram of the EFR32FG12 family is shown in

Figure 3.1 Detailed EFR32FG12 Block Diagram on page 8

. The diagram

shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult

Ordering Information

Radio Transceiver

Port I/O Configuration

Digital Peripherals

IOVDD

Sub-GHz RF

SUBGRF_IP

SUBGRF_IN

SUBGRF_OP

SUBGRF_ON

DEMOD

IFADC

AGC

LNA

LETIMER

Port A

Drivers

PGA

PAn

TIMER

CRYOTIMER

PCNT

RFSENSE

BALUN

2.4 GHz RF

Frequency

LNA

Synthesizer

Port B

Drivers

PBn

PCn

PDn

PFn

2G4RF_IOP

2G4RF_ION

To RF

MOD

Frontend

Circuits

RTC / RTCC

USART

Port

Mapper

Port C

Drivers

LEUART

I2C

Reset

Management

Unit

ARM Cortex-M4 Core

RESETn

Port D

Serial Wire

and ETM

Debug /

Up to 1024 KB ISP Flash

Program Memory

CRYPTO

CRC

Drivers

Debug Signals

(shared w/GPIO)

Brown Out /

Power-On

Reset

Up to 256 KB RAM

Memory Protection Unit

Floating Point Unit

LDMA Controller

Programming

Port F

Drivers

LESENSE

Energy Management

Analog Peripherals

Port I

Drivers

PAVDD

RFVDD

IOVDD

AVDD

IDAC

Voltage

Monitor

Port J

Drivers

–

Watchdog

Timer

PJn

VDAC

DVDD

bypass

Op-Amp

VDD

Internal

Reference

Port K

Drivers

Clock Management

PKn

VREGVDD

VREGSW

DC-DC

Converter

Voltage

Regulator

ULFRCO

AUXHFRCO

LFRCO

12-bit ADC

DECOUPLE

Temp

Sense

LFXTAL_P

LFXTAL_N

HFXTAL_P

HFXTAL_N

LFXO

HFRCO

HFXO

Capacitive

Sense

–

Analog Comparator

Figure 3.1.

Detailed EFR32FG12 Block Diagram

3.2 Radio

The Gecko family features a radio transceiver supporting proprietary wireless protocols.

3.2.1 Antenna

Interface

The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The

2G4RF_ION pin should be grounded externally.

The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching

Networks section.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

System Overview

3.2.2 Fractional-N

Frequency Synthesizer

The EFR32FG12 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is

used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly

generate the modulated RF carrier.

The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with

low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to

optimize system energy consumption.

3.2.3 Receiver

Architecture

The EFR32FG12 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion

mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital

converter (IFADC).

The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-

ing flexibility with respect to known interferers at the image frequency.

The Automatic Gain Control (AGC) block adjusts the receiver gain to optimize performance and avoid saturation for excellent selectivity

and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz radio

can be calibrated on-demand by the user for the desired frequency band.

Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-

ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and

compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by

block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS) for 2.4 GHz and sub-GHz bands.

A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-

nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received

frame and the dynamic RSSI measurement can be monitored throughout reception.

The EFR32FG12 features integrated support for antenna diversity to mitigate the problem of frequency-selective fading due to multipath

propagation and improve link budget. Support for antenna diversity is available for specific PHY configurations in 2.4 GHz and sub-GHz

bands. Internal configurable hardware controls an external switch for automatic switching between antennae during RF receive detec-

tion operations.

Note:

Due to the shorter preamble of 802.15.4 and BLE packets, RX diversity is not supported.

3.2.4 Transmitter

Architecture

The EFR32FG12 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls

phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping

filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-

ing.

Carrier Sense Multiple Access – Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by

the EFR32FG12. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-

tween devices that otherwise lack synchronized RF channel access.

3.2.5 Wake

on Radio

The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-

ing a subsystem of the EFR32FG12 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-

als.

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System Overview

3.2.6 RFSENSE

The RFSENSE peripheral generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, provid-

ing true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.

RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-

sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by

enabling normal RF reception.

Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using

available timer peripherals.

3.2.7 Flexible

Frame Handling

EFR32FG12 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.

The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-

tor:

• Highly

adjustable preamble length

• Up

to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts

• Frame

disassembly and address matching (filtering) to accept or reject frames

• Automatic

ACK frame assembly and transmission

• Fully

flexible CRC generation and verification:

• Multiple

CRC values can be embedded in a single frame

• 8,

16, 24 or 32-bit CRC value

• Configurable

CRC bit and byte ordering

• Selectable

bit-ordering (least significant or most significant bit first)

• Optional

data whitening

• Optional

Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding

• Half

rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing

• Optional

symbol interleaving, typically used in combination with FEC

• Symbol

coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware

• UART

encoding over air, with start and stop bit insertion / removal

• Test

mode support, such as modulated or unmodulated carrier output

• Received

frame timestamping

3.2.8 Packet

and State Trace

The EFR32FG12 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.

It features:

• Non-intrusive

trace of transmit data, receive data and state information

• Data

observability on a single-pin UART data output, or on a two-pin SPI data output

• Configurable

data output bitrate / baudrate

• Multiplexed

transmitted data, received data and state / meta information in a single serial data stream

3.2.9 Data

Buffering

The EFR32FG12 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64

bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.

3.2.10 Radio

Controller (RAC)

The Radio Controller controls the top level state of the radio subsystem in the EFR32FG12. It performs the following tasks:

• Precisely-timed

control of enabling and disabling of the receiver and transmitter circuitry

• Run-time

calibration of receiver, transmitter and frequency synthesizer

• Detailed

frame transmission timing, including optional LBT or CSMA-CA

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System Overview

3.2.11 Random

Number Generator

The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.

The data is suitable for use in cryptographic applications.

Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-

ber generator algorithms such as Fortuna.

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System Overview

3.3 Power

The EFR32FG12 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only

a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator

can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-

tor.

The EFR32FG12 device family includes support for internal supply voltage scaling, as well as two different power domains groups for

peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.

AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will

operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.

Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB

components, supplying up to a total of 200 mA.

3.3.1 Energy

Management Unit (EMU)

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and

features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM

blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi-

ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has

fallen below a chosen threshold.

3.3.2 DC-DC

Converter

The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2

and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation

of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,

short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low

for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance

switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-

sients.

3.3.3 Power

Domains

The EFR32FG12 has two peripheral power domains for operation in EM2 and lower. If all of the peripherals in a peripheral power do-

main are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall cur-

rent consumption of the device.

Table 3.1.

Peripheral Power Subdomains

Peripheral Power Domain 1

Peripheral Power Domain 2

ACMP0

ACMP1

PCNT1

PCNT2

CSEN

DAC0

PCNT0

ADC0

LETIMER0

LESENSE

APORT

LEUART0

I2C0

–

I2C1

IDAC

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System Overview

3.4 General

Purpose Input/Output (GPIO)

EFR32FG12 has up to 65 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or in-

put. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO

pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to

several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-

als. The GPIO subsystem supports asynchronous external pin interrupts.

3.5 Clocking

3.5.1 Clock

Management Unit (CMU)

The Clock Management Unit controls oscillators and clocks in the EFR32FG12. Individual enabling and disabling of clocks to all periph-

erals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows

software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscilla-

tors.

3.5.2 Internal

and External Oscillators

The EFR32FG12 supports two crystal oscillators and fully integrates four RC oscillators, listed below.

• A

high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-

ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can

also be applied to the HFXO input for improved accuracy over temperature.

• A

32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.

• An

integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The

HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.

• An

integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial

Wire Viewer port with a wide frequency range.

• An

integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-

tal accuracy is not required.

• An

integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-

sumption in low energy modes.

3.6 Counters/Timers

and PWM

3.6.1 Timer/Counter

(TIMER)

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the

PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one

of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output

reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width

modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional

dead-time insertion available in timer unit TIMER_0 only.

3.6.2 Wide

Timer/Counter (WTIMER)

WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM

outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to

4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a

buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh-

old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by

the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.

3.6.3 Real

Time Counter and Calendar (RTCC)

The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a

Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-

tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving

frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy

and convenient data storage in all energy modes down to EM4H.

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3.6.4 Low

Energy Timer (LETIMER)

The unique LETIMER is a 16-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This

allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed

while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-

forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-

figured to start counting on compare matches from the RTCC.

3.6.5 Ultra

Low Power Wake-up Timer (CRYOTIMER)

The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal

oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events

and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-

rupt periods, facilitating flexible ultra-low energy operation.

3.6.6 Pulse

Counter (PCNT)

The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The

clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from

among any of the internal oscillators, except the AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep,

EM2 Deep Sleep, and EM3 Stop.

3.6.7 Watchdog

Timer (WDOG)

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed

monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can

also monitor autonomous systems driven by PRS.

3.7 Communications

and Other Digital Peripherals

3.7.1 Universal

Synchronous/Asynchronous Receiver/Transmitter (USART)

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous

UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-

porting:

• ISO7816

SmartCards

• IrDA

•

3.7.2 Low

Energy Universal Asynchronous Receiver/Transmitter (LEUART)

The unique LEUART

provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow

UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication

possible with a minimum of software intervention and energy consumption.

3.7.3 Inter-Integrated

Circuit Interface (I

The I

C interface enables communication between the MCU and a serial I

C bus. It is capable of acting as both a master and a slave

and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates

from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system.

The interface provided to software by the I

C peripheral allows precise timing control of the transmission process and highly automated

transfers. Automatic recognition of slave addresses is provided in active and low energy modes.

3.7.4 Peripheral

Reflex System (PRS)

The Peripheral Reflex System provides a communication network between different peripherals without software involvement. Peripher-

als producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals, which in

turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied

by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.

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3.7.5 Low

Energy Sensor Interface (LESENSE)

The Low Energy Sensor Interface LESENSE

is a highly configurable sensor interface with support for up to 16 individually configura-

ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and

measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a

programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is

available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy

budget.

3.8 Security

Features

3.8.1 General

Purpose Cyclic Redundancy Check (GPCRC)

The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The suppor-

ted 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the

needs of the application.

3.8.2 Crypto

Accelerator (CRYPTO)

The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-

port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2

), SHA-1 and SHA-2 (SHA-224 and

SHA-256).

Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.

Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.

The CRYPTO1 block is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on

data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention.

CRYPTO also provides trigger signals for DMA read and write operations.

3.8.3 True

Random Number Generator (TRNG)

The TRNG is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with NIST800-22

and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key generation).

Note:

TRNG operation is only supported at VSCALE2. TRNG cannot be used at VSCALE0.

3.8.4 Security

Management Unit (SMU)

The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the

Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to

the peripheral’s register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and

can optionally generate an interrupt.

3.9 Analog

3.9.1 Analog

Port (APORT)

The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins.

Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are

grouped by X/Y pairs.

3.9.2 Analog

Comparator (ACMP)

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the

programmable threshold.

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3.9.3 Analog

to Digital Converter (ADC)

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output

sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.

The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of

sources, including pins configurable as either single-ended or differential.

3.9.4 Capacitive

Sense (CSEN)

The CSEN peripheral is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a

switches and sliders. The CSEN peripheral uses a charge ramping measurement technique, which provides robust sensing even in

adverse conditions including radiated noise and moisture. The peripheral can be configured to take measurements on a single port pin

or scan through multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the

combined capacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an aver-

aging filter, as well as digital threshold comparators to reduce software overhead.

3.9.5 Digital

to Analog Current Converter (IDAC)

The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC

input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of

various step sizes.

3.9.6 Digital

to Analog Converter (VDAC)

The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500

ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-

ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications

such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low

frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any

CPU intervention. The VDAC is available in all energy modes down to and including EM3.

3.9.7 Operational

Amplifiers

The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and

are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple

common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to

rail output. They can be used in conjunction with the VDAC peripheral or in stand-alone configurations. The opamps save energy, PCB

space, and cost as compared with standalone opamps because they are integrated on-chip.

3.10 Reset

Management Unit (RMU)

The RMU is responsible for handling reset of the EFR32FG12. A wide range of reset sources are available, including several power

supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.

3.11 Core

and Memory

3.11.1 Processor

Core

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:

• ARM

Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz

• Memory

Protection Unit (MPU) supporting up to 8 memory segments

• Up

to 1024 kB flash program memory

• Up

to 256 kB RAM data memory

• Configuration

and event handling of all peripherals

• 2-pin

Serial-Wire debug interface

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3.11.2 Memory

System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable

from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code

is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a

read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-

ergy modes EM0 Active and EM1 Sleep.

3.11.3 Linked

Direct Memory Access Controller (LDMA)

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This

reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-

phisticated operations to be implemented.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

System Overview

3.12 Memory

Map

The EFR32FG12 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.

Figure 3.2.

EFR32FG12 Memory Map — Core Peripherals and Code Space

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

System Overview

Figure 3.3.

EFR32FG12 Memory Map — Peripherals

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

System Overview

3.13 Configuration

Summary

The features of the EFR32FG12 are a subset of the feature set described in the device reference manual. The table below describes

device specific implementation of the features. Remaining modules support full configuration.

Table 3.2.

Configuration Summary

Module

Configuration

IrDA

Pin Connections

USART0

US0_TX, US0_RX, US0_CLK, US0_CS

SmartCard

USART1

US1_TX, US1_RX, US1_CLK, US1_CS

SmartCard

IrDA

USART2

USART3

US2_TX, US2_RX, US2_CLK, US2_CS

US3_TX, US3_RX, US3_CLK, US3_CS

SmartCard

TIMER0

with DTI

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[3:0]

TIMER1

–

WTIMER0

WTIMER1

with DTI

–

WTIM0_CC[2:0], WTIM0_CDTI[2:0]

WTIM1_CC[3:0]

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4. Electrical

Specifications

4.1 Electrical

Characteristics

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical

values are based on T

AMB

=25 °C and V

= 3.3 V, by production test and/or technology characterization.

• Radio

performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-

er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.

• Minimum

and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,

unless stated otherwise.

Refer to

4.1.2.1 General Operating Conditions

for more details about operational supply and temperature limits.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.1 Absolute

Maximum Ratings

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-

bility data, see the Quality and Reliability Monitor Report at

http://www.silabs.com/support/quality/pages/default.aspx

Table 4.1.

Absolute Maximum Ratings

Parameter

Symbol

STG

Test Condition

Min

-50

-0.3

—

Typ

—

Max

150

3.8

Unit

°C

Storage temperature range

Voltage on any supply pin

DDMAX

DDRAMPMAX

—

Voltage ramp rate on any

supply pin

—

V / µs

5V tolerant GPIO pins

1 2 3

Standard GPIO pins

DC voltage on any GPIO pin

DIGPIN

-0.3

—

Min of 5.25

and IOVDD

-0.3

—

IOVDD+0.3

Voltage on HFXO pins

HFXOPIN

1.4

Input RF level on pins

2G4RF_IOP and

2G4RF_ION

RFMAX2G4

dBm

Voltage differential between

MAXDIFF2G4

RF pins (2G4RF_IOP –

2G4RF_ION)

-50

—

Absolute voltage on RF pins

MAX2G4

2G4RF_IOP and

-0.3

3.8

2G4RF_ION

Absolute voltage on Sub-

GHz RF pins

MAXSUBG

Pins SUBGRF_OP and

SUBGRF_ON

-0.3

—

3.8

0.3

Pins SUBGRF_IP and

SUBGRF_IN,

Total current into VDD power

VDDMAX

lines

Source

200

Total current into VSS

ground lines

VSSMAX

Sink

—

Current per I/O pin

IOMAX

Sink

—

°C

Source

Current for all I/O pins

Junction temperature

IOALLMAX

Sink

—

200

105

125

Source

—

-G grade devices

-I grade devices

-40

°C

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. When a GPIO pin is routed to the analog block through the APORT, the maximum voltage = IOVDD.

2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source

below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the

maximum IO current specifications.

3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.

Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.2 Operating

Conditions

When assigning supply sources, the following requirements must be observed:

• VREGVDD

must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies.

• VREGVDD

= AVDD

• DVDD

≤ AVDD

• IOVDD

≤ AVDD

• RFVDD

≤ AVDD

• PAVDD

≤ AVDD

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.2.1 General

Operating Conditions

Table 4.2.

General Operating Conditions

Parameter

Symbol

Test Condition

Min

-40

1.8

Typ

Max

Unit

°C

Operating ambient tempera-

ture range

-G temperature grade

-I temperature grade

125

3.8

AVDD supply voltage

AVDD

3.3

VREGVDD operating supply

VREGVDD

voltage

2 3

DCDC in regulation

2.4

1.8

3.3

3.8

DCDC in bypass, 50mA load

DCDC not in use. DVDD external-

ly shorted to VREGVDD

VREGVDD current

VREGVDD

DCDC in bypass, T ≤ 85 °C

DCDC in bypass, T > 85 °C

—

200

100

RFVDD operating supply

voltage

RFVDD

1.62

VREGVDD

DVDD operating supply volt-

DVDD

age

1.62

0.75

—

VREGVDD

2.75

PAVDD operating supply

voltage

PAVDD

All IOVDD pins

IOVDD operating supply volt-

IOVDD

age

—

DECOUPLE output capaci-

tor

5 6

DECOUPLE

1.0

µF

Difference between AVDD

—

0.1

and VREGVDD, ABS(AVDD-

VREGVDD)

HFCORECLK frequency

CORE

VSCALE2, MODE = WS1

VSCALE2, MODE = WS0

VSCALE0, MODE = WS2

VSCALE0, MODE = WS1

VSCALE0, MODE = WS0

VSCALE2

—

MHz

HFCLK frequency

HFCLK

VSCALE0

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. The maximum limit on T

may be lower due to device self-heating, which depends on the power dissipation of the specific appli-

cation. T

(max) = T

(max) – (THETA

x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal

Characteristics table for T

and THETA

2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.

3. The minimum voltage required in bypass mode is calculated using R

BYP

from the DCDC specification table. Requirements for

other loads can be calculated as V

DVDD_min

LOAD

* R

BYP_max

4. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.

5. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-

ue stays within the specified bounds across temperature and DC bias.

6. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transi-

tion, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70

mA (with a 2.7 µF capacitor).

4.1.3 Thermal

Characteristics

Table 4.3.

Thermal Characteristics

Parameter

Symbol

Test Condition

Min

—

Typ

75.7

61.5

55.4

30.2

26.3

24.9

90.7

73.7

66.4

Max

—

Unit

°C/W

Thermal resistance, QFN48

THETA

JA_QFN48

2-Layer PCB, Air velocity = 0 m/s

Package

2-Layer PCB, Air velocity = 1 m/s

2-Layer PCB, Air velocity = 2 m/s

4-Layer PCB, Air velocity = 0 m/s

4-Layer PCB, Air velocity = 1 m/s

4-Layer PCB, Air velocity = 2 m/s

Thermal resistance, BGA125

THE-

Package TA

JA_BGA125

2-Layer PCB, Air velocity = 0 m/s

2-Layer PCB, Air velocity = 1 m/s

2-Layer PCB, Air velocity = 2 m/s

4-Layer PCB, Air velocity = 0 m/s

4-Layer PCB, Air velocity = 1 m/s

4-Layer PCB, Air velocity = 2 m/s

39.6

37.6

21.5

18.9

17.1

Thermal resistance, QFN68

THETA

JA_QFN68

4-Layer PCB, Air velocity = 0 m/s

Package

4-Layer PCB, Air velocity = 1 m/s

4-Layer PCB, Air velocity = 2 m/s

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.4 DC-DC

Converter

Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3

V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.

Table 4.4.

DC-DC Converter

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Input voltage range

DCDC_I

Bypass mode, I

DCDC_LOAD

= 50

1.8

—

VREGVDD_

MAX

Low noise (LN) mode, 1.8 V out-

put, I

DCDC_LOAD

= 100 mA, or

Low power (LP) mode, 1.8 V out-

put, I

DCDC_LOAD

= 10 mA

2.4

—

VREGVDD_

MAX

Low noise (LN) mode, 1.8 V out-

put, I

DCDC_LOAD

= 200 mA

2.6

1.8

—

VREGVDD_

MAX

Output voltage programma-

DCDC_O

ble range

VREGVDD

Regulation DC accuracy

ACC

Low Noise (LN) mode, 1.8 V tar-

get output

1.7

—

1.9

2.2

Regulation window

WIN

REG

Low Power (LP) mode,

LPCMPBIASEMxx

= 0, 1.8 V tar-

get output, I

DCDC_LOAD

≤ 75 µA

1.63

Low Power (LP) mode,

1.63

—

2.1

LPCMPBIASEMxx

= 3, 1.8 V tar-

get output, I

DCDC_LOAD

≤ 10 mA

Steady-state output ripple

Radio disabled

—

mVpp

CCM Mode (LNFORCECCM

1), Load changes between 0 mA

and 100 mA

Output voltage under/over-

shoot

DCM Mode (LNFORCECCM

0), Load changes between 0 mA

and 10 mA

—

Overshoot during LP to LN

CCM/DCM mode transitions com-

pared to DC level in LN mode

—

200

—

Undershoot during BYP/LP to LN

CCM (LNFORCECCM

= 1) mode

transitions compared to DC level

in LN mode

Undershoot during BYP/LP to LN

—

100

—

DCM (LNFORCECCM

= 0) mode

transitions compared to DC level

in LN mode

DC line regulation

DC load regulation

REG

Input changes between

VREGVDD_MAX

and 2.4 V

—

0.1

—

REG

Load changes between 0 mA and

100 mA in CCM mode

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Max load current

LOAD_MAX

Low noise (LN) mode, Heavy

Drive

, T ≤ 85 °C

—

200

Low noise (LN) mode, Heavy

Drive

, T > 85 °C

—

4.7

100

µA

Low noise (LN) mode, Medium

Drive

Low noise (LN) mode, Light

Drive

Low power (LP) mode,

LPCMPBIASEMxx

= 0

Low power (LP) mode,

LPCMPBIASEMxx

= 3

µF

DCDC nominal output ca-

pacitor

DCDC

25% tolerance

4.7

DCDC nominal output induc-

DCDC

tor

20% tolerance

4.7

—

4.7

1.2

4.7

2.5

µH

Ω

Resistance in Bypass mode

BYP

Note:

1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, V

VREGVDD

2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.

3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the

EMU_DCDCLOEM01CFG register, depending on the energy mode.

4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-

um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.

5. Output voltage under/over-shoot and regulation are specified with C

DCDC

4.7 µF. Different settings for DCDCLNCOMPCTRL

must be used if C

DCDC

is lower than 4.7 µF. See Application Note AN0948 for details.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.5 Current

Consumption

4.1.5.1 Current

Consumption 3.3 V without DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C. DCDC is off.

Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.

Table 4.5.

Current Consumption 3.3 V without DC-DC Converter

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM0

ACTIVE

mode with all peripherals dis-

abled

38.4 MHz crystal, CPU running

while loop from flash

—

130

—

µA/MHz

38 MHz HFRCO, CPU running

Prime from flash

—

105

—

µA/MHz

38 MHz HFRCO, CPU running

while loop from flash

38 MHz HFRCO, CPU running

CoreMark from flash

124

102

280

26 MHz HFRCO, CPU running

while loop from flash

108

435

—

1 MHz HFRCO, CPU running

while loop from flash

Current consumption in EM0

ACTIVE_VS

mode with all peripherals dis-

abled and voltage scaling

enabled

19 MHz HFRCO, CPU running

while loop from flash

1 MHz HFRCO, CPU running

while loop from flash

234

—

38.4 MHz crystal

38 MHz HFRCO

26 MHz HFRCO

1 MHz HFRCO

19 MHz HFRCO

1 MHz HFRCO

Current consumption in EM1

EM1

mode with all peripherals dis-

abled

—

µA/MHz

230

400

—

Current consumption in EM1

EM1_VS

mode with all peripherals dis-

abled and voltage scaling

enabled

193

—

Current consumption in EM2

EM2_VS

mode, with voltage scaling

enabled

Full 256 kB RAM retention and

RTCC running from LFXO

—

2.9

3.2

2.1

—

µA

Full 256 kB RAM retention and

RTCC running from LFRCO

16 kB (1 bank) RAM retention and

RTCC running from LFRCO

3.5

Current consumption in EM3

EM3_VS

mode, with voltage scaling

enabled

Full 256 kB RAM retention and

CRYOTIMER running from ULFR-

—

2.56

4.8

µA

Current consumption in

EM4H mode, with voltage

scaling enabled

EM4H_VS

128 byte RAM retention, RTCC

running from LFXO

—

1.0

—

µA

128 byte RAM retention, CRYO-

TIMER running from ULFRCO

0.45

0.43

128 byte RAM retention, no RTCC

0.9

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in

EM4S mode

EM4S

No RAM retention, no RTCC

—

0.04

0.1

µA

Note:

1. CMU_HFXOCTRL_LOWPOWER=0.

2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.5.2 Current

Consumption 3.3 V using DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC

output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.

Table 4.6.

Current Consumption 3.3 V using DC-DC Converter

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM0

ACTIVE_DCM

mode with all peripherals dis-

abled, DCDC in Low Noise

DCM mode

38.4 MHz crystal, CPU running

while loop from flash

—

µA/MHz

38 MHz HFRCO, CPU running

Prime from flash

—

µA/MHz

38 MHz HFRCO, CPU running

while loop from flash

38 MHz HFRCO, CPU running

CoreMark from flash

26 MHz HFRCO, CPU running

while loop from flash

1 MHz HFRCO, CPU running

while loop from flash

636

Current consumption in EM0

ACTIVE_CCM

mode with all peripherals dis-

abled, DCDC in Low Noise

CCM mode

38.4 MHz crystal, CPU running

while loop from flash

38 MHz HFRCO, CPU running

Prime from flash

—

µA/MHz

38 MHz HFRCO, CPU running

while loop from flash

38 MHz HFRCO, CPU running

CoreMark from flash

26 MHz HFRCO, CPU running

while loop from flash

1 MHz HFRCO, CPU running

while loop from flash

1155

101

1128

Current consumption in EM0

ACTIVE_CCM_VS

19 MHz HFRCO, CPU running

mode with all peripherals dis-

abled and voltage scaling

enabled, DCDC in Low

Noise CCM mode

while loop from flash

1 MHz HFRCO, CPU running

while loop from flash

38.4 MHz crystal

38 MHz HFRCO

26 MHz HFRCO

1 MHz HFRCO

19 MHz HFRCO

1 MHz HFRCO

Current consumption in EM1

EM1_DCM

mode with all peripherals dis-

abled, DCDC in Low Noise

—

µA/MHz

—

µA/MHz

DCM mode

610

Current consumption in EM1

EM1_DCM_VS

mode with all peripherals dis-

abled and voltage scaling

587

enabled, DCDC in Low

Noise DCM mode

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM2

EM2_VS

mode, with voltage scaling

enabled, DCDC in LP mode

Full 256 kB RAM retention and

RTCC running from LFXO

—

2.1

—

µA

Full 256 kB RAM retention and

RTCC running from LFRCO

—

2.2

1.5

—

µA

16 kB (1 bank) RAM retention and

RTCC running from LFRCO

Current consumption in EM3

EM3_VS

mode, with voltage scaling

enabled

Full 256 kB RAM retention and

CRYOTIMER running from ULFR-

—

1.81

—

µA

Current consumption in

EM4H mode, with voltage

scaling enabled

EM4H_VS

128 byte RAM retention, RTCC

running from LFXO

—

0.69

0.39

—

µA

128 byte RAM retention, CRYO-

TIMER running from ULFRCO

128 byte RAM retention, no RTCC

No RAM retention, no RTCC

—

0.39

0.06

—

µA

Current consumption in

EM4S mode

EM4S

Note:

1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.

2. CMU_HFXOCTRL_LOWPOWER=0.

3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.

4. DCDC Low Power Mode = Medium Drive, LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIMSEL=1, ANASW=DVDD.

5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.5.3 Current

Consumption 1.8 V without DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.8 V. T = 25 °C. DCDC is off.

Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.

Table 4.7.

Current Consumption 1.8 V without DC-DC Converter

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in EM0

ACTIVE

mode with all peripherals dis-

abled

38.4 MHz crystal, CPU running

while loop from flash

—

130

—

µA/MHz

38 MHz HFRCO, CPU running

Prime from flash

—

µA/MHz

38 MHz HFRCO, CPU running

while loop from flash

38 MHz HFRCO, CPU running

CoreMark from flash

124

102

277

26 MHz HFRCO, CPU running

while loop from flash

1 MHz HFRCO, CPU running

while loop from flash

Current consumption in EM0

ACTIVE_VS

mode with all peripherals dis-

abled and voltage scaling

enabled

19 MHz HFRCO, CPU running

while loop from flash

1 MHz HFRCO, CPU running

while loop from flash

231

38.4 MHz crystal

38 MHz HFRCO

26 MHz HFRCO

1 MHz HFRCO

19 MHz HFRCO

1 MHz HFRCO

Current consumption in EM1

EM1

mode with all peripherals dis-

abled

—

µA/MHz

227

Current consumption in EM1

EM1_VS

mode with all peripherals dis-

abled and voltage scaling

enabled

190

Current consumption in EM2

EM2_VS

mode, with voltage scaling

enabled

Full 256 kB RAM retention and

RTCC running from LFXO

—

2.8

3.0

1.9

—

µA

Full 256 kB RAM retention and

RTCC running from LFRCO

16 kB (1 bank) RAM retention and

RTCC running from LFRCO

Current consumption in EM3

EM3_VS

mode, with voltage scaling

enabled

Full 256 kB RAM retention and

CRYOTIMER running from ULFR-

—

2.47

—

µA

Current consumption in

EM4H mode, with voltage

scaling enabled

EM4H_VS

128 byte RAM retention, RTCC

running from LFXO

—

0.91

0.35

—

µA

128 byte RAM retention, CRYO-

TIMER running from ULFRCO

128 byte RAM retention, no RTCC

No RAM retention, no RTCC

—

0.35

0.04

—

µA

Current consumption in

EM4S mode

EM4S

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. CMU_HFXOCTRL_LOWPOWER=0.

2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.5.4 Current

Consumption Using Radio 3.3 V with DC-DC

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V. T = 25

°C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.

Table 4.8.

Current Consumption Using Radio 3.3 V with DC-DC

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in re-

ceive mode, active packet

reception (MCU in EM1 @

38.4 MHz, peripheral clocks

disabled), T ≤ 85 °C

RX_ACTIVE

500 kbit/s, 2GFSK, F = 915 MHz,

Radio clock prescaled by 4

—

9.3

10.2

38.4 kbit/s, 2GFSK, F = 868 MHz,

Radio clock prescaled by 4

—

8.6

8.4

10.0

11.5

10.2

—

38.4 kbit/s, 2GFSK, F = 490 MHz,

Radio clock prescaled by 4

50 kbit/s, 2GFSK, F = 433 MHz,

Radio clock prescaled by 4

38.4 kbit/s, 2GFSK, F = 315 MHz,

Radio clock prescaled by 4

38.4 kbit/s, 2GFSK, F = 169 MHz,

Radio clock prescaled by 4

1 Mbit/s, 2GFSK, F = 2.4 GHz,

Radio clock prescaled by 4

2 Mbit/s, 2GFSK, F = 2.4 GHz,

Radio clock prescaled by 4

—

802.15.4 receiving frame, F = 2.4

GHz, Radio clock prescaled by 3

—

Current consumption in re-

ceive mode, active packet

reception (MCU in EM1 @

38.4 MHz, peripheral clocks

disabled), T > 85 °C

RX_ACTIVE_HT

500 kbit/s, 2GFSK, F = 915 MHz,

Radio clock prescaled by 4

—

38.4 kbit/s, 2GFSK, F = 868 MHz,

Radio clock prescaled by 4

—

38.4 kbit/s, 2GFSK, F = 490 MHz,

Radio clock prescaled by 4

—

50 kbit/s, 2GFSK, F = 433 MHz,

Radio clock prescaled by 4

—

38.4 kbit/s, 2GFSK, F = 315 MHz,

Radio clock prescaled by 4

—

38.4 kbit/s, 2GFSK, F = 169 MHz,

Radio clock prescaled by 4

—

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in re-

ceive mode, listening for

packet (MCU in EM1 @ 38.4

MHz, peripheral clocks disa-

bled), T ≤ 85 °C

RX_LISTEN

500 kbit/s, 2GFSK, F = 915 MHz,

No radio clock prescaling

—

10.2

38.4 kbit/s, 2GFSK, F = 868 MHz,

No radio clock prescaling

—

9.5

9.4

9.3

10.9

11.9

12.5

—

38.4 kbit/s, 2GFSK, F = 490 MHz,

No radio clock prescaling

50 kbit/s, 2GFSK, F = 433 MHz,

No radio clock prescaling

38.4 kbit/s, 2GFSK, F = 315 MHz,

No radio clock prescaling

38.4 kbit/s, 2GFSK, F = 169 MHz,

No radio clock prescaling

1 Mbit/s, 2GFSK, F = 2.4 GHz, No

radio clock prescaling

2 Mbit/s, 2GFSK, F = 2.4 GHz, No

radio clock prescaling

802.15.4, F = 2.4 GHz, No radio

clock prescaling

Current consumption in re-

ceive mode, listening for

packet (MCU in EM1 @ 38.4

MHz, peripheral clocks disa-

bled), T > 85 °C

RX_LISTEN_HT

500 kbit/s, 2GFSK, F = 915 MHz,

No radio clock prescaling

38.4 kbit/s, 2GFSK, F = 868 MHz,

No radio clock prescaling

—

38.4 kbit/s, 2GFSK, F = 490 MHz,

No radio clock prescaling

—

50 kbit/s, 2GFSK, F = 433 MHz,

No radio clock prescaling

—

38.4 kbit/s, 2GFSK, F = 315 MHz,

No radio clock prescaling

—

38.4 kbit/s, 2GFSK, F = 169 MHz,

No radio clock prescaling

—

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in

transmit mode (MCU in EM1

@ 38.4 MHz, peripheral

clocks disabled), T ≤ 85 °C

F = 915 MHz, CW, 20 dBm

match, External PA supply = 3.3V

—

90.2

134.3

F = 915 MHz, CW, 14 dBm

match, External PA supply con-

nected to DCDC output

—

42.5

F = 868 MHz, CW, 20 dBm

match, External PA supply = 3.3V

—

79.7

35.3

106.7

F = 868 MHz, CW, 14 dBm

match, External PA supply con-

nected to DCDC output

F = 490 MHz, CW, 20 dBm

match, External PA supply = 3.3V

—

93.8

20.3

125.4

F = 433 MHz, CW, 10 dBm

match, External PA supply con-

nected to DC-DC output

F = 433 MHz, CW, 14 dBm

match, External PA supply con-

nected to DCDC output

—

41.5

F = 315 MHz, CW, 14 dBm

match, External PA supply con-

nected to DCDC output

33.5

F = 169 MHz, CW, 20 dBm

match, External PA supply = 3.3V

—

88.6

8.5

9.5

16.5

116.7

—

F = 2.4 GHz, CW, 0 dBm output

power, Radio clock prescaled by 3

F = 2.4 GHz, CW, 0 dBm output

power, Radio clock prescaled by 1

—

F = 2.4 GHz, CW, 3 dBm output

power

—

F = 2.4 GHz, CW, 8 dBm output

power

—

F = 2.4 GHz, CW, 10.5 dBm out-

put power

—

F = 2.4 GHz, CW, 16.5 dBm out-

put power, PAVDD connected di-

rectly to external 3.3V supply

—

F = 2.4 GHz, CW, 19.5 dBm out-

put power, PAVDD connected di-

rectly to external 3.3V supply

—

131

—

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Current consumption in

transmit mode (MCU in EM1

@ 38.4 MHz, peripheral

clocks disabled), T > 85 °C

TX_HT

F = 915 MHz, CW, 20 dBm

match, External PA supply = 3.3V

—

134.3

F = 915 MHz, CW, 14 dBm

match, External PA supply con-

nected to DCDC output

—

42.5

F = 868 MHz, CW, 20 dBm

match, External PA supply = 3.3V

—

109.8

41.3

F = 868 MHz, CW, 14 dBm

match, External PA supply con-

nected to DCDC output

F = 490 MHz, CW, 20 dBm

match, External PA supply = 3.3V

—

130.8

24.4

F = 433 MHz, CW, 10 dBm

match, External PA supply con-

nected to DC-DC output

F = 433 MHz, CW, 14 dBm

match, External PA supply con-

nected to DCDC output

—

41.5

F = 315 MHz, CW, 14 dBm

match, External PA supply con-

nected to DCDC output

F = 169 MHz, CW, 20 dBm

122.8

match, External PA supply = 3.3V

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.6 Wake

Up Times

Table 4.9.

Wake Up Times

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Wake up time from EM1

EM1_WU

—

AHB

Clocks

Wake up from EM2

Wake up from EM3

EM2_WU

Code execution from flash

Code execution from RAM

Code execution from flash

Code execution from RAM

Executing from flash

—

10.1

3.2

—

µs

EM3_WU

10.1

3.2

Wake up from EM4H

Wake up from EM4S

EM4H_WU

EM4S_WU

RESET

Executing from flash

—

291

—

µs

Time from release of reset

source to first instruction ex-

ecution

Soft Pin Reset released

Any other reset released

—

µs

350

Power mode scaling time

SCALE

VSCALE0 to VSCALE2, HFCLK =

19 MHz

2 3

—

31.8

4.3

—

µs

VSCALE2 to VSCALE0, HFCLK =

19 MHz

Note:

1. Time from wake up request until first instruction is executed. Wakeup results in device reset.

2. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 µs + 28 HFCLKs.

3. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,

peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70 mA

(with a 2.7 µF capacitor).

4. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 µs + 29 HFCLKs.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.7 Brown

Out Detector (BOD)

Table 4.10.

Brown Out Detector (BOD)

Parameter

Symbol

Test Condition

Min

—

Typ

—

Max

1.62

—

Unit

DVDD BOD threshold

DVDDBOD

DVDD rising

DVDD falling (EM0/EM1)

DVDD falling (EM2/EM3)

1.35

1.3

—

DVDD BOD hysteresis

DVDD BOD response time

AVDD BOD threshold

DVDDBOD_HYST

2.4

—

µs

DVDDBOD_DELAY

Supply drops at 0.1V/µs rate

—

AVDDBOD

AVDD rising

—

1.8

—

AVDD falling (EM0/EM1)

AVDD falling (EM2/EM3)

1.62

1.53

—

AVDD BOD hysteresis

AVDD BOD response time

EM4 BOD threshold

AVDDBOD_HYST

2.4

—

µs

AVDDBOD_DELAY

Supply drops at 0.1V/µs rate

—

EM4DBOD

AVDD rising

AVDD falling

—

1.7

—

1.45

—

EM4 BOD hysteresis

EM4BOD_HYST

300

—

µs

EM4 BOD response time

EM4BOD_DELAY

Supply drops at 0.1V/µs rate

—

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.8 Frequency

Synthesizer

Table 4.11.

Frequency Synthesizer

Parameter

Symbol

Test Condition

2400 – 2483.5 MHz

779 – 956 MHz

584 – 717 MHz

358 – 574 MHz

191 – 358 MHz

110 – 191 MHz

2400 – 2483.5 MHz

779 – 956 MHz

584 – 717 MHz

358 – 574 MHz

191 – 358 MHz

110 – 191 MHz

2400 – 2483.5 MHz

779 – 956 MHz

584 – 717 MHz

358 – 574 MHz

191 – 358 MHz

110 – 191 MHz

2400 – 2483.5 MHz

779 – 956 MHz

584 – 717 MHz

358 – 574 MHz

191 – 358 MHz

110 – 191 MHz

Min

2400

779

584

358

191

110

—

Typ

—

Max

2483.5

956

717

574

358

191

Unit

MHz

RF synthesizer frequency

range

RANGE

LO tuning frequency resolu-

RES

tion with 38.4 MHz crystal

—

18.3

12.2

7.3

—

4.6

Frequency deviation resolu-

RES

tion with 38.4 MHz crystal

—

18.3

12.2

7.3

—

4.6

Maximum frequency devia-

tion with 38.4 MHz crystal

MAX

—

1677

559

419

280

167

105

kHz

—

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.9 2.4

GHz RF Transceiver Characteristics

4.1.9.1 RF

Transmitter General Characteristics for 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.

Table 4.12.

RF Transmitter General Characteristics for 2.4 GHz Band

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Maximum TX power

POUT

MAX

19 dBm-rated part numbers.

PAVDD connected directly to ex-

ternal 3.3V supply

—

19.5

—

dBm

Minimum active TX Power

Output power step size

POUT

MIN

-30

—

dBm

POUT

STEP

-5 dBm< Output power < 0 dBm

—

0 dBm < output power <

POUT

MAX

0.5

Output power variation vs

supply at POUT

MAX

POUT

VAR_V

1.8 V < V

VREGVDD

< 3.3 V,

PAVDD connected directly to ex-

ternal supply, for output power >

10 dBm.

—

4.5

—

1.8 V < V

VREGVDD

< 3.3 V using

DC-DC converter

—

2.2

1.5

2.2

1.5

3.4

0.4

—

Output power variation vs

temperature at POUT

MAX

POUT

VAR_T

From -40 to +85 °C, PAVDD con-

nected to DC-DC output

From -40 to +125 °C, PAVDD

connected to DC-DC output

—

From -40 to +85 °C, PAVDD con-

nected to external supply

—

From -40 to +125 °C, PAVDD

connected to external supply

—

Output power variation vs RF

POUT

VAR_F

frequency at POUT

MAX

Over RF tuning frequency range

—

RF tuning frequency range

RANGE

2400

2483.5

MHz

Note:

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-

ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.9.2 RF

Receiver General Characteristics for 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.

Table 4.13.

RF Receiver General Characteristics for 2.4 GHz Band

Parameter

Symbol

RANGE

SPUR

Test Condition

Min

2400

—

Typ

—

Max

2483.5

—

Unit

MHz

dBm

RF tuning frequency range

Receive mode maximum

spurious emission

30 MHz to 1 GHz

1 GHz to 12 GHz

-57

—

-47

—

Max spurious emissions dur-

SPUR

RX_FCC

ing active receive mode, per

FCC Part 15.109(a)

216 MHz to 960 MHz, Conducted

Measurement

—

-55.2

—

Above 960 MHz, Conducted

Measurement

—

-47.2

-24

—

dBm

Level above which

RFSENSE will trigger

RFSENSE

TRIG

CW at 2.45 GHz

Level below which

RFSENSE will not trigger

RFSENSE

THRES

CW at 2.45 GHz

—

-50

—

dBm

1% PER sensitivity

SENS

2GFSK

2 Mbps 2GFSK signal

250 kbps 2GFSK signal

—

-89.6

—

dBm

-100.7

Note:

1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.9.3 RF

Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of

85%.

Table 4.14.

RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate

Parameter

Symbol

TXBW

Test Condition

Min

—

Typ

781

-8.4

Max

—

Unit

Transmit 6dB bandwidth

Power spectral density limit

10 dBm

kHz

PSD

LIMIT

Per FCC part 15.247 at 10 dBm

—

dBm/

3kHz

Per FCC part 15.247 at 20 dBm

—

-0.4

10.1

1.1

—

dBm/

3kHz

Per ETSI 300.328 at 10 dBm/1

MHz

dBm

MHz

dBm

Occupied channel bandwidth

OCP

ETSI328

per ETSI EN300.328

99% BW at highest and lowest

channels in band, 10 dBm

Emissions of harmonics out-

SPUR

HRM_FCC

2nd,3rd, 5, 6, 8, 9,10 harmonics;

-47

of-band, per FCC part

15.247

continuous transmission of modu-

lated carrier

Spurious emissions out-of-

band, excluding harmonics

captured in SPUR

HARM,FCC

Emissions taken at

POUT

MAX

, PAVDD connec-

ted to external 3.3 V supply

SPUR

OOB_FCC

Per FCC part 15.205/15.209,

Above 2.483 GHz or below 2.4

GHz; continuous transmission of

—

-47

-26

—

dBm

dBc

CW carrier, Restricted Bands

1 2

Per FCC part 15.247, Above

2.483 GHz or below 2.4 GHz;

continuous transmission of CW

carrier, Non-Restricted Bands

Spurious emissions out-of-

band; per ETSI 300.328

SPUR

ETSI328

[2400-BW to 2400] MHz, [2483.5

to 2483.5+BW] MHz

—

-16

-26

—

dBm

[2400-2BW to 2400-BW] MHz,

[2483.5+BW to 2483.5+2BW]

MHz per ETSI 300.328

Spurious emissions per ETSI

SPUR

ETSI440

EN300.440

47-74 MHz,87.5-108 MHz,

174-230 MHz, 470-862 MHz

—

-60

—

dBm

25-1000 MHz

1-12 GHz

—

-42

-36

—

dBm

Note:

1. For 2476 MHz, 1.5 dB of power backoff is used to achieve this value.

2. For 2478 MHz, 4.2 dB of power backoff is used to achieve this value.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.9.4 RF

Receiver Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz.

Table 4.15.

RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal is reference signal

. Packet

length is 20 bytes.

Max usable receiver input

level, 0.1% BER

SAT

—

dBm

Signal is reference signal

. Using

DC-DC converter.

Sensitivity, 0.1% BER

SENS

—

-94.8

—

dBm

Signal to co-channel interfer-

C/I

er, 0.1% BER

Desired signal 3 dB above refer-

ence sensitivity.

—

10.3

-1.8

—

N+1 adjacent channel selec-

C/I

tivity, 0.1% BER, with allowa-

ble exceptions. Desired is

Interferer is reference signal at +1

MHz offset. Desired frequency

2402 MHz ≤ Fc ≤ 2480 MHz

reference signal at -67 dBm

N-1 adjacent channel selec-

C/I

tivity, 0.1% BER, with allowa-

ble exceptions. Desired is

Interferer is reference signal at -1

MHz offset. Desired frequency

2402 MHz ≤ Fc ≤ 2480 MHz

—

-0.7

—

reference signal at -67 dBm

Alternate selectivity, 0.1%

BER, with allowable excep-

tions. Desired is reference

signal at -67 dBm

C/I

Interferer is reference signal at ± 2

MHz offset. Desired frequency

2402 MHz ≤ Fc ≤ 2480 MHz,

QFN48 and BGA125 packages.

-40.6

-34.1

-46.2

Interferer is reference signal at ± 2

MHz offset. Desired frequency

2402 MHz ≤ Fc ≤ 2480 MHz,

QFN68 package.

Alternate selectivity, 0.1%

BER, with allowable excep-

tions. Desired is reference

signal at -67 dBm

C/I

Interferer is reference signal at ± 3

MHz offset. Desired frequency

2404 MHz ≤ Fc ≤ 2480 MHz

Selectivity to image frequen-

C/I

cy, 0.1% BER. Desired is ref-

erence signal at -67 dBm

Interferer is reference signal at im-

age frequency with 1 MHz preci-

sion

—

-38.1

-46.5

—

Selectivity to image frequen-

C/I

IM+1

cy ± 1 MHz, 0.1% BER. De-

sired is reference signal at

-67 dBm

Interferer is reference signal at im-

age frequency ± 1 MHz with 1

MHz precision

Blocking, less than 0.1%

BER. Desired is -67dBm

BLE reference signal at

2426MHz. Interferer is CW in

BLOCK

OOB

Interferer frequency 30 MHz ≤ f ≤

2000 MHz

-5

—

dBm

Interferer frequency 2003 MHz ≤ f

≤ 2399 MHz

-24

-10

-17

OOB range

Interferer frequency 2484 MHz ≤ f

≤ 2997 MHz

Interferer frequency 3 GHz ≤ f ≤ 6

GHz

Interferer frequency 6 GHz ≤ f ≤

12.75 GHz

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;

interferer data = PRBS15; frequency accuracy better than 1 ppm.

2. Interferer max power limited by equipment capabilities and path loss. Minimum specified at 25 °C.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.9.5 RF

Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of

85%.

Table 4.16.

RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate

Parameter

Symbol

TXBW

Test Condition

Min

—

Typ

1404

-12.3

Max

—

Unit

Transmit 6dB bandwidth

Power spectral density limit

10 dBm

kHz

PSD

LIMIT

Per FCC part 15.247 at 10 dBm

—

dBm/

3kHz

Per FCC part 15.247 at 20 dBm

—

-4.0

11.3

2.1

—

dBm/

3kHz

Per ETSI 300.328 at 10 dBm/1

MHz

dBm

MHz

dBm

Occupied channel bandwidth

OCP

ETSI328

per ETSI EN300.328

99% BW at highest and lowest

channels in band, 10 dBm

Emissions of harmonics out-

SPUR

HRM_FCC

2nd,3rd, 5, 6, 8, 9,10 harmonics;

-47

of-band, per FCC part

15.247

continuous transmission of modu-

lated carrier

Spurious emissions out-of-

band, excluding harmonics

captured in SPUR

HARM,FCC

Emissions taken at

POUT

MAX

, PAVDD connec-

ted to external 3.3 V supply

SPUR

OOB_FCC

Per FCC part 15.205/15.209,

Above 2.483 GHz or below 2.4

GHz; continuous transmission of

—

-47

-26

—

dBm

dBc

CW carrier, Restricted Bands

1 2 3

Per FCC part 15.247, Above

2.483 GHz or below 2.4 GHz;

continuous transmission of CW

carrier, Non-Restricted Bands

Spurious emissions out-of-

band; per ETSI 300.328

SPUR

ETSI328

[2400-BW to 2400] MHz, [2483.5

to 2483.5+BW] MHz

—

-16

-26

—

dBm

[2400-2BW to 2400-BW] MHz,

[2483.5+BW to 2483.5+2BW]

MHz per ETSI 300.328

Spurious emissions per ETSI

SPUR

ETSI440

EN300.440

47-74 MHz,87.5-108 MHz,

174-230 MHz, 470-862 MHz

—

-60

—

dBm

25-1000 MHz

1-12 GHz

—

-42

-36

—

dBm

Note:

1. For 2472 MHz, 1.3 dB of power backoff is used to achieve this value.

2. For 2474 MHz, 3.8 dB of power backoff is used to achieve this value.

3. For 2476 MHz, 7 dB of power backoff is used to achieve this value.

4. For 2478 MHz, 11.2 dB of power backoff is used to achieve this value.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.9.6 RF

Receiver Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz

Table 4.17.

RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal is reference signal

. Packet

length is 20 bytes.

Max usable receiver input

level, 0.1% BER

SAT

—

dBm

Signal is reference signal

. Using

DC-DC converter. QFN48 and

BGA125 packages.

Sensitivity, 0.1% BER

SENS

—

-91.3

—

dBm

Signal is reference signal

. Using

DC-DC converter. QFN68 pack-

age.

Signal to co-channel interfer-

C/I

er, 0.1% BER

Desired signal 3 dB above refer-

ence sensitivity.

—

7.3

—

N+1 adjacent channel selec-

C/I

tivity, 0.1% BER, with allowa-

ble exceptions. Desired is

Interferer is reference signal at +2

MHz offset. Desired frequency

2402 MHz ≤ Fc ≤ 2480 MHz

-10.4

reference signal at -67 dBm

N-1 adjacent channel selec-

C/I

tivity, 0.1% BER, with allowa-

ble exceptions. Desired is

Interferer is reference signal at -2

MHz offset. Desired frequency

2402 MHz ≤ Fc ≤ 2480 MHz

—

-13.9

-40.9

-43.7

—

reference signal at -67 dBm

Alternate selectivity, 0.1%

BER, with allowable excep-

tions. Desired is reference

signal at -67 dBm

C/I

Interferer is reference signal at ± 4

MHz offset. Desired frequency

2402 MHz ≤ Fc ≤ 2480 MHz

Alternate selectivity, 0.1%

BER, with allowable excep-

tions. Desired is reference

signal at -67 dBm

C/I

Interferer is reference signal at ± 6

MHz offset. Desired frequency

2404 MHz ≤ Fc ≤ 2480 MHz

Selectivity to image frequen-

C/I

cy, 0.1% BER. Desired is ref-

erence signal at -67 dBm

Interferer is reference signal at im-

age frequency with 1 MHz preci-

sion

—

-10.4

-40.9

—

Selectivity to image frequen-

C/I

IM+1

cy ± 2 MHz, 0.1% BER. De-

sired is reference signal at

-67 dBm

Interferer is reference signal at im-

age frequency ± 2 MHz with 2

MHz precision

Note:

1. For the BLE 2Mbps in-band blocking performance, there may be up to 5 spurious response channels where the requirement of

30.8% PER is not met and therefore an exception will need to be taken for each of these frequencies to meet the requirements of

the BLE standard.

2. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 2 Mbps, desired data = PRBS9;

interferer data = PRBS15; frequency accuracy better than 1 ppm.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.9.7 RF

Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz. Maximum duty cycle

of 66%.

Table 4.18.

RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Error vector magnitude (off-

EVM

set EVM), per 802.15.4-2011

Average across frequency. Signal

is DSSS-OQPSK reference pack-

—

3.8

—

% rms

Power spectral density limit

PSD

LIMIT

Relative, at carrier ± 3.5 MHz, out-

put power at POUT

MAX

—

-26

-36

—

dBc/

100kHz

Absolute, at carrier ± 3.5 MHz,

dBm/

100kHz

output power at POUT

MAX

Per FCC part 15.247, output pow-

er at POUT

MAX

—

-4

—

dBm/

3kHz

ETSI

—

12.1

2.25

—

dBm

MHz

Occupied channel bandwidth

OCP

ETSI328

per ETSI EN300.328

99% BW at highest and lowest

channels in band

Spurious emissions of har-

monics in restricted bands

per FCC Part 15.205/15.209,

Emissions taken at

POUT

MAX

, PAVDD connec-

ted to external 3.3 V supply,

Test Frequency is 2450 MHz

SPUR

HRM_FCC_

Continuous transmission of modu-

—

-45.8

—

dBm

lated carrier

Spurious emissions of har-

monics in non-restricted

bands per FCC Part

SPUR

HRM_FCC_

Continuous transmission of modu-

-26

dBc

lated carrier

NRR

15.247/15.35, Emissions tak-

en at POUT

MAX

, PAVDD

connected to external 3.3 V

supply, Test Frequency is

2450 MHz

Spurious emissions out-of-

band (above 2.483 GHz or

below 2.4 GHz) in restricted

bands, per FCC part

15.205/15.209, Emissions

taken at POUT

MAX

, PAVDD

connected to external 3.3 V

supply, Test Frequency =

2450 MHz

SPUR

OOB_FCC_

Restricted bands 30-88 MHz; con-

—

-61

-58

-55

-47

—

dBm

tinuous transmission of modulated

carrier

Restricted bands 88-216 MHz;

continuous transmission of modu-

lated carrier

Restricted bands 216-960 MHz;

continuous transmission of modu-

lated carrier

Restricted bands >960 MHz; con-

tinuous transmission of modulated

carrier

3 4

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Spurious emissions out-of-

band in non-restricted bands

per FCC Part 15.247, Emis-

SPUR

OOB_FCC_

Above 2.483 GHz or below 2.4

—

-26

—

dBc

GHz; continuous transmission of

modulated carrier

sions taken at POUT

MAX

PAVDD connected to exter-

nal 3.3 V supply, Test Fre-

quency = 2450 MHz

Spurious emissions out-of-

band; per ETSI 300.328

SPUR

ETSI328

[2400-BW to 2400], [2483.5 to

2483.5+BW];

—

-16

-26

—

dBm

[2400-2BW to 2400-BW],

[2483.5+BW to 2483.5+2BW]; per

ETSI 300.328

Spurious emissions per ETSI

SPUR

ETSI440

EN300.440

47-74 MHz,87.5-108 MHz,

174-230 MHz, 470-862 MHz

—

-60

-42

-36

—

dBm

25-1000 MHz, excluding above

frequencies

1G-14G

Note:

1. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with

pseudo-random packet data content.

2. For 2415 MHz, 2 dB of power backoff is used to achieve this value.

3. For 2475 MHz, 2 dB of power backoff is used to achieve this value.

4. For 2480 MHz, 13 dB of power backoff is used to achieve this value.

5. Specified at maximum power output level of 10 dBm.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.9.8 RF

Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.

Table 4.19.

RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal is reference signal

. Packet

length is 20 octets.

Max usable receiver input

level, 1% PER

SAT

—

dBm

Sensitivity, 1% PER

SENS

Signal is reference signal. Packet

length is 20 octets. Using DC-DC

converter.

—

-102.7

—

dBm

Signal is reference signal. Packet

length is 20 octets. Without DC-

DC converter.

Co-channel interferer rejec-

CCR

tion, 1% PER

Desired signal 3 dB above sensi-

tivity limit

—

-4.6

40.7

—

High-side adjacent channel

rejection, 1% PER. Desired

is reference signal at 3dB

above reference sensitivity

ACR

Interferer is reference signal at +1

channel-spacing.

Interferer is filtered reference sig-

nal

at +1 channel-spacing.

level

Interferer is CW at +1 channel-

spacing

—

54.3

—

Low-side adjacent channel

rejection, 1% PER. Desired

is reference signal at 3dB

above reference sensitivity

ACR

Interferer is reference signal at -1

channel-spacing.

—

40.8

47.5

—

Interferer is filtered reference sig-

nal

at -1 channel-spacing.

level

Interferer is CW at -1 channel-

spacing.

—

56.5

51.5

53.7

—

Alternate channel rejection,

1% PER. Desired is refer-

ence signal at 3dB above

reference sensitivity level

Interferer is reference signal at ± 2

channel-spacing

Interferer is filtered reference sig-

nal

at ± 2 channel-spacing

Interferer is CW at ± 2 channel-

spacing

—

62.4

50.4

—

Interferer is CW in image band

Image rejection , 1% PER,

Desired is reference signal at

3dB above reference sensi-

tivity level

Blocking rejection of all other

BLOCK

channels. 1% PER, Desired

is reference signal at 3dB

above reference sensitivity

level

. Interferer is reference

signal

Interferer frequency < Desired fre-

quency – 3 channel-spacing

—

58.5

56.4

—

Interferer frequency > Desired fre-

quency + 3 channel-spacing

Blocking rejection of 802.11g

BLOCK

80211G

signal centered at +12MHz

or -13MHz

Desired is reference signal at 6dB

above reference sensitivity level

—

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Upper limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MAX

—

dBm

Lower limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MIN

-98

—

dBm

RSSI resolution

RSSI

RES

RSSI

LIN

over RSSI

MIN

to RSSI

MAX

—

0.25

+/-6

—

RSSI accuracy in the linear

region as defined by

802.15.4-2003

Note:

1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-

bols/s.

2. Reference sensitivity level is -85 dBm.

3. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-

band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.

4. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker

tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection

test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.

5. This is an IEEE 802.11b/g ERP-PBCC 22 MBit/s signal as defined by the IEEE 802.11 specification and IEEE 802.11g adden-

dum.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10 Sub-GHz

RF Transceiver Characteristics

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.1 Sub-GHz

RF Transmitter characteristics for 915 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz.

Table 4.20.

Sub-GHz RF Transmitter characteristics for 915 MHz Band

Parameter

Symbol

RANGE

Test Condition

Min

902

Typ

—

Max

930

Unit

MHz

dBm

RF tuning frequency range

Maximum TX Power

POUT

MAX

External PA supply = 3.3V, 20

dBm output power setting

19.8

23.3

External PA supply connected to

DC-DC output, 14 dBm output

power setting

12.6

14.2

16.1

dBm

Minimum active TX Power

Output power step size

POUT

MIN

—

-45.5

0.5

—

dBm

POUT

STEP

POUT

VAR_V

output power > 0 dBm

Output power variation vs

supply at POUT

MAX

1.8 V < V

VREGVDD

< 3.3 V, Exter-

nal PA supply = 3.3 V, T = 25 °C

4.8

1.8 V < V

VREGVDD

< 3.3 V, Exter-

nal PA supply connected to DC-

DC output, T = 25 °C

—

1.9

—

Output power variation vs

temperature, peak to peak

POUT

VAR_T

-40 to +85 °C with External PA

supply = 3.3 V

—

0.6

0.7

1.3

1.4

-40 to +85 °C with External PA

supply connected to DC-DC out-

put

Output power variation vs RF

POUT

VAR_F

frequency

External PA supply = 3.3 V, T =

25 °C

—

0.2

0.3

-45

-26

0.6

-42

-20

External PA supply connected to

DC-DC output, T = 25 °C

Spurious emissions of har-

monics at 20 dBm output

power, Conducted measure-

ment, 20dBm match, Exter-

nal PA supply = 3.3V, Test

Frequency = 915 MHz

SPUR

HARM_FCC

In restricted bands, per FCC Part

dBm

dBc

15.205 / 15.209

_20

In non-restricted bands, per FCC

Part 15.247

Spurious emissions out-of-

band at 20 dBm output pow-

er, Conducted measurement,

20dBm match, External PA

supply = 3.3V, Test Frequen-

cy = 915 MHz

SPUR

OOB_FCC_

In non-restricted bands, per FCC

—

-26

-62

-61

-58

-20

-56

-52

dBc

dBm

Part 15.247

In restricted bands (30-88 MHz),

per FCC Part 15.205 / 15.209

In restricted bands (88-216 MHz),

per FCC Part 15.205 / 15.209

In restricted bands (216-960

MHz), per FCC Part 15.205 /

15.209

In restricted bands (>960 MHz),

per FCC Part 15.205 / 15.209

—

-47

-42

dBm

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Spurious emissions of har-

monics at 14 dBm output

power, Conducted measure-

ment, 14dBm match, Exter-

nal PA supply connected to

DC-DC output, Test Fre-

quency = 915 MHz

SPUR

HARM_FCC

In restricted bands, per FCC Part

—

-47

-42

dBm

15.205 / 15.209

_14

In non-restricted bands, per FCC

Part 15.247

—

-26

-20

dBc

Spurious emissions out-of-

band at 14 dBm output pow-

er, Conducted measurement,

14dBm match, External PA

supply connected to DC-DC

output, Test Frequency =

915 MHz

SPUR

OOB_FCC_

In non-restricted bands, per FCC

—

-26

-62

-61

-58

-20

-56

-52

dBc

dBm

Part 15.247

In restricted bands (30-88 MHz),

per FCC Part 15.205 / 15.209

In restricted bands (88-216 MHz),

per FCC Part 15.205 / 15.209

In restricted bands (216-960

MHz), per FCC Part 15.205 /

15.209

In restricted bands (>960 MHz),

per FCC Part 15.205 / 15.209

—

-45

1.0

-42

2.8

dBm

Error vector magnitude (off-

EVM

set EVM), per 802.15.4-2011

Signal is DSSS-OQPSK reference

packet. Modulated according to

802.15.4-2011 DSSS-OQPSK in

the 915MHz band, with pseudo-

random packet data content. Ex-

ternal PA supply = 3.3V.

%rms

Power spectral density limit

PSD

Relative, at carrier ± 1.2 MHz.

Average spectral power shall be

measured using a 100kHz resolu-

tion bandwidth. The reference lev-

el shall be the highest average

spectral power measured within ±

600kHz of the carrier frequency.

External PA supply = 3.3V.

—

-37.1

-24.8

dBc/

100kHz

Absolute, at carrier ± 1.2 MHz.

Average spectral power shall be

measured using a 100kHz resolu-

tion bandwidth. External PA sup-

ply = 3.3V.

—

-24.2

-20

dBm/

100kHz

Note:

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-

ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.

2. Definition of reference signal is O-QPSK DSSS per 802.15.4, Frequency Range = 902-928 MHz, Data rate = 250 kbps, 16-chip

PN sequence mapping.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.2 Sub-GHz

RF Receiver Characteristics for 915 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz.

Table 4.21.

Sub-GHz RF Receiver Characteristics for 915 MHz Band

Parameter

Symbol

Test Condition

Min

902

—

Typ

—

Max

930

—

Unit

MHz

dBm

Tuning frequency range

RANGE

Max usable input level, 0.1%

SAT

500K

BER

Desired is reference 500 kbps

GFSK signal

Sensitivity

SENS

Desired is reference 4.8 kbps

—

-105.2

-126.2

-108.2

-100.7

—

dBm

OOK signal

, 20% PER, T ≤ 85 °C

Desired is reference 600 bps

GFSK signal

, 0.1% BER

Desired is reference 50 kbps

-104.2

GFSK signal

, 0.1% BER, T ≤ 85

°C

Desired is reference 100 kbps

GFSK signal

, 0.1% BER, T ≤ 85

°C

—

-105.1

-98.2

-101.5

-93.2

-91

dBm

Desired is reference 500 kbps

GFSK signal

, 0.1% BER, T ≤ 85

°C

Desired is reference 400 kbps

4GFSK signal

, 1% PER, T ≤ 85

°C

-95.2

Desired is reference O-QPSK

-100.1

—

DSSS signal

, 1% PER, Payload

length is 20 octets

Level above which

RFSENSE

TRIG

CW at 915 MHz

—

-28.1

-50

—

dBm

RFSENSE will trigger

Level below which

RFSENSE will not trigger

RFSENSE

THRES

CW at 915 MHz

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Desired is 4.8 kbps OOK signal

at 3dB above sensitivity level,

20% PER

Adjacent channel selectivity,

C/I

Interferer is CW at ± 1 ×

channel-spacing

—

48.1

—

Desired is 600 bps GFSK signal

at 3dB above sensitivity level,

0.1% BER

—

71.4

49.8

51.1

48.1

41.4

49.1

56.3

74.7

55.8

56.4

51.8

46.8

57.7

—

Desired is 50 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 100 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 500 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 400 kbps 4GFSK sig-

nal

at 3dB above sensitivity level,

0.1% BER

Desired is reference O-QPSK

DSSS signal

at 3dB above sensi-

tivity level, 1% PER

Desired is 4.8 kbps OOK signal

at 3dB above sensitivity level,

20% PER

Alternate channel selectivity,

C/I

Interferer is CW at ± 2 ×

channel-spacing

Desired is 600 bps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 50 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 100 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 500 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 400 kbps 4GFSK sig-

nal

at 3dB above sensitivity level,

0.1% BER

Desired is reference O-QPSK

DSSS signal

at 3dB above sensi-

tivity level, 1% PER

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Desired is 4.8 kbps OOK signal

at 3dB above sensitivity level,

20% PER

Image rejection, Interferer is

C/I

IMAGE

CW at image frequency

—

48.4

—

Desired is 50 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

—

54.9

49.1

47.9

42.8

48.9

—

Desired is 100 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 500 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 400 kbps 4GFSK sig-

nal

at 3dB above sensitivity level,

0.1% BER

Desired is reference O-QPSK

DSSS signal

at 3dB above sensi-

tivity level, 1% PER

Blocking selectivity, 0.1%

BER. Desired is 100 kbps

GFSK signal at 3dB above

sensitivity level

C/I

BLOCKER

Interferer CW at Desired ± 1 MHz

Interferer CW at Desired ± 2 MHz

—

58.7

62.5

76.4

—

Interferer CW at Desired ± 10

MHz

Desired is 100 kbps GFSK signal

at 3dB above sensitivity level

Intermod selectivity, 0.1%

BER. CW interferers at 400

kHz and 800 kHz offsets

C/I

—

Upper limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MAX

RSSI

MIN

RSSI

RES

dBm

Lower limit of input power

range over which RSSI reso-

lution is maintained

-98

—

RSSI resolution

Over RSSI

MIN

to RSSI

MAX

range

216-960 MHz

—

0.25

-55

—

dBm

Max spurious emissions dur-

SPUR

RX_FCC

ing active receive mode, per

FCC Part 15.109(a)

-49.2

-41.2

Above 960 MHz

-47

Max spurious emissions dur-

SPUR

RX_ARIB

ing active receive mode,per

ARIB STD-T108 Section 3.3

Below 710 MHz, RBW=100kHz

710-900 MHz, RBW=1MHz

900-915 MHz, RBW=100kHz

915-930 MHz, RBW=100kHz

930-1000 MHz, RBW=100kHz

Above 1000 MHz, RBW=1MHz

—

-60

-61

-53

-54

-55

-47

dBm

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 175 kHz, RX channel BW = 835.076 kHz, channel spacing = 1

MHz.

2. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.

3. Definition of reference signal is 600 bps 2GFSK, BT=0.5, Δf = 0.3 kHz, RX channel BW = 1.2 kHz, channel spacing = 300 kHz.

4. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.

5. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 400

kHz.

6. Definition of reference signal is 400 kbps 4GFSK, BT=0.5, inner deviation = 33.3 kHz, RX channel BW = 368.920 kHz, channel

spacing = 600 kHz.

7. Definition of reference signal is O-QPSK DSSS per 802.15.4, Frequency Range = 902-928 MHz, Data rate = 250 kbps, 16-chip

PN sequence mapping.

8. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.3 Sub-GHz

RF Transmitter characteristics for 868 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 868 MHz.

Table 4.22.

Sub-GHz RF Transmitter characteristics for 868 MHz Band

Parameter

Symbol

RANGE

Test Condition

Min

863

17.1

Typ

—

Max

876

Unit

MHz

dBm

RF tuning frequency range

Maximum TX Power

POUT

MAX

External PA supply = 3.3V, 20

dBm output power setting, T ≤ 85

°C

19.3

22.9

External PA supply connected to

DC-DC output, 14 dBm output

power setting

11.4

13.7

16.5

dBm

Minimum active TX Power

Output power step size

POUT

MIN

—

-43.5

0.5

—

dBm

POUT

STEP

POUT

VAR_V

output power > 0 dBm

Output power variation vs

supply at POUT

MAX

1.8 V < V

VREGVDD

< 3.3 V, Exter-

nal PA supply = 3.3 V, T = 25 °C

1.8 V < V

VREGVDD

< 3.3 V, Exter-

nal PA supply connected to DC-

DC output, T = 25 °C

—

Output power variation vs

temperature, peak to peak

POUT

VAR_T

-40 to +85 °C with External PA

supply = 3.3 V

—

0.6

0.5

0.9

1.2

-40 to +85 °C with External PA

supply connected to DC-DC out-

put

Output power variation vs RF

POUT

VAR_F

frequency

External PA supply = 3.3 V, T =

25 °C

—

0.2

-35

0.6

0.8

-30

External PA supply connected to

DC-DC output, T = 25 °C

Spurious emissions of har-

monics, Conducted meas-

urement, Test Frequency =

868 MHz

SPUR

HARM_ETSI

Per ETSI EN 300-220, Section

7.8.2.1, External PA supply con-

nected to: DCDC at 14 dBm, or

3.3 V at 19.5 dBm

dBm

Spurious emissions out-of-

band, Conducted measure-

ment, Test Frequency = 868

MHz

SPUR

OOB_ETSI

Per ETSI EN 300-220, Section

7.8.2.1 (47-74 MHz, 87.5-118

MHz, 174-230 MHz, and 470-862

MHz), External PA supply connec-

ted to: DCDC at 14 dBm, or 3.3 V

at 19.5 dBm

—

-59

-54

dBm

Per ETSI EN 300-220, Section

7.8.2.1 (other frequencies below 1

GHz), External PA supply connec-

ted to: DCDC at 14 dBm, or 3.3 V

at 19.5 dBm

—

-42

-36

-30

dBm

Per ETSI EN 300-220, Section

7.8.2.1 (frequencies above 1

GHz), External PA supply connec-

ted to: DCDC at 14 dBm, or 3.3 V

at 19.5 dBm

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Error vector magnitude (off-

EVM

set EVM), per 802.15.4-2015

Signal is DSSS-BPSK reference

packet. Modulated according to

802.15.4-2015 DSSS-BPSK in the

868MHz band, with pseudo-ran-

dom packet data content. External

PA supply connected to external

3.3V supply

—

5.7

—

%rms

Note:

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-

ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.4 Sub-GHz

RF Receiver Characteristics for 868 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 868 MHz.

Table 4.23.

Sub-GHz RF Receiver Characteristics for 868 MHz Band

Parameter

Symbol

Test Condition

Min

863

—

Typ

—

Max

876

—

Unit

MHz

dBm

Tuning frequency range

RANGE

Max usable input level, 0.1%

SAT

2k4

BER

Desired is reference 2.4 kbps

GFSK signal

Max usable input level, 0.1%

SAT

38k4

BER

Desired is reference 38.4 kbps

GFSK signal

—

dBm

Sensitivity

SENS

Desired is reference 2.4 kbps

GFSK signal

, 0.1% BER

-120.6

-109.5

Desired is reference 38.4 kbps

-105.4

GFSK signal

, 0.1% BER, T ≤ 85

°C

Desired is reference 500 kbps

GFSK signal

, 0.1% BER

—

-96.4

-110.6

-28.1

-50

—

dBm

Desired is reference BPSK sig-

nal

, 1% PER

Level above which

RFSENSE

TRIG

CW at 868 MHz

—

RFSENSE will trigger

Level below which

RFSENSE will not trigger

RFSENSE

THRES

CW at 868 MHz

—

Desired is 2.4 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Adjacent channel selectivity,

C/I

Interferer is CW at ± 1 ×

channel-spacing

44.5

56.9

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

35.4

—

Desired is 2.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Alternate channel selectivity,

C/I

Interferer is CW at ± 2 ×

channel-spacing

56.8

48.2

50.2

48.7

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

—

Desired is 2.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Image rejection, Interferer is

C/I

IMAGE

CW at image frequency

—

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

—

Blocking selectivity, 0.1%

BER. Desired is 2.4 kbps

GFSK signal

at 3 dB above

sensitivity level

C/I

BLOCKER

Interferer CW at Desired ± 1 MHz

Interferer CW at Desired ± 2 MHz

—

72.1

77.5

90.4

—

Interferer CW at Desired ± 10

MHz

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Upper limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MAX

—

dBm

Lower limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MIN

-98

—

dBm

RSSI resolution

RSSI

RES

Over RSSI

MIN

to RSSI

MAX

range

30 MHz to 1 GHz

—

0.25

-63

—

dBm

Max spurious emissions dur-

SPUR

ing active receive mode

-57

-47

1 GHz to 12 GHz

-53

Note:

1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.797 kHz, channel spacing = 12.5

kHz.

2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100

kHz.

3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.

4. Definition of reference signal is 20 kbps BPSK

5. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.5 Sub-GHz

RF Transmitter characteristics for 490 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 490 MHz.

Table 4.24.

Sub-GHz RF Transmitter characteristics for 490 MHz Band

Parameter

Symbol

RANGE

Test Condition

Min

470

18.1

Typ

—

Max

510

Unit

MHz

dBm

RF tuning frequency range

Maximum TX Power

POUT

MAX

External PA supply = 3.3V

20.3

23.7

Minimum active TX Power

Output power step size

POUT

MIN

-44.9

0.5

—

dBm

POUT

STEP

POUT

VAR_V

output power > 0 dBm

—

Output power variation vs

supply, peak to peak

at 20 dBm;1.8 V < V

VREGVDD

4.3

3.3 V, External PA supply connec-

ted directly to external supply, T =

25 °C

Output power variation vs

temperature, peak to peak

POUT

VAR_T

-40 to +85 °C at 20 dBm

—

0.2

-40

0.9

0.4

-36

Output power variation vs RF

POUT

VAR_F

frequency

T = 25 °C

Harmonic emissions, 20

dBm output power setting,

490 MHz

SPUR

HARM_CN

Per China SRW Requirement,

Section 2.1, frequencies below

1GHz

dBm

Per China SRW Requirement,

Section 2.1, frequencies above

1GHz

—

-36

-54

-30

—

dBm

Spurious emissions, 20 dBm

SPUR

OOB_CN

Per China SRW Requirement,

Section 3 (48.5-72.5MHz,

output power setting, 490

MHz

76-108MHz, 167-223MHz,

470-556MHz, and 606-798MHz)

Per China SRW Requirement,

Section 2.1 (other frequencies be-

low 1GHz)

—

-42

-36

—

dBm

Per China SRW Requirement,

Section 2.1 (frequencies above

1GHz)

Note:

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-

ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.6 Sub-GHz

RF Receiver Characteristics for 490 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 490 MHz.

Table 4.25.

Sub-GHz RF Receiver Characteristics for 490 MHz Band

Parameter

Symbol

Test Condition

Min

470

—

Typ

—

Max

510

—

Unit

MHz

dBm

Tuning frequency range

RANGE

Max usable input level, 0.1%

SAT

2k4

BER

Desired is reference 2.4 kbps

GFSK signal

Max usable input level, 0.1%

SAT

38k4

BER

Desired is reference 38.4 kbps

GFSK signal

—

dBm

Sensitivity

SENS

Desired is reference 2.4 kbps

GFSK signal

, 0.1% BER

-122.2

-111.4

Desired is reference 38.4 kbps

-108.9

GFSK signal

, 0.1% BER, T ≤ 85

°C

Desired is reference 10 kbps

GFSK signal

, 0.1% BER, T ≤ 85

°C

—

-116.8

-107.3

-113.9

-104.7

dBm

Desired is reference 100 kbps

GFSK signal

, 0.1% BER, T ≤ 85

°C

Level above which

RFSENSE

TRIG

Desired is reference 100 kbps

GFSK signal

, 0.1% BER

—

-28.1

-50

—

dBm

RFSENSE will trigger

Level below which

RFSENSE will not trigger

RFSENSE

THRES

CW at 490 MHz

Desired is 2.4 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Adjacent channel selectivity,

C/I

Interferer is CW at ± 1 ×

channel-spacing

60.3

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

38.3

—

45.6

60.4

52.6

56.5

54.1

—

Desired is 2.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Alternate channel selectivity,

C/I

Interferer is CW at ± 2 ×

channel-spacing

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

—

Desired is 2.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Image rejection, Interferer is

C/I

IMAGE

CW at image frequency

—

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

—

Blocking selectivity, 0.1%

BER. Desired is 2.4 kbps

GFSK signal

at 3 dB above

sensitivity level

C/I

BLOCKER

Interferer CW at Desired ± 1 MHz

Interferer CW at Desired ± 2 MHz

—

73.9

75.4

90.2

—

Interferer CW at Desired ± 10

MHz

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Upper limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MAX

—

dBm

Lower limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MIN

-98

—

dBm

RSSI resolution

RSSI

RES

Over RSSI

MIN

to RSSI

MAX

range

30 MHz to 1 GHz

—

0.25

-53

—

dBm

Max spurious emissions dur-

SPUR

ing active receive mode

-47

1 GHz to 12 GHz

-53

Note:

1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5

kHz.

2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100

kHz.

3. Definition of reference signal is 10 kbps 2GFSK, BT=0.5, Δf = 5 kHz, RX channel BW = 20.038 kHz.

4. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz.

5. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.7 Sub-GHz

RF Transmitter characteristics for 433 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 433 MHz.

Table 4.26.

Sub-GHz RF Transmitter characteristics for 433 MHz Band

Parameter

Symbol

RANGE

Test Condition

Min

426

12.5

Typ

—

Max

445

Unit

MHz

dBm

RF tuning frequency range

Maximum TX Power

POUT

MAX

External PA supply connected to

DC-DC output, 14dBm output

power

15.1

17.4

External PA supply connected to

DC-DC output, 10dBm output

power

8.3

10.6

13.3

dBm

Minimum active TX Power

Output power step size

POUT

MIN

—

-42

0.5

1.7

—

dBm

POUT

STEP

POUT

VAR_V

output power > 0 dBm

Output power variation vs

supply, peak to peak, Pout =

10dBm

At 10 dBm;1.8 V < V

VREGVDD

3.3 V, External PA supply = DC-

DC output, T = 25 °C

Output power variation vs

temperature, peak to peak,

Pout= 10dBm

POUT

VAR_T

-40 to +85C at 10dBm

—

0.5

1.2

Output power variation vs RF

POUT

VAR_F

frequency, Pout = 10dBm

T = 25 °C

—

0.1

-47

-26

0.2

-42

-20

Spurious emissions of har-

monics FCC, Conducted

measurement, 14dBm

SPUR

HARM_FCC

In restricted bands, per FCC Part

15.205 / 15.209

dBm

dBc

In non-restricted bands, per FCC

Part 15.231

match, External PA supply

connected to DC-DC output,

Test Frequency = 434 MHz

Spurious emissions out-of-

band FCC, Conducted

measurement, 14dBm

match, External PA supply

connected to DC-DC output,

Test Frequency = 434 MHz

SPUR

OOB_FCC

In non-restricted bands, per FCC

Part 15.231

—

-26

-52

-61

-58

-20

-46

-56

-52

dBc

dBm

In restricted bands (30-88 MHz),

per FCC Part 15.205 / 15.209

In restricted bands (88-216 MHz),

per FCC Part 15.205 / 15.209

In restricted bands (216-960

MHz), per FCC Part 15.205 /

15.209

In restricted bands (>960 MHz),

per FCC Part 15.205 / 15.209

—

-47

-42

-36

-42

-36

-30

dBm

Spurious emissions of har-

monics ETSI, Conducted

measurement, 14dBm

match, External PA supply

connected to DC-DC output,

Test Frequency = 434 MHz

SPUR

HARM_ETSI

Per ETSI EN 300-220, Section

7.8.2.1 (frequencies below 1Ghz)

Per ETSI EN 300-220, Section

7.8.2.1 (frequencies above 1Ghz)

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Spurious emissions out-of-

band ETSI, Conducted

measurement, 14dBm

match, External PA supply

connected to DC-DC output,

Test Frequency = 434 MHz

SPUR

OOB_ETSI

Per ETSI EN 300-220, Section

7.8.2.1 (47-74 MHz, 87.5-118

MHz, 174-230 MHz, and 470-862

MHz)

—

-60

-54

dBm

Per ETSI EN 300-220, Section

7.8.2.1 (other frequencies below 1

GHz)

—

-42

-36

-30

dBm

Per ETSI EN 300-220, Section

7.8.2.1 (frequencies above 1

GHz)

Note:

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-

ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.8 Sub-GHz

RF Receiver Characteristics for 433 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 433 MHz.

Table 4.27.

Sub-GHz RF Receiver Characteristics for 433 MHz Band

Parameter

Symbol

Test Condition

Min

426

—

Typ

—

Max

445

—

Unit

MHz

dBm

Tuning frequency range

RANGE

Max usable input level, 0.1%

SAT

2k4

BER

Desired is reference 2.4 kbps

GFSK signal

Max usable input level, 0.1%

SAT

50k

BER

Desired is reference 50 kbps

GFSK signal

—

dBm

Sensitivity

SENS

Desired is reference 4.8 kbps

OOK signal

, 20% PER

-107.4

-107.3

Desired is reference 100 kbps

-105

GFSK signal

, 0.1% BER, T ≤ 85

°C

Desired is reference 50 kbps

—

-110.3

-107.2

dBm

GFSK signal

, 0.1% BER, T ≤ 85

°C

Desired is reference 2.4 kbps

GFSK signal

, 0.1% BER

—

-123.1

-112.6

-28.1

-50

—

-109

—

dBm

Desired is reference 9.6 kbps

GFSK signal

, 1% PER, T ≤ 85 °C

Level above which

RFSENSE

TRIG

CW at 433 MHz

RFSENSE will trigger

Level below which

RFSENSE will not trigger

RFSENSE

THRES

CW at 433 MHz

—

Desired is 4.8 kbps OOK signal

at 3dB above sensitivity level,

20% PER

Adjacent channel selectivity,

C/I

Interferer is CW at ± 1 ×

channel-spacing

51.6

—

Desired is 100 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

44.1

61.5

53.1

35.7

—

Desired is 2.4 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 50 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

45.6

—

Desired is 9.6 kbps 4GFSK sig-

nal

at 3dB above sensitivity level,

1% PER

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Desired is 4.8 kbps OOK signal

at 3dB above sensitivity level,

20% PER

Alternate channel selectivity,

C/I

Interferer is CW at ± 2 ×

channel-spacing

—

57.8

—

Desired is 100 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

—

54.6

62.4

58.1

50.6

46.5

51.7

57.5

54.4

—

Desired is 2.4 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 50 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 9.6 kbps 4GFSK sig-

nal

at 3dB above sensitivity level,

1% PER

Desired is 4.8 kbps OOK signal

at 3dB above sensitivity level,

20% PER

Image rejection, Interferer is

C/I

IMAGE

CW at image frequency

Desired is 100 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 2.4 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 50 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Desired is 9.6 kbps 4GFSK sig-

nal

at 3dB above sensitivity level,

1% PER

Blocking selectivity, 0.1%

BER. Desired is 2.4 kbps

GFSK signal

at 3dB above

sensitivity level

C/I

BLOCKER

Interferer CW at Desired ± 1 MHz

Interferer CW at Desired ± 2 MHz

—

75.7

77.2

—

Interferer CW at Desired ± 10

MHz

Desired is 2.4 kbps GFSK signal

at 3dB above sensitivity level

Intermod selectivity, 0.1%

BER. CW interferers at 12.5

kHz and 25 kHz offsets

C/I

—

58.8

—

Upper limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MAX

RSSI

MIN

RSSI

RES

dBm

Lower limit of input power

range over which RSSI reso-

lution is maintained

-98

—

RSSI resolution

Over RSSI

MIN

to RSSI

MAX

range

216-960 MHz

—

0.25

-55

—

dBm

Max spurious emissions dur-

SPUR

RX_FCC

ing active receive mode, per

FCC Part 15.109(a)

-49

-41

Above 960 MHz

-47

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Below 1000 MHz

Above 1000 MHz

Min

—

Typ

-63

-53

Max

-57

Unit

dBm

Max spurious emissions dur-

SPUR

RX_ETSI

ing active receive mode, per

ETSI 300-220 Section 8.6

—

-47

Max spurious emissions dur-

SPUR

RX_ARIB

ing active receive mode, per

ARIB STD T67 Section

Below 710 MHz, RBW=100kHz

—

-60

-54

dBm

3.3(5)

Note:

1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5

kHz.

2. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.

3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.

4. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 200

kHz.

5. Definition of reference signal is 9.6 kbps 4GFSK, BT=0.5, inner deviation = 0.8 kHz, RX channel BW = 8.5 kHz, channel spacing

= 12.5 kHz.

6. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.9 Sub-GHz

RF Transmitter characteristics for 315 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 315 MHz.

Table 4.28.

Sub-GHz RF Transmitter characteristics for 315 MHz Band

Parameter

Symbol

RANGE

Test Condition

Min

195

13.8

Typ

—

Max

358

Unit

MHz

dBm

RF tuning frequency range

Maximum TX Power

POUT

MAX

External PA supply connected to

DC-DC output, T ≤ 85 °C

17.2

21.1

Minimum active TX Power

Output power step size

POUT

MIN

-43.9

0.5

—

dBm

POUT

STEP

POUT

VAR_V

output power > 0 dBm

—

Output power variation vs

supply

1.8 V < V

VREGVDD

< 3.3 V, Exter-

nal PA supply = DC-DC output, T

= 25 °C

1.8

Output power variation vs

temperature

POUT

VAR_T

-40 to +85C

—

0.5

0.1

-47

-26

1.2

0.7

-42

-20

Output power variation vs RF

POUT

VAR_F

frequency

T = 25 °C

Spurious emissions of har-

monics at 14 dBm output

power, Conducted measure-

ment, 14dBm match, Exter-

nal PA supply connected to

DC-DC output, Test Fre-

quency = 303 MHz

SPUR

HARM_FCC

In restricted bands, per FCC Part

15.205 / 15.209

dBm

dBc

In non-restricted bands, per FCC

Part 15.231

Spurious emissions out-of-

band at 14 dBm output pow-

er, Conducted measurement,

14dBm match, External PA

supply connected to DC-DC

output, Test Frequency =

303 MHz

SPUR

OOB_FCC

In non-restricted bands, per FCC

Part 15.231

—

-26

-52

-61

-58

-20

-46

-56

-52

dBc

dBm

In restricted bands (30-88 MHz),

per FCC Part 15.205 / 15.209

In restricted bands (88-216 MHz),

per FCC Part 15.205 / 15.209

In restricted bands (216-960

MHz), per FCC Part 15.205 /

15.209

In restricted bands (>960 MHz),

per FCC Part 15.205 / 15.209

—

-47

-42

dBm

Note:

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-

ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.10 Sub-GHz

RF Receiver Characteristics for 315 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 315 MHz.

Table 4.29.

Sub-GHz RF Receiver Characteristics for 315 MHz Band

Parameter

Symbol

Test Condition

Min

195

—

Typ

—

Max

358

—

Unit

MHz

dBm

Tuning frequency range

RANGE

Max usable input level, 0.1%

SAT

2k4

BER

Desired is reference 2.4 kbps

GFSK signal

Max usable input level, 0.1%

SAT

38k4

BER

Desired is reference 38.4 kbps

GFSK signal

—

dBm

Sensitivity

SENS

Desired is reference 2.4 kbps

-123.2

-120.7

GFSK signal

, 0.1% BER, T ≤ 85

°C

Desired is reference 38.4 kbps

GFSK signal

, 0.1% BER, T ≤ 85

°C

—

-111.4

-98.8

-108.6

-95.5

dBm

Desired is reference 500 kbps

GFSK signal

, 0.1% BER, T ≤ 85

°C

Level above which

RFSENSE

TRIG

CW at 315 MHz

—

-28.1

-50

—

dBm

RFSENSE will trigger

Level below which

RFSENSE will not trigger

RFSENSE

THRES

CW at 315 MHz

Desired is 2.4 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Adjacent channel selectivity,

C/I

Interferer is CW at ± 1 ×

channel-spacing

54.1

63.6

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

—

49.9

64.2

56.2

—

Desired is 2.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Alternate channel selectivity,

C/I

Interferer is CW at ± 2 ×

channel-spacing

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level

0.1% BER

Desired is 2.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Image rejection, Interferer is

C/I

IMAGE

CW at image frequency

—

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

51.4

Blocking selectivity, 0.1%

BER. Desired is 2.4 kbps

GFSK signal

at 3 dB above

sensitivity level

C/I

BLOCKER

Interferer CW at Desired ± 1 MHz

Interferer CW at Desired ± 2 MHz

—

76.5

91.9

Interferer CW at Desired ± 10

MHz

72.6

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Upper limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MAX

—

dBm

Lower limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MIN

-98

—

dBm

RSSI resolution

RSSI

RES

Over RSSI

MIN

to RSSI

MAX

range

216-960 MHz

—

0.25

-63

—

dBm

Max spurious emissions dur-

SPUR

RX_FCC

ing active receive mode, per

FCC Part 15.109(a)

-57

-47

Above 960MHz

-53

Note:

1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5

kHz.

2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100

kHz.

3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.

4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.11 Sub-GHz

RF Transmitter Characteristics for 169 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 169 MHz.

Table 4.30.

Sub-GHz RF Transmitter Characteristics for 169 MHz Band

Parameter

Symbol

RANGE

Test Condition

Min

169

18.1

Typ

—

Max

170

Unit

MHz

dBm

RF tuning frequency range

Maximum TX Power

POUT

MAX

External PA supply = 3.3 V

19.7

22.4

Minimum active TX Power

Output power step size

POUT

MIN

-42.6

0.5

—

dBm

POUT

STEP

POUT

VAR_V

output power > 0 dBm

—

Output power variation vs

supply, peak to peak

1.8 V < V

VREGVDD

< 3.3 V, Exter-

nal PA supply = 3.3 V, T = 25 °C

4.8

5.0

Output power variation vs

temperature, peak to peak

POUT

VAR_T

-40 to +85 °C at 20 dBm

—

0.6

-42

1.2

—

Spurious emissions of har-

monics, Conducted meas-

urement, External PA supply

= 3.3 V, Test Frequency =

169 MHz

SPUR

HARM_ETSI

Per ETSI EN 300-220, Section

7.8.2.1 (47-74 MHz, 87.5-118

MHz, 174-230 MHz, and 470-862

MHz)

dBm

Per ETSI EN 300-220, Section

7.8.2.1 (other frequencies below 1

GHz)

—

-38

-36

-42

—

dBm

Per ETSI EN 300-220, Section

7.8.2.1 (frequencies above 1

GHz)

Spurious emissions out-of-

band, Conducted measure-

ment, External PA supply =

3.3 V, Test Frequency = 169

MHz

SPUR

OOB_ETSI

Per ETSI EN 300-220, Section

7.8.2.1 (47-74 MHz, 87.5-118

MHz, 174-230 MHz, and 470-862

MHz)

-36

Per ETSI EN 300-220, Section

7.8.2.1 (other frequencies below 1

GHz)

—

-42

-36

-30

dBm

Per ETSI EN 300-220, Section

7.8.2.1 (frequencies above 1

GHz)

Note:

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-

ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.

2. Typical value marginally passes specification. Additional margin can be obtained by increasing the order of the harmonic filter.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.10.12 Sub-GHz

RF Receiver Characteristics for 169 MHz Band

Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA

Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 169 MHz.

Table 4.31.

Sub-GHz RF Receiver Characteristics for 169 MHz Band

Parameter

Symbol

Test Condition

Min

169

—

Typ

—

Max

170

—

Unit

MHz

dBm

Tuning frequency range

RANGE

Max usable input level, 0.1%

SAT

2k4

BER

Desired is reference 2.4 kbps

GFSK signal

Max usable input level, 0.1%

SAT

38k4

BER

Desired is reference 38.4 kbps

GFSK signal

—

dBm

Sensitivity

SENS

Desired is reference 2.4 kbps

GFSK signal

, 0.1% BER

-124

Desired is reference 38.4 kbps

-112.2

-108

GFSK signal

, 0.1% BER, T ≤ 85

°C

Desired is reference 500 kbps

—

-99.2

-96

dBm

GFSK signal

, 0.1% BER, T ≤ 85

°C

Level above which

RFSENSE

TRIG

CW at 169 MHz

—

-28.1

-50

—

dBm

RFSENSE will trigger

Level below which

RFSENSE will not trigger

RFSENSE

THRES

CW at 169 MHz

Desired is 2.4 kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Adjacent channel selectivity,

C/I

Interferer is CW at ± 1 x

channel-spacing

64.8

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

43.3

—

51.4

67.4

60.6

47.1

—

Desired is 2.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Alternate channel selectivity,

C/I

Interferer is CW at ± 2 x

channel-spacing

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

—

Desired is 2.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

Image rejection, Interferer is

C/I

IMAGE

CW at image frequency

—

Desired is 38.4kbps GFSK signal

at 3dB above sensitivity level,

0.1% BER

—

Blocking selectivity, 0.1%

BER. Desired is 2.4 kbps

GFSK signal

at 3 dB above

sensitivity level

C/I

BLOCKER

Interferer CW at Desired ± 1 MHz

Interferer CW at Desired ± 2 MHz

—

73.4

—

Interferer CW at Desired ± 10

MHz

90.1

Upper limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MAX

—

dBm

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Lower limit of input power

range over which RSSI reso-

lution is maintained

RSSI

MIN

-98

—

dBm

RSSI resolution

RSSI

RES

Over RSSI

MIN

to RSSI

MAX

range

30 MHz to 1 GHz

—

0.25

-63

—

dBm

Max spurious emissions dur-

SPUR

ing active receive mode

-57

-47

1 GHz to 12 GHz

-53

Note:

1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5

kHz.

2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100

kHz.

3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.

4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.

4.1.11 Modem

Table 4.32.

Modem

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Receive bandwidth

Configurable range with 38.4 MHz

crystal

0.1

—

2530

kHz

IF frequency

Configurable range with 38.4 MHz

crystal. Selected steps available.

150

—

1371

kHz

DSSS symbol length

DSSS bits per symbol

DSSS

Configurable in steps of 1 chip

Configurable

—

chips

BPS

DSSS

bits/

symbol

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.12 Oscillators

4.1.12.1 Low-Frequency

Crystal Oscillator (LFXO)

Table 4.33.

Low-Frequency Crystal Oscillator (LFXO)

Parameter

Symbol

Test Condition

Min

—

Typ

32.768

—

Max

—

Unit

kHz

kΩ

Crystal frequency

LFXO

Supported crystal equivalent

ESR

LFXO

series resistance (ESR)

—

Supported range of crystal

load capacitance

LFXO_CL

—

On-chip tuning cap range

LFXO_T

On each of LFXTAL_N and

LFXTAL_P pins

On-chip tuning cap step size

LFXO

—

0.25

273

—

Current consumption after

startup

LFXO

ESR = 70 kOhm, C

= 7 pF,

GAIN

= 2, AGC

= 1

Start- up time

LFXO

ESR = 70 kOhm, C

= 7 pF,

GAIN

= 2

—

308

—

Note:

1. Total load capacitance as seen by the crystal.

2. The effective load capacitance seen by the crystal will be C

LFXO_T

/2. This is because each XTAL pin has a tuning cap and the

two caps will be seen in series by the crystal.

3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.

4. In CMU_LFXOCTRL register.

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Electrical Specifications

4.1.12.2 High-Frequency

Crystal Oscillator (HFXO)

Table 4.34.

High-Frequency Crystal Oscillator (HFXO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Crystal frequency

HFXO

38.4 MHz required for radio trans-

ciever operation

38.4

MHz

Supported crystal equivalent

ESR

HFXO_38M4

Crystal frequency 38.4 MHz

series resistance (ESR)

—

Ω

Supported range of crystal

load capacitance

HFXO_CL

On-chip tuning cap range

HFXO_T

HFXO

On each of HFXTAL_N and

HFXTAL_P pins

0.04

300

—

On-chip tuning capacitance

step

—

Startup time

38.4 MHz, ESR = 50 Ohm, C

10 pF

—

µs

Frequency tolerance for the

HFXO

crystal

38.4 MHz, ESR = 50 Ohm, C

10 pF

-40

ppm

Note:

1. Total load capacitance as seen by the crystal.

2. The effective load capacitance seen by the crystal will be C

HFXO_T

/2. This is because each XTAL pin has a tuning cap and the

two caps will be seen in series by the crystal.

4.1.12.3 Low-Frequency

RC Oscillator (LFRCO)

Table 4.35.

Low-Frequency RC Oscillator (LFRCO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

ENVREF

= 1, T ≤ 85 °C

ENVREF

= 1, T > 85 °C

ENVREF

= 0, T ≤ 85 °C

ENVREF

= 0, T > 85 °C

Oscillation frequency

LFRCO

31.3

32.768

33.6

kHz

31.6

31.3

30.0

—

32.768

500

36.8

33.4

—

kHz

µs

Startup time

LFRCO

Current consumption

ENVREF = 1 in

CMU_LFRCOCTRL

—

370

—

ENVREF = 0 in

—

520

—

CMU_LFRCOCTRL

Note:

1. In CMU_LFRCOCTRL register.

2. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.12.4 High-Frequency

RC Oscillator (HFRCO)

Table 4.36.

High-Frequency RC Oscillator (HFRCO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Frequency accuracy

HFRCO_ACC

At production calibrated frequen-

cies, across supply voltage and

temperature

-2.5

—

2.5

Start-up time

HFRCO

≥ 19 MHz

4 < f

HFRCO

< 19 MHz

HFRCO

≤ 4 MHz

HFRCO

= 38 MHz

HFRCO

= 32 MHz

HFRCO

= 26 MHz

HFRCO

= 19 MHz

HFRCO

= 16 MHz

HFRCO

= 13 MHz

HFRCO

= 7 MHz

HFRCO

= 4 MHz

HFRCO

= 2 MHz

HFRCO

= 1 MHz

—

300

—

µs

2.5

244

204

173

143

123

110

—

µs

Current consumption on all

supplies

HFRCO

265

222

188

156

136

124

µA

Coarse trim step size (% of

period)

HFRCO_COARS

0.8

—

Fine trim step size (% of pe-

HFRCO_FINE

riod)

—

0.1

0.2

—

Period jitter

HFRCO

% RMS

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.12.5 Auxiliary

High-Frequency RC Oscillator (AUXHFRCO)

Table 4.37.

Auxiliary High-Frequency RC Oscillator (AUXHFRCO)

Parameter

Symbol

Test Condition

Min

-3

Typ

Max

Unit

Frequency accuracy

AUXHFRCO_ACC

At production calibrated frequen-

—

cies, across supply voltage and

temperature

Start-up time

AUXHFRCO

≥ 19 MHz

4 < f

AUXHFRCO

< 19 MHz

AUXHFRCO

≤ 4 MHz

AUXHFRCO

= 38 MHz

AUXHFRCO

= 32 MHz

AUXHFRCO

= 26 MHz

AUXHFRCO

= 19 MHz

AUXHFRCO

= 16 MHz

AUXHFRCO

= 13 MHz

AUXHFRCO

= 7 MHz

AUXHFRCO

= 4 MHz

AUXHFRCO

= 2 MHz

AUXHFRCO

= 1 MHz

—

400

1.4

2.5

193

157

135

108

100

—

µs

—

µs

Current consumption on all

supplies

AUXHFRCO

213

175

151

122

113

µA

Coarse trim step size (% of

period)

AUXHFR-

0.8

—

CO_COARSE

Fine trim step size (% of pe-

AUXHFR-

—

0.1

0.2

—

riod)

CO_FINE

Period jitter

AUXHFRCO

% RMS

4.1.12.6 Ultra-low

Frequency RC Oscillator (ULFRCO)

Table 4.38.

Ultra-low Frequency RC Oscillator (ULFRCO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Oscillation frequency

ULFRCO

0.95

1.07

kHz

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.13 Flash

Memory Characteristics

Table 4.39.

Flash Memory Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Flash erase cycles before

failure

FLASH

10000

—

cycles

Flash data retention

RET

FLASH

T ≤ 85 °C

—

years

µs

T ≤ 125 °C

Word (32-bit) programming

time

W_PROG

Burst write, 128 words, average

time per word

24.4

Single word

68.4

26.4

µs

Page erase time

Mass erase time

Device erase time

4 5

PERASE

MERASE

DERASE

26.5

T ≤ 85 °C

—

100

110

1.6

T ≤ 125 °C

Page Erase

Erase current

Write current

ERASE

WRITE

FLASH

—

3.8

3.6

Supply voltage during flash

erase and write

1.62

Note:

1. Flash data retention information is published in the Quarterly Quality and Reliability Report.

2. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup

and hold times for flash control signals are included.

3. Mass erase is issued by the CPU and erases all flash.

4. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock

Word (ULW).

5. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup

and hold times for flash control signals are included.

6. Measured at 25 °C.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.14 General-Purpose

I/O (GPIO)

Table 4.40.

General-Purpose I/O (GPIO)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Input low voltage

Input high voltage

GPIO pins

—

IOVDD*0.3

GPIO pins

IOVDD*0.7

IOVDD*0.8

—

Output high voltage relative

to IOVDD

Sourcing 3 mA, IOVDD ≥ 3 V,

DRIVESTRENGTH

= WEAK

Sourcing 1.2 mA, IOVDD ≥ 1.62

IOVDD*0.6

—

DRIVESTRENGTH

= WEAK

Sourcing 20 mA, IOVDD ≥ 3 V,

IOVDD*0.8

—

DRIVESTRENGTH

= STRONG

Sourcing 8 mA, IOVDD ≥ 1.62 V,

IOVDD*0.6

—

DRIVESTRENGTH

= STRONG

Sinking 3 mA, IOVDD ≥ 3 V,

Output low voltage relative to

IOVDD

—

IOVDD*0.2

IOVDD*0.4

IOVDD*0.2

IOVDD*0.4

DRIVESTRENGTH

= WEAK

Sinking 1.2 mA, IOVDD ≥ 1.62 V,

DRIVESTRENGTH

= WEAK

Sinking 20 mA, IOVDD ≥ 3 V,

DRIVESTRENGTH

= STRONG

Sinking 8 mA, IOVDD ≥ 1.62 V,

DRIVESTRENGTH

= STRONG

Input leakage current

IOLEAK

All GPIO except LFXO pins, GPIO

≤ IOVDD, T ≤ 85 °C

—

0.1

—

µA

kΩ

LFXO Pins, GPIO ≤ IOVDD, T ≤

85 °C

All GPIO except LFXO pins, GPIO

≤ IOVDD, T > 85 °C

110

250

LFXO Pins, GPIO ≤ IOVDD, T >

85 °C

—

Input leakage current on

5VTOL pads above IOVDD

5VTOLLEAK

IOVDD < GPIO ≤ IOVDD + 2 V

3.3

I/O pin pull-up/pull-down re-

PUD

sistor

Pulse width of pulses re-

moved by the glitch suppres-

sion filter

IOGLITCH

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output fall time, From 70%

to 30% of V

IOOF

= 50 pF,

—

1.8

—

DRIVESTRENGTH

= STRONG,

SLEWRATE

= 0x6

= 50 pF,

—

4.5

2.2

7.4

—

DRIVESTRENGTH

= WEAK,

SLEWRATE

= 0x6

= 50 pF,

Output rise time, From 30%

IOOR

to 70% of V

DRIVESTRENGTH

= STRONG,

SLEWRATE = 0x6

= 50 pF,

DRIVESTRENGTH

= WEAK,

SLEWRATE

= 0x6

Note:

1. GPIO input threshold are proportional to the IOVDD supply, except for RESETn which is proportional to AVDD.

2. In GPIO_Pn_CTRL register.

3. GPIO pull-ups are referenced to the IOVDD supply, except for RESETn, which connects to AVDD.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.15 Voltage

Monitor (VMON)

Table 4.41.

Voltage Monitor (VMON)

Parameter

Symbol

VMON

Test Condition

Min

Typ

Max

Unit

Supply current (including

I_SENSE)

In EM0 or EM1, 1 active channel,

T ≤ 85 °C

—

6.3

µA

In EM0 or EM1, 1 active channel,

T > 85 °C

—

12.5

—

µA

In EM0 or EM1, All channels ac-

tive, T ≤ 85 °C

In EM0 or EM1, All channels ac-

tive, T > 85 °C

In EM2, EM3 or EM4, 1 channel

active and above threshold

In EM2, EM3 or EM4, 1 channel

active and below threshold

In EM2, EM3 or EM4, All channels

active and above threshold

In EM2, EM3 or EM4, All channels

active and below threshold

Loading of monitored supply

SENSE

In EM0 or EM1

—

3.4

—

µA

In EM2, EM3 or EM4

Threshold range

VMON_RANGE

1.62

—

Threshold step size

VMON_STESP

Coarse

200

460

Fine

—

Response time

Hysteresis

VMON_RES

Supply drops at 1V/µs rate

—

VMON_HYST

—

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.16 Analog

to Digital Converter (ADC)

Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated.

Table 4.42.

Analog to Digital Converter (ADC)

Parameter

Symbol

Test Condition

Min

Typ

—

Max

Unit

Bits

Resolution

RESOLUTION

ADCIN

—

Input voltage range

Single ended

Differential

—

-V

—

AVDD

Input range of external refer-

ADCREFIN_P

ence voltage, single ended

and differential

—

Power supply rejection

PSRR

ADC

At DC

—

Analog input common mode

CMRR

ADC

rejection ratio

Current from all supplies, us-

ADC_CONTINU-

1 Msps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1

—

270

125

315

—

µA

ing internal reference buffer.

OUS_LP

Continuous operation. WAR-

MUPMODE

= KEEPADC-

WARM

250 ksps / 4 MHz ADCCLK, BIA-

SPROG = 6, GPBIASACC = 1

62.5 ksps / 1 MHz ADCCLK, BIA-

SPROG = 15, GPBIASACC = 1

Current from all supplies, us-

ADC_NORMAL_LP

35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1

ing internal reference buffer.

Duty-cycled operation. WAR-

MUPMODE

= NORMAL

5 ksps / 16 MHz ADCCLK BIA-

SPROG = 0, GPBIASACC = 1

Current from all supplies, us-

ADC_STAND-

125 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1

105

ing internal reference buffer.

BY_LP

Duty-cycled operation.

35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 1

AWARMUPMODE

= KEEP-

INSTANDBY or KEEPIN-

SLOWACC

Current from all supplies, us-

ADC_CONTINU-

1 Msps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0

—

325

175

125

—

µA

ing internal reference buffer.

OUS_HP

Continuous operation. WAR-

MUPMODE

= KEEPADC-

WARM

250 ksps / 4 MHz ADCCLK, BIA-

SPROG = 6, GPBIASACC = 0

62.5 ksps / 1 MHz ADCCLK, BIA-

SPROG = 15, GPBIASACC = 0

Current from all supplies, us-

ADC_NORMAL_HP

35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0

ing internal reference buffer.

Duty-cycled operation. WAR-

MUPMODE

= NORMAL

5 ksps / 16 MHz ADCCLK BIA-

SPROG = 0, GPBIASACC = 0

Current from all supplies, us-

ADC_STAND-

125 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0

160

125

ing internal reference buffer.

BY_HP

Duty-cycled operation.

35 ksps / 16 MHz ADCCLK, BIA-

SPROG = 0, GPBIASACC = 0

AWARMUPMODE

= KEEP-

INSTANDBY or KEEPIN-

SLOWACC

Current from HFPERCLK

ADC_CLK

HFPERCLK = 16 MHz

—

160

—

µA

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

ADCCLK

Test Condition

Min

—

Typ

—

Max

Unit

MHz

ADC clock frequency

Throughput rate

ADCRATE

ADCCONV

—

Msps

cycles

µs

Conversion time

6 bit

8 bit

12 bit

—

WARMUPMODE

= NORMAL

Startup time of reference

generator and ADC core

ADCSTART

—

WARMUPMODE

= KEEPIN-

STANDBY

—

µs

WARMUPMODE

= KEEPINSLO-

WACC

Internal reference

, differential

measurement

SNDR at 1Msps and f

10kHz

SNDR

ADC

—

External reference

, differential

measurement

Spurious-free dynamic range

SFDR

ADC

(SFDR)

1 MSamples/s, 10 kHz full-scale

sine wave

—

-1

-6

—

Differential non-linearity

(DNL)

DNL

ADC

12 bit resolution, No missing co-

des

LSB

Integral non-linearity (INL),

End point method

INL

ADC

12 bit resolution

Offset error

ADCOFFSETERR

ADCGAIN

-3

—

LSB

Gain error in ADC

Using internal reference

Using external reference

-0.2

-1

3.5

—

Temperature sensor slope

TS_SLOPE

-1.84

mV/°C

Note:

1. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than

the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on

EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin.

2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.

3. In ADCn_CTRL register.

4. In ADCn_BIASPROG register.

5. Derived from ADCCLK.

6. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The

differential input range with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum

value is production-tested using sine wave input at 1.5 dB lower than full scale.

7. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or

SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential

input range with this configuration is ± 1.25 V.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.17 Analog

Comparator (ACMP)

Table 4.43.

Analog Comparator (ACMP)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Input voltage range

ACMPIN

ACMPVDD =

ACMPn_CTRL_PWRSEL

—

ACMPVDD

BIASPROG

≤ 0x10 or FULL-

BIAS

= 0

Supply voltage

ACMPVDD

1.8

2.1

—

VREGVDD_

MAX

0x10 < BIASPROG

≤ 0x20 and

FULLBIAS

= 1

VREGVDD_

MAX

BIASPROG

= 1, FULLBIAS

= 0

Active current not including

voltage reference

ACMP

—

BIASPROG

= 0x10, FULLBIAS

= 0

306

BIASPROG

= 0x02, FULLBIAS

= 1

—

6.5

—

µA

BIASPROG

= 0x20, FULLBIAS

= 1

Current consumption of inter-

ACMPREF

nal voltage reference

VLP selected as input using 2.5 V

Reference / 4 (0.625 V)

VLP selected as input using VDD

—

µA

VBDIV selected as input using

1.25 V reference / 1

4.1

VADIV selected as input using

VDD/1

—

2.4

—

µA

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

HYSTSEL

= HYST0

HYSTSEL

= HYST1

HYSTSEL

= HYST2

HYSTSEL

= HYST3

HYSTSEL

= HYST4

HYSTSEL

= HYST5

HYSTSEL

= HYST6

HYSTSEL

= HYST7

HYSTSEL

= HYST8

HYSTSEL

= HYST9

HYSTSEL

= HYST10

HYSTSEL

= HYST11

HYSTSEL

= HYST12

HYSTSEL

= HYST13

HYSTSEL

= HYST14

HYSTSEL

= HYST15

BIASPROG

= 1, FULLBIAS

= 0

Hysteresis (V

= 1.25 V,

BIASPROG

= 0x10, FULL-

BIAS

= 1)

ACMPHYST

-3

µs

130

150

-3

-27

-50

-65

-82

-98

-130

-150

—

-18

-33

-45

-57

-67

-78

-88

-5

-12

-17

-23

-26

-30

-34

—

Comparator delay

ACMPDELAY

BIASPROG

= 0x10, FULLBIAS

= 0

—

3.7

—

µs

BIASPROG

= 0x02, FULLBIAS

= 1

—

360

—

BIASPROG

= 0x20, FULLBIAS

= 1

BIASPROG

=0x10, FULLBIAS

= 1

Offset voltage

ACMPOFFSET

-35

—

Reference voltage

ACMPREF

Internal 1.25 V reference

Internal 2.5 V reference

1.25

2.5

1.47

2.8

—

CSRESSEL

= 0

CSRESSEL

= 1

CSRESSEL

= 2

CSRESSEL

= 3

CSRESSEL

= 4

CSRESSEL

= 5

CSRESSEL

= 6

CSRESSEL

= 7

Capacitive sense internal re-

CSRES

sistance

—

infinite

kΩ

—

kΩ

100

162

235

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD.

2. In ACMPn_CTRL register.

3. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. I

ACMPTOTAL

= I

ACMP

ACMPREF

4. In ACMPn_HYSTERESIS registers.

5. ± 100 mV differential drive.

6. In ACMPn_INPUTSEL register.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.18 Digital

to Analog Converter (VDAC)

DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output.

Table 4.44.

Digital to Analog Converter (VDAC)

Parameter

Symbol

Test Condition

Single-Ended

Min

Typ

—

Max

Unit

Output voltage

DACOUT

VREF

Differential

-V

VREF

—

Current consumption includ-

DAC

ing references (2 channels)

500 ksps, 12-bit, DRIVES-

TRENGTH = 2, REFSEL = 4

396

—

µA

44.1 ksps, 12-bit, DRIVES-

TRENGTH = 1, REFSEL = 4

—

200 Hz refresh rate, 12-bit Sam-

ple-Off mode in EM2, DRIVES-

TRENGTH = 2, REFSEL = 4,

SETTLETIME = 0x02, WARMUP-

TIME = 0x0A

1.2

Current from HFPERCLK

Sample rate

DAC_CLK

—

5.8

—

500

µA/MHz

ksps

MHz

µs

DAC

DAC clock frequency

Conversion time

Settling time

DAC

—

DACCONV

DACSETTLE

DACSTARTUP

DAC

= 1MHz

—

50% fs step settling to 5 LSB

—

2.5

—

µs

Startup time

Enable to 90% fs output, settling

to 10 LSB

µs

Output impedance

OUT

DRIVESTRENGTH = 2, 0.4 V ≤

OUT

≤ V

OPA

– 0.4 V, -8 mA <

OUT

< 8 mA, Full supply range

—

Ω

DRIVESTRENGTH = 0 or 1, 0.4 V

≤ V

OUT

≤ V

OPA

– 0.4 V, -400 µA <

OUT

< 400 µA, Full supply range

DRIVESTRENGTH = 2, 0.1 V ≤

OUT

≤ V

OPA

– 0.1 V, -2 mA <

OUT

< 2 mA, Full supply range

Ω

DRIVESTRENGTH = 0 or 1, 0.1 V

≤ V

OUT

≤ V

OPA

– 0.1 V, -100 µA <

OUT

< 100 µA, Full supply range

Ω

Power supply rejection ratio

PSRR

Vout = 50% fs. DC

65.5

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal to noise and distortion

SNDR

DAC

ratio (1 kHz sine wave),

Noise band limited to 250

kHz

500 ksps, single-ended, internal

1.25V reference

—

60.4

—

500 ksps, single-ended, internal

2.5V reference

—

61.6

64.0

63.3

64.4

65.8

65.3

66.7

70.0

67.8

69.0

68.5

—

500 ksps, single-ended, 3.3V

VDD reference

500 ksps, differential, internal

1.25V reference

500 ksps, differential, internal

2.5V reference

500 ksps, differential, 3.3V VDD

reference

Signal to noise and distortion

SNDR

DAC_BAND

500 ksps, single-ended, internal

ratio (1 kHz sine wave),

Noise band limited to 22 kHz

1.25V reference

500 ksps, single-ended, internal

2.5V reference

500 ksps, single-ended, 3.3V

VDD reference

500 ksps, differential, internal

1.25V reference

500 ksps, differential, internal

2.5V reference

500 ksps, differential, 3.3V VDD

reference

Total harmonic distortion

THD

—

70.2

—

Differential non-linearity

Intergral non-linearity

DNL

DAC

-0.99

LSB

INL

DAC

-4

-8

—

LSB

Offset error

OFFSET

T = 25 °C

Across operating temperature

range

-25

Gain error

GAIN

T = 25 °C, Low-noise internal ref-

erence (REFSEL = 1V25LN or

2V5LN)

-2.5

—

2.5

T = 25 °C, Internal reference (RE-

FSEL = 1V25 or 2V5)

-5

—

T = 25 °C, External reference

(REFSEL = VDD or EXT)

-1.8

-3.5

1.8

3.5

Across operating temperature

range, Low-noise internal refer-

ence (REFSEL = 1V25LN or

2V5LN)

Across operating temperature

range, Internal reference (RE-

FSEL = 1V25 or 2V5)

-7.5

-2.0

—

7.5

2.0

Across operating temperature

range, External reference (RE-

FSEL = VDD or EXT)

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

External load capactiance,

OUTSCALE=0

LOAD

—

Note:

1. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is

limited to the single-ended range.

2. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive

the load.

3. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when

the clock to the DAC peripheral is enabled in the CMU.

4. PSRR calculated as 20 * log

(ΔVDD / ΔV

OUT

), VDAC output at 90% of full scale

5. Entire range is monotonic and has no missing codes.

6. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at

10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.19 Current

Digital to Analog Converter (IDAC)

Table 4.45.

Current Digital to Analog Converter (IDAC)

Parameter

Symbol

Test Condition

Min

—

Typ

Max

—

Unit

ranges

µA

Number of ranges

Output current

IDAC_RANGES

IDAC_OUT

RANGESEL

= RANGE0

RANGESEL

= RANGE1

RANGESEL

= RANGE2

RANGESEL

= RANGE3

0.05

—

1.6

0.5

—

4.7

—

µA

Linear steps within each

range

IDAC_STEPS

—

steps

RANGESEL

= RANGE0

RANGESEL

= RANGE1

RANGESEL

= RANGE2

RANGESEL

= RANGE3

Step size

IDAC

—

-3

100

500

—

µA

Total accuracy, STEPSEL

0x10

ACC

IDAC

EM0 or EM1, AVDD=3.3 V, T = 25

°C

—

EM0 or EM1, Across operating

temperature range

-18

—

-2

—

EM2 or EM3, Source mode, RAN-

GESEL

= RANGE0, AVDD=3.3

V, T = 25 °C

EM2 or EM3, Source mode, RAN-

GESEL

= RANGE1, AVDD=3.3

V, T = 25 °C

—

-1.7

-0.8

-0.5

-0.7

-0.6

-0.5

—

EM2 or EM3, Source mode, RAN-

GESEL

= RANGE2, AVDD=3.3

V, T = 25 °C

EM2 or EM3, Source mode, RAN-

GESEL

= RANGE3, AVDD=3.3

V, T = 25 °C

EM2 or EM3, Sink mode, RAN-

GESEL

= RANGE0, AVDD=3.3

V, T = 25 °C

EM2 or EM3, Sink mode, RAN-

GESEL

= RANGE1, AVDD=3.3

V, T = 25 °C

EM2 or EM3, Sink mode, RAN-

GESEL

= RANGE2, AVDD=3.3

V, T = 25 °C

EM2 or EM3, Sink mode, RAN-

GESEL

= RANGE3, AVDD=3.3

V, T = 25 °C

µs

Start up time

IDAC_SU

Output within 1% of steady state

value

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

—

Typ

Max

—

Unit

µs

Settling time, (output settled

IDAC_SETTLE

within 1% of steady state val-

ue),

Range setting is changed

Step value is changed

—

µs

Current consumption

IDAC

EM0 or EM1 Source mode, ex-

cluding output current, Across op-

erating temperature range

—

µA

EM0 or EM1 Sink mode, exclud-

ing output current, Across operat-

ing temperature range

EM2 or EM3 Source mode, ex-

cluding output current, T = 25 °C

—

0.023

0.041

—

µA

EM2 or EM3 Sink mode, exclud-

ing output current, T = 25 °C

EM2 or EM3 Source mode, ex-

cluding output current, T ≥ 85 °C

EM2 or EM3 Sink mode, exclud-

ing output current, T ≥ 85 °C

RANGESEL

= RANGE0, output

Output voltage compliance in

COMP_SRC

source mode, source current

change relative to current

sourced at 0 V

0.11

voltage = min(V

IOVDD

AVDD

-100 mV)

RANGESEL

= RANGE1, output

—

0.06

0.04

0.03

—

voltage = min(V

IOVDD

AVDD

-100 mV)

RANGESEL

= RANGE2, output

voltage = min(V

IOVDD

AVDD

-150 mV)

RANGESEL

= RANGE3, output

voltage = min(V

IOVDD

AVDD

-250 mV)

RANGESEL

= RANGE0, output

voltage = 100 mV

Output voltage compliance in

COMP_SINK

sink mode, sink current

change relative to current

sunk at IOVDD

—

0.12

0.05

0.04

0.03

—

RANGESEL

= RANGE1, output

voltage = 100 mV

RANGESEL

= RANGE2, output

voltage = 150 mV

RANGESEL

= RANGE3, output

voltage = 250 mV

Note:

1. In IDAC_CURPROG register.

2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and

PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-

tween AVDD (0) and DVDD (1).

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.20 Capacitive

Sense (CSEN)

Table 4.46.

Capacitive Sense (CSEN)

Parameter

Symbol

CNV

Test Condition

Min

—

Typ

20.2

26.4

1.55

Max

—

Unit

µs

Single conversion time (1x

accumulation)

12-bit SAR Conversions

16-bit SAR Conversions

—

µs

Delta Modulation Conversion (sin-

gle comparison)

—

µs

Maximum external capacitive

EXTMAX

load

IREFPROG=7 (Gain = 1x), includ-

ing routing parasitics

—

680

—

kΩ

IREFPROG=0 (Gain = 10x), in-

cluding routing parasitics

Maximum external series im-

EXTMAX

pedance

Supply current, EM2 bonded

CSEN_BOND

conversions, WARMUP-

MODE=NORMAL, WAR-

MUPCNT=0

12-bit SAR conversions, 20 ms

conversion rate, IREFPROG=7

(Gain = 1x), 10 channels bonded

(total capacitance of 330 pF)

326

Delta Modulation conversions, 20

ms conversion rate, IRE-

—

226

—

FPROG=7 (Gain = 1x), 10 chan-

nels bonded (total capacitance of

330 pF)

12-bit SAR conversions, 200 ms

conversion rate, IREFPROG=7

(Gain = 1x), 10 channels bonded

—

(total capacitance of 330 pF)

Delta Modulation conversions,

200 ms conversion rate, IRE-

FPROG=7 (Gain = 1x), 10 chan-

nels bonded (total capacitance of

330 pF)

Supply current, EM2 scan

conversions, WARMUP-

MODE=NORMAL, WAR-

MUPCNT=0

CSEN_EM2

12-bit SAR conversions, 20 ms

scan rate, IREFPROG=0 (Gain =

—

690

515

—

10x), 8 samples per scan

Delta Modulation conversions, 20

ms scan rate, 8 comparisons per

sample (DMCR = 1, DMR = 2),

IREFPROG=0 (Gain = 10x), 8

samples per scan

12-bit SAR conversions, 200 ms

scan rate, IREFPROG=0 (Gain =

—

10x), 8 samples per scan

Delta Modulation conversions,

200 ms scan rate, 8 comparisons

per sample (DMCR = 1, DMR =

2), IREFPROG=0 (Gain = 10x), 8

samples per scan

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Supply current, continuous

conversions, WARMUP-

MODE=KEEPCSENWARM

CSEN_ACTIVE

SAR or Delta Modulation conver-

sions of 33 pF capacitor, IRE-

FPROG=0 (Gain = 10x), always

—

90.5

—

µA

HFPERCLK supply current

CSEN_HFPERCLK

Current contribution from

HFPERCLK when clock to CSEN

block is enabled.

—

2.25

—

µA/MHz

Note:

1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the periph-

eral is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a

specific application can be estimated by multiplying the current per sample by the total number of samples per period (total_cur-

rent = single_sample_current * (number_of_channels * accumulation)).

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.21 Operational

Amplifier (OPAMP)

Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAIN-

OUTEN = 1, C

LOAD

= 75 pF with OUTSCALE = 0, or C

LOAD

= 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as

specified in table footnotes

1 2

Table 4.47.

Operational Amplifier (OPAMP)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Supply voltage (from AVDD)

OPA

HCMDIS = 0, Rail-to-rail input

range

—

3.8

HCMDIS = 1

1.62

—

3.8

Input voltage

HCMDIS = 0, Rail-to-rail input

range

VSS

OPA

HCMDIS = 1

VSS

100

VSS

—

OPA

-1.2

—

MΩ

Input impedance

Output voltage

OUT

LOAD

—

OPA

Load capacitance

OUTSCALE = 0

OUTSCALE = 1

—

Ω

—

37.5

—

Output impedance

OUT

DRIVESTRENGTH = 2 or 3, 0.4 V

≤ V

OUT

≤ V

OPA

– 0.4 V, -8 mA <

OUT

< 8 mA, Buffer connection,

Full supply range

—

0.25

DRIVESTRENGTH = 0 or 1, 0.4 V

≤ V

OUT

≤ V

OPA

– 0.4 V, -400 µA <

OUT

< 400 µA, Buffer connection,

Full supply range

—

0.6

0.4

—

Ω

DRIVESTRENGTH = 2 or 3, 0.1 V

≤ V

OUT

≤ V

OPA

– 0.1 V, -2 mA <

OUT

< 2 mA, Buffer connection,

Full supply range

DRIVESTRENGTH = 0 or 1, 0.1 V

≤ V

OUT

≤ V

OPA

– 0.1 V, -100 µA <

OUT

< 100 µA, Buffer connection,

Full supply range

Internal closed-loop gain

Active current

Buffer connection

3x Gain connection

16x Gain connection

0.99

2.93

15.07

—

1.01

3.05

16.33

—

–

2.99

15.7

580

–

OPA

DRIVESTRENGTH = 3, OUT-

SCALE = 0

µA

DRIVESTRENGTH = 2, OUT-

SCALE = 0

—

176

—

µA

DRIVESTRENGTH = 1, OUT-

SCALE = 0

DRIVESTRENGTH = 0, OUT-

SCALE = 0

4.7

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Electrical Specifications

Parameter

Symbol

Test Condition

Min

—

Typ

135

137

121

109

3.38

Max

—

Unit

Open-loop gain

DRIVESTRENGTH = 3

DRIVESTRENGTH = 2

DRIVESTRENGTH = 1

DRIVESTRENGTH = 0

—

Loop unit-gain frequency

UGF

DRIVESTRENGTH = 3, Buffer

connection

—

MHz

DRIVESTRENGTH = 2, Buffer

connection

—

0.9

132

—

MHz

kHz

DRIVESTRENGTH = 1, Buffer

connection

DRIVESTRENGTH = 0, Buffer

connection

kHz

DRIVESTRENGTH = 3, 3x Gain

connection

2.57

0.71

113

MHz

kHz

DRIVESTRENGTH = 2, 3x Gain

connection

DRIVESTRENGTH = 1, 3x Gain

connection

DRIVESTRENGTH = 0, 3x Gain

connection

kHz

Phase margin

DRIVESTRENGTH = 3, Buffer

connection

DRIVESTRENGTH = 2, Buffer

connection

DRIVESTRENGTH = 1, Buffer

connection

DRIVESTRENGTH = 0, Buffer

connection

Output voltage noise

OUT

DRIVESTRENGTH = 3, Buffer

connection, 10 Hz – 10 MHz

146

163

170

176

313

271

247

245

µVrms

DRIVESTRENGTH = 2, Buffer

connection, 10 Hz – 10 MHz

DRIVESTRENGTH = 1, Buffer

connection, 10 Hz – 1 MHz

DRIVESTRENGTH = 0, Buffer

connection, 10 Hz – 1 MHz

DRIVESTRENGTH = 3, 3x Gain

connection, 10 Hz – 10 MHz

DRIVESTRENGTH = 2, 3x Gain

connection, 10 Hz – 10 MHz

DRIVESTRENGTH = 1, 3x Gain

connection, 10 Hz – 1 MHz

DRIVESTRENGTH = 0, 3x Gain

connection, 10 Hz – 1 MHz

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Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Slew rate

DRIVESTRENGTH = 3,

INCBW=1

—

4.7

—

V/µs

DRIVESTRENGTH = 3,

INCBW=0

—

1.5

—

V/µs

DRIVESTRENGTH = 2,

INCBW=1

1.27

DRIVESTRENGTH = 2,

INCBW=0

—

0.42

0.17

—

V/µs

DRIVESTRENGTH = 1,

INCBW=1

DRIVESTRENGTH = 1,

INCBW=0

—

0.058

0.044

—

V/µs

DRIVESTRENGTH = 0,

INCBW=1

DRIVESTRENGTH = 0,

INCBW=0

—

0.015

—

V/µs

Startup time

START

OSI

DRIVESTRENGTH = 2

—

-2

—

µs

Input offset voltage

DRIVESTRENGTH = 2 or 3, T =

25 °C

DRIVESTRENGTH = 1 or 0, T =

25 °C

-2

—

DRIVESTRENGTH = 2 or 3,

across operating temperature

range

-12

DRIVESTRENGTH = 1 or 0,

across operating temperature

range

-30

—

DC power supply rejection

ratio

PSRR

Input referred

—

DC common-mode rejection

CMRR

ratio

Input referred

Total harmonic distortion

THD

OPA

DRIVESTRENGTH = 2, 3x Gain

connection, 1 kHz, V

OUT

= 0.1 V

to V

OPA

– 0.1 V

DRIVESTRENGTH = 0, 3x Gain

connection, 0.1 kHz, V

OUT

= 0.1 V

to V

OPA

– 0.1 V

—

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Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. V

INPUT

= 0.5 V,

OUTPUT

= 0.5 V.

2. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, V

INPUT

= 0.5 V, V

OUTPUT

= 1.5

V. Nominal voltage gain is 3.

3. If the maximum C

LOAD

is exceeded, an isolation resistor is required for stability. See AN0038 for more information.

4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to

drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause

another ~10 µA current when the OPAMP drives 1.5 V between output and ground.

5. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth

product of the OPAMP and 1/3 attenuation of the feedback network.

6. Step between 0.2V and V

OPA

-0.2V, 10%-90% rising/falling range.

7. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is ≥ 3,

or the OPAMP may not be stable.

8. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.

9. When HCMDIS=1 and input common mode transitions the region from V

OPA

-1.4V to V

OPA

-1V, input offset will change. PSRR

and CMRR specifications do not apply to this transition region.

4.1.22 Pulse

Counter (PCNT)

Table 4.48.

Pulse Counter (PCNT)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Input frequency

Asynchronous Single and Quad-

rature Modes

—

MHz

Sampled Modes with Debounce

filter set to 0.

—

kHz

4.1.23 Analog

Port (APORT)

Table 4.49.

Analog Port (APORT)

Parameter

Symbol

Test Condition

Min

—

Typ

Max

—

Unit

µA

Supply current

1 2

APORT

Operation in EM0/EM1

Operation in EM2/EM3

—

Note:

1. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in repor-

ted peripheral currents. Additional peripherals requesting access to APORT do not incur further current.

2. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. peri-

odic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of

the requests by the specified continuous current number.

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Electrical Specifications

4.1.24 I2C

4.1.24.1 I2C

Standard-mode (Sm)

Table 4.50.

I2C Standard-mode (Sm)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCL clock frequency

SCL clock low time

SCL clock high time

SDA set-up time

SCL

—

100

kHz

LOW

4.7

—

µs

HIGH

SU_DAT

HD_DAT

250

100

4.7

—

SDA hold time

3450

—

Repeated START condition

SU_STA

set-up time

(Repeated) START condition

HD_STA

hold time

—

µs

STOP condition set-up time

SU_STO

—

µs

Bus free time between a

BUF

4.7

STOP and START condition

Note:

1. For CLHR set to 0 in the I2Cn_CTRL register.

2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.

3. The maximum SDA hold time (t

HD_DAT

) needs to be met only when the device does not stretch the low time of SCL (t

LOW

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Electrical Specifications

4.1.24.2 I2C

Fast-mode (Fm)

Table 4.51.

I2C Fast-mode (Fm)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCL clock frequency

SCL clock low time

SCL clock high time

SDA set-up time

SCL

—

400

kHz

LOW

1.3

0.6

—

µs

HIGH

SU_DAT

HD_DAT

100

0.6

—

SDA hold time

900

—

Repeated START condition

SU_STA

set-up time

(Repeated) START condition

HD_STA

hold time

0.6

—

µs

STOP condition set-up time

SU_STO

0.6

1.3

—

µs

Bus free time between a

BUF

STOP and START condition

Note:

1. For CLHR set to 1 in the I2Cn_CTRL register.

2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual.

3. The maximum SDA hold time (t

HD,DAT

) needs to be met only when the device does not stretch the low time of SCL (t

LOW

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Electrical Specifications

4.1.24.3 I2C

Fast-mode Plus (Fm+)

Table 4.52.

I2C Fast-mode Plus (Fm+)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCL clock frequency

SCL clock low time

SCL clock high time

SDA set-up time

SCL

—

1000

kHz

LOW

0.5

0.26

—

µs

HIGH

SU_DAT

HD_DAT

SDA hold time

100

0.26

Repeated START condition

SU_STA

set-up time

(Repeated) START condition

HD_STA

hold time

0.26

—

µs

STOP condition set-up time

SU_STO

0.26

0.5

—

µs

Bus free time between a

BUF

STOP and START condition

Note:

1. For CLHR set to 0 or 1 in the I2Cn_CTRL register.

2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.1.25 USART

SPI

SPI Master Timing

Table 4.53.

SPI Master Timing

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK period

1 2 3

SCLK

2 *

HFPERCLK

—

CS to MOSI

1 2

CS_MO

SCLK_MO

SU_MI

-14.5

-8.5

—

13.5

SCLK to MOSI

1 2

MISO setup time

1 2

IOVDD = 1.62 V

IOVDD = 3.0 V

—

MISO hold time

1 2

H_MI

-10

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 8 pF output loading at 10% and 90% of V

(figure shows 50% of V

3. t

HFPERCLK

is one period of the selected HFPERCLK.

CS_MO

SCKL_MO

SCLK

CLKPOL = 0

SCLK

CLKPOL = 1

MOSI

MISO

SU_MI

H_MI

Figure 4.1.

SPI Master Timing Diagram

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

SPI Slave Timing

Table 4.54.

SPI Slave Timing

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SCLK period

1 2 3

SCLK

6 *

HFPERCLK

—

SCLK high time

1 2 3

SCLK low time

1 2 3

SCLK_HI

2.5 *

HFPERCLK

—

SCLK_LO

2.5 *

HFPERCLK

CS active to MISO

1 2

CS disable to MISO

1 2

MOSI setup time

1 2

MOSI hold time

1 2 3

SCLK to MISO

1 2 3

CS_ACT_MI

CS_DIS_MI

SU_MO

—

H_MO

SCLK_MI

10 + 1.5 *

HFPERCLK

65 + 2.5 *

HFPERCLK

Note:

1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).

2. Measurement done with 8 pF output loading at 10% and 90% of V

(figure shows 50% of V

3. t

HFPERCLK

is one period of the selected HFPERCLK.

CS_ACT_MI

CS_DIS_MI

SCLK

CLKPOL = 0

SCLK_HI

SCLK_LO

SCLK

SU_MO

CLKPOL = 1

SCLK

H_MO

MOSI

MISO

SCLK_MI

Figure 4.2.

SPI Slave Timing Diagram

4.2 Typical

Performance Curves

Typical performance curves indicate typical characterized performance under the stated conditions.

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Electrical Specifications

4.2.1 Supply

Current

Figure 4.3.

EM0 Active Mode Typical Supply Current vs. Temperature

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Figure 4.4.

EM1 Sleep Mode Typical Supply Current vs. Temperature

Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.

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Electrical Specifications

Figure 4.5.

EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

Figure 4.6.

EM0 and EM1 Mode Typical Supply Current vs. Supply

Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.

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Electrical Specifications

Figure 4.7.

EM2, EM3, EM4H and EM4S Typical Supply Current vs. Supply

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Electrical Specifications

4.2.2 DC-DC

Converter

Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 4.7 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz

Figure 4.8.

DC-DC Converter Typical Performance Characteristics

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Electrical Specifications

Load Step Response in LN (CCM) mode

(Heavy Drive)

LN (CCM) and LP mode transition (load: 5mA)

DVDD

20mV/div

offset:1.8V

60mV/div

offset:1.8V

100mA

LOAD

1mA

2V/div

offset:1.8V

10μs/div

100μs/div

Figure 4.9.

DC-DC Converter Transition Waveforms

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Electrical Specifications

4.2.3 2.4

GHz Radio

Figure 4.10.

2.4 GHz RF Transmitter Output Power

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Electrical Specifications

Figure 4.11.

2.4 GHz RF Receiver Sensitivity

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Typical Connection Diagrams

5. Typical

Connection Diagrams

5.1 Power

Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure.

Main

Supply

–

VREGVDD

AVDD

IOVDD

VREGSW

HFXTAL_N

HFXTAL_P

LFXTAL_N

LFXTAL_P

VREGVSS

DVDD

DECOUPLE

RFVDD

PAVDD

Figure 5.1.

EFR32FG12 Typical Application Circuit: Direct Supply Configuration without DC-DC converter

Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter sup-

ply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs support-

ing high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm.

Main

Supply

–

VREGVDD

AVDD

IOVDD

DCDC

VREGSW

HFXTAL_N

HFXTAL_P

LFXTAL_N

LFXTAL_P

VREGVSS

DVDD

DECOUPLE

RFVDD

PAVDD

Figure 5.2.

EFR32FG12 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC)

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Typical Connection Diagrams

Main

Supply

–

VREGVDD

AVDD

IOVDD

DCDC

VREGSW

HFXTAL_N

HFXTAL_P

LFXTAL_N

LFXTAL_P

VREGVSS

DVDD

DECOUPLE

RFVDD

PAVDD

Figure 5.3.

EFR32FG12 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD)

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Typical Connection Diagrams

5.2 RF

Matching Networks

Typical RF matching network circuit diagrams are shown in

Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on

page 118

for applications in the 2.4GHz band, and in

Figure 5.5 Typical Sub-GHz RF impedance-matching network circuits on page

118

for applications in the sub-GHz band. Application-specific component values can be found in application notes

AN923: EFR32 sub-

GHz Matching Guide

and

AN930: EFR32 2.4 GHz Matching Guide

. For low RF transmit power applications less than 13dBm, the two-

element match is recommended. For OPNs supporting high power RF transmission, the four-element match is recommended for high

RF transmit power (> 13dBm).

4-Element Match for 2.4GHz Band

2-Element Match for 2.4GHz Band

PAVDD

2G4RF_IOP

2G4RF_ION

2G4RF_IOP

2G4RF_ION

50Ω

Figure 5.4.

Typical 2.4 GHz RF impedance-matching network circuits

Sub-GHz Match Topology I (169-500 MHz)

PAVDD

SUBGRF_IN

SUBGRF_IP

50Ω

C10

BAL1

SUBGRF_ON

SUBGRF_OP

Sub-GHz Match Topology 2 (500-915 MHz)

PAVDD

SUBGRF_IN

50Ω

SUBGRF_IP

BAL1

SUBGRF_ON

SUBGRF_OP

Figure 5.5.

Typical Sub-GHz RF impedance-matching network circuits

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Typical Connection Diagrams

5.3 Other

Connections

Other components or connections may be required to meet the system-level requirements. Application Note AN0002: “Hardware De-

sign Considerations” contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs web-

site (

www.silabs.com/32bit-appnotes

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Pin Definitions

6. Pin

Definitions

6.1 BGA125

2.4 GHz and Sub-GHz Device Pinout

Figure 6.1.

BGA125 2.4 GHz and Sub-GHz Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see

6.9 GPIO Functionality Table

6.10 Alternate Functionality Overview

Table 6.1.

BGA125 2.4 GHz and Sub-GHz Device Pinout

Pin Name

PF3

Pin(s) Description

Pin Name

PF1

Pin(s) Description

GPIO (5V)

PC5

PC3

PC0

PC11

PC7

PC9

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Pin Definitions

Pin Name

Pin(s) Description

Decouple output for on-chip voltage

Pin Name

Pin(s) Description

regulator. An external decoupling ca-

pacitor is required at this pin. This pin

should not be used to power any exter-

nal circuits.

DECOUPLE

DVDD

A10

Digital power supply.

VREGVDD

VREGVSS

A11

Voltage regulator VDD input

VREGSW

PF8

A12

DCDC regulator switching node

GPIO (5V)

A13

B11

B12

Voltage regulator VSS

PF2

PC4

PJ14

PC8

GPIO (5V)

PF0

PC1

GPIO (5V)

PC10

PC6

B10

F11

M12

IOVDD

Digital IO power supply.

AVDD

B13

Analog power supply.

PF11

PF9

GPIO (5V)

GPIO

PF10

PC2

GPIO (5V)

GPIO

PJ15

PB14

PB12

PF13

PB11

PB9

PB15

PB13

PF14

PF12

PB10

PK1

C10

C12

C11

C13

GPIO

GPIO (5V)

GPIO

D11

D13

D12

GPIO (5V)

GPIO

PK0

PF15

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

Pin(s) Description

Pin Name

Pin(s) Description

VSS

Ground

PB8

E12

GPIO (5V)

PB7

PB6

PF5

PI2

E13

F12

GPIO (5V)

PK2

PI3

F13

GPIO (5V)

PF4

PI1

G11

G13

G12

PI0

PF7

PA9

PF6

H12

PA8

H13

GPIO (5V)

RFVDD

Radio power supply

PA7

PA5

PA4

J11

J13

K12

GPIO (5V)

GPIO

PA6

HFXTAL_N

PA3

J12

GPIO (5V)

High Frequency Crystal input pin.

GPIO

K13

Brown-Out Detector Enable. This pin

may be left disconnected or tied to

AVDD.

HFXTAL_P

PA2

High Frequency Crystal output pin.

GPIO

BODEN

PA1

L10

L13

L12

GPIO

Reset input, active low. This pin is inter-

nally pulled up to AVDD. To apply an

external reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

RESETn

PAVSS

RFVSS

Radio Ground

Power Amplifier (PA) voltage regulator

VSS

Power Amplifier (PA) voltage regulator

VDD input

PAVDD

PD9

GPIO (5V)

GPIO

PD11

PA0

M10

M13

GPIO (5V)

GPIO

PD13

M11

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

Pin(s) Description

Pin Name

Pin(s) Description

Sub GHz Differential RF output, positive

path.

Sub GHz Differential RF output, nega-

tive path.

SUBGRF_OP

SUBGRF_ON

SUBGRF_IN

Sub GHz Differential RF input, positive

path.

Sub GHz Differential RF input, negative

path.

SUBGRF_IP

2G4RF_ION

2.4 GHz Differential RF input/output,

negative path. This pin should be exter-

nally grounded.

2.4 GHz Differential RF input/output,

positive path.

2G4RF_IOP

PD8

PD12

GPIO (5V)

GPIO

PD10

PD14

N10

N12

GPIO (5V)

GPIO

N11

N13

PD15

Note:

1. GPIO with 5V tolerance are indicated by (5V).

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

6.2 BGA125

2.4 GHz Device Pinout

Figure 6.2.

BGA125 2.4 GHz Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see

6.9 GPIO Functionality Table

6.10 Alternate Functionality Overview

Table 6.2.

BGA125 2.4 GHz Device Pinout

Pin Name

PF3

Pin(s) Description

Pin Name

PF1

Pin(s) Description

GPIO (5V)

PC5

PC3

PC0

PC11

PC7

PC9

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin. This pin

should not be used to power any exter-

nal circuits.

DECOUPLE

DVDD

A10

Digital power supply.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

Pin(s) Description

Pin Name

Pin(s) Description

VREGVDD

A11

Voltage regulator VDD input

VREGSW

A12

DCDC regulator switching node

A13

B11

B12

VREGVSS

Voltage regulator VSS

PF8

GPIO (5V)

PF2

PC4

PJ14

PC8

GPIO (5V)

PF0

PC1

GPIO (5V)

PC10

PC6

B10

F11

M12

IOVDD

Digital IO power supply.

AVDD

B13

Analog power supply.

PF11

PF9

GPIO (5V)

GPIO

PF10

PC2

GPIO (5V)

GPIO

PJ15

PB14

PB12

PF13

PB11

PB9

PB15

PB13

PF14

PF12

PB10

PK1

C10

C12

C11

C13

GPIO

GPIO (5V)

GPIO

D11

D13

D12

GPIO (5V)

GPIO

PK0

PF15

VSS

Ground

PB8

E12

GPIO (5V)

PB7

PB6

E13

F12

GPIO (5V)

PK2

PI3

GPIO (5V)

F13

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

PF5

Pin(s) Description

Pin Name

Pin(s) Description

G11

G13

GPIO (5V)

PF4

PI1

G12

GPIO (5V)

PI2

PI0

PF7

PA9

PF6

H12

PA8

H13

GPIO (5V)

RFVDD

Radio power supply

PA7

PA5

PA4

J11

J13

K12

GPIO (5V)

GPIO

PA6

HFXTAL_N

PA3

J12

GPIO (5V)

High Frequency Crystal input pin.

GPIO

K13

Brown-Out Detector Enable. This pin

may be left disconnected or tied to

AVDD.

HFXTAL_P

PA2

High Frequency Crystal output pin.

GPIO

BODEN

PA1

L10

L13

L12

GPIO

Reset input, active low. This pin is inter-

nally pulled up to AVDD. To apply an

external reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

RESETn

PAVSS

RFVSS

Radio Ground

Power Amplifier (PA) voltage regulator

VSS

Power Amplifier (PA) voltage regulator

VDD input

PAVDD

PD9

GPIO (5V)

GPIO

PD11

PA0

M10

M13

GPIO (5V)

GPIO

PD13

M11

2.4 GHz Differential RF input/output,

negative path. This pin should be exter-

nally grounded.

No Connect.

2G4RF_ION

2.4 GHz Differential RF input/output,

positive path.

2G4RF_IOP

PD8

GPIO (5V)

PD10

PD14

N10

N12

GPIO (5V)

GPIO

PD12

PD15

N11

N13

GPIO (5V)

GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

6.3 BGA125

Sub-GHz Device Pinout

Figure 6.3.

BGA125 Sub-GHz Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see

6.9 GPIO Functionality Table

6.10 Alternate Functionality Overview

Table 6.3.

BGA125 Sub-GHz Device Pinout

Pin Name

PF3

Pin(s) Description

Pin Name

PF1

Pin(s) Description

GPIO (5V)

PC5

PC3

PC0

PC11

PC7

PC9

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin. This pin

should not be used to power any exter-

nal circuits.

DECOUPLE

DVDD

A10

Digital power supply.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

Pin(s) Description

Pin Name

Pin(s) Description

VREGVDD

A11

Voltage regulator VDD input

VREGSW

A12

DCDC regulator switching node

A13

B11

B12

VREGVSS

Voltage regulator VSS

PF8

GPIO (5V)

PF2

PC4

PJ14

PC8

GPIO (5V)

PF0

PC1

GPIO (5V)

PC10

PC6

B10

F11

M12

IOVDD

Digital IO power supply.

AVDD

B13

Analog power supply.

PF11

PF9

GPIO (5V)

GPIO

PF10

PC2

GPIO (5V)

GPIO

PJ15

PB14

PB12

PF13

PB11

PB9

PB15

PB13

PF14

PF12

PB10

PK1

C10

C12

C11

C13

GPIO

GPIO (5V)

GPIO

D11

D13

D12

GPIO (5V)

GPIO

PK0

PF15

VSS

Ground

PB8

E12

GPIO (5V)

PB7

E13

GPIO (5V)

PK2

GPIO (5V)

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

PB6

Pin(s) Description

Pin Name

Pin(s) Description

F12

GPIO (5V)

PI3

PF4

PI1

F13

GPIO (5V)

PF5

PI2

G11

G13

G12

PI0

PF7

PA9

PF6

H12

PA8

H13

GPIO (5V)

RFVDD

Radio power supply

PA7

PA5

PA4

J11

J13

K12

GPIO (5V)

GPIO

PA6

HFXTAL_N

PA3

J12

GPIO (5V)

High Frequency Crystal input pin.

GPIO

K13

Brown-Out Detector Enable. This pin

may be left disconnected or tied to

AVDD.

HFXTAL_P

PA2

High Frequency Crystal output pin.

GPIO

BODEN

PA1

L10

L13

L12

GPIO

Reset input, active low. This pin is inter-

nally pulled up to AVDD. To apply an

external reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

RESETn

RFVSS

PD9

Radio Ground

No Connect.

GPIO (5V)

GPIO

PD11

PA0

M10

M13

GPIO (5V)

GPIO

PD13

M11

Sub GHz Differential RF output, positive

path.

SUBGRF_OP

Sub GHz Differential RF output, nega-

tive path.

Sub GHz Differential RF input, positive

path.

SUBGRF_ON

SUBGRF_IN

SUBGRF_IP

PD8

Sub GHz Differential RF input, negative

path.

GPIO (5V)

PD10

PD14

N10

N12

GPIO (5V)

GPIO

PD12

PD15

N11

N13

GPIO (5V)

GPIO

Note:

1. GPIO with 5V tolerance are indicated by (5V).

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

6.4 QFN68

2.4 GHz and Sub-GHz Device Pinout

Figure 6.4.

QFN68 2.4 GHz and Sub-GHz Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see

6.9 GPIO Functionality Table

6.10 Alternate Functionality Overview

Table 6.4.

QFN68 2.4 GHz and Sub-GHz Device Pinout

Pin Name

VSS

Pin(s) Description

Pin Name

PC5

Pin(s) Description

Ground

GPIO (5V)

PF0

GPIO (5V)

PF1

PF2

PF3

PF8

PF9

PF10

PF4

GPIO (5V)

IOVDD

PF5

Digital IO power supply.

GPIO (5V)

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

PF6

Pin(s) Description

Pin Name

Pin(s) Description

GPIO (5V)

PF7

GPIO (5V)

RFVDD

Radio power supply

HFXTAL_N

High Frequency Crystal input pin.

Reset input, active low. This pin is inter-

nally pulled up to AVDD. To apply an

external reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

HFXTAL_P

High Frequency Crystal output pin.

RESETn

Sub GHz Differential RF output, positive

path.

Sub GHz Differential RF output, nega-

tive path.

SUBGRF_OP

SUBGRF_IP

RFVSS

SUBGRF_ON

SUBGRF_IN

PAVSS

Sub GHz Differential RF input, positive

path.

Sub GHz Differential RF input, negative

path.

Power Amplifier (PA) voltage regulator

VSS

Radio Ground

2.4 GHz Differential RF input/output,

negative path. This pin should be exter-

nally grounded.

2.4 GHz Differential RF input/output,

positive path.

2G4RF_ION

PAVDD

2G4RF_IOP

PD8

Power Amplifier (PA) voltage regulator

VDD input

GPIO (5V)

PD9

PD11

PD13

PD15

PA1

GPIO (5V)

PD10

PD12

PD14

PA0

GPIO (5V)

GPIO

PA2

GPIO

PA3

GPIO

PA4

GPIO

PA5

GPIO (5V)

PB7

GPIO (5V)

PB8

GPIO (5V)

PB9

GPIO (5V)

PB10

PB12

AVDD

PB15

VREGSW

GPIO (5V)

PB11

GPIO

PB13

GPIO

Analog power supply.

GPIO

PB14

GPIO

VREGVSS

VREGVDD

Voltage regulator VSS

Voltage regulator VDD input

DCDC regulator switching node

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin. This pin

should not be used to power any exter-

nal circuits.

DVDD

Digital power supply.

DECOUPLE

PC6

PC8

PC10

PC0

PC2

PC4

GPIO (5V)

PC7

PC9

PC11

PC1

PC3

GPIO (5V)

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

Note:

Pin(s) Description

Pin Name

Pin(s) Description

1. GPIO with 5V tolerance are indicated by (5V).

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

6.5 QFN68

Sub-GHz Device Pinout

Figure 6.5.

QFN68 Sub-GHz Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see

6.9 GPIO Functionality Table

6.10 Alternate Functionality Overview

Table 6.5.

QFN68 Sub-GHz Device Pinout

Pin Name

Pin(s) Description

Pin Name

Pin(s) Description

VSS

Ground

PC5

GPIO (5V)

PF0

PF2

PF8

GPIO (5V)

PF1

PF3

PF9

GPIO (5V)

PF10

GPIO (5V)

IOVDD

Digital IO power supply.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

PF4

Pin(s) Description

Pin Name

Pin(s) Description

GPIO (5V)

PF5

PF7

GPIO (5V)

PF6

GPIO (5V)

RFVDD

Radio power supply

HFXTAL_N

High Frequency Crystal input pin.

Reset input, active low. This pin is inter-

nally pulled up to AVDD. To apply an

external reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

HFXTAL_P

High Frequency Crystal output pin.

RESETn

Sub GHz Differential RF output, positive

path.

Sub GHz Differential RF output, nega-

tive path.

SUBGRF_OP

SUBGRF_IP

SUBGRF_ON

SUBGRF_IN

Sub GHz Differential RF input, positive

path.

Sub GHz Differential RF input, negative

path.

RFVSS

Radio Ground

No Connect.

PD8

PD10

PD12

PD14

PA0

GPIO (5V)

GPIO

PD9

PD11

PD13

PD15

PA1

GPIO (5V)

GPIO

PA2

GPIO

PA3

GPIO

PA4

GPIO

PA5

GPIO (5V)

PB7

GPIO (5V)

GPIO

PB8

GPIO (5V)

PB9

PB10

PB12

AVDD

PB15

VREGSW

DVDD

GPIO (5V)

PB11

PB13

PB14

VREGVSS

VREGVDD

GPIO

Analog power supply.

GPIO

Voltage regulator VSS

Voltage regulator VDD input

DCDC regulator switching node

Digital power supply.

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin. This pin

should not be used to power any exter-

nal circuits.

DECOUPLE

PC6

GPIO (5V)

PC7

PC9

GPIO (5V)

PC8

PC10

PC0

PC2

PC4

GPIO (5V)

PC11

PC1

PC3

Note:

1. GPIO with 5V tolerance are indicated by (5V).

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

6.6 QFN48

2.4 GHz and Sub-GHz Device Pinout

Figure 6.6.

QFN48 2.4 GHz and Sub-GHz Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see

6.9 GPIO Functionality Table

6.10 Alternate Functionality Overview

Table 6.6.

QFN48 2.4 GHz and Sub-GHz Device Pinout

Pin Name

VSS

Pin(s) Description

Pin Name

PF0

Pin(s) Description

Ground

GPIO (5V)

PF1

GPIO (5V)

PF2

GPIO (5V)

PF3

GPIO (5V)

PF4

GPIO (5V)

PF5

GPIO (5V)

PF6

GPIO (5V)

PF7

GPIO (5V)

RFVDD

HFXTAL_P

Radio power supply

High Frequency Crystal output pin.

HFXTAL_N

High Frequency Crystal input pin.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

Pin(s) Description

Reset input, active low. This pin is inter-

Pin Name

Pin(s) Description

nally pulled up to AVDD. To apply an

external reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

Sub GHz Differential RF output, positive

path.

RESETn

SUBGRF_OP

Sub GHz Differential RF output, nega-

tive path.

Sub GHz Differential RF input, positive

path.

SUBGRF_ON

SUBGRF_IN

SUBGRF_IP

RFVSS

Sub GHz Differential RF input, negative

path.

Radio Ground

2.4 GHz Differential RF input/output,

negative path. This pin should be exter-

nally grounded.

Power Amplifier (PA) voltage regulator

VSS

PAVSS

2G4RF_ION

PAVDD

2.4 GHz Differential RF input/output,

positive path.

Power Amplifier (PA) voltage regulator

VDD input

2G4RF_IOP

PD13

PD15

PA1

GPIO

PD14

PA0

GPIO

PA2

GPIO

PA3

GPIO

PA4

GPIO

PA5

GPIO (5V)

PB11

GPIO

PB12

AVDD

PB15

VREGSW

GPIO

PB13

GPIO

Analog power supply.

GPIO

PB14

GPIO

VREGVSS

VREGVDD

Voltage regulator VSS

Voltage regulator VDD input

DCDC regulator switching node

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin. This pin

should not be used to power any exter-

nal circuits.

DVDD

Digital power supply.

DECOUPLE

IOVDD

PC7

Digital IO power supply.

GPIO (5V)

PC6

PC8

GPIO (5V)

PC9

GPIO (5V)

PC10

PC11

Note:

GPIO (5V)

1. GPIO with 5V tolerance are indicated by (5V).

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

6.7 QFN48

2.4 GHz Device Pinout

Figure 6.7.

QFN48 2.4 GHz Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see

6.9 GPIO Functionality Table

6.10 Alternate Functionality Overview

Table 6.7.

QFN48 2.4 GHz Device Pinout

Pin Name

VSS

Pin(s) Description

Pin Name

PF0

Pin(s) Description

Ground

GPIO (5V)

PF1

GPIO (5V)

PF2

GPIO (5V)

PF3

GPIO (5V)

PF4

GPIO (5V)

PF5

GPIO (5V)

PF6

GPIO (5V)

PF7

GPIO (5V)

RFVDD

HFXTAL_P

Radio power supply

High Frequency Crystal output pin.

HFXTAL_N

High Frequency Crystal input pin.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

Pin(s) Description

Reset input, active low. This pin is inter-

Pin Name

Pin(s) Description

nally pulled up to AVDD. To apply an

external reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

RESETn

No Connect.

Power Amplifier (PA) voltage regulator

VSS

RFVSS

2G4RF_ION

PAVDD

Radio Ground

PAVSS

2G4RF_IOP

PD10

2.4 GHz Differential RF input/output,

negative path. This pin should be exter-

nally grounded.

2.4 GHz Differential RF input/output,

positive path.

Power Amplifier (PA) voltage regulator

VDD input

GPIO (5V)

PD11

PD13

PD15

PA1

GPIO (5V)

PD12

PD14

GPIO (5V)

GPIO

PA0

GPIO

PA2

GPIO

PA3

GPIO

PA4

GPIO

PA5

GPIO (5V)

PB11

GPIO

PB12

AVDD

PB15

VREGSW

GPIO

PB13

GPIO

Analog power supply.

GPIO

PB14

GPIO

VREGVSS

VREGVDD

Voltage regulator VSS

Voltage regulator VDD input

DCDC regulator switching node

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin. This pin

should not be used to power any exter-

nal circuits.

DVDD

Digital power supply.

DECOUPLE

IOVDD

PC7

Digital IO power supply.

GPIO (5V)

PC6

PC8

GPIO (5V)

PC9

GPIO (5V)

PC10

PC11

Note:

GPIO (5V)

1. GPIO with 5V tolerance are indicated by (5V).

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

6.8 QFN48

Sub-GHz Device Pinout

Figure 6.8.

QFN48 Sub-GHz Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-

ported features for each GPIO pin, see

6.9 GPIO Functionality Table

6.10 Alternate Functionality Overview

Table 6.8.

QFN48 Sub-GHz Device Pinout

Pin Name

VSS

Pin(s) Description

Pin Name

PF0

Pin(s) Description

Ground

GPIO (5V)

PF1

GPIO (5V)

PF2

GPIO (5V)

PF3

GPIO (5V)

PF4

GPIO (5V)

PF5

GPIO (5V)

PF6

GPIO (5V)

PF7

GPIO (5V)

RFVDD

HFXTAL_P

Radio power supply

High Frequency Crystal output pin.

HFXTAL_N

High Frequency Crystal input pin.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Pin Name

Pin(s) Description

Reset input, active low. This pin is inter-

Pin Name

Pin(s) Description

nally pulled up to AVDD. To apply an

external reset source to this pin, it is re-

quired to only drive this pin low during

reset, and let the internal pull-up ensure

that reset is released.

Sub GHz Differential RF output, positive

path.

RESETn

SUBGRF_OP

Sub GHz Differential RF output, nega-

tive path.

Sub GHz Differential RF input, positive

path.

SUBGRF_ON

SUBGRF_IN

SUBGRF_IP

RFVSS

Sub GHz Differential RF input, negative

path.

Radio Ground

PD9

PD11

PD13

PD15

PA1

GPIO (5V)

PD10

PD12

GPIO (5V)

GPIO

PD14

GPIO

PA0

GPIO

PA2

GPIO

PA3

GPIO

PA4

GPIO

PA5

GPIO (5V)

PB11

GPIO

PB12

AVDD

PB15

VREGSW

GPIO

PB13

GPIO

Analog power supply.

GPIO

PB14

GPIO

VREGVSS

VREGVDD

Voltage regulator VSS

Voltage regulator VDD input

DCDC regulator switching node

Decouple output for on-chip voltage

regulator. An external decoupling ca-

pacitor is required at this pin. This pin

should not be used to power any exter-

nal circuits.

DVDD

Digital power supply.

DECOUPLE

IOVDD

PC7

Digital IO power supply.

GPIO (5V)

PC6

PC8

GPIO (5V)

PC9

GPIO (5V)

PC10

PC11

Note:

GPIO (5V)

1. GPIO with 5V tolerance are indicated by (5V).

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Pin Definitions

6.9 GPIO

Functionality Table

A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO

pin, followed by the functionality available on that pin. Refer to

6.10 Alternate Functionality Overview

for a list of GPIO locations availa-

ble for each function.

Table 6.9.

GPIO Functionality Table

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #0

Radio

Other

TIM0_CC0 #0

TIM0_CC1 #31

TIM0_CC2 #30

TIM0_CDTI0 #29

TIM0_CDTI1 #28

TIM0_CDTI2 #27

TIM1_CC0 #0

US0_RX #31

US0_CLK #30

US0_CS #29

US0_CTS #28

US0_RTS #27

US1_TX #0

FRC_DCLK #0

FRC_DOUT #31

CMU_CLK1 #0

PRS_CH6 #0

PRS_CH7 #10

PRS_CH8 #9

PRS_CH9 #8

ACMP0_O #0

ACMP1_O #0

LES_CH8

FRC_DFRAME #30

MODEM_DCLK #0

MODEM_DIN #31

MODEM_DOUT #30

MODEM_ANT0 #29

MODEM_ANT1 #28

BUSDY

BUSCX

US1_RX #31

US1_CLK #30

US1_CS #29

US1_CTS #28

US1_RTS #27

LEU0_TX #0

LEU0_RX #31

I2C0_SDA #0

I2C0_SCL #31

PA0

TIM1_CC1 #31

TIM1_CC2 #30

TIM1_CC3 #29

WTIM0_CC0 #0

LETIM0_OUT0 #0

LETIM0_OUT1 #31

PCNT0_S0IN #0

PCNT0_S1IN #31

ADC0_EXTN

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #1

Radio

Other

TIM0_CC0 #1

TIM0_CC1 #0

US0_RX #0

US0_CLK #31

US0_CS #30

US0_CTS #29

US0_RTS #28

US1_TX #1

TIM0_CC2 #31

TIM0_CDTI0 #30

TIM0_CDTI1 #29

TIM0_CDTI2 #28

TIM1_CC0 #1

FRC_DCLK #1

FRC_DOUT #0

CMU_CLK0 #0

PRS_CH6 #1

PRS_CH7 #0

PRS_CH8 #10

PRS_CH9 #9

ACMP0_O #1

ACMP1_O #1

LES_CH9

BUSCY

BUSDX

FRC_DFRAME #31

MODEM_DCLK #1

MODEM_DIN #0

US1_RX #0

PA1

TIM1_CC1 #0

ADC0_EXTP

VDAC0_EXT

US1_CLK #31

US1_CS #30

US1_CTS #29

US1_RTS #28

LEU0_TX #1

LEU0_RX #0

I2C0_SDA #1

I2C0_SCL #0

US0_TX #2

TIM1_CC2 #31

TIM1_CC3 #30

WTIM0_CC0 #1

LETIM0_OUT0 #1

LETIM0_OUT1 #0

PCNT0_S0IN #1

PCNT0_S1IN #0

MODEM_DOUT #31

MODEM_ANT0 #30

MODEM_ANT1 #29

TIM0_CC0 #2

TIM0_CC1 #1

US0_RX #1

TIM0_CC2 #0

US0_CLK #0

US0_CS #31

US0_CTS #30

US0_RTS #29

US1_TX #2

TIM0_CDTI0 #31

TIM0_CDTI1 #30

TIM0_CDTI2 #29

TIM1_CC0 #2

FRC_DCLK #2

FRC_DOUT #1

PRS_CH6 #2

PRS_CH7 #1

PRS_CH8 #0

PRS_CH9 #10

ACMP0_O #2

ACMP1_O #2

LES_CH10

VDAC0_OUT1ALT /

OPA1_OUTALT #1

FRC_DFRAME #0

MODEM_DCLK #2

MODEM_DIN #1

MODEM_DOUT #0

MODEM_ANT0 #31

MODEM_ANT1 #30

TIM1_CC1 #1

US1_RX #1

BUSDY

BUSCX

OPA0_P

PA2

TIM1_CC2 #0

US1_CLK #0

US1_CS #31

US1_CTS #30

US1_RTS #29

LEU0_TX #2

LEU0_RX #1

I2C0_SDA #2

I2C0_SCL #1

TIM1_CC3 #31

WTIM0_CC0 #2

WTIM0_CC1 #0

LETIM0_OUT0 #2

LETIM0_OUT1 #1

PCNT0_S0IN #2

PCNT0_S1IN #1

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #3

Radio

Other

TIM0_CC0 #3

TIM0_CC1 #2

US0_RX #2

TIM0_CC2 #1

US0_CLK #1

US0_CS #0

TIM0_CDTI0 #0

TIM0_CDTI1 #31

TIM0_CDTI2 #30

TIM1_CC0 #3

US0_CTS #31

US0_RTS #30

US1_TX #3

FRC_DCLK #3

FRC_DOUT #2

PRS_CH6 #3

PRS_CH7 #2

PRS_CH8 #1

PRS_CH9 #0

ACMP0_O #3

ACMP1_O #3

LES_CH11

FRC_DFRAME #1

MODEM_DCLK #3

MODEM_DIN #2

MODEM_DOUT #1

MODEM_ANT0 #0

MODEM_ANT1 #31

BUSCY

BUSDX

TIM1_CC1 #2

US1_RX #2

PA3

TIM1_CC2 #1

US1_CLK #1

US1_CS #0

VDAC0_OUT0 /

OPA0_OUT

TIM1_CC3 #0

WTIM0_CC0 #3

WTIM0_CC1 #1

LETIM0_OUT0 #3

LETIM0_OUT1 #2

PCNT0_S0IN #3

PCNT0_S1IN #2

TIM0_CC0 #4

US1_CTS #31

US1_RTS #30

LEU0_TX #3

LEU0_RX #2

I2C0_SDA #3

I2C0_SCL #2

GPIO_EM4WU8

US0_TX #4

US0_RX #3

US0_CLK #2

US0_CS #1

US0_CTS #0

US0_RTS #31

US1_TX #4

TIM0_CC1 #3

TIM0_CC2 #2

TIM0_CDTI0 #1

TIM0_CDTI1 #0

TIM0_CDTI2 #31

TIM1_CC0 #4

FRC_DCLK #4

FRC_DOUT #3

PRS_CH6 #4

PRS_CH7 #3

PRS_CH8 #2

PRS_CH9 #1

ACMP0_O #4

ACMP1_O #4

LES_CH12

VDAC0_OUT1ALT /

OPA1_OUTALT #2

FRC_DFRAME #2

MODEM_DCLK #4

MODEM_DIN #3

MODEM_DOUT #2

MODEM_ANT0 #1

MODEM_ANT1 #0

TIM1_CC1 #3

US1_RX #3

US1_CLK #2

US1_CS #1

US1_CTS #0

US1_RTS #31

LEU0_TX #4

LEU0_RX #3

I2C0_SDA #4

I2C0_SCL #3

BUSDY

BUSCX

OPA0_N

PA4

TIM1_CC2 #2

TIM1_CC3 #1

WTIM0_CC0 #4

WTIM0_CC1 #2

WTIM0_CC2 #0

LETIM0_OUT0 #4

LETIM0_OUT1 #3

PCNT0_S0IN #4

PCNT0_S1IN #3

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #5

Radio

Other

US0_RX #4

US0_CLK #3

US0_CS #2

TIM0_CC0 #5

TIM0_CC1 #4

US0_CTS #1

US0_RTS #0

US1_TX #5

TIM0_CC2 #3

TIM0_CDTI0 #2

TIM0_CDTI1 #1

TIM0_CDTI2 #0

TIM1_CC0 #5

CMU_CLKI0 #4

PRS_CH6 #5

PRS_CH7 #4

PRS_CH8 #3

PRS_CH9 #2

ACMP0_O #5

ACMP1_O #5

LES_CH13

US1_RX #4

FRC_DCLK #5

FRC_DOUT #4

US1_CLK #3

US1_CS #2

FRC_DFRAME #3

MODEM_DCLK #5

MODEM_DIN #4

MODEM_DOUT #3

MODEM_ANT0 #2

MODEM_ANT1 #1

VDAC0_OUT0ALT /

OPA0_OUTALT #0

TIM1_CC1 #4

US1_CTS #1

US1_RTS #0

US2_TX #0

PA5

TIM1_CC2 #3

BUSCY

BUSDX

TIM1_CC3 #2

WTIM0_CC0 #5

WTIM0_CC1 #3

WTIM0_CC2 #1

LETIM0_OUT0 #5

LETIM0_OUT1 #4

PCNT0_S0IN #5

PCNT0_S1IN #4

US2_RX #31

US2_CLK #30

US2_CS #29

US2_CTS #28

US2_RTS #27

LEU0_TX #5

LEU0_RX #4

I2C0_SDA #5

I2C0_SCL #4

US2_TX #1

ETM_TCLK #1

WTIM0_CC0 #6

WTIM0_CC1 #4

WTIM0_CC2 #2

PCNT1_S0IN #0

PCNT1_S1IN #31

PCNT2_S0IN #0

PCNT2_S1IN #31

US2_RX #0

US2_CLK #31

US2_CS #30

US2_CTS #29

US2_RTS #28

I2C1_SDA #0

I2C1_SCL #31

BUSDY

BUSCX

LES_CH14

PA6

ETM_TD0 #1

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US2_TX #2

Radio

Other

WTIM0_CC0 #7

WTIM0_CC1 #5

WTIM0_CC2 #3

PCNT1_S0IN #1

PCNT1_S1IN #0

PCNT2_S0IN #1

PCNT2_S1IN #0

US2_RX #1

US2_CLK #0

US2_CS #31

US2_CTS #30

US2_RTS #29

I2C1_SDA #1

I2C1_SCL #0

US2_TX #3

BUSCY

BUSDX

LES_CH15

PA7

ETM_TD1 #1

WTIM0_CC0 #8

WTIM0_CC1 #6

WTIM0_CC2 #4

WTIM0_CDTI0 #0

PCNT1_S0IN #2

PCNT1_S1IN #1

PCNT2_S0IN #2

PCNT2_S1IN #1

WTIM0_CC0 #9

WTIM0_CC1 #7

WTIM0_CC2 #5

WTIM0_CDTI0 #1

PCNT1_S0IN #3

PCNT1_S1IN #2

PCNT2_S0IN #3

PCNT2_S1IN #2

US2_RX #2

US2_CLK #1

US2_CS #0

BUSACMP0Y

BUSACMP0X

LES_ALTEX0

ETM_TD2 #1

PA8

US2_CTS #31

US2_RTS #30

I2C1_SDA #2

I2C1_SCL #1

US2_TX #4

US2_RX #3

US2_CLK #2

US2_CS #1

BUSACMP0Y

BUSACMP0X

LES_ALTEX1

ETM_TD3 #1

PA9

US2_CTS #0

US2_RTS #31

I2C1_SDA #3

I2C1_SCL #2

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US2_TX #9

Radio

Other

US2_RX #8

US2_CLK #7

US2_CS #6

US2_CTS #5

US2_RTS #4

US3_TX #10

US3_RX #9

US3_CLK #8

US3_CS #7

US3_CTS #6

US3_RTS #5

I2C1_SDA #6

I2C1_SCL #5

US2_TX #10

US2_RX #9

US2_CLK #8

US2_CS #7

US2_CTS #6

US2_RTS #5

US3_TX #11

US3_RX #10

US3_CLK #9

US3_CS #8

US3_CTS #7

US3_RTS #6

I2C1_SDA #7

I2C1_SCL #6

WTIM0_CC0 #10

WTIM0_CC1 #8

WTIM0_CC2 #6

WTIM0_CDTI0 #2

WTIM0_CDTI1 #0

PCNT1_S0IN #6

PCNT1_S1IN #5

PCNT2_S0IN #6

PCNT2_S1IN #5

BUSDY

BUSCX

CMU_CLKI0 #3

ETM_TD1 #2

PB6

WTIM0_CC0 #11

WTIM0_CC1 #9

WTIM0_CC2 #7

WTIM0_CDTI0 #3

WTIM0_CDTI1 #1

PCNT1_S0IN #7

PCNT1_S1IN #6

PCNT2_S0IN #7

PCNT2_S1IN #6

BUSCY

BUSDX

PB7

ETM_TD2 #2

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US2_TX #11

US2_RX #10

US2_CLK #9

US2_CS #8

Radio

Other

WTIM0_CC0 #12

WTIM0_CC1 #10

WTIM0_CC2 #8

WTIM0_CDTI0 #4

WTIM0_CDTI1 #2

WTIM0_CDTI2 #0

PCNT1_S0IN #8

PCNT1_S1IN #7

PCNT2_S0IN #8

PCNT2_S1IN #7

US2_CTS #7

US2_RTS #6

US3_TX #12

US3_RX #11

US3_CLK #10

US3_CS #9

BUSDY

BUSCX

PB8

ETM_TD3 #2

US3_CTS #8

US3_RTS #7

I2C1_SDA #8

I2C1_SCL #7

US2_TX #12

US2_RX #11

US2_CLK #10

US2_CS #9

WTIM0_CC0 #13

WTIM0_CC1 #11

WTIM0_CC2 #9

WTIM0_CDTI0 #5

WTIM0_CDTI1 #3

WTIM0_CDTI2 #1

PCNT1_S0IN #9

PCNT1_S1IN #8

PCNT2_S0IN #9

PCNT2_S1IN #8

US2_CTS #8

US2_RTS #7

US3_TX #13

US3_RX #12

US3_CLK #11

US3_CS #10

US3_CTS #9

US3_RTS #8

I2C1_SDA #9

I2C1_SCL #8

OPA2_OUTALT #0

BUSCY

PB9

BUSDX

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US2_TX #13

US2_RX #12

US2_CLK #11

US2_CS #10

US2_CTS #9

US2_RTS #8

US3_TX #14

US3_RX #13

US3_CLK #12

US3_CS #11

US3_CTS #10

US3_RTS #9

I2C1_SDA #10

I2C1_SCL #9

Radio

Other

WTIM0_CC0 #14

WTIM0_CC1 #12

WTIM0_CC2 #10

WTIM0_CDTI0 #6

WTIM0_CDTI1 #4

WTIM0_CDTI2 #2

PCNT1_S0IN #10

PCNT1_S1IN #9

PCNT2_S0IN #10

PCNT2_S1IN #9

OPA2_OUTALT #1

BUSDY

PB10

BUSCX

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #6

Radio

Other

TIM0_CC0 #6

TIM0_CC1 #5

US0_RX #5

US0_CLK #4

US0_CS #3

TIM0_CC2 #4

TIM0_CDTI0 #3

TIM0_CDTI1 #2

TIM0_CDTI2 #1

TIM1_CC0 #6

US0_CTS #2

US0_RTS #1

US1_TX #6

US1_RX #5

FRC_DCLK #6

FRC_DOUT #5

TIM1_CC1 #5

US1_CLK #4

US1_CS #3

PRS_CH6 #6

PRS_CH7 #5

PRS_CH8 #4

PRS_CH9 #3

ACMP0_O #6

ACMP1_O #6

TIM1_CC2 #4

FRC_DFRAME #4

MODEM_DCLK #6

MODEM_DIN #5

MODEM_DOUT #4

MODEM_ANT0 #3

MODEM_ANT1 #2

BUSCY

BUSDX

OPA2_P

TIM1_CC3 #3

US1_CTS #2

US1_RTS #1

US3_TX #15

US3_RX #14

US3_CLK #13

US3_CS #12

US3_CTS #11

US3_RTS #10

LEU0_TX #6

LEU0_RX #5

I2C0_SDA #6

I2C0_SCL #5

PB11

WTIM0_CC0 #15

WTIM0_CC1 #13

WTIM0_CC2 #11

WTIM0_CDTI0 #7

WTIM0_CDTI1 #5

WTIM0_CDTI2 #3

LETIM0_OUT0 #6

LETIM0_OUT1 #5

PCNT0_S0IN #6

PCNT0_S1IN #5

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #7

TIM0_CC1 #6

TIM0_CC2 #5

US0_TX #7

US0_RX #6

US0_CLK #5

US0_CS #4

US0_CTS #3

US0_RTS #2

US1_TX #7

US1_RX #6

US1_CLK #5

US1_CS #4

US1_CTS #3

US1_RTS #2

LEU0_TX #7

LEU0_RX #6

I2C0_SDA #7

I2C0_SCL #6

TIM0_CDTI0 #4

TIM0_CDTI1 #3

TIM0_CDTI2 #2

TIM1_CC0 #7

FRC_DCLK #7

FRC_DOUT #6

TIM1_CC1 #6

PRS_CH6 #7

PRS_CH7 #6

PRS_CH8 #5

PRS_CH9 #4

ACMP0_O #7

ACMP1_O #7

TIM1_CC2 #5

FRC_DFRAME #5

MODEM_DCLK #7

MODEM_DIN #6

MODEM_DOUT #5

MODEM_ANT0 #4

MODEM_ANT1 #3

BUSDY

BUSCX

TIM1_CC3 #4

PB12

WTIM0_CC0 #16

WTIM0_CC1 #14

WTIM0_CC2 #12

WTIM0_CDTI0 #8

WTIM0_CDTI1 #6

WTIM0_CDTI2 #4

WTIM1_CC0 #0

LETIM0_OUT0 #7

LETIM0_OUT1 #6

PCNT0_S0IN #7

PCNT0_S1IN #6

OPA2_OUT

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #8

TIM0_CC1 #7

TIM0_CC2 #6

US0_TX #8

US0_RX #7

US0_CLK #6

US0_CS #5

US0_CTS #4

US0_RTS #3

US1_TX #8

US1_RX #7

US1_CLK #6

US1_CS #5

US1_CTS #4

US1_RTS #3

LEU0_TX #8

LEU0_RX #7

I2C0_SDA #8

I2C0_SCL #7

TIM0_CDTI0 #5

TIM0_CDTI1 #4

TIM0_CDTI2 #3

TIM1_CC0 #8

CMU_CLKI0 #0

PRS_CH6 #8

PRS_CH7 #7

PRS_CH8 #6

PRS_CH9 #5

ACMP0_O #8

ACMP1_O #8

DBG_SWO #1

GPIO_EM4WU9

FRC_DCLK #8

FRC_DOUT #7

TIM1_CC1 #7

TIM1_CC2 #6

FRC_DFRAME #6

MODEM_DCLK #8

MODEM_DIN #7

MODEM_DOUT #6

MODEM_ANT0 #5

MODEM_ANT1 #4

BUSCY

BUSDX

OPA2_N

TIM1_CC3 #5

PB13

WTIM0_CC0 #17

WTIM0_CC1 #15

WTIM0_CC2 #13

WTIM0_CDTI0 #9

WTIM0_CDTI1 #7

WTIM0_CDTI2 #5

WTIM1_CC0 #1

LETIM0_OUT0 #8

LETIM0_OUT1 #7

PCNT0_S0IN #8

PCNT0_S1IN #7

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #9

TIM0_CC1 #8

TIM0_CC2 #7

TIM0_CDTI0 #6

TIM0_CDTI1 #5

TIM0_CDTI2 #4

TIM1_CC0 #9

US0_TX #9

US0_RX #8

US0_CLK #7

US0_CS #6

US0_CTS #5

US0_RTS #4

US1_TX #9

US1_RX #8

US1_CLK #7

US1_CS #6

US1_CTS #5

US1_RTS #4

LEU0_TX #9

LEU0_RX #8

I2C0_SDA #9

I2C0_SCL #8

TIM1_CC1 #8

FRC_DCLK #9

FRC_DOUT #8

CMU_CLK1 #1

PRS_CH6 #9

PRS_CH7 #8

PRS_CH8 #7

PRS_CH9 #6

ACMP0_O #9

ACMP1_O #9

TIM1_CC2 #7

TIM1_CC3 #6

FRC_DFRAME #7

MODEM_DCLK #9

MODEM_DIN #8

MODEM_DOUT #7

MODEM_ANT0 #6

MODEM_ANT1 #5

BUSDY

BUSCX

WTIM0_CC0 #18

WTIM0_CC1 #16

WTIM0_CC2 #14

WTIM0_CDTI0 #10

WTIM0_CDTI1 #8

WTIM0_CDTI2 #6

WTIM1_CC0 #2

WTIM1_CC1 #0

LETIM0_OUT0 #9

LETIM0_OUT1 #8

PCNT0_S0IN #9

PCNT0_S1IN #8

PB14

LFXTAL_N

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #10

TIM0_CC1 #9

TIM0_CC2 #8

TIM0_CDTI0 #7

TIM0_CDTI1 #6

TIM0_CDTI2 #5

TIM1_CC0 #10

TIM1_CC1 #9

US0_TX #10

US0_RX #9

US0_CLK #8

US0_CS #7

US0_CTS #6

US0_RTS #5

US1_TX #10

US1_RX #9

FRC_DCLK #10

FRC_DOUT #9

CMU_CLK0 #1

PRS_CH6 #10

PRS_CH7 #9

PRS_CH8 #8

PRS_CH9 #7

ACMP0_O #10

ACMP1_O #10

TIM1_CC2 #8

TIM1_CC3 #7

FRC_DFRAME #8

MODEM_DCLK #10

MODEM_DIN #9

MODEM_DOUT #8

MODEM_ANT0 #7

MODEM_ANT1 #6

BUSCY

BUSDX

WTIM0_CC0 #19

WTIM0_CC1 #17

WTIM0_CC2 #15

WTIM0_CDTI0 #11

WTIM0_CDTI1 #9

WTIM0_CDTI2 #7

WTIM1_CC0 #3

WTIM1_CC1 #1

LETIM0_OUT0 #10

LETIM0_OUT1 #9

PCNT0_S0IN #10

PCNT0_S1IN #9

WTIM0_CC0 #20

WTIM0_CC1 #18

WTIM0_CC2 #16

WTIM0_CDTI0 #12

WTIM0_CDTI1 #10

WTIM0_CDTI2 #8

WTIM1_CC0 #4

WTIM1_CC1 #2

WTIM1_CC2 #0

PCNT1_S0IN #13

PCNT1_S1IN #12

PCNT2_S0IN #13

PCNT2_S1IN #12

PB15

US1_CLK #8

US1_CS #7

LFXTAL_P

US1_CTS #6

US1_RTS #5

LEU0_TX #10

LEU0_RX #9

I2C0_SDA #10

I2C0_SCL #9

US3_TX #18

US3_RX #17

US3_CLK #16

US3_CS #15

US3_CTS #14

US3_RTS #13

I2C1_SDA #13

I2C1_SCL #12

BUSBY

BUSAX

PC0

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

WTIM0_CC0 #21

WTIM0_CC1 #19

WTIM0_CC2 #17

WTIM0_CDTI0 #13

WTIM0_CDTI1 #11

WTIM0_CDTI2 #9

WTIM1_CC0 #5

WTIM1_CC1 #3

WTIM1_CC2 #1

PCNT1_S0IN #14

PCNT1_S1IN #13

PCNT2_S0IN #14

PCNT2_S1IN #13

WTIM0_CC0 #22

WTIM0_CC1 #20

WTIM0_CC2 #18

WTIM0_CDTI0 #14

WTIM0_CDTI1 #12

WTIM0_CDTI2 #10

WTIM1_CC0 #6

WTIM1_CC1 #4

WTIM1_CC2 #2

WTIM1_CC3 #0

PCNT1_S0IN #15

PCNT1_S1IN #14

PCNT2_S0IN #15

PCNT2_S1IN #14

US3_TX #19

US3_RX #18

US3_CLK #17

US3_CS #16

US3_CTS #15

US3_RTS #14

I2C1_SDA #14

I2C1_SCL #13

BUSAY

BUSBX

PC1

US3_TX #20

US3_RX #19

US3_CLK #18

US3_CS #17

US3_CTS #16

US3_RTS #15

I2C1_SDA #15

I2C1_SCL #14

BUSBY

BUSAX

PC2

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

WTIM0_CC0 #23

WTIM0_CC1 #21

WTIM0_CC2 #19

WTIM0_CDTI0 #15

WTIM0_CDTI1 #13

WTIM0_CDTI2 #11

WTIM1_CC0 #7

WTIM1_CC1 #5

WTIM1_CC2 #3

WTIM1_CC3 #1

PCNT1_S0IN #16

PCNT1_S1IN #15

PCNT2_S0IN #16

PCNT2_S1IN #15

WTIM0_CC0 #24

WTIM0_CC1 #22

WTIM0_CC2 #20

WTIM0_CDTI0 #16

WTIM0_CDTI1 #14

WTIM0_CDTI2 #12

WTIM1_CC0 #8

WTIM1_CC1 #6

WTIM1_CC2 #4

WTIM1_CC3 #2

PCNT1_S0IN #17

PCNT1_S1IN #16

PCNT2_S0IN #17

PCNT2_S1IN #16

US3_TX #21

US3_RX #20

US3_CLK #19

US3_CS #18

US3_CTS #17

US3_RTS #16

I2C1_SDA #16

I2C1_SCL #15

BUSAY

BUSBX

PC3

US3_TX #22

US3_RX #21

US3_CLK #20

US3_CS #19

US3_CTS #18

US3_RTS #17

I2C1_SDA #17

I2C1_SCL #16

BUSBY

BUSAX

PC4

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

WTIM0_CC0 #25

WTIM0_CC1 #23

WTIM0_CC2 #21

WTIM0_CDTI0 #17

WTIM0_CDTI1 #15

WTIM0_CDTI2 #13

WTIM1_CC0 #9

WTIM1_CC1 #7

WTIM1_CC2 #5

WTIM1_CC3 #3

PCNT1_S0IN #18

PCNT1_S1IN #17

PCNT2_S0IN #18

PCNT2_S1IN #17

US3_TX #23

US3_RX #22

US3_CLK #21

US3_CS #20

US3_CTS #19

US3_RTS #18

I2C1_SDA #18

I2C1_SCL #17

BUSAY

BUSBX

PC5

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #11

TIM0_CC1 #10

TIM0_CC2 #9

TIM0_CDTI0 #8

TIM0_CDTI1 #7

TIM0_CDTI2 #6

TIM1_CC0 #11

TIM1_CC1 #10

TIM1_CC2 #9

US0_TX #11

US0_RX #10

US0_CLK #9

US0_CS #8

CMU_CLK0 #2

CMU_CLKI0 #2

PRS_CH0 #8

US0_CTS #7

US0_RTS #6

US1_TX #11

US1_RX #10

US1_CLK #9

US1_CS #8

FRC_DCLK #11

FRC_DOUT #10

TIM1_CC3 #8

WTIM0_CC0 #26

WTIM0_CC1 #24

WTIM0_CC2 #22

WTIM0_CDTI0 #18

WTIM0_CDTI1 #16

WTIM0_CDTI2 #14

WTIM1_CC0 #10

WTIM1_CC1 #8

WTIM1_CC2 #6

WTIM1_CC3 #4

LETIM0_OUT0 #11

LETIM0_OUT1 #10

PCNT0_S0IN #11

PCNT0_S1IN #10

FRC_DFRAME #9

MODEM_DCLK #11

MODEM_DIN #10

MODEM_DOUT #9

MODEM_ANT0 #8

MODEM_ANT1 #7

PRS_CH9 #11

PRS_CH10 #0

PRS_CH11 #5

ACMP0_O #11

ACMP1_O #11

ETM_TCLK #3

BUSBY

BUSAX

PC6

US1_CTS #7

US1_RTS #6

LEU0_TX #11

LEU0_RX #10

I2C0_SDA #11

I2C0_SCL #10

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #12

TIM0_CC1 #11

TIM0_CC2 #10

TIM0_CDTI0 #9

TIM0_CDTI1 #8

TIM0_CDTI2 #7

TIM1_CC0 #12

TIM1_CC1 #11

TIM1_CC2 #10

TIM1_CC3 #9

US0_TX #12

US0_RX #11

US0_CLK #10

US0_CS #9

US0_CTS #8

US0_RTS #7

US1_TX #12

US1_RX #11

US1_CLK #10

US1_CS #9

FRC_DCLK #12

FRC_DOUT #11

CMU_CLK1 #2

PRS_CH0 #9

PRS_CH9 #12

PRS_CH10 #1

PRS_CH11 #0

ACMP0_O #12

ACMP1_O #12

ETM_TD0 #3

WTIM0_CC0 #27

WTIM0_CC1 #25

WTIM0_CC2 #23

WTIM0_CDTI0 #19

WTIM0_CDTI1 #17

WTIM0_CDTI2 #15

WTIM1_CC0 #11

WTIM1_CC1 #9

WTIM1_CC2 #7

WTIM1_CC3 #5

LETIM0_OUT0 #12

LETIM0_OUT1 #11

PCNT0_S0IN #12

PCNT0_S1IN #11

FRC_DFRAME #10

MODEM_DCLK #12

MODEM_DIN #11

MODEM_DOUT #10

MODEM_ANT0 #9

MODEM_ANT1 #8

BUSAY

BUSBX

PC7

US1_CTS #8

US1_RTS #7

LEU0_TX #12

LEU0_RX #11

I2C0_SDA #12

I2C0_SCL #11

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #13

TIM0_CC1 #12

TIM0_CC2 #11

TIM0_CDTI0 #10

TIM0_CDTI1 #9

TIM0_CDTI2 #8

TIM1_CC0 #13

US0_TX #13

US0_RX #12

US0_CLK #11

US0_CS #10

US0_CTS #9

US0_RTS #8

US1_TX #13

US1_RX #12

US1_CLK #11

US1_CS #10

US1_CTS #9

US1_RTS #8

LEU0_TX #13

LEU0_RX #12

I2C0_SDA #13

I2C0_SCL #12

TIM1_CC1 #12

TIM1_CC2 #11

FRC_DCLK #13

FRC_DOUT #12

PRS_CH0 #10

PRS_CH9 #13

PRS_CH10 #2

PRS_CH11 #1

ACMP0_O #13

ACMP1_O #13

ETM_TD1 #3

TIM1_CC3 #10

WTIM0_CC0 #28

WTIM0_CC1 #26

WTIM0_CC2 #24

WTIM0_CDTI0 #20

WTIM0_CDTI1 #18

WTIM0_CDTI2 #16

WTIM1_CC0 #12

WTIM1_CC1 #10

WTIM1_CC2 #8

WTIM1_CC3 #6

LETIM0_OUT0 #13

LETIM0_OUT1 #12

PCNT0_S0IN #13

PCNT0_S1IN #12

FRC_DFRAME #11

MODEM_DCLK #13

MODEM_DIN #12

MODEM_DOUT #11

MODEM_ANT0 #10

MODEM_ANT1 #9

BUSBY

BUSAX

PC8

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #14

TIM0_CC1 #13

TIM0_CC2 #12

TIM0_CDTI0 #11

TIM0_CDTI1 #10

TIM0_CDTI2 #9

TIM1_CC0 #14

US0_TX #14

US0_RX #13

US0_CLK #12

US0_CS #11

US0_CTS #10

US0_RTS #9

US1_TX #14

US1_RX #13

US1_CLK #12

US1_CS #11

US1_CTS #10

US1_RTS #9

LEU0_TX #14

LEU0_RX #13

I2C0_SDA #14

I2C0_SCL #13

TIM1_CC1 #13

TIM1_CC2 #12

FRC_DCLK #14

FRC_DOUT #13

PRS_CH0 #11

PRS_CH9 #14

PRS_CH10 #3

PRS_CH11 #2

ACMP0_O #14

ACMP1_O #14

ETM_TD2 #3

TIM1_CC3 #11

WTIM0_CC0 #29

WTIM0_CC1 #27

WTIM0_CC2 #25

WTIM0_CDTI0 #21

WTIM0_CDTI1 #19

WTIM0_CDTI2 #17

WTIM1_CC0 #13

WTIM1_CC1 #11

WTIM1_CC2 #9

WTIM1_CC3 #7

LETIM0_OUT0 #14

LETIM0_OUT1 #13

PCNT0_S0IN #14

PCNT0_S1IN #13

FRC_DFRAME #12

MODEM_DCLK #14

MODEM_DIN #13

MODEM_DOUT #12

MODEM_ANT0 #11

MODEM_ANT1 #10

BUSAY

BUSBX

PC9

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #15

TIM0_CC1 #14

TIM0_CC2 #13

TIM0_CDTI0 #12

TIM0_CDTI1 #11

TIM0_CDTI2 #10

TIM1_CC0 #15

US0_TX #15

US0_RX #14

US0_CLK #13

US0_CS #12

US0_CTS #11

US0_RTS #10

US1_TX #15

US1_RX #14

US1_CLK #13

US1_CS #12

US1_CTS #11

US1_RTS #10

LEU0_TX #15

LEU0_RX #14

I2C0_SDA #15

I2C0_SCL #14

I2C1_SDA #19

I2C1_SCL #18

TIM1_CC1 #14

TIM1_CC2 #13

CMU_CLK1 #3

PRS_CH0 #12

PRS_CH9 #15

PRS_CH10 #4

PRS_CH11 #3

ACMP0_O #15

ACMP1_O #15

ETM_TD3 #3

TIM1_CC3 #12

FRC_DCLK #15

FRC_DOUT #14

WTIM0_CC0 #30

WTIM0_CC1 #28

WTIM0_CC2 #26

WTIM0_CDTI0 #22

WTIM0_CDTI1 #20

WTIM0_CDTI2 #18

WTIM1_CC0 #14

WTIM1_CC1 #12

WTIM1_CC2 #10

WTIM1_CC3 #8

LETIM0_OUT0 #15

LETIM0_OUT1 #14

PCNT0_S0IN #15

PCNT0_S1IN #14

PCNT2_S0IN #19

PCNT2_S1IN #18

FRC_DFRAME #13

MODEM_DCLK #15

MODEM_DIN #14

MODEM_DOUT #13

MODEM_ANT0 #12

MODEM_ANT1 #11

BUSBY

BUSAX

PC10

GPIO_EM4WU12

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #16

TIM0_CC1 #15

TIM0_CC2 #14

TIM0_CDTI0 #13

TIM0_CDTI1 #12

TIM0_CDTI2 #11

TIM1_CC0 #16

US0_TX #16

US0_RX #15

US0_CLK #14

US0_CS #13

US0_CTS #12

US0_RTS #11

US1_TX #16

US1_RX #15

US1_CLK #14

US1_CS #13

US1_CTS #12

US1_RTS #11

LEU0_TX #16

LEU0_RX #15

I2C0_SDA #16

I2C0_SCL #15

I2C1_SDA #20

I2C1_SCL #19

TIM1_CC1 #15

TIM1_CC2 #14

TIM1_CC3 #13

FRC_DCLK #16

FRC_DOUT #15

CMU_CLK0 #3

PRS_CH0 #13

PRS_CH9 #16

PRS_CH10 #5

PRS_CH11 #4

ACMP0_O #16

ACMP1_O #16

DBG_SWO #3

WTIM0_CC0 #31

WTIM0_CC1 #29

WTIM0_CC2 #27

WTIM0_CDTI0 #23

WTIM0_CDTI1 #21

WTIM0_CDTI2 #19

WTIM1_CC0 #15

WTIM1_CC1 #13

WTIM1_CC2 #11

WTIM1_CC3 #9

LETIM0_OUT0 #16

LETIM0_OUT1 #15

PCNT0_S0IN #16

PCNT0_S1IN #15

PCNT2_S0IN #20

PCNT2_S1IN #19

WTIM0_CC1 #30

WTIM0_CC2 #28

WTIM0_CDTI0 #24

WTIM0_CDTI1 #22

WTIM0_CDTI2 #20

WTIM1_CC0 #16

WTIM1_CC1 #14

WTIM1_CC2 #12

WTIM1_CC3 #10

FRC_DFRAME #14

MODEM_DCLK #16

MODEM_DIN #15

MODEM_DOUT #14

MODEM_ANT0 #13

MODEM_ANT1 #12

BUSAY

BUSBX

PC11

US3_TX #0

US3_RX #31

US3_CLK #30

US3_CS #29

US3_CTS #28

US3_RTS #27

BUSDY

BUSCX

PD8

LES_CH0

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #17

US0_TX #17

US0_RX #16

US0_CLK #15

US0_CS #14

US0_CTS #13

US0_RTS #12

US1_TX #17

US1_RX #16

US1_CLK #15

US1_CS #14

US1_CTS #13

US1_RTS #12

US3_TX #1

TIM0_CC1 #16

TIM0_CC2 #15

TIM0_CDTI0 #14

TIM0_CDTI1 #13

TIM0_CDTI2 #12

TIM1_CC0 #17

TIM1_CC1 #16

FRC_DCLK #17

FRC_DOUT #16

CMU_CLK0 #4

PRS_CH3 #8

PRS_CH4 #0

PRS_CH5 #6

PRS_CH6 #11

ACMP0_O #17

ACMP1_O #17

LES_CH1

TIM1_CC2 #15

TIM1_CC3 #14

FRC_DFRAME #15

MODEM_DCLK #17

MODEM_DIN #16

MODEM_DOUT #15

MODEM_ANT0 #14

MODEM_ANT1 #13

WTIM0_CC1 #31

WTIM0_CC2 #29

WTIM0_CDTI0 #25

WTIM0_CDTI1 #23

WTIM0_CDTI2 #21

WTIM1_CC0 #17

WTIM1_CC1 #15

WTIM1_CC2 #13

WTIM1_CC3 #11

LETIM0_OUT0 #17

LETIM0_OUT1 #16

PCNT0_S0IN #17

PCNT0_S1IN #16

BUSCY

BUSDX

PD9

US3_RX #0

US3_CLK #31

US3_CS #30

US3_CTS #29

US3_RTS #28

LEU0_TX #17

LEU0_RX #16

I2C0_SDA #17

I2C0_SCL #16

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #18

US0_RX #17

US0_CLK #16

US0_CS #15

US0_CTS #14

US0_RTS #13

US1_TX #18

US1_RX #17

US1_CLK #16

US1_CS #15

US1_CTS #14

US1_RTS #13

US3_TX #2

Radio

Other

TIM0_CC0 #18

TIM0_CC1 #17

TIM0_CC2 #16

TIM0_CDTI0 #15

TIM0_CDTI1 #14

TIM0_CDTI2 #13

TIM1_CC0 #18

TIM1_CC1 #17

FRC_DCLK #18

FRC_DOUT #17

CMU_CLK1 #4

PRS_CH3 #9

PRS_CH4 #1

PRS_CH5 #0

PRS_CH6 #12

ACMP0_O #18

ACMP1_O #18

LES_CH2

TIM1_CC2 #16

TIM1_CC3 #15

FRC_DFRAME #16

MODEM_DCLK #18

MODEM_DIN #17

MODEM_DOUT #16

MODEM_ANT0 #15

MODEM_ANT1 #14

BUSDY

BUSCX

WTIM0_CC2 #30

WTIM0_CDTI0 #26

WTIM0_CDTI1 #24

WTIM0_CDTI2 #22

WTIM1_CC0 #18

WTIM1_CC1 #16

WTIM1_CC2 #14

WTIM1_CC3 #12

LETIM0_OUT0 #18

LETIM0_OUT1 #17

PCNT0_S0IN #18

PCNT0_S1IN #17

PD10

US3_RX #1

US3_CLK #0

US3_CS #31

US3_CTS #30

US3_RTS #29

LEU0_TX #18

LEU0_RX #17

I2C0_SDA #18

I2C0_SCL #17

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #19

US0_RX #18

US0_CLK #17

US0_CS #16

US0_CTS #15

US0_RTS #14

US1_TX #19

US1_RX #18

US1_CLK #17

US1_CS #16

US1_CTS #15

US1_RTS #14

US3_TX #3

Radio

Other

TIM0_CC0 #19

TIM0_CC1 #18

TIM0_CC2 #17

TIM0_CDTI0 #16

TIM0_CDTI1 #15

TIM0_CDTI2 #14

TIM1_CC0 #19

TIM1_CC1 #18

FRC_DCLK #19

FRC_DOUT #18

PRS_CH3 #10

PRS_CH4 #2

PRS_CH5 #1

PRS_CH6 #13

ACMP0_O #19

ACMP1_O #19

LES_CH3

TIM1_CC2 #17

TIM1_CC3 #16

FRC_DFRAME #17

MODEM_DCLK #19

MODEM_DIN #18

MODEM_DOUT #17

MODEM_ANT0 #16

MODEM_ANT1 #15

BUSCY

BUSDX

WTIM0_CC2 #31

WTIM0_CDTI0 #27

WTIM0_CDTI1 #25

WTIM0_CDTI2 #23

WTIM1_CC0 #19

WTIM1_CC1 #17

WTIM1_CC2 #15

WTIM1_CC3 #13

LETIM0_OUT0 #19

LETIM0_OUT1 #18

PCNT0_S0IN #19

PCNT0_S1IN #18

PD11

US3_RX #2

US3_CLK #1

US3_CS #0

US3_CTS #31

US3_RTS #30

LEU0_TX #19

LEU0_RX #18

I2C0_SDA #19

I2C0_SCL #18

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #20

US0_RX #19

US0_CLK #18

US0_CS #17

US0_CTS #16

US0_RTS #15

US1_TX #20

US1_RX #19

US1_CLK #18

US1_CS #17

US1_CTS #16

US1_RTS #15

US3_TX #4

Radio

Other

TIM0_CC0 #20

TIM0_CC1 #19

TIM0_CC2 #18

TIM0_CDTI0 #17

TIM0_CDTI1 #16

TIM0_CDTI2 #15

TIM1_CC0 #20

FRC_DCLK #20

FRC_DOUT #19

TIM1_CC1 #19

PRS_CH3 #11

PRS_CH4 #3

PRS_CH5 #2

PRS_CH6 #14

ACMP0_O #20

ACMP1_O #20

LES_CH4

TIM1_CC2 #18

FRC_DFRAME #18

MODEM_DCLK #20

MODEM_DIN #19

MODEM_DOUT #18

MODEM_ANT0 #17

MODEM_ANT1 #16

VDAC0_OUT1ALT /

OPA1_OUTALT #0

TIM1_CC3 #17

PD12

WTIM0_CDTI0 #28

WTIM0_CDTI1 #26

WTIM0_CDTI2 #24

WTIM1_CC0 #20

WTIM1_CC1 #18

WTIM1_CC2 #16

WTIM1_CC3 #14

LETIM0_OUT0 #20

LETIM0_OUT1 #19

PCNT0_S0IN #20

PCNT0_S1IN #19

BUSDY

BUSCX

US3_RX #3

US3_CLK #2

US3_CS #1

US3_CTS #0

US3_RTS #31

LEU0_TX #20

LEU0_RX #19

I2C0_SDA #20

I2C0_SCL #19

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #21

US0_RX #20

US0_CLK #19

US0_CS #18

US0_CTS #17

US0_RTS #16

US1_TX #21

US1_RX #20

US1_CLK #19

US1_CS #18

US1_CTS #17

US1_RTS #16

US3_TX #5

Radio

Other

TIM0_CC0 #21

TIM0_CC1 #20

TIM0_CC2 #19

TIM0_CDTI0 #18

TIM0_CDTI1 #17

TIM0_CDTI2 #16

TIM1_CC0 #21

FRC_DCLK #21

FRC_DOUT #20

TIM1_CC1 #20

PRS_CH3 #12

PRS_CH4 #4

PRS_CH5 #3

PRS_CH6 #15

ACMP0_O #21

ACMP1_O #21

LES_CH5

TIM1_CC2 #19

VDAC0_OUT0ALT /

OPA0_OUTALT #1

FRC_DFRAME #19

MODEM_DCLK #21

MODEM_DIN #20

MODEM_DOUT #19

MODEM_ANT0 #18

MODEM_ANT1 #17

TIM1_CC3 #18

BUSCY

BUSDX

OPA1_P

PD13

WTIM0_CDTI0 #29

WTIM0_CDTI1 #27

WTIM0_CDTI2 #25

WTIM1_CC0 #21

WTIM1_CC1 #19

WTIM1_CC2 #17

WTIM1_CC3 #15

LETIM0_OUT0 #21

LETIM0_OUT1 #20

PCNT0_S0IN #21

PCNT0_S1IN #20

US3_RX #4

US3_CLK #3

US3_CS #2

US3_CTS #1

US3_RTS #0

LEU0_TX #21

LEU0_RX #20

I2C0_SDA #21

I2C0_SCL #20

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #22

US0_RX #21

US0_CLK #20

US0_CS #19

US0_CTS #18

US0_RTS #17

US1_TX #22

US1_RX #21

US1_CLK #20

US1_CS #19

US1_CTS #18

US1_RTS #17

US3_TX #6

Radio

Other

TIM0_CC0 #22

TIM0_CC1 #21

TIM0_CC2 #20

TIM0_CDTI0 #19

TIM0_CDTI1 #18

TIM0_CDTI2 #17

TIM1_CC0 #22

CMU_CLK0 #5

PRS_CH3 #13

PRS_CH4 #5

PRS_CH5 #4

PRS_CH6 #16

ACMP0_O #22

ACMP1_O #22

LES_CH6

FRC_DCLK #22

FRC_DOUT #21

TIM1_CC1 #21

TIM1_CC2 #20

FRC_DFRAME #20

MODEM_DCLK #22

MODEM_DIN #21

MODEM_DOUT #20

MODEM_ANT0 #19

MODEM_ANT1 #18

BUSDY

BUSCX

TIM1_CC3 #19

PD14

WTIM0_CDTI0 #30

WTIM0_CDTI1 #28

WTIM0_CDTI2 #26

WTIM1_CC0 #22

WTIM1_CC1 #20

WTIM1_CC2 #18

WTIM1_CC3 #16

LETIM0_OUT0 #22

LETIM0_OUT1 #21

PCNT0_S0IN #22

PCNT0_S1IN #21

VDAC0_OUT1 /

OPA1_OUT

US3_RX #5

US3_CLK #4

US3_CS #3

GPIO_EM4WU4

US3_CTS #2

US3_RTS #1

LEU0_TX #22

LEU0_RX #21

I2C0_SDA #22

I2C0_SCL #21

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #23

US0_RX #22

US0_CLK #21

US0_CS #20

US0_CTS #19

US0_RTS #18

US1_TX #23

US1_RX #22

US1_CLK #21

US1_CS #20

US1_CTS #19

US1_RTS #18

US3_TX #7

Radio

Other

TIM0_CC0 #23

TIM0_CC1 #22

TIM0_CC2 #21

TIM0_CDTI0 #20

TIM0_CDTI1 #19

TIM0_CDTI2 #18

TIM1_CC0 #23

CMU_CLK1 #5

PRS_CH3 #14

PRS_CH4 #6

PRS_CH5 #5

PRS_CH6 #17

ACMP0_O #23

ACMP1_O #23

LES_CH7

FRC_DCLK #23

FRC_DOUT #22

TIM1_CC1 #22

TIM1_CC2 #21

VDAC0_OUT0ALT /

OPA0_OUTALT #2

FRC_DFRAME #21

MODEM_DCLK #23

MODEM_DIN #22

MODEM_DOUT #21

MODEM_ANT0 #20

MODEM_ANT1 #19

TIM1_CC3 #20

BUSCY

BUSDX

OPA1_N

PD15

WTIM0_CDTI0 #31

WTIM0_CDTI1 #29

WTIM0_CDTI2 #27

WTIM1_CC0 #23

WTIM1_CC1 #21

WTIM1_CC2 #19

WTIM1_CC3 #17

LETIM0_OUT0 #23

LETIM0_OUT1 #22

PCNT0_S0IN #23

PCNT0_S1IN #22

US3_RX #6

US3_CLK #5

US3_CS #4

DBG_SWO #2

US3_CTS #3

US3_RTS #2

LEU0_TX #23

LEU0_RX #22

I2C0_SDA #23

I2C0_SCL #22

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #24

US0_RX #23

US0_CLK #22

US0_CS #21

US0_CTS #20

US0_RTS #19

US1_TX #24

US1_RX #23

US1_CLK #22

US1_CS #21

US1_CTS #20

US1_RTS #19

US2_TX #14

US2_RX #13

US2_CLK #12

US2_CS #11

US2_CTS #10

US2_RTS #9

LEU0_TX #24

LEU0_RX #23

I2C0_SDA #24

I2C0_SCL #23

Radio

Other

TIM0_CC0 #24

TIM0_CC1 #23

TIM0_CC2 #22

TIM0_CDTI0 #21

TIM0_CDTI1 #20

TIM0_CDTI2 #19

TIM1_CC0 #24

FRC_DCLK #24

FRC_DOUT #23

PRS_CH0 #0

PRS_CH1 #7

PRS_CH2 #6

PRS_CH3 #5

ACMP0_O #24

ACMP1_O #24

DBG_SWCLKTCK

BOOT_TX

TIM1_CC1 #23

TIM1_CC2 #22

FRC_DFRAME #22

MODEM_DCLK #24

MODEM_DIN #23

MODEM_DOUT #22

MODEM_ANT0 #21

MODEM_ANT1 #20

BUSBY

BUSAX

TIM1_CC3 #21

PF0

WTIM0_CDTI1 #30

WTIM0_CDTI2 #28

WTIM1_CC0 #24

WTIM1_CC1 #22

WTIM1_CC2 #20

WTIM1_CC3 #18

LETIM0_OUT0 #24

LETIM0_OUT1 #23

PCNT0_S0IN #24

PCNT0_S1IN #23

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #25

US0_RX #24

US0_CLK #23

US0_CS #22

US0_CTS #21

US0_RTS #20

US1_TX #25

US1_RX #24

US1_CLK #23

US1_CS #22

US1_CTS #21

US1_RTS #20

US2_TX #15

US2_RX #14

US2_CLK #13

US2_CS #12

US2_CTS #11

US2_RTS #10

LEU0_TX #25

LEU0_RX #24

I2C0_SDA #25

I2C0_SCL #24

Radio

Other

TIM0_CC0 #25

TIM0_CC1 #24

TIM0_CC2 #23

TIM0_CDTI0 #22

TIM0_CDTI1 #21

TIM0_CDTI2 #20

TIM1_CC0 #25

FRC_DCLK #25

FRC_DOUT #24

PRS_CH0 #1

PRS_CH1 #0

PRS_CH2 #7

PRS_CH3 #6

ACMP0_O #25

ACMP1_O #25

DBG_SWDIOTMS

BOOT_RX

TIM1_CC1 #24

TIM1_CC2 #23

FRC_DFRAME #23

MODEM_DCLK #25

MODEM_DIN #24

MODEM_DOUT #23

MODEM_ANT0 #22

MODEM_ANT1 #21

BUSAY

BUSBX

TIM1_CC3 #22

PF1

WTIM0_CDTI1 #31

WTIM0_CDTI2 #29

WTIM1_CC0 #25

WTIM1_CC1 #23

WTIM1_CC2 #21

WTIM1_CC3 #19

LETIM0_OUT0 #25

LETIM0_OUT1 #24

PCNT0_S0IN #25

PCNT0_S1IN #24

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

Radio

Other

TIM0_CC0 #26

TIM0_CC1 #25

US0_TX #26

US0_RX #25

US0_CLK #24

US0_CS #23

US0_CTS #22

US0_RTS #21

US1_TX #26

US1_RX #25

US1_CLK #24

US1_CS #23

US1_CTS #22

US1_RTS #21

LEU0_TX #26

LEU0_RX #25

I2C0_SDA #26

I2C0_SCL #25

TIM0_CC2 #24

TIM0_CDTI0 #23

TIM0_CDTI1 #22

TIM0_CDTI2 #21

TIM1_CC0 #26

CMU_CLK0 #6

PRS_CH0 #2

PRS_CH1 #1

PRS_CH2 #0

PRS_CH3 #7

ACMP0_O #26

ACMP1_O #26

DBG_TDO

FRC_DCLK #26

FRC_DOUT #25

TIM1_CC1 #25

FRC_DFRAME #24

MODEM_DCLK #26

MODEM_DIN #25

MODEM_DOUT #24

MODEM_ANT0 #23

MODEM_ANT1 #22

TIM1_CC2 #24

BUSBY

BUSAX

PF2

TIM1_CC3 #23

WTIM0_CDTI2 #30

WTIM1_CC0 #26

WTIM1_CC1 #24

WTIM1_CC2 #22

WTIM1_CC3 #20

LETIM0_OUT0 #26

LETIM0_OUT1 #25

PCNT0_S0IN #26

PCNT0_S1IN #25

DBG_SWO #0

GPIO_EM4WU0

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #27

US0_RX #26

US0_CLK #25

US0_CS #24

US0_CTS #23

US0_RTS #22

US1_TX #27

US1_RX #26

US1_CLK #25

US1_CS #24

US1_CTS #23

US1_RTS #22

US2_TX #16

US2_RX #15

US2_CLK #14

US2_CS #13

US2_CTS #12

US2_RTS #11

LEU0_TX #27

LEU0_RX #26

I2C0_SDA #27

I2C0_SCL #26

Radio

Other

TIM0_CC0 #27

TIM0_CC1 #26

TIM0_CC2 #25

TIM0_CDTI0 #24

TIM0_CDTI1 #23

TIM0_CDTI2 #22

TIM1_CC0 #27

FRC_DCLK #27

FRC_DOUT #26

CMU_CLK1 #6

PRS_CH0 #3

PRS_CH1 #2

PRS_CH2 #1

PRS_CH3 #0

ACMP0_O #27

ACMP1_O #27

DBG_TDI

TIM1_CC1 #26

FRC_DFRAME #25

MODEM_DCLK #27

MODEM_DIN #26

MODEM_DOUT #25

MODEM_ANT0 #24

MODEM_ANT1 #23

TIM1_CC2 #25

BUSAY

BUSBX

PF3

TIM1_CC3 #24

WTIM0_CDTI2 #31

WTIM1_CC0 #27

WTIM1_CC1 #25

WTIM1_CC2 #23

WTIM1_CC3 #21

LETIM0_OUT0 #27

LETIM0_OUT1 #26

PCNT0_S0IN #27

PCNT0_S1IN #26

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #28

US0_RX #27

US0_CLK #26

US0_CS #25

US0_CTS #24

US0_RTS #23

US1_TX #28

US1_RX #27

US1_CLK #26

US1_CS #25

US1_CTS #24

US1_RTS #23

US2_TX #17

US2_RX #16

US2_CLK #15

US2_CS #14

US2_CTS #13

US2_RTS #12

LEU0_TX #28

LEU0_RX #27

I2C0_SDA #28

I2C0_SCL #27

Radio

Other

TIM0_CC0 #28

TIM0_CC1 #27

TIM0_CC2 #26

TIM0_CDTI0 #25

TIM0_CDTI1 #24

TIM0_CDTI2 #23

TIM1_CC0 #28

FRC_DCLK #28

FRC_DOUT #27

PRS_CH0 #4

PRS_CH1 #3

PRS_CH2 #2

PRS_CH3 #1

ACMP0_O #28

ACMP1_O #28

TIM1_CC1 #27

FRC_DFRAME #26

MODEM_DCLK #28

MODEM_DIN #27

MODEM_DOUT #26

MODEM_ANT0 #25

MODEM_ANT1 #24

BUSBY

BUSAX

TIM1_CC2 #26

PF4

TIM1_CC3 #25

WTIM1_CC0 #28

WTIM1_CC1 #26

WTIM1_CC2 #24

WTIM1_CC3 #22

LETIM0_OUT0 #28

LETIM0_OUT1 #27

PCNT0_S0IN #28

PCNT0_S1IN #27

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #29

US0_RX #28

US0_CLK #27

US0_CS #26

US0_CTS #25

US0_RTS #24

US1_TX #29

US1_RX #28

US1_CLK #27

US1_CS #26

US1_CTS #25

US1_RTS #24

US2_TX #18

US2_RX #17

US2_CLK #16

US2_CS #15

US2_CTS #14

US2_RTS #13

LEU0_TX #29

LEU0_RX #28

I2C0_SDA #29

I2C0_SCL #28

Radio

Other

TIM0_CC0 #29

TIM0_CC1 #28

TIM0_CC2 #27

TIM0_CDTI0 #26

TIM0_CDTI1 #25

TIM0_CDTI2 #24

TIM1_CC0 #29

FRC_DCLK #29

FRC_DOUT #28

PRS_CH0 #5

PRS_CH1 #4

PRS_CH2 #3

PRS_CH3 #2

ACMP0_O #29

ACMP1_O #29

TIM1_CC1 #28

FRC_DFRAME #27

MODEM_DCLK #29

MODEM_DIN #28

MODEM_DOUT #27

MODEM_ANT0 #26

MODEM_ANT1 #25

BUSAY

BUSBX

TIM1_CC2 #27

PF5

TIM1_CC3 #26

WTIM1_CC0 #29

WTIM1_CC1 #27

WTIM1_CC2 #25

WTIM1_CC3 #23

LETIM0_OUT0 #29

LETIM0_OUT1 #28

PCNT0_S0IN #29

PCNT0_S1IN #28

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #30

US0_RX #29

US0_CLK #28

US0_CS #27

US0_CTS #26

US0_RTS #25

US1_TX #30

US1_RX #29

US1_CLK #28

US1_CS #27

US1_CTS #26

US1_RTS #25

US2_TX #19

US2_RX #18

US2_CLK #17

US2_CS #16

US2_CTS #15

US2_RTS #14

LEU0_TX #30

LEU0_RX #29

I2C0_SDA #30

I2C0_SCL #29

Radio

Other

TIM0_CC0 #30

TIM0_CC1 #29

TIM0_CC2 #28

TIM0_CDTI0 #27

TIM0_CDTI1 #26

TIM0_CDTI2 #25

TIM1_CC0 #30

FRC_DCLK #30

FRC_DOUT #29

CMU_CLK1 #7

PRS_CH0 #6

PRS_CH1 #5

PRS_CH2 #4

PRS_CH3 #3

ACMP0_O #30

ACMP1_O #30

TIM1_CC1 #29

TIM1_CC2 #28

FRC_DFRAME #28

MODEM_DCLK #30

MODEM_DIN #29

MODEM_DOUT #28

MODEM_ANT0 #27

MODEM_ANT1 #26

BUSBY

BUSAX

TIM1_CC3 #27

PF6

WTIM1_CC0 #30

WTIM1_CC1 #28

WTIM1_CC2 #26

WTIM1_CC3 #24

LETIM0_OUT0 #30

LETIM0_OUT1 #29

PCNT0_S0IN #30

PCNT0_S1IN #29

PCNT1_S0IN #19

PCNT1_S1IN #18

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US0_TX #31

US0_RX #30

US0_CLK #29

US0_CS #28

US0_CTS #27

US0_RTS #26

US1_TX #31

US1_RX #30

US1_CLK #29

US1_CS #28

US1_CTS #27

US1_RTS #26

US2_TX #20

US2_RX #19

US2_CLK #18

US2_CS #17

US2_CTS #16

US2_RTS #15

LEU0_TX #31

LEU0_RX #30

I2C0_SDA #31

I2C0_SCL #30

US2_TX #21

US2_RX #20

US2_CLK #19

US2_CS #18

US2_CTS #17

US2_RTS #16

I2C1_SDA #21

I2C1_SCL #20

Radio

Other

TIM0_CC0 #31

TIM0_CC1 #30

TIM0_CC2 #29

TIM0_CDTI0 #28

TIM0_CDTI1 #27

TIM0_CDTI2 #26

TIM1_CC0 #31

CMU_CLKI0 #1

CMU_CLK0 #7

PRS_CH0 #7

PRS_CH1 #6

PRS_CH2 #5

PRS_CH3 #4

ACMP0_O #31

ACMP1_O #31

GPIO_EM4WU1

FRC_DCLK #31

FRC_DOUT #30

TIM1_CC1 #30

TIM1_CC2 #29

FRC_DFRAME #29

MODEM_DCLK #31

MODEM_DIN #30

MODEM_DOUT #29

MODEM_ANT0 #28

MODEM_ANT1 #27

BUSAY

BUSBX

TIM1_CC3 #28

PF7

WTIM1_CC0 #31

WTIM1_CC1 #29

WTIM1_CC2 #27

WTIM1_CC3 #25

LETIM0_OUT0 #31

LETIM0_OUT1 #30

PCNT0_S0IN #31

PCNT0_S1IN #30

PCNT1_S0IN #20

PCNT1_S1IN #19

WTIM1_CC1 #30

WTIM1_CC2 #28

WTIM1_CC3 #26

PCNT1_S0IN #21

PCNT1_S1IN #20

PCNT2_S0IN #21

PCNT2_S1IN #20

BUSBY

BUSAX

PF8

ETM_TCLK #0

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US2_TX #22

US2_RX #21

US2_CLK #20

US2_CS #19

US2_CTS #18

US2_RTS #17

I2C1_SDA #22

I2C1_SCL #21

US2_TX #23

US2_RX #22

US2_CLK #21

US2_CS #20

US2_CTS #19

US2_RTS #18

I2C1_SDA #23

I2C1_SCL #22

US2_TX #24

US2_RX #23

US2_CLK #22

US2_CS #21

US2_CTS #20

US2_RTS #19

US3_TX #24

US3_RX #23

US3_CLK #22

US3_CS #21

US3_CTS #20

US3_RTS #19

I2C1_SDA #24

I2C1_SCL #23

Radio

Other

WTIM1_CC1 #31

WTIM1_CC2 #29

WTIM1_CC3 #27

PCNT1_S0IN #22

PCNT1_S1IN #21

PCNT2_S0IN #22

PCNT2_S1IN #21

BUSAY

BUSBX

PF9

ETM_TD0 #0

WTIM1_CC2 #30

WTIM1_CC3 #28

PCNT1_S0IN #23

PCNT1_S1IN #22

PCNT2_S0IN #23

PCNT2_S1IN #22

BUSBY

BUSAX

PF10

ETM_TD1 #0

WTIM1_CC2 #31

WTIM1_CC3 #29

PCNT1_S0IN #24

PCNT1_S1IN #23

PCNT2_S0IN #24

PCNT2_S1IN #23

BUSAY

BUSBX

PF11

ETM_TD2 #0

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US2_TX #25

US2_RX #24

US2_CLK #23

US2_CS #22

US2_CTS #21

US2_RTS #20

US3_TX #25

US3_RX #24

US3_CLK #23

US3_CS #22

US3_CTS #21

US3_RTS #20

I2C1_SDA #25

I2C1_SCL #24

US2_TX #26

US2_RX #25

US2_CLK #24

US2_CS #23

US2_CTS #22

US2_RTS #21

US3_TX #26

US3_RX #25

US3_CLK #24

US3_CS #23

US3_CTS #22

US3_RTS #21

I2C1_SDA #26

I2C1_SCL #25

Radio

Other

WTIM1_CC3 #30

PCNT1_S0IN #25

PCNT1_S1IN #24

PCNT2_S0IN #25

PCNT2_S1IN #24

BUSBY

BUSAX

PF12

ETM_TD3 #0

WTIM1_CC3 #31

PCNT1_S0IN #26

PCNT1_S1IN #25

PCNT2_S0IN #26

PCNT2_S1IN #25

BUSAY

BUSBX

PF13

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US2_TX #27

US2_RX #26

US2_CLK #25

US2_CS #24

US2_CTS #23

US2_RTS #22

US3_TX #27

US3_RX #26

US3_CLK #25

US3_CS #24

US3_CTS #23

US3_RTS #22

I2C1_SDA #27

I2C1_SCL #26

US2_TX #28

US2_RX #27

US2_CLK #26

US2_CS #25

US2_CTS #24

US2_RTS #23

US3_TX #28

US3_RX #27

US3_CLK #26

US3_CS #25

US3_CTS #24

US3_RTS #23

I2C1_SDA #28

I2C1_SCL #27

US2_TX #5

Radio

Other

PCNT1_S0IN #27

PCNT1_S1IN #26

PCNT2_S0IN #27

PCNT2_S1IN #26

BUSBY

BUSAX

PF14

PCNT1_S0IN #28

PCNT1_S1IN #27

PCNT2_S0IN #28

PCNT2_S1IN #27

BUSAY

BUSBX

PF15

US2_RX #4

BUSADC0Y

BUSADC0X

US2_CLK #3

US2_CS #2

PI0

LES_ALTEX4

US2_CTS #1

US2_RTS #0

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US2_TX #6

US2_RX #5

US2_CLK #4

US2_CS #3

US2_CTS #2

US2_RTS #1

US2_TX #7

US2_RX #6

US2_CLK #5

US2_CS #4

US2_CTS #3

US2_RTS #2

US3_TX #8

US3_RX #7

US3_CLK #6

US3_CS #5

US3_CTS #4

US3_RTS #3

I2C1_SDA #4

I2C1_SCL #3

US2_TX #8

US2_RX #7

US2_CLK #6

US2_CS #5

US2_CTS #4

US2_RTS #3

US3_TX #9

US3_RX #8

US3_CLK #7

US3_CS #6

US3_CTS #5

US3_RTS #4

I2C1_SDA #5

I2C1_SCL #4

Radio

Other

BUSADC0Y

BUSADC0X

PI1

LES_ALTEX5

PCNT1_S0IN #4

PCNT1_S1IN #3

PCNT2_S0IN #4

PCNT2_S1IN #3

BUSADC0Y

BUSADC0X

LES_ALTEX6

ETM_TCLK #2

PI2

PCNT1_S0IN #5

PCNT1_S1IN #4

PCNT2_S0IN #5

PCNT2_S1IN #4

BUSADC0Y

BUSADC0X

LES_ALTEX7

ETM_TD0 #2

PI3

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US3_TX #16

US3_RX #15

US3_CLK #14

US3_CS #13

US3_CTS #12

US3_RTS #11

I2C1_SDA #11

I2C1_SCL #10

US3_TX #17

US3_RX #16

US3_CLK #15

US3_CS #14

US3_CTS #13

US3_RTS #12

I2C1_SDA #12

I2C1_SCL #11

US2_TX #29

US2_RX #28

US2_CLK #27

US2_CS #26

US2_CTS #25

US2_RTS #24

US3_TX #29

US3_RX #28

US3_CLK #27

US3_CS #26

US3_CTS #25

US3_RTS #24

I2C1_SDA #29

I2C1_SCL #28

Radio

Other

PCNT1_S0IN #11

PCNT1_S1IN #10

PCNT2_S0IN #11

PCNT2_S1IN #10

BUSACMP1Y

BUSACMP1X

PJ14

LES_ALTEX2

PCNT1_S0IN #12

PCNT1_S1IN #11

PCNT2_S0IN #12

PCNT2_S1IN #11

BUSACMP1Y

BUSACMP1X

PJ15

LES_ALTEX3

PCNT1_S0IN #29

PCNT1_S1IN #28

PCNT2_S0IN #29

PCNT2_S1IN #28

PK0

IDAC0_OUT

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Pin Definitions

GPIO Name

Pin Alternate Functionality / Description

Analog

Timers

Communication

US2_TX #30

US2_RX #29

US2_CLK #28

US2_CS #27

US2_CTS #26

US2_RTS #25

US3_TX #30

US3_RX #29

US3_CLK #28

US3_CS #27

US3_CTS #26

US3_RTS #25

I2C1_SDA #30

I2C1_SCL #29

US2_TX #31

US2_RX #30

US2_CLK #29

US2_CS #28

US2_CTS #27

US2_RTS #26

US3_TX #31

US3_RX #30

US3_CLK #29

US3_CS #28

US3_CTS #27

US3_RTS #26

I2C1_SDA #31

I2C1_SCL #30

Radio

Other

PCNT1_S0IN #30

PCNT1_S1IN #29

PCNT2_S0IN #30

PCNT2_S1IN #29

PK1

PCNT1_S0IN #31

PCNT1_S1IN #30

PCNT2_S0IN #31

PCNT2_S1IN #30

PK2

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Pin Definitions

6.10 Alternate

Functionality Overview

A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-

nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO

pin. Refer to

6.9 GPIO Functionality Table

for a list of functions available on each GPIO pin.

Note:

Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 6.10.

Alternate Functionality Overview

Alternate

LOCATION

12 – 15

16 – 19

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

Functionality

0 – 3

0: PA0

1: PA1

2: PA2

3: PA3

0: PA0

1: PA1

2: PA2

3: PA3

0: PA0

4 – 7

4: PA4

5: PA5

6: PB11

7: PB12

4: PA4

5: PA5

6: PB11

7: PB12

8 – 11

8: PB13

9: PB14

20 – 23

24 – 27

28 – 31

28: PF4

29: PF5

30: PF6

31: PF7

28: PF4

29: PF5

30: PF6

31: PF7

Description

12: PC7

13: PC8

Analog comparator

ACMP0, digital out-

put.

ACMP0_O

ACMP1_O

10: PB15

14: PC9

11: PC6

8: PB13

9: PB14

12: PC7

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

Analog comparator

ACMP1, digital out-

put.

13: PC8

10: PB15

14: PC9

11: PC6

Analog to digital

converter ADC0 ex-

ternal reference in-

put negative pin.

ADC0_EXTN

ADC0_EXTP

0: PA1

Analog to digital

converter ADC0 ex-

ternal reference in-

put positive pin.

BOOT_RX

BOOT_TX

0: PF1

0: PF0

0: PA1

1: PB15

2: PC6

3: PC11

0: PA0

1: PB14

2: PC7

3: PC10

0: PB13

1: PF7

2: PC6

3: PB6

Bootloader RX.

Bootloader TX.

4: PD9

5: PD14

6: PF2

7: PF7

4: PD10

5: PD15

6: PF3

7: PF6

4: PA5

Clock Management

Unit, clock output

number 0.

CMU_CLK0

CMU_CLK1

CMU_CLKI0

Clock Management

Unit, clock output

number 1.

Clock Management

Unit, clock input

number 0.

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Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

Functionality

0 – 3

4 – 7

8 – 11

20 – 23

24 – 27

28 – 31

Description

0: PF0

Debug-interface

Serial Wire clock

input and JTAG

Test Clock.

DBG_SWCLKTCK

DBG_SWDIOTMS

DBG_SWO

Note that this func-

tion is enabled to

the pin out of reset,

and has a built-in

pull down.

0: PF1

Debug-interface

Serial Wire data in-

put / output and

JTAG Test Mode

Select.

Note that this func-

tion is enabled to

the pin out of reset,

and has a built-in

pull up.

0: PF2

Debug-interface

Serial Wire viewer

Output.

1: PB13

2: PD15

3: PC11

Note that this func-

tion is not enabled

after reset, and

must be enabled by

software to be

used.

0: PF3

Debug-interface

JTAG Test Data In.

Note that this func-

tion becomes avail-

able after the first

valid JTAG com-

mand is received,

and has a built-in

pull up when JTAG

is active.

DBG_TDI

0: PF2

Debug-interface

JTAG Test Data

Out.

Note that this func-

tion becomes avail-

able after the first

valid JTAG com-

mand is received.

DBG_TDO

0: PF8

1: PA5

2: PI2

Embedded Trace

Module ETM clock .

ETM_TCLK

3: PC6

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Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

Functionality

0 – 3

0: PF9

1: PA6

2: PI3

4 – 7

8 – 11

20 – 23

24 – 27

28 – 31

Description

Embedded Trace

Module ETM data

ETM_TD0

3: PC7

0: PF10

1: PA7

2: PB6

3: PC8

0: PF11

1: PA8

2: PB7

3: PC9

0: PF12

1: PA9

2: PB8

3: PC10

0: PA0

1: PA1

2: PA2

3: PA3

0: PA2

1: PA3

2: PA4

3: PA5

0: PA1

1: PA2

2: PA3

3: PA4

0: PF2

Embedded Trace

Module ETM data

ETM_TD1

Embedded Trace

Module ETM data

ETM_TD2

Embedded Trace

Module ETM data

ETM_TD3

4: PA4

8: PB13

9: PB14

12: PC7

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

12: PC9

16: PD10

20: PD14

24: PF2

13: PC10

17: PD11

21: PD15

25: PF3

28: PF4

29: PF5

30: PF6

31: PF7

28: PF6

29: PF7

30: PA0

31: PA1

28: PF5

29: PF6

30: PF7

31: PA0

5: PA5

13: PC8

Frame Controller,

Data Sniffer Clock.

FRC_DCLK

FRC_DFRAME

FRC_DOUT

6: PB11

7: PB12

4: PB11

5: PB12

6: PB13

7: PB14

4: PA5

10: PB15

14: PC9

11: PC6

8: PB15

9: PC6

Frame Controller,

Data Sniffer Frame

active

10: PC7

11: PC8

8: PB14

9: PB15

10: PC6

11: PC7

14: PC11

18: PD12

22: PF0

26: PF4

27: PF5

15: PD9

12: PC8

13: PC9

19: PD13

23: PF1

16: PD9

17: PD10

21: PD14

25: PF2

20: PD13

24: PF1

Frame Controller,

Data Sniffer Out-

put.

5: PB11

6: PB12

7: PB13

14: PC10

18: PD11

22: PD15

26: PF3

15: PC11

19: PD12

23: PF0

27: PF4

Pin can be used to

wake the system

up from EM4

GPIO_EM4WU0

GPIO_EM4WU1

GPIO_EM4WU4

0: PF7

Pin can be used to

wake the system

up from EM4

0: PD14

Pin can be used to

wake the system

up from EM4

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Pin Definitions

Alternate

LOCATION

Functionality

0 – 3

4 – 7

8 – 11

12 – 15

16 – 19

20 – 23

24 – 27

28 – 31

Description

0: PA3

Pin can be used to

wake the system

up from EM4

GPIO_EM4WU8

GPIO_EM4WU9

GPIO_EM4WU12

0: PB13

0: PC10

Pin can be used to

wake the system

up from EM4

Pin can be used to

wake the system

up from EM4

0: PA1

1: PA2

2: PA3

3: PA4

0: PA0

1: PA1

2: PA2

3: PA3

0: PA7

1: PA8

2: PA9

3: PI2

4: PA5

5: PB11

6: PB12

7: PB13

4: PA4

5: PA5

6: PB11

7: PB12

4: PI3

8: PB14

9: PB15

10: PC6

11: PC7

8: PB13

9: PB14

12: PC8

13: PC9

16: PD9

20: PD13

24: PF1

28: PF5

29: PF6

30: PF7

31: PA0

28: PF4

29: PF5

30: PF6

31: PF7

17: PD10

21: PD14

25: PF2

I2C0 Serial Clock

Line input / output.

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C1_SDA

14: PC10

18: PD11

22: PD15

26: PF3

15: PC11

19: PD12

23: PF0

27: PF4

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

12: PC7

13: PC8

I2C0 Serial Data in-

put / output.

10: PB15

14: PC9

11: PC6

8: PB9

12: PC0

13: PC1

16: PC4

17: PC5

20: PF8

21: PF9

24: PF12

28: PK0

25: PF13

29: PK1

5: PB6

6: PB7

7: PB8

4: PI2

9: PB10

I2C1 Serial Clock

Line input / output.

10: PJ14

14: PC2

18: PC10

22: PF10

26: PF14

30: PK2

19: PC11

23: PF11

27: PF15

31: PA6

12: PJ15

16: PC3

20: PC11

24: PF11

28: PF15

11: PJ15

15: PC3

0: PA6

1: PA7

2: PA8

3: PA9

0: PK0

0: PA8

8: PB8

9: PB9

5: PI3

13: PC0

17: PC4

18: PC5

21: PF8

22: PF9

25: PF12

29: PK0

26: PF13

30: PK1

I2C1 Serial Data in-

put / output.

6: PB6

7: PB7

10: PB10

14: PC1

11: PJ14

15: PC2

19: PC10

23: PF10

27: PF14

31: PK2

IDAC0_OUT

LES_ALTEX0

IDAC0 output.

LESENSE alternate

excite output 0.

0: PA9

0: PJ14

0: PJ15

0: PI0

LESENSE alternate

excite output 1.

LES_ALTEX1

LES_ALTEX2

LES_ALTEX3

LES_ALTEX4

LES_ALTEX5

LES_ALTEX6

LES_ALTEX7

LESENSE alternate

excite output 2.

LESENSE alternate

excite output 3.

LESENSE alternate

excite output 4.

0: PI1

LESENSE alternate

excite output 5.

0: PI2

LESENSE alternate

excite output 6.

0: PI3

LESENSE alternate

excite output 7.

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Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

Functionality

0 – 3

4 – 7

8 – 11

20 – 23

24 – 27

28 – 31

Description

0: PD8

LESENSE channel

LES_CH0

LES_CH1

LES_CH2

LES_CH3

LES_CH4

LES_CH5

LES_CH6

LES_CH7

LES_CH8

LES_CH9

LES_CH10

LES_CH11

LES_CH12

LES_CH13

LES_CH14

LES_CH15

0: PD9

0: PD10

0: PD11

0: PD12

0: PD13

0: PD14

0: PD15

0: PA0

0: PA1

0: PA2

0: PA3

0: PA4

0: PA5

0: PA6

0: PA7

LESENSE channel

10.

LESENSE channel

11.

LESENSE channel

12.

LESENSE channel

13.

LESENSE channel

14.

LESENSE channel

15.

0: PA0

1: PA1

2: PA2

3: PA3

0: PA1

1: PA2

2: PA3

3: PA4

4: PA4

8: PB13

9: PB14

12: PC7

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

28: PF4

29: PF5

30: PF6

31: PF7

28: PF5

29: PF6

30: PF7

31: PA0

Low Energy Timer

LETIM0, output

channel 0.

5: PA5

13: PC8

LETIM0_OUT0

LETIM0_OUT1

6: PB11

7: PB12

4: PA5

10: PB15

14: PC9

11: PC6

8: PB14

9: PB15

10: PC6

11: PC7

12: PC8

13: PC9

16: PD9

20: PD13

24: PF1

Low Energy Timer

LETIM0, output

channel 1.

5: PB11

6: PB12

7: PB13

17: PD10

21: PD14

25: PF2

14: PC10

18: PD11

22: PD15

26: PF3

15: PC11

19: PD12

23: PF0

27: PF4

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0 – 3

0: PA1

1: PA2

2: PA3

3: PA4

0: PA0

1: PA1

2: PA2

3: PA3

0: PB14

4 – 7

4: PA5

8 – 11

8: PB14

9: PB15

10: PC6

11: PC7

8: PB13

9: PB14

12 – 15

16 – 19

20 – 23

24 – 27

28 – 31

28: PF5

29: PF6

30: PF7

31: PA0

28: PF4

29: PF5

30: PF6

31: PF7

Description

12: PC8

13: PC9

16: PD9

20: PD13

24: PF1

5: PB11

6: PB12

7: PB13

4: PA4

17: PD10

21: PD14

25: PF2

LEUART0 Receive

input.

LEU0_RX

LEU0_TX

14: PC10

18: PD11

22: PD15

26: PF3

15: PC11

19: PD12

23: PF0

27: PF4

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

12: PC7

13: PC8

LEUART0 Transmit

output. Also used

as receive input in

half duplex commu-

nication.

5: PA5

6: PB11

7: PB12

10: PB15

14: PC9

11: PC6

Low Frequency

Crystal (typically

32.768 kHz) nega-

tive pin. Also used

as an optional ex-

ternal clock input

pin.

LFXTAL_N

0: PB15

Low Frequency

Crystal (typically

32.768 kHz) posi-

tive pin.

LFXTAL_P

0: PA3

1: PA4

2: PA5

3: PB11

0: PA4

1: PA5

2: PB11

3: PB12

0: PA0

1: PA1

2: PA2

3: PA3

0: PA1

1: PA2

2: PA3

3: PA4

0: PA2

1: PA3

2: PA4

3: PA5

4: PB12

5: PB13

6: PB14

7: PB15

4: PB13

5: PB14

6: PB15

7: PC6

8: PC6

9: PC7

10: PC8

11: PC9

8: PC7

9: PC8

10: PC9

12: PC10

16: PD11

20: PD15

24: PF3

28: PF7

29: PA0

30: PA1

31: PA2

28: PA0

29: PA1

30: PA2

31: PA3

28: PF4

29: PF5

30: PF6

31: PF7

28: PF5

29: PF6

30: PF7

31: PA0

28: PF6

29: PF7

30: PA0

31: PA1

MODEM antenna

control output 0,

used for antenna

diversity.

13: PC11

17: PD12

21: PF0

14: PD9

18: PD13

22: PF1

25: PF4

26: PF5

27: PF6

24: PF4

25: PF5

26: PF6

27: PF7

MODEM_ANT0

15: PD10

19: PD14

23: PF2

12: PC11

16: PD12

20: PF0

MODEM antenna

control output 1,

used for antenna

diversity.

13: PD9

17: PD13

21: PF1

MODEM_ANT1

MODEM_DCLK

MODEM_DIN

14: PD10

18: PD14

22: PF2

11: PC10

15: PD11

19: PD15

23: PF3

4: PA4

8: PB13

9: PB14

12: PC7

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

5: PA5

13: PC8

MODEM data clock

out.

6: PB11

7: PB12

4: PA5

10: PB15

14: PC9

11: PC6

8: PB14

9: PB15

10: PC6

11: PC7

8: PB15

9: PC6

12: PC8

13: PC9

16: PD9

20: PD13

24: PF1

5: PB11

6: PB12

7: PB13

4: PB11

5: PB12

6: PB13

7: PB14

17: PD10

21: PD14

25: PF2

MODEM data in.

14: PC10

18: PD11

22: PD15

26: PF3

15: PC11

19: PD12

23: PF0

27: PF4

12: PC9

16: PD10

20: PD14

24: PF2

13: PC10

17: PD11

21: PD15

25: PF3

MODEM_DOUT

MODEM data out.

10: PC7

11: PC8

14: PC11

18: PD12

22: PF0

15: PD9

19: PD13

23: PF1

26: PF4

27: PF5

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

Functionality

0 – 3

4 – 7

8 – 11

20 – 23

24 – 27

28 – 31

Description

0: PA4

Operational Amplifi-

er 0 external nega-

tive input.

OPA0_N

OPA0_P

OPA1_N

OPA1_P

0: PA2

Operational Amplifi-

er 0 external posi-

tive input.

0: PD15

0: PD13

0: PB13

0: PB12

Operational Amplifi-

er 1 external nega-

tive input.

Operational Amplifi-

er 1 external posi-

tive input.

Operational Amplifi-

er 2 external nega-

tive input.

OPA2_N

Operational Amplifi-

er 2 output.

OPA2_OUT

OPA2_OUTALT

0: PB9

Operational Amplifi-

er 2 alternative out-

put.

1: PB10

0: PB11

Operational Amplifi-

er 2 external posi-

tive input.

OPA2_P

0: PA0

1: PA1

2: PA2

3: PA3

0: PA1

1: PA2

2: PA3

3: PA4

0: PA6

1: PA7

2: PA8

3: PA9

0: PA7

1: PA8

2: PA9

3: PI2

4: PA4

5: PA5

6: PB11

7: PB12

4: PA5

5: PB11

6: PB12

7: PB13

4: PI2

8: PB13

9: PB14

12: PC7

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

28: PF4

29: PF5

30: PF6

31: PF7

28: PF5

29: PF6

30: PF7

31: PA0

Pulse Counter

PCNT0 input num-

ber 0.

13: PC8

PCNT0_S0IN

10: PB15

14: PC9

11: PC6

8: PB14

9: PB15

10: PC6

11: PC7

8: PB8

12: PC8

13: PC9

16: PD9

20: PD13

24: PF1

Pulse Counter

PCNT0 input num-

ber 1.

17: PD10

21: PD14

25: PF2

PCNT0_S1IN

PCNT1_S0IN

PCNT1_S1IN

14: PC10

18: PD11

22: PD15

26: PF3

15: PC11

19: PD12

23: PF0

27: PF4

12: PJ15

16: PC3

20: PF7

21: PF8

22: PF9

24: PF11

28: PF15

25: PF12

29: PK0

26: PF13

30: PK1

Pulse Counter

PCNT1 input num-

ber 0.

5: PI3

9: PB9

13: PC0

17: PC4

18: PC5

19: PF6

16: PC4

17: PC5

18: PF6

19: PF7

6: PB6

7: PB7

4: PI3

10: PB10

14: PC1

11: PJ14

15: PC2

23: PF10

27: PF14

31: PK2

8: PB9

12: PC0

13: PC1

20: PF8

21: PF9

24: PF12

28: PK0

25: PF13

29: PK1

Pulse Counter

PCNT1 input num-

ber 1.

5: PB6

6: PB7

7: PB8

9: PB10

10: PJ14

14: PC2

11: PJ15

15: PC3

22: PF10

26: PF14

30: PK2

23: PF11

27: PF15

31: PA6

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

12: PJ15

16: PC3

Functionality

0 – 3

0: PA6

1: PA7

2: PA8

3: PA9

0: PA7

1: PA8

2: PA9

3: PI2

4 – 7

4: PI2

8 – 11

8: PB8

9: PB9

20 – 23

24 – 27

28 – 31

Description

20: PC11

24: PF11

28: PF15

Pulse Counter

PCNT2 input num-

ber 0.

5: PI3

13: PC0

17: PC4

18: PC5

21: PF8

22: PF9

25: PF12

29: PK0

26: PF13

30: PK1

PCNT2_S0IN

PCNT2_S1IN

PRS_CH0

PRS_CH1

PRS_CH2

PRS_CH3

PRS_CH4

PRS_CH5

PRS_CH6

6: PB6

7: PB7

4: PI3

10: PB10

14: PC1

11: PJ14

15: PC2

19: PC10

23: PF10

27: PF14

31: PK2

8: PB9

12: PC0

13: PC1

16: PC4

17: PC5

20: PF8

21: PF9

24: PF12

28: PK0

25: PF13

29: PK1

Pulse Counter

PCNT2 input num-

ber 1.

5: PB6

6: PB7

7: PB8

4: PF4

5: PF5

6: PF6

7: PF7

4: PF5

5: PF6

6: PF7

7: PF0

4: PF6

5: PF7

6: PF0

7: PF1

4: PF7

5: PF0

6: PF1

7: PF2

4: PD13

5: PD14

6: PD15

9: PB10

10: PJ14

14: PC2

11: PJ15

15: PC3

18: PC10

22: PF10

26: PF14

30: PK2

19: PC11

23: PF11

27: PF15

31: PA6

0: PF0

1: PF1

2: PF2

3: PF3

0: PF1

1: PF2

2: PF3

3: PF4

0: PF2

1: PF3

2: PF4

3: PF5

0: PF3

1: PF4

2: PF5

3: PF6

0: PD9

1: PD10

2: PD11

3: PD12

0: PD10

1: PD11

2: PD12

3: PD13

0: PA0

1: PA1

2: PA2

3: PA3

8: PC6

9: PC7

10: PC8

11: PC9

12: PC10

13: PC11

Peripheral Reflex

System PRS, chan-

nel 0.

Peripheral Reflex

System PRS, chan-

nel 1.

Peripheral Reflex

System PRS, chan-

nel 2.

8: PD9

12: PD13

13: PD14

Peripheral Reflex

System PRS, chan-

nel 3.

9: PD10

10: PD11

14: PD15

11: PD12

Peripheral Reflex

System PRS, chan-

nel 4.

4: PD14

5: PD15

6: PD9

Peripheral Reflex

System PRS, chan-

nel 5.

4: PA4

5: PA5

6: PB11

7: PB12

8: PB13

9: PB14

12: PD10

16: PD14

13: PD11

17: PD15

Peripheral Reflex

System PRS, chan-

nel 6.

10: PB15

14: PD12

11: PD9

15: PD13

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0 – 3

0: PA1

1: PA2

2: PA3

3: PA4

0: PA2

1: PA3

2: PA4

3: PA5

0: PA3

1: PA4

2: PA5

3: PB11

0: PC6

1: PC7

2: PC8

3: PC9

0: PC7

1: PC8

2: PC9

3: PC10

0: PA0

1: PA1

2: PA2

3: PA3

0: PA1

1: PA2

2: PA3

3: PA4

0: PA2

1: PA3

2: PA4

3: PA5

0: PA3

1: PA4

2: PA5

3: PB11

4 – 7

4: PA5

8 – 11

8: PB14

9: PB15

10: PA0

12 – 15

16 – 19

20 – 23

24 – 27

28 – 31

Description

Peripheral Reflex

System PRS, chan-

nel 7.

5: PB11

6: PB12

7: PB13

4: PB11

5: PB12

6: PB13

7: PB14

4: PB12

5: PB13

6: PB14

7: PB15

4: PC10

5: PC11

PRS_CH7

PRS_CH8

PRS_CH9

PRS_CH10

PRS_CH11

TIM0_CC0

TIM0_CC1

TIM0_CC2

TIM0_CDTI0

8: PB15

9: PA0

Peripheral Reflex

System PRS, chan-

nel 8.

10: PA1

8: PA0

9: PA1

10: PA2

11: PC6

12: PC7

13: PC8

14: PC9

15: PC10

16: PC11

Peripheral Reflex

System PRS, chan-

nel 9.

Peripheral Reflex

System PRS, chan-

nel 10.

4: PC11

5: PC6

Peripheral Reflex

System PRS, chan-

nel 11.

4: PA4

8: PB13

9: PB14

12: PC7

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

28: PF4

29: PF5

30: PF6

31: PF7

28: PF5

29: PF6

30: PF7

31: PA0

28: PF6

29: PF7

30: PA0

31: PA1

28: PF7

29: PA0

30: PA1

31: PA2

Timer 0 Capture

Compare input /

output channel 0.

5: PA5

13: PC8

6: PB11

7: PB12

4: PA5

10: PB15

14: PC9

11: PC6

8: PB14

9: PB15

10: PC6

11: PC7

8: PB15

9: PC6

12: PC8

13: PC9

16: PD9

20: PD13

24: PF1

Timer 0 Capture

Compare input /

output channel 1.

5: PB11

6: PB12

7: PB13

4: PB11

5: PB12

6: PB13

7: PB14

4: PB12

5: PB13

6: PB14

7: PB15

17: PD10

21: PD14

25: PF2

14: PC10

18: PD11

22: PD15

26: PF3

15: PC11

19: PD12

23: PF0

27: PF4

12: PC9

16: PD10

20: PD14

24: PF2

13: PC10

17: PD11

21: PD15

25: PF3

Timer 0 Capture

Compare input /

output channel 2.

10: PC7

11: PC8

8: PC6

14: PC11

18: PD12

22: PF0

15: PD9

19: PD13

23: PF1

26: PF4

27: PF5

12: PC10

16: PD11

20: PD15

24: PF3

Timer 0 Compli-

mentary Dead Time

Insertion channel 0.

9: PC7

13: PC11

17: PD12

21: PF0

14: PD9

18: PD13

22: PF1

15: PD10

19: PD14

23: PF2

25: PF4

26: PF5

27: PF6

10: PC8

11: PC9

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

12: PC11

16: PD12

20: PF0

13: PD9

17: PD13

21: PF1

14: PD10

18: PD14

22: PF2

Functionality

0 – 3

0: PA4

1: PA5

2: PB11

3: PB12

0: PA5

1: PB11

2: PB12

3: PB13

0: PA0

1: PA1

2: PA2

3: PA3

0: PA1

1: PA2

2: PA3

3: PA4

0: PA2

1: PA3

2: PA4

3: PA5

0: PA3

1: PA4

2: PA5

3: PB11

0: PA2

1: PA3

2: PA4

3: PA5

0: PA3

1: PA4

2: PA5

3: PB11

0: PA4

1: PA5

2: PB11

3: PB12

4 – 7

4: PB13

5: PB14

6: PB15

7: PC6

8 – 11

8: PC7

9: PC8

10: PC9

20 – 23

24 – 27

24: PF4

25: PF5

26: PF6

27: PF7

24: PF5

25: PF6

26: PF7

27: PA0

28 – 31

28: PA0

29: PA1

30: PA2

31: PA3

28: PA1

29: PA2

30: PA3

31: PA4

28: PF4

29: PF5

30: PF6

31: PF7

28: PF5

29: PF6

30: PF7

31: PA0

28: PF6

29: PF7

30: PA0

31: PA1

28: PF7

29: PA0

30: PA1

31: PA2

28: PF6

29: PF7

30: PA0

31: PA1

28: PF7

29: PA0

30: PA1

31: PA2

28: PA0

29: PA1

30: PA2

31: PA3

Description

Timer 0 Compli-

mentary Dead Time

Insertion channel 1.

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

TIM1_CC1

TIM1_CC2

TIM1_CC3

US0_CLK

US0_CS

11: PC10

15: PD11

19: PD15

23: PF3

4: PB14

5: PB15

6: PC6

8: PC8

9: PC9

12: PD9

16: PD13

20: PF1

Timer 0 Compli-

mentary Dead Time

Insertion channel 2.

13: PD10

17: PD14

21: PF2

10: PC10

14: PD11

18: PD15

22: PF3

11: PC11

15: PD12

19: PF0

23: PF4

7: PC7

4: PA4

8: PB13

9: PB14

12: PC7

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

Timer 1 Capture

Compare input /

output channel 0.

5: PA5

13: PC8

6: PB11

7: PB12

4: PA5

10: PB15

14: PC9

11: PC6

8: PB14

9: PB15

10: PC6

11: PC7

8: PB15

9: PC6

12: PC8

13: PC9

16: PD9

20: PD13

24: PF1

Timer 1 Capture

Compare input /

output channel 1.

5: PB11

6: PB12

7: PB13

4: PB11

5: PB12

6: PB13

7: PB14

4: PB12

5: PB13

6: PB14

7: PB15

4: PB11

5: PB12

6: PB13

7: PB14

4: PB12

5: PB13

6: PB14

7: PB15

4: PB13

5: PB14

6: PB15

7: PC6

17: PD10

21: PD14

25: PF2

14: PC10

18: PD11

22: PD15

26: PF3

15: PC11

19: PD12

23: PF0

27: PF4

12: PC9

16: PD10

20: PD14

24: PF2

13: PC10

17: PD11

21: PD15

25: PF3

Timer 1 Capture

Compare input /

output channel 2.

10: PC7

11: PC8

8: PC6

14: PC11

18: PD12

22: PF0

15: PD9

19: PD13

23: PF1

26: PF4

27: PF5

12: PC10

16: PD11

20: PD15

24: PF3

Timer 1 Capture

Compare input /

output channel 3.

9: PC7

13: PC11

17: PD12

21: PF0

14: PD9

18: PD13

22: PF1

15: PD10

19: PD14

23: PF2

12: PC9

13: PC10

17: PD11

21: PD15

25: PF3

25: PF4

26: PF5

27: PF6

10: PC8

11: PC9

8: PB15

9: PC6

16: PD10

20: PD14

24: PF2

USART0 clock in-

put / output.

10: PC7

11: PC8

8: PC6

14: PC11

18: PD12

22: PF0

15: PD9

19: PD13

23: PF1

26: PF4

27: PF5

12: PC10

16: PD11

20: PD15

24: PF3

9: PC7

13: PC11

17: PD12

21: PF0

14: PD9

18: PD13

22: PF1

25: PF4

26: PF5

27: PF6

24: PF4

25: PF5

26: PF6

27: PF7

USART0 chip se-

lect input / output.

10: PC8

11: PC9

8: PC7

15: PD10

19: PD14

23: PF2

12: PC11

16: PD12

20: PF0

USART0 Clear To

Send hardware

flow control input.

9: PC8

13: PD9

17: PD13

21: PF1

US0_CTS

10: PC9

14: PD10

18: PD14

22: PF2

11: PC10

15: PD11

19: PD15

23: PF3

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

12: PD9

16: PD13

20: PF1

13: PD10

17: PD14

21: PF2

Functionality

0 – 3

0: PA5

1: PB11

2: PB12

3: PB13

0: PA1

1: PA2

2: PA3

3: PA4

4 – 7

4: PB14

5: PB15

6: PC6

7: PC7

4: PA5

8 – 11

8: PC8

9: PC9

20 – 23

24 – 27

24: PF5

25: PF6

26: PF7

27: PA0

28 – 31

28: PA1

29: PA2

30: PA3

31: PA4

28: PF5

29: PF6

30: PF7

31: PA0

Description

USART0 Request

To Send hardware

flow control output.

US0_RTS

US0_RX

10: PC10

14: PD11

18: PD15

22: PF3

11: PC11

15: PD12

19: PF0

23: PF4

8: PB14

9: PB15

10: PC6

11: PC7

12: PC8

13: PC9

16: PD9

20: PD13

24: PF1

USART0 Asynchro-

nous Receive.

5: PB11

6: PB12

7: PB13

17: PD10

21: PD14

25: PF2

USART0 Synchro-

nous mode Master

Input / Slave Out-

put (MISO).

14: PC10

18: PD11

22: PD15

26: PF3

15: PC11

19: PD12

23: PF0

27: PF4

0: PA0

1: PA1

2: PA2

3: PA3

4: PA4

5: PA5

6: PB11

7: PB12

8: PB13

9: PB14

12: PC7

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

28: PF4

29: PF5

30: PF6

31: PF7

USART0 Asynchro-

nous Transmit. Al-

so used as receive

input in half duplex

communication.

13: PC8

10: PB15

14: PC9

US0_TX

11: PC6

USART0 Synchro-

nous mode Master

Output / Slave In-

put (MOSI).

0: PA2

1: PA3

2: PA4

3: PA5

0: PA3

1: PA4

2: PA5

3: PB11

0: PA4

1: PA5

2: PB11

3: PB12

0: PA5

1: PB11

2: PB12

3: PB13

0: PA1

1: PA2

2: PA3

3: PA4

4: PB11

5: PB12

6: PB13

7: PB14

4: PB12

5: PB13

6: PB14

7: PB15

4: PB13

5: PB14

6: PB15

7: PC6

8: PB15

9: PC6

10: PC7

11: PC8

8: PC6

9: PC7

10: PC8

11: PC9

8: PC7

9: PC8

10: PC9

12: PC9

16: PD10

20: PD14

24: PF2

28: PF6

29: PF7

30: PA0

31: PA1

28: PF7

29: PA0

30: PA1

31: PA2

28: PA0

29: PA1

30: PA2

31: PA3

28: PA1

29: PA2

30: PA3

31: PA4

28: PF5

29: PF6

30: PF7

31: PA0

13: PC10

17: PD11

21: PD15

25: PF3

USART1 clock in-

put / output.

US1_CLK

US1_CS

14: PC11

18: PD12

22: PF0

15: PD9

19: PD13

23: PF1

26: PF4

27: PF5

12: PC10

16: PD11

20: PD15

24: PF3

13: PC11

17: PD12

21: PF0

14: PD9

18: PD13

22: PF1

25: PF4

26: PF5

27: PF6

24: PF4

25: PF5

26: PF6

27: PF7

24: PF5

25: PF6

26: PF7

27: PA0

USART1 chip se-

lect input / output.

15: PD10

19: PD14

23: PF2

12: PC11

16: PD12

20: PF0

USART1 Clear To

Send hardware

flow control input.

13: PD9

17: PD13

21: PF1

US1_CTS

US1_RTS

14: PD10

18: PD14

22: PF2

11: PC10

15: PD11

19: PD15

23: PF3

4: PB14

5: PB15

6: PC6

8: PC8

9: PC9

12: PD9

16: PD13

20: PF1

USART1 Request

To Send hardware

flow control output.

13: PD10

17: PD14

21: PF2

10: PC10

14: PD11

18: PD15

22: PF3

11: PC11

15: PD12

19: PF0

23: PF4

7: PC7

4: PA5

8: PB14

9: PB15

10: PC6

11: PC7

12: PC8

13: PC9

16: PD9

20: PD13

24: PF1

USART1 Asynchro-

nous Receive.

5: PB11

6: PB12

7: PB13

17: PD10

21: PD14

25: PF2

USART1 Synchro-

nous mode Master

Input / Slave Out-

put (MISO).

US1_RX

14: PC10

18: PD11

22: PD15

26: PF3

15: PC11

19: PD12

23: PF0

27: PF4

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

16: PC11

20: PD12

24: PF0

17: PD9

21: PD13

25: PF1

18: PD10

22: PD14

26: PF2

15: PC10

19: PD11

23: PD15

27: PF3

Functionality

0 – 3

0: PA0

1: PA1

2: PA2

3: PA3

4 – 7

4: PA4

5: PA5

6: PB11

7: PB12

8 – 11

8: PB13

9: PB14

20 – 23

24 – 27

28 – 31

28: PF4

29: PF5

30: PF6

31: PF7

Description

12: PC7

13: PC8

USART1 Asynchro-

nous Transmit. Al-

so used as receive

input in half duplex

communication.

10: PB15

14: PC9

US1_TX

11: PC6

USART1 Synchro-

nous mode Master

Output / Slave In-

put (MOSI).

0: PA7

1: PA8

2: PA9

3: PI0

0: PA8

1: PA9

2: PI0

3: PI1

0: PA9

1: PI0

2: PI1

3: PI2

0: PI0

1: PI1

2: PI2

3: PI3

0: PA6

1: PA7

2: PA8

3: PA9

4: PI1

5: PI2

6: PI3

7: PB6

4: PI2

5: PI3

6: PB6

7: PB7

4: PI3

5: PB6

6: PB7

7: PB8

4: PB6

5: PB7

6: PB8

7: PB9

4: PI0

5: PI1

6: PI2

7: PI3

8: PB7

9: PB8

10: PB9

12: PF0

13: PF1

14: PF3

16: PF5

17: PF6

18: PF7

19: PF8

16: PF6

17: PF7

18: PF8

19: PF9

16: PF7

17: PF8

18: PF9

20: PF9

24: PF13

28: PK1

21: PF10

25: PF14

29: PK2

22: PF11

26: PF15

30: PA5

USART2 clock in-

put / output.

US2_CLK

US2_CS

11: PB10

15: PF4

23: PF12

27: PK0

31: PA6

8: PB8

9: PB9

12: PF1

13: PF3

20: PF10

24: PF14

28: PK2

21: PF11

25: PF15

29: PA5

USART2 chip se-

lect input / output.

10: PB10

14: PF4

22: PF12

26: PK0

23: PF13

27: PK1

30: PA6

31: PA7

11: PF0

8: PB9

15: PF5

12: PF3

13: PF4

14: PF5

15: PF6

12: PF4

13: PF5

14: PF6

15: PF7

20: PF11

24: PF15

28: PA5

USART2 Clear To

Send hardware

flow control input.

9: PB10

10: PF0

11: PF1

8: PB10

9: PF0

21: PF12

25: PK0

22: PF13

26: PK1

29: PA6

30: PA7

US2_CTS

US2_RTS

19: PF10

23: PF14

27: PK2

31: PA8

16: PF8

17: PF9

20: PF12

24: PK0

21: PF13

25: PK1

28: PA6

USART2 Request

To Send hardware

flow control output.

29: PA7

10: PF1

11: PF3

8: PB6

18: PF10

22: PF14

26: PK2

19: PF11

23: PF15

27: PA5

30: PA8

31: PA9

12: PB10

16: PF4

20: PF8

21: PF9

24: PF12

28: PK0

25: PF13

29: PK1

USART2 Asynchro-

nous Receive.

9: PB7

13: PF0

14: PF1

15: PF3

17: PF5

18: PF6

19: PF7

USART2 Synchro-

nous mode Master

Input / Slave Out-

put (MISO).

US2_RX

10: PB8

11: PB9

22: PF10

26: PF14

30: PK2

23: PF11

27: PF15

31: PA5

0: PA5

1: PA6

2: PA7

3: PA8

4: PA9

5: PI0

6: PI1

7: PI2

8: PI3

12: PB9

16: PF3

20: PF7

21: PF8

22: PF9

24: PF11

28: PF15

USART2 Asynchro-

nous Transmit. Al-

9: PB6

10: PB7

11: PB8

13: PB10

17: PF4

25: PF12

29: PK0

so used as receive

input in half duplex

26: PF13

30: PK1

14: PF0

15: PF1

18: PF5

19: PF6

communication.

US2_TX

23: PF10

27: PF14

31: PK2

USART2 Synchro-

nous mode Master

Output / Slave In-

put (MOSI).

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

Functionality

0 – 3

0: PD10

1: PD11

2: PD12

3: PD13

0: PD11

1: PD12

2: PD13

3: PD14

0: PD12

1: PD13

2: PD14

3: PD15

0: PD13

1: PD14

2: PD15

3: PI2

4 – 7

4: PD14

5: PD15

6: PI2

8 – 11

8: PB6

9: PB7

10: PB8

11: PB9

8: PB7

9: PB8

10: PB9

20 – 23

20: PC4

21: PC5

24 – 27

28 – 31

Description

12: PB10

16: PC0

13: PB11

17: PC1

14: PJ14

18: PC2

15: PJ15

19: PC3

12: PB11

16: PC1

13: PJ14

17: PC2

14: PJ15

18: PC3

24: PF13

28: PK1

25: PF14

29: PK2

USART3 clock in-

put / output.

US3_CLK

US3_CS

22: PF11

26: PF15

30: PD8

23: PF12

27: PK0

31: PD9

20: PC5

24: PF14

28: PK2

21: PF11

25: PF15

29: PD8

7: PI3

4: PD15

5: PI2

USART3 chip se-

lect input / output.

6: PI3

22: PF12

26: PK0

23: PF13

27: PK1

30: PD9

7: PB6

4: PI2

11: PB10

15: PC0

19: PC4

31: PD10

8: PB8

9: PB9

12: PJ14

16: PC2

13: PJ15

17: PC3

20: PF11

24: PF15

28: PD8

USART3 Clear To

Send hardware

flow control input.

5: PI3

21: PF12

25: PK0

22: PF13

26: PK1

23: PF14

27: PK2

20: PF12

24: PK0

21: PF13

25: PK1

22: PF14

26: PK2

29: PD9

US3_CTS

US3_RTS

6: PB6

7: PB7

4: PI3

10: PB10

14: PC0

11: PB11

15: PC1

18: PC4

19: PC5

30: PD10

31: PD11

28: PD9

8: PB9

12: PJ15

16: PC3

USART3 Request

To Send hardware

flow control output.

5: PB6

6: PB7

7: PB8

4: PD13

5: PD14

6: PD15

7: PI2

9: PB10

13: PC0

17: PC4

18: PC5

29: PD10

30: PD11

31: PD12

10: PB11

14: PC1

11: PJ14

15: PC2

19: PF11

23: PF15

27: PD8

0: PD9

8: PI3

12: PB9

16: PJ15

20: PC3

24: PF12

28: PK0

25: PF13

29: PK1

26: PF14

30: PK2

USART3 Asynchro-

nous Receive.

1: PD10

2: PD11

3: PD12

9: PB6

10: PB7

11: PB8

13: PB10

17: PC0

14: PB11

18: PC1

15: PJ14

19: PC2

21: PC4

22: PC5

USART3 Synchro-

nous mode Master

Input / Slave Out-

put (MISO).

US3_RX

23: PF11

27: PF15

31: PD8

0: PD8

1: PD9

2: PD10

3: PD11

4: PD12

5: PD13

6: PD14

7: PD15

8: PI2

12: PB8

13: PB9

16: PJ14

20: PC2

17: PJ15

21: PC3

24: PF11

28: PF15

USART3 Asynchro-

nous Transmit. Al-

9: PI3

25: PF12

29: PK0

so used as receive

input in half duplex

26: PF13

30: PK1

10: PB6

11: PB7

14: PB10

18: PC0

15: PB11

19: PC1

22: PC4

23: PC5

communication.

US3_TX

27: PF14

31: PK2

USART3 Synchro-

nous mode Master

Output / Slave In-

put (MOSI).

0: PA1

0: PA3

Digital to analog

converter VDAC0

external reference

input pin.

VDAC0_EXT

Digital to Analog

Converter DAC0

output channel

number 0.

VDAC0_OUT0 /

OPA0_OUT

0: PA5

Digital to Analog

Converter DAC0 al-

ternative output for

channel 0.

VDAC0_OUT0AL

T / OPA0_OUT-

ALT

1: PD13

2: PD15

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

Functionality

0 – 3

4 – 7

8 – 11

20 – 23

24 – 27

28 – 31

Description

0: PD14

Digital to Analog

Converter DAC0

output channel

number 1.

VDAC0_OUT1 /

OPA1_OUT

0: PD12

1: PA2

2: PA4

0: PA0

1: PA1

2: PA2

3: PA3

0: PA2

1: PA3

2: PA4

3: PA5

0: PA4

1: PA5

2: PA6

3: PA7

0: PA8

1: PA9

2: PB6

3: PB7

0: PB6

1: PB7

2: PB8

3: PB9

0: PB8

1: PB9

2: PB10

3: PB11

0: PB12

1: PB13

2: PB14

3: PB15

Digital to Analog

Converter DAC0 al-

ternative output for

channel 1.

VDAC0_OUT1AL

T / OPA1_OUT-

ALT

4: PA4

5: PA5

6: PA6

7: PA7

4: PA6

5: PA7

6: PA8

7: PA9

4: PA8

5: PA9

6: PB6

7: PB7

4: PB8

5: PB9

6: PB10

7: PB11

4: PB10

5: PB11

6: PB12

7: PB13

4: PB12

5: PB13

6: PB14

7: PB15

4: PC0

5: PC1

6: PC2

7: PC3

8: PA8

9: PA9

10: PB6

11: PB7

8: PB6

9: PB7

10: PB8

11: PB9

8: PB8

9: PB9

12: PB8

13: PB9

16: PB12

20: PC0

17: PB13

21: PC1

24: PC4

25: PC5

26: PC6

27: PC7

24: PC6

25: PC7

26: PC8

27: PC9

24: PC8

25: PC9

28: PC8

29: PC9

30: PC10

31: PC11

28: PC10

29: PC11

30: PD8

31: PD9

28: PD8

29: PD9

Wide timer 0 Cap-

ture Compare in-

put / output channel

WTIM0_CC0

WTIM0_CC1

WTIM0_CC2

WTIM0_CDTI0

WTIM0_CDTI1

WTIM0_CDTI2

WTIM1_CC0

14: PB10

18: PB14

22: PC2

15: PB11

19: PB15

23: PC3

12: PB10

16: PB14

20: PC2

13: PB11

17: PB15

21: PC3

Wide timer 0 Cap-

ture Compare in-

put / output channel

14: PB12

18: PC0

15: PB13

19: PC1

12: PB12

16: PC0

13: PB13

17: PC1

22: PC4

23: PC5

20: PC4

21: PC5

22: PC6

23: PC7

20: PC8

21: PC9

Wide timer 0 Cap-

ture Compare in-

put / output channel

10: PB10

14: PB14

18: PC2

11: PB11

15: PB15

19: PC3

26: PC10

30: PD10

27: PC11

31: PD11

8: PB12

9: PB13

12: PC0

13: PC1

16: PC4

17: PC5

18: PC6

19: PC7

16: PC6

17: PC7

18: PC8

19: PC9

16: PC8

17: PC9

24: PD8

25: PD9

28: PD12

29: PD13

Wide timer 0 Com-

plimentary Dead

Time Insertion

channel 0.

10: PB14

14: PC2

11: PB15

15: PC3

22: PC10

26: PD10

30: PD14

23: PC11

27: PD11

31: PD15

20: PC10

24: PD10

28: PD14

21: PC11

25: PD11

29: PD15

8: PB14

9: PB15

10: PC0

11: PC1

8: PC0

12: PC2

13: PC3

14: PC4

15: PC5

12: PC4

13: PC5

14: PC6

15: PC7

12: PC8

13: PC9

Wide timer 0 Com-

plimentary Dead

Time Insertion

channel 1.

22: PD8

23: PD9

20: PD8

21: PD9

26: PD12

30: PF0

27: PD13

31: PF1

24: PD12

28: PF0

25: PD13

29: PF1

Wide timer 0 Com-

plimentary Dead

Time Insertion

channel 2.

9: PC1

10: PC2

11: PC3

8: PC4

18: PC10

22: PD10

26: PD14

30: PF2

19: PC11

23: PD11

27: PD15

31: PF3

16: PD8

17: PD9

20: PD12

24: PF0

21: PD13

25: PF1

28: PF4

29: PF5

30: PF6

31: PF7

Wide timer 1 Cap-

ture Compare in-

put / output channel

9: PC5

10: PC6

11: PC7

14: PC10

18: PD10

22: PD14

26: PF2

15: PC11

19: PD11

23: PD15

27: PF3

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Alternate

LOCATION

12 – 15

16 – 19

Functionality

0 – 3

0: PB14

1: PB15

2: PC0

3: PC1

0: PC0

1: PC1

2: PC2

3: PC3

0: PC2

1: PC3

2: PC4

3: PC5

4 – 7

4: PC2

5: PC3

6: PC4

7: PC5

4: PC4

5: PC5

6: PC6

7: PC7

4: PC6

5: PC7

6: PC8

7: PC9

8 – 11

8: PC6

9: PC7

10: PC8

11: PC9

8: PC8

9: PC9

20 – 23

24 – 27

28 – 31

28: PF6

29: PF7

30: PF8

31: PF9

28: PF8

29: PF9

30: PF10

31: PF11

28: PF10

29: PF11

30: PF12

31: PF13

Description

12: PC10

16: PD10

20: PD14

24: PF2

13: PC11

17: PD11

21: PD15

25: PF3

Wide timer 1 Cap-

ture Compare in-

put / output channel

WTIM1_CC1

WTIM1_CC2

WTIM1_CC3

14: PD8

15: PD9

12: PD8

13: PD9

18: PD12

22: PF0

19: PD13

23: PF1

16: PD12

20: PF0

17: PD13

21: PF1

26: PF4

27: PF5

24: PF4

25: PF5

26: PF6

27: PF7

24: PF6

25: PF7

26: PF8

27: PF9

Wide timer 1 Cap-

ture Compare in-

put / output channel

10: PC10

14: PD10

18: PD14

22: PF2

11: PC11

15: PD11

19: PD15

23: PF3

8: PC10

9: PC11

10: PD8

11: PD9

12: PD10

16: PD14

20: PF2

13: PD11

17: PD15

21: PF3

Wide timer 1 Cap-

ture Compare in-

put / output channel

14: PD12

18: PF0

15: PD13

19: PF1

22: PF4

23: PF5

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

6.11 Analog

Port (APORT) Client Maps

The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,

DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal rout-

ing.

Figure 6.9 APORT Connection Diagram on page 199

shows the APORT routing for this device family (note that available features

may vary by part number). A complete description of APORT functionality can be found in the Reference Manual.

IDAC0

ACMP1X

ACMP1Y

PB15

NEXT1

NEXT0

PB14

NEXT1

NEXT0

POS

NEG

PF0

PF1

PB13

POS

NEG

OPA2_N

PF2

ACMP0

PB12

PB11

PF3

ACMP1

OUT2

PF8

NEXT1

NEXT0

OPA2_P

PF9

PF10

PF11

PF12

PF13

PF14

PF15

PK0

PK1

PK2

PF4

PB10

PB9

VDAC0_OPA2ALT

NEXT0

NEXT2

OUT2ALT

POS

NEG

PB8

PB7

NEXT1

ADC0

PB6

PI3

PI2

EXTP

EXTN

PI1

OPA1_P

PI0

POS

OPA0_P

PF5

PA9

POS

NEG

PF6

PA8

OPA1_N

PF7

PA7 LESENSE

PA6 LESENSE

NEG

OUT

OPA0_N

OPA1

OPA0

PA5 LESENSE

PA4 LESENSE

PA3 LESENSE

PA2 LESENSE

OUT1

OUT1ALT

OUT1

OUT2

OUT3

VDAC0_OUT0ALT

VDAC0_OUT1ALT

OUT0ALT

OUT1ALT

OUT0

OUT0ALT

OUT1

OUT2

OUT3

OPA0_INN0

OUT

OPA0_N

OUT4

NEXT1

OUT4

NEXT0

OPA0_OUT

OUT0

VDAC0_OUT1ALT

OUT1ALT

OPA2_P

POS

NEG

OPA0_INP0

ADC0_EXTP

OPA0_P

PA1 LESENSE

PA0 LESENSE

ADC_EXTP

OPA2_N

ADC0_EXTN

OPA0ALT

ADC_EXTN

OUT0ALT

OPA2

PD15 LESENSE

OPA1_INN0

OUT2

OUT2ALT

OUT1

OPA1N

OUT

OUT2

OUT3

OUT4

NEXT2

CEXT

CSEN

APORT

X, APORT

CEXT_SENSE

AX, B

, …

BUSAX, BUSB

ADC0X,

ADC0Y

BUSADC0X,

BUSADC0Y

ACMP0X,

BUSACMP0X,

ACMP1

, …

USACMP1

Figure 6.9.

APORT Connection Diagram

Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the

peripheral’s port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.

In general, enumerations for the pin selection field in an analog peripheral’s register can be determined by finding the desired pin con-

nection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared

bus used by this connection is indicated in the Bus column.

Table 6.11.

ACMP0 Bus and Pin Mapping

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Table 6.12.

ACMP1 Bus and Pin Mapping

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Table 6.13.

ADC0 Bus and Pin Mapping

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Table 6.14.

CSEN Bus and Pin Mapping

CEXT

CEXT_SENSE

Table 6.15.

IDAC0 Bus and Pin Mapping

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

Table 6.16.

VDAC0 / OPA Bus and Pin Mapping

OPA0_N

OPA0_P

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

OPA1_N

OPA1_P

OPA2_N

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Pin Definitions

OPA2_OUT

OPA2_P

VDAC0_OUT0 / OPA0_OUT

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Pin Definitions

VDAC0_OUT1 / OPA1_OUT

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

BGA125 Package Specifications

7. BGA125

Package Specifications

7.1 BGA125

Package Dimensions

Figure 7.1.

BGA125 Package Drawing

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

BGA125 Package Specifications

Table 7.1.

BGA125 Package Dimensions

Dimension

Min

0.80

0.16

0.61

0.17

6.90

—

Typ

0.87

0.21

0.66

0.21

7.00

6.00

0.50

0.30

0.10

0.08

0.15

0.05

Max

0.94

0.26

0.71

0.25

7.10

—

0.25

0.35

aaa

bbb

ddd

eee

fff

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

BGA125 Package Specifications

7.2 BGA125

PCB Land Pattern

Figure 7.2.

BGA125 PCB Land Pattern Drawing

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

BGA125 Package Specifications

Table 7.2.

BGA125 PCB Land Pattern Dimensions

Dimension

Min

Nom

0.25

6.00

0.5

Max

0.5

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size should be 1:1.

8. A No-Clean, Type-3 solder paste is recommended.

9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

BGA125 Package Specifications

7.3 BGA125

Package Marking

EFR32

PPPPPPPPPP

YYWWTTTTTT

Figure 7.3.

BGA125 Package Marking

The package marking consists of:

• PPPPPPPPP

– The part number designation.

1. Family Code (B | M | F)

2. G (Gecko)

3. Series (1, 2,…)

4. Device Configuration (1, 2,…)

5. Performance Grade (P | B | V)

6. Feature Code (1, 2,…)

7. TRX Code (3 = TXRX | 2= RX | 1 = TX)

8. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)

9. Flash (J = 1024K | H = 512K | G = 256K | F = 128K | E = 64K | D = 32K)

10. Temperature Grade (G = -40 to 85 | I = -40 to 125)

• YY

– The last 2 digits of the assembly year.

• WW

– The 2-digit workweek when the device was assembled.

• TTTTTT

– A trace or manufacturing code. The first letter is the device revision.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

QFN48 Package Specifications

8. QFN48

Package Specifications

8.1 QFN48

Package Dimensions

Figure 8.1.

QFN48 Package Drawing

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

QFN48 Package Specifications

Table 8.1.

QFN48 Package Dimensions

Dimension

Min

0.80

0.00

Typ

0.85

Max

0.90

0.05

0.02

0.20 REF

0.25

0.18

6.90

5.15

0.30

7.10

5.45

7.00

5.30

0.50 BSC

0.40

0.30

0.20

0.09

0.50

—

aaa

bbb

ccc

ddd

eee

fff

0.15

0.10

0.05

0.08

0.10

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

QFN48 Package Specifications

8.2 QFN48

PCB Land Pattern

Figure 8.2.

QFN48 PCB Land Pattern Drawing

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

QFN48 Package Specifications

Table 8.2.

QFN48 PCB Land Pattern Dimensions

Dimension

Typ

6.01

4.70

0.50

0.26

0.86

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

5. The stencil thickness should be 0.125 mm (5 mils).

6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.

7. A 4×4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad.

8. A No-Clean, Type-3 solder paste is recommended.

9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

QFN48 Package Specifications

8.3 QFN48

Package Marking

EFR32

PPPPPPPPPP

YYWWTTTTTT

Figure 8.3.

QFN48 Package Marking

The package marking consists of:

• PPPPPPPPP

– The part number designation.

1. Family Code (B | M | F)

2. G (Gecko)

3. Series (1, 2,…)

4. Device Configuration (1, 2,…)

5. Performance Grade (P | B | V)

6. Feature Code (1, 2,…)

7. TRX Code (3 = TXRX | 2 = RX | 1 = TX)

8. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)

9. Flash (J = 1024K | H = 512K | G = 256K | F = 128K | E = 64K | D = 32K)

10. Temperature Grade (G = -40 to 85 | I = -40 to 125)

• YY

– The last 2 digits of the assembly year.

• WW

– The 2-digit workweek when the device was assembled.

• TTTTTT

– A trace or manufacturing code. The first letter is the device revision.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

QFN68 Package Specifications

9. QFN68

Package Specifications

9.1 QFN68

Package Dimensions

Figure 9.1.

QFN68 Package Drawing

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

QFN68 Package Specifications

Table 9.1.

QFN68 Package Dimensions

Dimension

Min

0.80

0.00

Typ

0.85

Max

0.90

0.05

0.02

0.20 REF

0.20

0.15

7.90

6.05

0.25

8.10

6.35

8.00

6.20

0.40 BSC

0.40

0.30

0.20

0.50

—

0.075

—

aaa

bbb

ccc

ddd

eee

fff

0.10

0.07

0.10

0.05

0.08

0.10

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

QFN68 Package Specifications

9.2 QFN68

PCB Land Pattern

Figure 9.2.

QFN68 PCB Land Pattern Drawing

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

QFN68 Package Specifications

Table 9.2.

QFN68 PCB Land Pattern Dimensions

Dimension

Typ

0.86

0.22

0.40

7.01

6.35

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-

cation Allowance of 0.05mm.

4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

6. The stencil thickness should be 0.100 mm (4 mils).

7. The ratio of stencil aperture to land pad size can be 1:1 for all pads.

8. A 3×3 array of 1.50 mm square openings on a 1.80 mm pitch can be used for the center ground pad.

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

QFN68 Package Specifications

9.3 QFN68

Package Marking

EFR32

PPPPPPPPPP

YYWWTTTTTT

Figure 9.3.

QFN68 Package Marking

The package marking consists of:

• PPPPPPPPPP

– The part number designation.

• TTTTTT

– A trace or manufacturing code. The first letter is the device revision.

• YY

– The last 2 digits of the assembly year.

• WW

– The 2-digit workweek when the device was assembled.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Revision History

10. Revision

History

Revision 1.6

September, 2020

• Updated

External PA supply connection conditions for SPUR

HARM_ETSI

and SPUR

OOB_ETSI

in section

4.1.10.3 Sub-GHz RF Trans-

mitter characteristics for 868 MHz Band

Revision 1.5

December, 2019

• In

the front page block diagram, updated the lowest energy mode for LETIMER.

• Updated

3.6.4 Low Energy Timer (LETIMER)

lowest energy mode.

• In

5.2 RF Matching Networks

, corrected document references for component values and added document reference to IPD solu-

tions.

• Corrected

the max value of the Absolute voltage on 2G4RF_IOP, 2G4RF_ION, SUBGRF_OP and SUBGRF_ON pins in Absolute

Maximum Ratings table in

4.1.1 Absolute Maximum Ratings

• Added

a Note about the operating voltage in

3.8.3 True Random Number Generator (TRNG)

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Revision History

Revision 1.4

July, 2019

• In

Feature List, removed wake on radio.

• In

System Overview:

• Replaced

reference to “modules” with “peripherals” or “blocks”

• Renamed

GPCRC section

• In

Electrical Specifications, reordered footnotes according to order of appearance in the table.

• In

General Operating Conditions for f

CORE

• Added

conditions for all usable wait state settings

• Corrected

maximum specification from 20 MHz to 7 MHz for test condition VSCALE0, MODE = WS0

• In

sub-GHz specifications, replaced references to “PAVDD” with “External PA Supply” for clarity.

• In

RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4GHz Band, updated parameter for EVM.

• In

Sub-GHz RF Transmitter characteristics for 915 MHz Band:

• Corrected

test conditions for:

• SPUR

HARM_FCC_14

, in non-restricted bands

• SPUR

OOB_FCC_14

, in non-restricted bands

• SPUR

HARM_FCC_20

, in non-restricted bands

• SPUR

OOB_FCC_20

, in non-restricted bands

• Updated

typical specification from -52 dBm to -62 dBm and maximum specification from -46 dBm to -56 dBm for:

• SPUR

OOB_FCC_20

, in restricted bands (30-88 MHz)

• SPUR

OOB_FCC_14

, in restricted bands (30-88 MHz)

• Added

footnote to PSD.

• In

4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band

, updated typical specification from -60 dBm to -61 dBm and

maximum specification from -54 dBm to -55 dBm for SPUR

RX_ARIB

, 930-1000 MHz, RBW=100 kHz.

• Corrected

units for F

RANGE

in:

• Sub-GHz

RF Receiver Characteristics for 490 MHz Band

• Sub-GHz

RF Receiver Characteristics for 315 MHz Band

• Sub-GHz

RF Receiver Characteristics for 169 MHz Band

• In

LFRCO, updated test conditions for f

LFRCO

• In

GPIO, added footnotes to V

and V

• In

VMON, updated test conditions for I

VMON

• In

VDAC, updated test conditions for I

DAC

, 200 Hz refresh rate.

• In

CSEN, updated test conditions for:

• C

EXTMAX

• I

CSEN_BOND

• I

CSEN_EM2

• I

CSEN_ACTIVE

• In

Pin Definitions, updated pin descriptions for DECOUPLE and RESETn.

• Updated

feature code in:

•

7.3 BGA125 Package Marking

•

8.3 QFN48 Package Marking

Revision 1.3

June, 2018

•

4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC

: Updated typical 802.15.4 receive current specifications.

•

Table 6.9 GPIO Functionality Table on page 141

: Changed presentation to order table by pin name instead of pin location.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Revision History

Revision 1.2

February, 2018

• Added

new orderable part numbers for QFN68 variants and associated packaging and pinout information.

•

Absolute Maximum Ratings Table

: Added footnote to clarify IOVDD over-voltage operation conditions.

•

APORT Connection Diagram

: Corrected OPA output connections to route through “Y” buses.

Revision 1.1

October, 2017

• Updated

Ordering Table

to revision-C OPNs.

• Added

high-temperature part numbers to

Ordering Table

and added associated specifications / content throughout document.

• Updated

product highlights on

Front Page

and

Feature List

for consistency across EFR32xG1x family documentation.

•

System Overview Updates

• Expanded

Receiver Architecture section.

• Clarified

/ corrected energy mode mentions in RTCC and Opamp sections.

• Memory

maps updated with LE peripherals and new formatting.

•

Absolute Maximum Ratings

Table:

• Removed

redundant I

VSSMAX

line.

• Added

footnote to clarify V

DIGPIN

specification for 5V tolerant GPIO.

•

General Operating Conditions

Table:

• Removed

redundant footnote about shorting VREGVDD and AVDD together.

• Added

footnote about IOVDD voltage restriction when CSEN peripheral is used with chopping enabled.

• Added

footnote for additional information on peak current during voltage scaling operations.

•

RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate

Table:

• Sensitivity,

Co-channel interferer and Selectivity typical numbers updated to latest phy characterization data.

• BLOCK

OOB

specifications changed to show Min values instead of Typ.

•

RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate

Table:

• SAT

Typical value corrected from 5 to 10 dBm.

• BLOCK

OOB

specifications removed.

•

RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band

Table: Footnote added to BLOCK

80211G

specifica-

tion to clarify blocker signal definition.

•

Sub-GHz RF Receiver Characteristics for 915 MHz Band

Table: Added O-QPSK DSSS phy specifications.

•

Sub-GHz RF Transmitter Characteristics for 868 MHz Band

Table: SPUR

OOB_ETSI

below 1 GHz Typ corrected from -60 to -42

dBm.

•

Sub-GHz RF Receiver Characteristics for 490 MHz Band

Table: Corrected 10 kbps 2GFSK reference signal bandwidth to 20.038

kHz.

•

Flash Memory Characteristics

Table:

• Added

timing measurement clarification for Device Erase and Mass Erase.

• Device

Erase Time typical values corrected from 69 to 82 ms.

•

Analog to Digital Converter (ADC)

Table:

• Added

header text for general specification conditions.

• Added

footnote for clarification of input voltage limits.

•

Digital to Analog Converter (VDAC)

Table: Gain Error min/max specifications relaxed for REFSEL on 1V25LN, VDD, and EXT

settings.

•

Current Digital to Analog Converter (IDAC)

Table: Total accuracy STEPSEL value setting corrected from 0x80 to 0x10.

•

Analog Port (APORT)

Table: Operation in EM2/EM3 supply current changed from 915 to 67 nA (silicon fix from rev B to C).

•

2.4 GHz RF Transmitter Output Power

Figure: Extended temperature range to 125 C.

•

2.4 GHz RF Receiver Sensitivity

Figure: Updated with latest characterization data and added 125 C operational plots.

•

Typical Sub-GHz Impedance-matching network circuits

Figure: Corrected split between two examples from 450 MHz to 500

MHz.

• Minor

typographical corrections, including capitalization, mis-spellings and punctuation marks, throughout document.

• Minor

formatting and styling updates, including table formats, TOC location, and boilerplate information throughout document.

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EFR32FG12 Gecko Proprietary Protocol SoC Family Data Sheet

Revision History

Revision 1.0

2017-04-14

• Added

Thermal Characteristics table.

• Finalized

specification tables. All tables were updated with latest characterization data and production test limits.

• Updated

typical performance graphs for DC-DC.

• Minor

typographical, clarity, and consistency improvements.

• Condensed

pin function tables with new formatting.

Revision 0.6

2017-02-23

• Updated

2 Mbps 2GFSK receiver specifications with latest characteriztion data.

• Added

table-wide conditions to 2GFSK 1 Mbps and 2 Mbps receiver tables.

• Clarified

opamp noise measurement conditions in electrical spec table.

Revision 0.5

2017-02-03

• New

corporate stylesheet applied.

• Updated

device block diagrams on front page and in System Overview.

• Updated

Feature List with latest characterization numbers.

• “Bluetooth

Smart” changed to “Bluetooth Low Energy” throughout document.

• All

OPNs changed to revision B.

• Minor

typographical corrections and clarifications in System Overview.

• Electrical

Characteristics Table Changes

• All

specification tables updated with latest characterization data and production test limits.

• Split

2.4 GHz 2GFSK tables into separate tables for 1 Mbps and 2 Mbps data rates.

• Split

HFRCO/AUXHFRCO table into separate tables for HFRCO and AUXHFRCO.

• OPAMP,

CSEN, and VDAC specification line items updated to match test conditions.

• Added

tables for Analog Port (APORT) and Pulse Counter (PCNT).

• Added

Typical Performance Curves for supply current, DCDC, and RF parameters.

• Added

missing alternate functions and descriptions to Pinout and Alternate Function tables.

• Added

APORT Connection Diagram.

• Corrected

Package Marking description for QFN48 and BGA125.

• Corrected

Package Marking diagram for QFN48.

Revision 0.2

2016-09-21

Initial release.

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Simplicity Studio

One-click access to MCU and wireless

tools, documentation, software, source

code libraries & more. Available for

Windows, Mac and Linux!

IoT Portfolio

www.silabs.com/IoT

SW/HW

www.silabs.com/simplicity

Quality

www.silabs.com/quality

Support & Community

www.silabs.com/community

Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and “Typical”

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information.

Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons.

Such changes will not alter the specifications or

the performance of the product.

Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly

grant any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA

premarket approval is required, or Life Support Systems without the specific written consent of Silicon Labs. A “Life Support System” is any product or system intended to support or

sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military

applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or

missiles capable of delivering such weapons. Silicon Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of

a Silicon Labs product in such unauthorized applications.

Trademark Information

Silicon Laboratories Inc.®, Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, ClockBuilder®, CMEMS®, DSPLL®, EFM®,

EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, “the world’s most energy friendly microcontrollers”, Ember®, EZLink®, EZRadio®, EZRadioPRO®,

Gecko®, Gecko OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®, Zentri, the Zentri logo and

Zentri DMS,

Z-Wave®, and others are trademarks or registered trademarks of Silicon Labs.

ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM

Holdings. Keil is a registered trademark of ARM Limited. Wi-Fi is a registered trademark of the Wi-Fi Alliance.

All other products or brand names mentioned herein are trademarks of

their respective holders.

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USA

http://www.silabs.com

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