SKYWORKS-SILICON-LABS-EFR32FG12P232F1024GL125-BR

EFR32FG12 Flex Gecko Proprietary  

Protocol SoC Family Data Sheet  

The Flex Gecko proprietary protocol family of SoCs is part of the  

KEY FEATURES  

Wireless Gecko portfolio. Flex Gecko SoCs are ideal for enabling  

energy-friendly proprietary protocol networking for IoT devices.  

• 32-bit

 

ARM® Cortex®-M4 core with 40  

MHz maximum operating frequency  

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup  

times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-  

tures.  

• Up

 

to 1 MB of flash and 256 kB of RAM  

• Pin-compatible

 

with EFR32MG1 QFN48  

devices  

• 12-channel

 

Peripheral Reflex System,  

Low-Energy Sensor Interface & Multi-  

channel Capacitive Sense Interface  

Flex Gecko applications include:  

• Home

 

and Building Automation and Security  

• Metering  

• Autonomous

 

Hardware Crypto Accelerator  

and True Random Number Generator  

• Electronic

 

Shelf Labels  

• Integrated

 

PA with up to 19 dBm transmit  

power for 2.4 GHz and Sub-GHz radios  

• Industrial

 

Automation  

• Commercial

 

and Retail Lighting and Sensing  

• Integrated

 

balun for 2.4 GHz  

• Robust

 

peripheral set and up to 65 GPIO  

Core / Memory  

Clock Management  

Energy Management  

Other  

High Frequency  

Crystal  

Oscillator  

High Frequency  

RC Oscillator  

Voltage  

CRYPTO  

Voltage Monitor  

Regulator  

ARM Cortex

TM

M4 processor  

Memory  

with DSP extensions and FPU  

Protection Unit  

Auxiliary High  

Frequency RC  

Oscillator  

Low Frequency  

RC Oscillator  

DC-DC  

Power-On Reset  

Converter  

CRC  

Low Frequency  

Crystal  

Oscillator  

Ultra Low  

Frequency RC  

Oscillator  

Flash Program  

RAM Memory  

Memory  

Debug Interface  

with ETM  

Brown-Out  

Detector  

True Random  

Number Generator  

DMA Controller  

32-bit bus  

Peripheral Reflex System  

Radio Transceiver  

Serial  

I/O Ports  

Timers and Triggers  

Analog I/F  

Interfaces  

RFSENSE  

Sub GHz  

LNA  

DEMOD  

ADC  

I

External  

Interrupts  

USART  

Timer/Counter  

Protocol Timer  

RF Frontend  

Analog  

Comparator  

IFADC  

AGC  

PGA  

PA  

Low Energy  

UART

TM  

General  

Purpose I/O  

Low Energy  

Timer  

Watchdog Timer  

Q

IDAC  

To Sub GHz  

receive I/Q  

mixers and PA  

Real Time  

Counter and  

Calendar  

Capacitive  

Touch  

RFSENSE  

BALUN  

I

2

C  

Pin Reset  

Pulse Counter  

2.4 GHz  

LNA  

I

Frequency  

Synthesizer  

MOD  

VDAC  

RF Frontend  

Low Energy  

Sensor Interface  

Pin Wakeup  

Cryotimer  

Op-Amp  

PA  

To 2.4 GHz receive  

I/Q mixers and PA  

To Sub GHz  

and 2.4 GHz PA  

Q

Lowest power mode with peripheral operational:  

EM0—Active EM1—Sleep  

EM2—Deep Sleep  

EM3—Stop  

EM4—Hibernate  

EM4—Shutoff  

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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon  

Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).  

Preliminary Rev. 0.5  

EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Feature List  

1. Feature

 

List  

The EFR32FG12 highlighted features are listed below.  

•

Low Power Wireless System-on-Chip

.  

•

Wide selection of MCU peripherals  

• 12-bit

 

1 Msps SAR Analog to Digital Converter (ADC)  

• 2×Analog

 

Comparator (ACMP)  

High Performance 32-bit 40 MHz ARM Cortex

®

-M4 with  

DSP instruction and floating-point unit for efficient signal  

processing  

•

• 2×Digital

 

to Analog Converter (VDAC)  

• 3×Operational

 

Amplifier (Opamp)  

• Embedded

 

Trace Macrocell (ETM) for advanced debugging  

• Up

 

to 1024 kB flash program memory  

• Digital

 

to Analog Current Converter (IDAC)  

• Low-Energy

 

Sensor Interface (LESENSE)  

• Multi-channel

 

Capacitive Sense Interface (CSEN)  

• Up

 

to 256 kB RAM data memory  

• 2.4

 

GHz and Sub-GHz radio operation  

• TX

 

power up to 19 dBm  

• Up

 

to 54 pins connected to analog channels (APORT)  

shared between analog peripherals  

•

Low Energy Consumption  

• 10.0

 

mA RX current at 2.4 GHz (1 Mbps GFSK)  

• 10.8

 

mA RX current at 2.4 GHz (250 kbps O-QPSK DSSS)  

• 8.2

 

mA TX current @ 0 dBm output power at 2.4 GHz  

• 66

 

μA/MHz in Active Mode (EM0)  

• Up

 

to 65 General Purpose I/O pins with output state reten-  

tion and asynchronous interrupts  

• 8

 

Channel DMA Controller  

• 12

 

Channel Peripheral Reflex System (PRS)  

• 2×16-bit

 

Timer/Counter  

• TBD

 

μA EM2 DeepSleep current (256 kB RAM retention  

and RTCC running from LFXO)  

• 3

 

+ 4 Compare/Capture/PWM channels  

• 2×32-bit

 

Timer/Counter  

• 1.5

 

μA EM2 DeepSleep current (16 kB RAM retention and  

RTCC running from LFRCO)  

• 3

 

+ 4 Compare/Capture/PWM channels  

• 32-bit

 

Real Time Counter and Calendar  

• 16-bit

 

Low Energy Timer for waveform generation  

• 1.75

 

μA EM3 Stop current (State and 256 kB RAM reten-  

tion)  

• Wake

 

on Radio with signal strength detection, preamble  

pattern detection, frame detection and timeout  

• 32-bit

 

Ultra Low Energy Timer/Counter for periodic wake-up  

from any Energy Mode  

•

High Receiver Performance  

• -95.2

 

dBm sensitivity @ 1 Mbit/s GFSK  

• -102

 

dBm sensitivity @ 250 kbps O-QPSK DSSS  

•

Supported Modulation Formats  

• 2-FSK

 

/ 4-FSK with fully configurable shaping  

• Shaped

 

OQPSK / (G)MSK  

• Configurable

 

DSSS and FEC  

• BPSK

 

/ DBPSK TX  

• 3×16-bit

 

Pulse Counter with asynchronous operation  

• 2×Watchdog

 

Timer with dedicated RC oscillator  

• 4×Universal

 

Synchronous/Asynchronous Receiver/Trans-  

mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I

2

S)  

Low Energy UART (LEUART

™

)  

2×I

2

C interface with SMBus support and address recogni-  

tion in EM3 Stop  

•

•

•

Wide Operating Range  

• OOK

 

/ ASK  

• 1.8

 

V to 3.8 V single power supply  

•

Supported Protocols:  

• Integrated

 

DC-DC, down to 1.8 V output with up to 200 mA  

load current for system  

• Proprietary

 

Protocols  

• Wireless

 

M-Bus  

• -40

 

°C to 85 °C  

• Low

 

Power Wide Area Networks  

•

Support for Internet Security  

• General

 

Purpose CRC  

•

QFN48 7×7 mm Package  

•

BGA125 7×7 mm Package  

• True

 

Random Number Generator  

• Hardware

 

Cryptographic Acceleration for AES 128/256,  

SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC  

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Preliminary Rev. 0.5

 

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Ordering Information  

2. Ordering

 

Information  

Table 2.1.

 

Ordering Information  

Ordering Code  

Protocol Stack  

Frequency Band  

@ Max TX Power  

2.4 GHz @ 19 dBm  

Flash  

(kB)  

RAM  

(kB)  

GPIO  

Package  

EFR32FG12P433F1024GL125-B  

EFR32FG12P433F1024GM48-B  

Proprietary  

Proprietary  

•

1024  

1024  

256  

256  

65  

28  

BGA125  

QFN48  

• Sub-GHz

 

@ 20 dBm  

•

2.4 GHz @ 19 dBm  

• Sub-GHz

 

@ 20 dBm  

EFR32FG12P432F1024GL125-B  

EFR32FG12P432F1024GM48-B  

EFR32FG12P431F1024GL125-B  

EFR32FG12P431F1024GM48-B  

EFR32FG12P232F1024GL125-B  

EFR32FG12P232F1024GM48-B  

EFR32FG12P231F1024GL125-B  

EFR32FG12P231F1024GM48-B  

Proprietary  

Proprietary  

Proprietary  

Proprietary  

Proprietary  

Proprietary  

Proprietary  

Proprietary  

2.4 GHz @ 19 dBm  

2.4 GHz @ 19 dBm  

Sub-GHz @ 20 dBm  

Sub-GHz @ 20 dBm  

2.4 GHz @ 19 dBm  

2.4 GHz @ 19 dBm  

Sub-GHz @ 20 dBm  

Sub-GHz @ 20 dBm  

1024  

1024  

1024  

1024  

1024  

1024  

1024  

1024  

256  

256  

256  

256  

128  

128  

128  

128  

65  

31  

65  

31  

65  

31  

65  

31  

BGA125  

QFN48  

BGA125  

QFN48  

BGA125  

QFN48  

BGA125  

QFN48  

EFR32 X G 1 2 P 132 F

 

1024 G

 

L 125

 

–

A R  

Tape and Reel (Optional)  

Revision  

Pin Count  

Package – M (QFN), L (BGA)  

Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)  

Flash Memory Size in kB  

Memory Type (Flash)  

Feature Set Code – r2r1r0  

r2: Reserved  

r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)  

r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)  

Performance Grade – P (Performance), B (Basic), V (Value)  

Device Configuration  

Series  

Gecko  

Family – M (Mighty), B (Blue), F (Flex)  

Wireless Gecko 32-bit  

Figure 2.1.

 

OPN Decoder  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

System Overview  

3. System

 

Overview  

3.1 Introduction  

The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for  

any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a  

short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32 Reference Manual.  

A block diagram of the EFR32FG12 family is shown in

Figure 3.1 Detailed EFR32FG12 Block Diagram on page 3

. The diagram  

shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult  

Ordering Information

.  

Radio Transceiver  

Port I/O Configuration  

Digital Peripherals  

IOVDD  

Sub-GHz RF  

SUBGRF_IP  

SUBGRF_IN  

SUBGRF_OP  

SUBGRF_ON  

I

DEMOD  

IFADC  

AGC  

LNA  

LETIMER  

PA  

Port A  

Drivers  

PGA  

Q

PAn  

TIMER  

CRYOTIMER  

PCNT  

RFSENSE  

BALUN  

2.4 GHz RF  

I

Frequency  

LNA  

Synthesizer  

Port B  

Drivers  

PBn  

PCn  

PDn  

PFn  

2G4RF_IOP  

2G4RF_ION  

To RF  

MOD  

PA  

Frontend  

Circuits  

RTC / RTCC  

USART  

Q

Port  

Mapper  

Port C  

Drivers  

LEUART  

I2C  

Reset  

Management  

Unit  

ARM Cortex-M4 Core  

RESETn  

Port D  

Serial Wire  

and ETM  

Debug /  

Up to 1024 KB ISP Flash  

Program Memory  

CRYPTO  

CRC  

Drivers  

Debug Signals  

(shared w/GPIO)  

Brown Out /  

Power-On  

Reset  

A

H

B

A

P

B

Up to 256 KB RAM  

Memory Protection Unit  

Floating Point Unit  

DMA Controller  

Programming  

Port F  

Drivers  

LESENSE  

Energy Management  

Analog Peripherals  

Port I  

Drivers  

PAVDD  

RFVDD  

IOVDD  

AVDD  

PIn  

IDAC  

Voltage  

Monitor  

Port J  

Drivers  

–

+

Watchdog  

Timer  

PJn  

VDAC  

DVDD  

bypass  

Op-Amp  

VDD  

Internal  

Reference  

Port K  

Drivers  

Clock Management  

PKn  

VREGVDD  

VREGSW  

DC-DC  

Converter  

Voltage  

Regulator  

ULFRCO  

AUXHFRCO  

LFRCO  

12-bit ADC  

DECOUPLE  

Temp  

Sense  

LFXTAL_P  

LFXTAL_N  

HFXTAL_P  

HFXTAL_N  

LFXO  

HFRCO  

HFXO  

Capacitive  

Touch  

+

–

Analog Comparator  

Figure 3.1.

 

Detailed EFR32FG12 Block Diagram  

3.2 Radio  

The Flex Gecko family features a radio transceiver supporting proprietary wireless protocols.  

3.2.1 Antenna

 

Interface  

The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The  

2G4RF_ION pin should be grounded externally.  

The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching  

Networks section.  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

System Overview  

3.2.2 Fractional-N

 

Frequency Synthesizer  

The EFR32FG12 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is  

used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly  

generate the modulated RF carrier.  

The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with  

low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to  

optimize system energy consumption.  

3.2.3 Receiver

 

Architecture  

The EFR32FG12 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion  

mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital  

converter (IFADC).  

The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-  

ing flexibility with respect to known interferers at the image frequency.  

The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-  

tivity and blocking performance. Devices are production-calibrated to improve image rejection performance.  

Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-  

ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and  

compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by  

block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).  

A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-  

nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received  

frame and the dynamic RSSI measurement can be monitored throughout reception.  

3.2.4 Transmitter

 

Architecture  

The EFR32FG12 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls  

phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping  

filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-  

ing.  

Carrier Sense Multiple Access – Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by  

the EFR32FG12. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-  

tween devices that otherwise lack synchronized RF channel access.  

3.2.5 Wake

 

on Radio  

The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-  

ing a subsystem of the EFR32FG12 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-  

als.  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

System Overview  

3.2.6 Flexible

 

Frame Handling  

EFR32FG12 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.  

The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-  

tor:  

• Highly

 

adjustable preamble length  

• Up

 

to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts  

• Frame

 

disassembly and address matching (filtering) to accept or reject frames  

• Automatic

 

ACK frame assembly and transmission  

• Fully

 

flexible CRC generation and verification:  

• Multiple

 

CRC values can be embedded in a single frame  

• 8,

 

16, 24 or 32-bit CRC value  

• Configurable

 

CRC bit and byte ordering  

• Selectable

 

bit-ordering (least significant or most significant bit first)  

• Optional

 

data whitening  

• Optional

 

Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding  

• Half

 

rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing  

• Optional

 

symbol interleaving, typically used in combination with FEC  

• Symbol

 

coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware  

• UART

 

encoding over air, with start and stop bit insertion / removal  

• Test

 

mode support, such as modulated or unmodulated carrier output  

• Received

 

frame timestamping  

3.2.7 Packet

 

and State Trace  

The EFR32FG12 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.  

It features:  

• Non-intrusive

 

trace of transmit data, receive data and state information  

• Data

 

observability on a single-pin UART data output, or on a two-pin SPI data output  

• Configurable

 

data output bitrate / baudrate  

• Multiplexed

 

transmitted data, received data and state / meta information in a single serial data stream  

3.2.8 Data

 

Buffering  

The EFR32FG12 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64  

bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.  

3.2.9 Radio

 

Controller (RAC)  

The Radio Controller controls the top level state of the radio subsystem in the EFR32FG12. It performs the following tasks:  

• Precisely-timed

 

control of enabling and disabling of the receiver and transmitter circuitry  

• Run-time

 

calibration of receiver, transmitter and frequency synthesizer  

• Detailed

 

frame transmission timing, including optional LBT or CSMA-CA  

3.2.10 Random

 

Number Generator  

The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.  

The data is suitable for use in cryptographic applications.  

Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-  

ber generator algorithms such as Fortuna.  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

System Overview  

3.3 Power  

The EFR32FG12 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only  

a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator  

can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-  

tor.  

The EFR32FG12 device family includes support for internal supply voltage scaling, as well as two different power domains groups for  

peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.  

AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will  

operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.  

Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB  

components, supplying up to a total of 200 mA.  

3.3.1 Energy

 

Management Unit (EMU)  

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and  

features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM  

blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi-  

ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has  

fallen below a chosen threshold.  

3.3.2 DC-DC

 

Converter  

The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2  

and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation  

of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,  

short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low  

for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance  

switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-  

sients.  

3.3.3 Power

 

Domains  

The EFR32FG12 has two peripheral power domains for operation in EM2 and lower. If all of the peripherals in a peripheral power do-  

main are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall cur-  

rent consumption of the device.  

Table 3.1.

 

Peripheral Power Subdomains  

Peripheral Power Domain 1  

Peripheral Power Domain 2  

ACMP0  

ACMP1  

PCNT1  

PCNT2  

CSEN  

DAC0  

PCNT0  

ADC0  

LETIMER0  

LESENSE  

APORT  

LEUART0  

I2C0  

–

–

–

I2C1  

IDAC  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

System Overview  

3.4 General

 

Purpose Input/Output (GPIO)  

EFR32FG12 has up to 65 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or in-  

put. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO  

pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to  

several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-  

als. The GPIO subsystem supports asynchronous external pin interrupts.  

3.5 Clocking  

3.5.1 Clock

 

Management Unit (CMU)  

The Clock Management Unit controls oscillators and clocks in the EFR32FG12. Individual enabling and disabling of clocks to all periph-  

eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility  

allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and  

oscillators.  

3.5.2 Internal

 

and External Oscillators  

The EFR32FG12 supports two crystal oscillators and fully integrates four RC oscillators, listed below.  

• A

 

high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-  

ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can  

also be applied to the HFXO input for improved accuracy over temperature.  

• A

 

32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.  

• An

 

integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The  

HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.  

• An

 

integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial  

Wire debug port with a wide frequency range.  

• An

 

integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-  

tal accuracy is not required.  

• An

 

integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-  

sumption in low energy modes.  

3.6 Counters/Timers

 

and PWM  

3.6.1 Timer/Counter

 

(TIMER)  

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the  

PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one  

of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output  

reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width  

modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional  

dead-time insertion available in timer unit TIMER_0 only.  

3.6.2 Wide

 

Timer/Counter (WTIMER)  

WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM  

outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to  

4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a  

buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh-  

old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by  

the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.  

3.6.3 Real

 

Time Counter and Calendar (RTCC)  

The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a  

Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-  

tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving  

frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy  

and convenient data storage in all energy modes.  

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3.6.4 Low

 

Energy Timer (LETIMER)  

The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This  

allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed  

while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-  

forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-  

figured to start counting on compare matches from the RTCC.  

3.6.5 Ultra

 

Low Power Wake-up Timer (CRYOTIMER)  

The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal  

oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events  

and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-  

rupt periods, facilitating flexible ultra-low energy operation.  

3.6.6 Pulse

 

Counter (PCNT)  

The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The  

clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from  

among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2  

Deep Sleep, and EM3 Stop.  

3.6.7 Watchdog

 

Timer (WDOG)  

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed  

monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can  

also monitor autonomous systems driven by PRS.  

3.7 Communications

 

and Other Digital Peripherals  

3.7.1 Universal

 

Synchronous/Asynchronous Receiver/Transmitter (USART)  

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous  

UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-  

porting:  

• ISO7816

 

SmartCards  

• IrDA  

I

2

S  

•

3.7.2 Low

 

Energy Universal Asynchronous Receiver/Transmitter (LEUART)  

The unique LEUART

TM

provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow  

UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication  

possible with a minimum of software intervention and energy consumption.  

3.7.3 Inter-Integrated

 

Circuit Interface (I

2

C)  

The I

2

C module provides an interface between the MCU and a serial I

2

C bus. It is capable of acting as both a master and a slave and  

supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10  

kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The  

interface provided to software by the I

2

C module allows precise timing control of the transmission process and highly automated trans-  

fers. Automatic recognition of slave addresses is provided in active and low energy modes.  

3.7.4 Peripheral

 

Reflex System (PRS)  

The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.  

Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-  

erals which in turn perform actions in response. Edge triggers and other functionality can be applied by the PRS. The PRS allows pe-  

ripheral to act autonomously without waking the MCU core, saving power.  

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3.7.5 Low

 

Energy Sensor Interface (LESENSE)  

The Low Energy Sensor Interface LESENSE

TM

is a highly configurable sensor interface with support for up to 16 individually configura-  

ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and  

measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a  

programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is  

available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy  

budget.  

3.8 Security

 

Features  

3.8.1 GPCRC

 

(General Purpose Cyclic Redundancy Check)  

The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-  

ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the  

needs of the application.  

3.8.2 Crypto

 

Accelerator (CRYPTO)  

The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-  

port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2

m

), SHA-1 and SHA-2 (SHA-224 and  

SHA-256).  

Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.  

Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.  

The CRYPTO is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data  

buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger sig-  

nals for DMA read and write operations.  

3.8.3 True

 

Random Number Generator (TRNG)  

The TRNG module is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with  

NIST800-22 and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key genera-  

tion).  

3.8.4 Security

 

Management Unit (SMU)  

The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the  

Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to  

the peripheral’s register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and  

can optionally generate an interrupt.  

3.9 Analog  

3.9.1 Analog

 

Port (APORT)  

The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog modules on a flexible selection of pins.  

Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are  

grouped by X/Y pairs.  

3.9.2 Analog

 

Comparator (ACMP)  

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-  

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption  

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The  

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the  

programmable threshold.  

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3.9.3 Analog

 

to Digital Converter (ADC)  

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output  

sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.  

The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of  

sources, including pins configurable as either single-ended or differential.  

3.9.4 Capacitive

 

Sense (CSEN)  

The CSEN module is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches  

and sliders. The module can be configured to take measurements on a single port pin or scan through multiple pins and store results to  

memory through DMA. Several channels can also be shorted together to measure the combined capacitance or implement wake-on-  

touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter, as well as digital threshold compa-  

rators to reduce software overhead.  

3.9.5 Digital

 

to Analog Current Converter (IDAC)  

The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin  

or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with  

several ranges consisting of various step sizes.  

3.9.6 Digital

 

to Analog Converter (VDAC)  

The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500  

ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-  

ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications  

such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low  

frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any  

CPU intervention. The VDAC is available in all energy modes down to and including EM3.  

3.9.7 Operational

 

Amplifiers  

The three opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application  

areas. With flexible built-in programming for gain and interconnection they can be configured to support multiple common opamp func-  

tions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to rail output. They can  

be used in conjunction with the VDAC module or in stand-alone configurations. The opamps save energy, PCB space, and cost as  

compared with standalone opamps because they are integrated on-chip.  

3.10 Reset

 

Management Unit (RMU)  

The RMU is responsible for handling reset of the EFR32FG12. A wide range of reset sources are available, including several power  

supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.  

3.11 Core

 

and Memory  

3.11.1 Processor

 

Core  

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:  

• ARM

 

Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz  

• Memory

 

Protection Unit (MPU) supporting up to 8 memory segments  

• Up

 

to 1024 kB flash program memory  

• Up

 

to 256 kB RAM data memory  

• Configuration

 

and event handling of all modules  

• 2-pin

 

Serial-Wire debug interface  

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3.11.2 Memory

 

System Controller (MSC)  

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable  

from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code  

is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a  

read-only page in the information block containing system and device calibration data. Read and write operations are supported in  

energy modes EM0 Active and EM1 Sleep.  

3.11.3 Linked

 

Direct Memory Access Controller (LDMA)  

The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of  

software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and stag-  

ed, enabling sophisticated operations to be implemented.  

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3.12 Memory

 

Map  

The EFR32FG12 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.  

Figure 3.2.

 

EFR32FG12 Memory Map — Core Peripherals and Code Space  

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Figure 3.3.

 

EFR32FG12 Memory Map — Peripherals  

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3.13 Configuration

 

Summary  

The features of the EFR32FG12 are a subset of the feature set described in the device reference manual. The table below describes  

device specific implementation of the features. Remaining modules support full configuration.  

Table 3.2.

 

Configuration Summary  

Module  

USART0  

USART1  

Configuration  

Pin Connections  

IrDA SmartCard  

US0_TX, US0_RX, US0_CLK, US0_CS  

US1_TX, US1_RX, US1_CLK, US1_CS  

IrDA I

2

S SmartCard  

IrDA SmartCard  

USART2  

USART3  

US2_TX, US2_RX, US2_CLK, US2_CS  

US3_TX, US3_RX, US3_CLK, US3_CS  

IrDA I

2

S SmartCard  

TIMER0  

with DTI  

TIM0_CC[2:0], TIM0_CDTI[2:0]  

TIM1_CC[3:0]  

TIMER1  

–

WTIMER0  

WTIMER1  

with DTI  

–

WTIM0_CC[2:0], WTIM0_CDTI[2:0]  

WTIM1_CC[3:0]  

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4. Electrical

 

Specifications  

4.1 Electrical

 

Characteristics  

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:  

• Typical

 

values are based on T

AMB

=25 °C and V

DD

= 3.3 V, by production test and/or technology characterization.  

• Radio

 

performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-  

er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.  

• Minimum

 

and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,  

unless stated otherwise.  

Refer to

4.1.2.1 General Operating Conditions

for more details about operational supply and temperature limits.  

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4.1.1 Absolute

 

Maximum Ratings  

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of  

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure  

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-  

bility data, see the Quality and Reliability Monitor Report at

.  

Table 4.1.

 

Absolute Maximum Ratings  

Parameter  

Symbol  

T

STG  

Test Condition  

Min  

-50  

-0.3  

—

Typ  

—

Max  

150  

3.8  

1

Unit  

°C  

Storage temperature range  

Voltage on any supply pin  

V

DDMAX  

V

DDRAMPMAX  

—

V

Voltage ramp rate on any  

supply pin  

—

V / μs  

DC Voltage on any over-volt-

 

V

DIGPIN  

age tolerant GPIO pin

1  

-0.3  

—

Min of 5.25  

and IOVDD  

+2  

V

-0.3  

-0.3  

—

—

—

—

IOVDD+0.3  

V

V

Voltage on HFXO pins  

V

HFXOPIN  

1.4  

10  

Input RF level on pins  

2G4RF_IOP and  

2G4RF_ION  

P

RFMAX2G4  

dBm  

Voltage differential between

 

V

MAXDIFF2G4  

RF pins (2G4RF_IOP –  

2G4RF_ION)  

-50  

-0.3  

—

—

—

—

—

—

50  

3.3  

10  

mV  

V

Absolute Voltage on RF pins

 

V

MAX2G4  

2G4RF_IOP and  

2G4RF_ION  

Input RF level on pins  

SUBGRF_IP and  

SUBGRF_IN  

P

RFMAXSUBG  

dBm  

mV  

V

Voltage differential between

 

V

MAXDIFFSUBG  

RF pins (SUBGRF_IP –  

SUBGRF_IN)  

-50  

-0.3  

50  

Absolute Voltage on RF pins

 

V

MAXSUBG  

SUBGRF_IP, SUBGRF_IN,  

SUBGRF_OP, and  

3.3  

SUBGRF_ON  

Total current into VDD power

 

I

VDDMAX  

lines  

Source  

—

—

200  

mA  

Total current into VSS  

ground lines  

I

VSSMAX  

I

IOMAX  

I

IOALLMAX  

T

J  

Sink  

—

—

—

—

—

—

-40  

—

—

—

—

—

—

—

200  

200  

50  

mA  

mA  

mA  

mA  

mA  

mA  

°C  

Sink  

Current per I/O pin  

Sink  

Source  

Sink  

50  

Current for all I/O pins  

Junction Temperature  

200  

200  

105  

Source  

-G grade devices  

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Electrical Specifications  

Parameter  

Note:  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.  

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4.1.2 Operating

 

Conditions  

When assigning supply sources, the following requirements must be observed:  

• VREGVDD

 

must be the highest voltage in the system  

• VREGVDD

 

= AVDD  

• DVDD

 

≤ AVDD  

• IOVDD

 

≤ AVDD  

• RFVDD

 

≤ AVDD  

• PAVDD

 

≤ AVDD  

4.1.2.1 General

 

Operating Conditions  

Table 4.2.

 

General Operating Conditions  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Operating Ambient tempera-

 

T

A  

ture range  

-G temperature grade  

-40  

25  

85  

°C  

AVDD Supply voltage

3  

V

AVDD  

1.8  

3.3  

3.8  

V

VREGVDD Operating supply

 

V

VREGVDD  

voltage

3 1  

DCDC in regulation  

2.4  

1.8  

1.8  

3.3  

3.3  

3.3  

3.8  

3.8  

3.8  

V

V

V

DCDC in bypass 50mA load  

DCDC not in use. DVDD external-  

ly shorted to VREGVDD  

VREGVDD Current  

I

VREGVDD  

V

RFVDD  

DCDC in bypass  

—

—

—

200  

mA  

V

RFVDD Operating supply  

voltage  

1.62  

V

VREGVDD  

DVDD Operating supply volt-

 

V

DVDD  

age  

1.62  

1.62  

1.62  

—

—

—

—

—

V

VREGVDD  

V

VREGVDD  

V

VREGVDD  

0.1  

V

V

V

V

PAVDD Operating supply  

voltage  

V

PAVDD  

V

IOVDD  

dV

DD  

IOVDD Operating supply  

voltage  

Difference between AVDD  

and VREGVDD, ABS(AVDD-  

VREGVDD)

2  

Core Clock Frequency  

f

CORE  

FWAIT = 1, VSCALE=0  

FWAIT = 0, VSCALE = 2  

—

—

—

—

40  

20  

MHz  

MHz  

Note:  

1. The minimum voltage required in bypass mode is calculated using R

BYP

from the DCDC specification table. Requirements for  

other loads can be calculated as V

DVDD_min

+I

LOAD

* R

BYP_max  

2. AVDD and VREGVDD pins should be physically shorted.  

3. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.  

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4.1.3 Thermal

 

Characteristics  

Table 4.3.

 

Thermal Characteristics  

Parameter  

Symbol  

THETA

JA  

Test Condition  

Min  

Typ  

Max  

Unit  

Thermal Resistance  

QFN48 Package, 2-Layer PCB,  

Air velocity = 0 m/s  

—

TBD  

—

°C/W  

QFN48 Package, 2-Layer PCB,  

Air velocity = 1 m/s  

—

—

—

—

—

—

—

—

—

—

—

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

—

—

—

—

—

—

—

—

—

—

—

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

°C/W  

QFN48 Package, 2-Layer PCB,  

Air velocity = 2 m/s  

QFN48 Package, 4-Layer PCB,  

Air velocity = 0 m/s  

QFN48 Package, 4-Layer PCB,  

Air velocity = 1 m/s  

QFN48 Package, 4-Layer PCB,  

Air velocity = 2 m/s  

BGA125 Package, 2-Layer PCB,  

Air velocity = 0 m/s  

BGA125 Package, 2-Layer PCB,  

Air velocity = 1 m/s  

BGA125 Package, 2-Layer PCB,  

Air velocity = 2 m/s  

BGA125 Package, 4-Layer PCB,  

Air velocity = 0 m/s  

BGA125 Package, 4-Layer PCB,  

Air velocity = 1 m/s  

BGA125 Package, 4-Layer PCB,  

Air velocity = 2 m/s  

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4.1.4 DC-DC

 

Converter  

Test conditions: L_DCDC=4.7 μH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 μF (Murata GRM188R71A105KA61D), V_DCDC_I=3.3  

V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.  

Table 4.4.

 

DC-DC Converter  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Input voltage range  

V

DCDC_I  

Bypass mode, I

DCDC_LOAD

= 50  

mA  

1.8  

—

V

VREGVDD_  

V

MAX  

Low noise (LN) mode, 1.8 V out-  

put, I

DCDC_LOAD

= 100 mA, or  

Low power (LP) mode, 1.8 V out-  

put, I

DCDC_LOAD

= 10 mA  

TBD  

—

V

VREGVDD_  

V

MAX  

Low noise (LN) mode, 1.8 V out-  

put, I

DCDC_LOAD

= 200 mA  

TBD  

1.8  

—

—

V

VREGVDD_  

V

V

MAX  

Output voltage programma-

 

V

DCDC_O  

ble range

1  

V

VREGVDD  

Regulation DC Accuracy  

ACC

DC  

Low Noise (LN) mode, 1.8 V tar-  

get output  

TBD  

TBD  

—

—

TBD  

TBD  

V

V

Regulation Window

4  

WIN

REG  

Low Power (LP) mode,  

LPCMPBIASEMxx

3

= 0, 1.8 V tar-  

get output, I

DCDC_LOAD

≤ 75 μA  

Low Power (LP) mode,  

TBD  

—

TBD  

V

LPCMPBIASEMxx

3

= 3, 1.8 V tar-  

get output, I

DCDC_LOAD

≤ 10 mA  

Steady-state output ripple  

V

R  

Radio disabled.  

—

—

3

—

mVpp  

mV  

CCM Mode (LNFORCECCM

3

=  

1), Load changes between 0 mA  

and 100 mA  

Output voltage under/over-  

shoot  

V

OV  

—

TBD  

DCM Mode (LNFORCECCM

3

=  

0), Load changes between 0 mA  

and 10 mA  

—

—

TBD  

mV  

Overshoot during LP to LN  

CCM/DCM mode transitions com-  

pared to DC level in LN mode  

—

—

200  

50  

—

—

mV  

mV  

Undershoot during BYP/LP to LN  

CCM (LNFORCECCM

3

= 1) mode  

transitions compared to DC level  

in LN mode  

Undershoot during BYP/LP to LN  

—

125  

—

mV  

DCM (LNFORCECCM

3

= 0) mode  

transitions compared to DC level  

in LN mode  

DC line regulation  

DC load regulation  

V

REG  

Input changes between  

V

VREGVDD_MAX

and 2.4 V  

—

—

0.1  

0.1  

—

—

%

%

I

REG  

Load changes between 0 mA and  

100 mA in CCM mode  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Max load current  

I

LOAD_MAX  

Low noise (LN) mode, Heavy  

Drive

2  

—

—

TBD  

mA  

Low noise (LN) mode, Medium  

Drive

2  

—

—

—

—

—

—

—

—

TBD  

TBD  

TBD  

TBD  

mA  

mA  

μA  

Low noise (LN) mode, Light  

Drive

2  

Low power (LP) mode,  

LPCMPBIASEMxx

3

= 0  

Low power (LP) mode,  

LPCMPBIASEMxx

3

= 3  

mA  

DCDC nominal output ca-  

pacitor  

C

DCDC  

25% tolerance  

1

4.7  

4.7  

1.2  

4.7  

4.7  

μF  

μH  

Ω

DCDC nominal output induc-

 

L

DCDC  

tor  

20% tolerance  

4.7  

—

Resistance in Bypass mode

 

R

BYP  

TBD  

Note:  

1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, V

VREGVDD  

2. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-  

um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.  

3. In EMU_DCDCMISCCTRL register  

4. LP mode controller is a hysteretic controller that maintains the output voltage withinthe specified limits  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.5 Current

 

Consumption  

4.1.5.1 Current

 

Consumption 3.3 V without DC-DC Converter  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T

OP

= 25 °C. DCDC is off.  

Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T

OP

= 25 °C.  

Table 4.5.

 

Current Consumption 3.3 V without DC-DC Converter  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

mode with all peripherals dis-  

abled  

38.4 MHz crystal, CPU running  

while loop from flash

1  

—

129  

—

μA/MHz  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

—

—

—

99  

99  

—

TBD  

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

123  

101  

277  

TBD  

234  

80  

26 MHz HFRCO, CPU running  

while loop from flash  

TBD  

TBD  

—

1 MHz HFRCO, CPU running  

while loop from flash  

Current consumption in EM0

 

I

ACTIVE_VS  

mode with all peripherals dis-  

abled and voltage scaling  

enabled  

19 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

—

38.4 MHz crystal

1  

38 MHz HFRCO  

26 MHz HFRCO  

1 MHz HFRCO  

19 MHz HFRCO  

1 MHz HFRCO  

Current consumption in EM1

 

I

EM1  

mode with all peripherals dis-  

abled and voltage scaling  

enabled  

—

—

—

—

—

—

50  

52  

TBD  

TBD  

TBD  

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

228  

TBD  

193  

Current consumption in EM1

 

I

EM1_VS  

mode with all peripherals dis-  

abled  

—

Current consumption in EM2

 

I

EM2_VS  

mode, with votage scaling  

enabled.  

Full RAM retention and RTCC  

running from LFXO  

—

—

—

—

3.0  

3.3  

2.4  

2.7  

—

—

μA  

μA  

μA  

μA  

Full RAM retention and RTCC  

running from LFRCO  

1 bank RAM retention and RTCC  

running from LFRCO  

TBD  

TBD  

Current consumption in EM3

 

I

EM3_VS  

mode, with voltage scaling  

enabled.  

Full RAM retention and CRYO-  

TIMER running from ULFRCO  

Current consumption in  

EM4H mode, with voltage  

scaling enabled.  

I

EM4H_VS  

128 byte RAM retention, RTCC  

running from LFXO  

—

—

—

1.1  

0.6  

0.5  

—

—

μA  

μA  

μA  

128 byte RAM retention, CRYO-  

TIMER running from ULFRCO  

128 byte RAM retention, no RTCC  

TBD  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in  

EM4S mode  

I

EM4S  

No RAM retention, no RTCC  

—

0.1  

TBD  

μA  

Note:  

1. CMU_HFXOCTRL_LOWPOWER=0.  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.5.2 Current

 

Consumption 3.3 V using DC-DC Converter  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC  

output. T

OP

= 25 °C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process  

variation at T

OP

= 25 °C.  

Table 4.6.

 

Current Consumption 3.3 V using DC-DC Converter  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE_DCM  

mode with all peripherals dis-  

abled, DCDC in Low Noise  

DCM mode

2

.  

38.4 MHz crystal, CPU running  

while loop from flash

4  

—

TBD  

—

μA/MHz  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

—

66  

—

—

—

—

—

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

66  

38 MHz HFRCO, CPU running  

CoreMark from flash  

TBD  

TBD  

TBD  

TBD  

26 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

Current consumption in EM0

 

I

ACTIVE_CCM  

mode with all peripherals dis-  

abled, DCDC in Low Noise  

CCM mode

1

.  

38.4 MHz crystal, CPU running  

while loop from flash

4  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

—

—

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

—

—

—

—

—

—

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

26 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

Current consumption in EM0

 

I

ACTIVE_CCM_VS

19 MHz HFRCO, CPU running  

mode with all peripherals dis-  

abled and voltage scaling  

enabled, DCDC in Low  

Noise CCM mode

1

.  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

38.4 MHz crystal

4  

38 MHz HFRCO  

26 MHz HFRCO  

1 MHz HFRCO  

19 MHz HFRCO  

1 MHz HFRCO  

Current consumption in EM1

 

I

EM1_DCM  

mode with all peripherals dis-  

abled, DCDC in Low Noise  

—

TBD  

—

μA/MHz  

—

—

—

—

—

36  

—

—

—

—

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

DCM mode

2

.  

43  

TBD  

TBD  

TBD  

Current consumption in EM1

 

I

EM1_DCM_VS  

mode with all peripherals dis-  

abled and voltage scaling  

enabled, DCDC in Low  

Noise DCM mode

2

.  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM2

 

I

EM2_VS  

mode, with votage scaling  

Full RAM retention and RTCC  

running from LFXO  

—

TBD  

—

μA  

enabled, DCDC in LP mode.  

.

Full RAM retention and RTCC  

running from LFRCO  

—

—

—

2.1  

1.5  

—

—

—

μA  

μA  

μA  

3

1 bank RAM retention and RTCC  

running from LFRCO  

Full Ram retention and RTCC run-  

ning from LFRCO. 5Ksps 12-bit  

ADC using internal reference, du-  

ty-cycled operation. Wake on win-  

dow compare. 16Mhz ADCLK,  

IBIASPROT=0, GPBIASACC=1,  

WARMUPMODE=NORMAL  

TBD  

Full RAM retention, LEUART con-  

figured for 9600 baud RX. No traf-  

fic present. Wake on RX.  

—

—

TBD  

1.75  

—

—

μA  

μA  

Current consumption in EM3

 

I

EM3_VS  

mode, with voltage scaling  

enabled.  

Full RAM retention and CRYO-  

TIMER running from ULFRCO  

Current consumption in  

EM4H mode, with voltage  

scaling enabled.  

I

EM4H_VS  

128 byte RAM retention, RTCC  

running from LFXO  

—

—

TBD  

TBD  

—

—

μA  

μA  

128 byte RAM retention, CRYO-  

TIMER running from ULFRCO  

128 byte RAM retention, no RTCC  

No RAM retention, no RTCC  

—

—

0.52  

TBD  

—

—

μA  

μA  

Current consumption in  

EM4S mode  

I

EM4S  

Note:  

1. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.  

2. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.  

3. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIM-  

SEL=1, ANASW=DVDD.  

4. CMU_HFXOCTRL_LOWPOWER=0.  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.5.3 Current

 

Consumption 1.8 V without DC-DC Converter  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.8 V. T

OP

= 25 °C. DCDC is off.  

Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T

OP

= 25 °C.  

Table 4.7.

 

Current Consumption 1.8 V without DC-DC Converter  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in EM0

 

I

ACTIVE  

mode with all peripherals dis-  

abled  

38.4 MHz crystal, CPU running  

while loop from flash

1  

—

129  

—

μA/MHz  

38 MHz HFRCO, CPU running  

Prime from flash  

—

—

—

—

—

—

—

—

99  

99  

—

—

—

—

—

—

—

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

38 MHz HFRCO, CPU running  

while loop from flash  

38 MHz HFRCO, CPU running  

CoreMark from flash  

123  

101  

275  

TBD  

232  

80  

26 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

Current consumption in EM0

 

I

ACTIVE_VS  

mode with all peripherals dis-  

abled and voltage scaling  

enabled  

19 MHz HFRCO, CPU running  

while loop from flash  

1 MHz HFRCO, CPU running  

while loop from flash  

38.4 MHz crystal

1  

38 MHz HFRCO  

26 MHz HFRCO  

1 MHz HFRCO  

19 MHz HFRCO  

1 MHz HFRCO  

Current consumption in EM1

 

I

EM1  

mode with all peripherals dis-  

abled and voltage scaling  

enabled  

—

—

—

—

—

50  

52  

—

—

—

—

—

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

μA/MHz  

226  

TBD  

191  

Current consumption in EM1

 

I

EM1_VS  

mode with all peripherals dis-  

abled  

Current consumption in EM2

 

I

EM2_VS  

mode, with votage scaling  

enabled.  

Full RAM retention and RTCC  

running from LFXO  

—

—

—

—

3.4  

3.5  

2.7  

3.0  

—

—

—

—

μA  

μA  

μA  

μA  

Full RAM retention and RTCC  

running from LFRCO  

1 bank RAM retention and RTCC  

running from LFRCO  

Current consumption in EM3

 

I

EM3_VS  

mode, with voltage scaling  

enabled.  

Full RAM retention and CRYO-  

TIMER running from ULFRCO  

Current consumption in  

EM4H mode, with voltage  

scaling enabled.  

I

EM4H_VS  

128 byte RAM retention, RTCC  

running from LFXO  

—

—

1.5  

1.0  

—

—

μA  

μA  

128 byte RAM retention, CRYO-  

TIMER running from ULFRCO  

128 byte RAM retention, no RTCC  

no RAM retention, no RTCC  

—

—

1.0  

0.5  

—

—

μA  

μA  

Current consumption in  

EM4S mode  

I

EM4S  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Note:  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

1. CMU_HFXOCTRL_LOWPOWER=0.  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.5.4 Current

 

Consumption Using Radio 3.3 V with DC-DC  

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V. T

OP

= 25  

°C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T

OP

= 25  

°C.  

Table 4.8.

 

Current Consumption Using Radio 3.3 V with DC-DC  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in re-  

ceive mode, active packet  

reception (MCU in EM1 @  

38.4 MHz, peripheral clocks  

disabled)  

I

RX  

500 kbit/s, 2GFSK, F = 915 MHz,  

Radio clock prescaled by 4  

—

8.9  

TBD  

mA  

38.4 kbit/s, 2GFSK, F = 868 MHz,  

Radio clock prescaled by 4  

—

—

—

—

—

—

—

8.6  

8.4  

TBD  

TBD  

TBD  

TBD  

TBD  

—

mA  

mA  

mA  

mA  

mA  

mA  

mA  

38.4 kbit/s, 2GFSK, F = 490 MHz,  

Radio clock prescaled by 4  

50 kbit/s, 2GFSK, F = 433 MHz,  

Radio clock prescaled by 4  

8.2  

38.4 kbit/s, 2GFSK, F = 315 MHz,  

Radio clock prescaled by 4  

8.4  

38.4 kbit/s, 2GFSK, F = 169 MHz,  

Radio clock prescaled by 4  

8.0  

1 Mbit/s, 2GFSK, F = 2.4 GHz,  

Radio clock prescaled by 4  

10.0  

10.8  

802.15.4 receiving frame, F = 2.4  

GHz, Radio clock prescaled by 3  

—

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Current consumption in  

transmit mode (MCU in EM1  

@ 38.4 MHz, peripheral  

clocks disabled)  

I

TX  

F = 915 MHz, CW, 20 dBm  

match, PAVDD connected directly  

to external 3.3V supply  

—

80.2  

TBD  

mA  

F = 915 MHz, CW, 14 dBm  

match, PAVDD connected to  

DCDC output  

—

—

—

—

—

—

—

—

35.5  

84.9  

34.5  

82.8  

32.3  

19.5  

32.5  

80.2  

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

TBD  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

mA  

F = 868 MHz, CW, 20 dBm  

match, PAVDD connected directly  

to external 3.3V supply  

F = 868 MHz, CW, 14 dBm  

match, PAVDD connected to  

DCDC output  

F = 490 MHz, CW, 20 dBm  

match, PAVDD connected directly  

to external 3.3V supply  

F = 433 MHz, CW, 14 dBm  

match, PAVDD connected to  

DCDC output  

F = 433 MHz, CW, 10 dBm  

match, PAVDD connected to  

DCDC output  

F = 315 MHz, CW, 14 dBm  

match, PAVDD connected to  

DCDC output  

F = 169 MHz, CW, 20 dBm  

match, PAVDD connected directly  

to external 3.3V supply  

F = 2.4 GHz, CW, 0 dBm output  

power, Radio clock prescaled by 3  

—

—

—

—

—

8.2  

—

—

—

—

—

mA  

mA  

mA  

mA  

mA  

F = 2.4 GHz, CW, 3 dBm output  

power  

16.5  

23.3  

32.7  

83.9  

F = 2.4 GHz, CW, 8 dBm output  

power  

F = 2.4 GHz, CW, 10.5 dBm out-  

put power  

F = 2.4 GHz, CW, 16.5 dBm out-  

put power, PAVDD connected di-  

rectly to external 3.3V supply  

F = 2.4 GHz, CW, 19.5 dBm out-  

put power, PAVDD connected di-  

rectly to external 3.3V supply  

—

—

126.7  

51  

—

—

mA  

nA  

RFSENSE current consump-

 

I

RFSENSE  

tion  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.6 Wake

 

Up Times  

Table 4.9.

 

Wake Up Times  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Wakeup time from EM1  

t

EM1_WU  

—

3

—

AHB  

Clocks  

Wake up from EM2  

Wake up from EM3  

t

EM2_WU  

Code execution from flash  

Code execution from RAM  

Code execution from flash  

Code execution from RAM  

Executing from flash  

—

—

—

—

—

10.7  

3

—

—

—

—

—

μs  

μs  

μs  

μs  

μs  

t

EM3_WU  

10.7  

3

Wake up from EM4H

1  

Wake up from EM4S

1  

t

EM4H_WU  

t

EM4S_WU  

t

RESET  

60  

Executing from flash  

—

290  

—

μs  

Time from release of reset  

source to first instruction ex-  

ectution.  

Soft Pin Reset released  

Any other reset released  

—

—

TBD  

TBD  

TBD  

TBD  

μs  

μs  

Power Mode Scaling time  

t

SCALE  

SCALE2 to SCALE0  

—

TBD  

TBD  

μs  

Note:  

1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.  

4.1.7 Brown

 

Out Detector (BOD)  

Table 4.10.

 

Brown Out Detector (BOD)  

Parameter  

Symbol  

Test Condition  

DVDD rising  

Min  

—

Typ  

—

Max  

TBD  

—

Unit  

V

DVDD BOD threshold  

V

DVDDBOD  

DVDD falling  

TBD  

—

—

V

DVDD BOD hysteresis  

DVDD BOD response time  

AVDD BOD threshold  

V

DVDDBOD_HYST  

24  

2.4  

—

—

mV  

μs  

V

t

DVDDBOD_DELAY

Supply drops at 0.1V/μs rate  

—

—

V

AVDDBOD  

AVDD rising  

AVDD falling  

—

TBD  

—

TBD  

—

—

V

AVDD BOD hysteresis  

AVDD BOD response time  

EM4 BOD threshold  

V

AVDDBOD_HYST  

21  

2.4  

—

—

mV  

μs  

V

t

AVDDBOD_DELAY

Supply drops at 0.1V/μs rate  

—

—

V

EM4DBOD  

AVDD rising  

AVDD falling  

—

TBD  

—

TBD  

—

—

V

EM4 BOD hysteresis  

V

EM4BOD_HYST  

46  

300  

—

mV  

μs  

EM4 BOD response time  

t

EM4BOD_DELAY

Supply drops at 0.1V/μs rate  

—

—

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.8 Frequency

 

Synthesizer  

Table 4.11.

 

Frequency Synthesizer  

Parameter  

Symbol  

Test Condition  

2400 – 2483.5 MHz  

779 – 956 MHz  

584 – 717 MHz  

358 – 574 MHz  

191 – 358 MHz  

110 – 191 MHz  

2400 – 2483.5 MHz  

779 – 956 MHz  

584 – 717 MHz  

358 – 574 MHz  

191 – 358 MHz  

110 – 191 MHz  

2400 – 2483.5 MHz  

779 – 956 MHz  

584 – 717 MHz  

358 – 574 MHz  

191 – 358 MHz  

110 – 191 MHz  

2400 – 2483.5 MHz  

779 – 956 MHz  

584 – 717 MHz  

358 – 574 MHz  

191 – 358 MHz  

110 – 191 MHz  

Min  

2400  

779  

584  

358  

191  

110  

—

Typ  

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Max  

2483.5  

956  

717  

574  

358  

191  

73  

Unit  

MHz  

MHz  

MHz  

MHz  

MHz  

MHz  

Hz  

RF Synthesizer Frequency  

range  

f

RANGE  

LO tuning frequency resolu-

 

f

RES  

tion with 38.4 MHz crystal  

—

24  

Hz  

—

18.3  

12.2  

7.3  

Hz  

—

Hz  

—

Hz  

—

4.6  

Hz  

Frequency deviation resolu-

 

df

RES  

tion with 38.4 MHz crystal  

—

73  

Hz  

—

24  

Hz  

—

18.3  

12.2  

7.3  

Hz  

—

Hz  

—

Hz  

—

4.6  

Hz  

Maximum frequency devia-  

tion with 38.4 MHz crystal  

df

MAX  

—

1677  

559  

419  

280  

167  

105  

kHz  

kHz  

kHz  

kHz  

kHz  

kHz  

—

—

—

—

—

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.9 2.4

 

GHz RF Transceiver Characteristics  

4.1.9.1 RF

 

Transmitter General Characteristics for 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T

OP

= 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.  

Table 4.12.

 

RF Transmitter General Characteristics for 2.4 GHz Band  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Maximum TX power

1  

POUT

MAX  

19.5 dBm-rated part numbers.  

PAVDD connected directly to ex-  

ternal 3.3V supply

2  

—

19.5  

—

dBm  

Minimum active TX Power  

Output power step size  

POUT

MIN  

CW  

-30  

1

—

—

—

dBm  

dB  

POUT

STEP  

-5 dBm< Output power < 0 dBm  

—

—

0 dBm < output power <  

POUT

MAX  

0.5  

dB  

Output power variation vs  

supply at POUT

MAX  

POUT

VAR_V  

1.8 V < V

VREGVDD

< 3.3 V,  

PAVDD connected directly to ex-  

ternal supply, for output power >  

10.5 dBm.  

—

4.5  

—

dB  

1.85 V < V

VREGVDD

< 3.3 V using  

DC-DC converter  

—

—

2.2  

1.5  

1.5  

0.4  

—

—

—

dB  

dB  

Output power variation vs  

temperature at POUT

MAX  

POUT

VAR_T  

From -40 to +85 °C, PAVDD con-  

nected to DC-DC output  

From -40 to +85 °C, PAVDD con-  

nected to external supply  

—

—

dB  

Output power variation vs RF

 

POUT

VAR_F  

frequency at POUT

MAX  

Over RF tuning frequency range  

—

—

dB  

RF tuning frequency range  

F

RANGE  

2400  

2483.5  

MHz  

Note:  

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-  

ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.  

2. For Bluetooth, the Maximum TX power on Channel 2456 is limited to +15 dBm to comply with In-band Spurious emissions.  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.9.2 RF

 

Receiver General Characteristics for 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T

OP

= 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.  

Table 4.13.

 

RF Receiver General Characteristics for 2.4 GHz Band  

Parameter  

Symbol  

F

RANGE  

SPUR

RX  

Test Condition  

Min  

2400  

—

Typ  

—

Max  

2483.5  

—

Unit  

MHz  

dBm  

dBm  

dBm  

RF tuning frequency range  

Receive mode maximum  

spurious emission  

30 MHz to 1 GHz  

1 GHz to 12 GHz  

-57  

—

-47  

—

Max spurious emissions dur-

 

SPUR

RX_FCC  

ing active receive mode, per  

FCC Part 15.109(a)  

216 MHz to 960 MHz, Conducted  

Measurement  

—

-55.2  

—

Above 960 MHz, Conducted  

Measurement  

—

—

-47.2  

-24  

—

—

dBm  

dBm  

Level above which  

RFSENSE will trigger

1  

RFSENSE

TRIG  

CW at 2.45 GHz  

Level below which  

RFSENSE will not trigger

1  

RFSENSE

THRES

CW at 2.45 GHz  

—

-50  

—

dBm  

1% PER Sensitivity  

SENS

2GFSK  

2 Mbps 2GFSK signal  

250 kbps 2GFSK signal  

—

—

-89.2  

-99.1  

—

—

dBm  

dBm  

Note:  

1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.9.3 RF

 

Transmitter Characteristics for 1Mbps 2GFSK in the 2.4GHz Band  

Unless otherwise indicated, typical conditions are: T

OP

= 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.  

Table 4.14.

 

RF Transmitter Characteristics for 1Mbps 2GFSK in the 2.4GHz Band  

Parameter  

Symbol  

TXBW  

Test Condition  

Min  

—

Typ  

740  

-6.5  

Max  

—

Unit  

Transmit 6dB bandwidth  

Power spectral density limit  

kHz  

PSD

LIMIT  

Per FCC part 15.247 at 10 dBm  

Per FCC part 15.247 at 20 dBm  

—

—

dBm/  

3kHz  

—

—

—

—

-2.6  

10  

—

—

—

—

dBm/  

3kHz  

Per ETSI 300.328 at 10 dBm/1  

MHz  

dBm  

MHz  

dBm  

Occupied channel bandwidth

 

OCP

ETSI328  

per ETSI EN300.328  

99% BW at highest and lowest  

channels in band  

1.1  

-47  

Emissions of harmonics out-

 

SPUR

HRM_FCC

2nd,3rd, 5, 6, 8, 9,10 harmonics;  

of-band, per FCC part  

15.247  

continuous transmission of modu-  

lated carrier  

Spurious emissions out-of-  

band, per FCC part 15.247,  

excluding harmonics cap-  

tured in SPUR

HARM,FCC

. Re-  

stricted Bands  

SPUR

OOB_FCC  

Above 2.483 GHz or below 2.4  

GHz; continuous transmission of  

—

—

-47  

-26  

—

—

dBm  

dBc  

modulated carrier

1  

Above 2.483 GHz or below 2.4  

GHz; continuous transmission of  

modulated carrier  

Spurious emissions out-of-  

band; per ETSI 300.328  

SPUR

ETSI328  

[2400-BW to 2400] MHz, [2483.5  

to 2483.5+BW] MHz  

—

—

-16  

-26  

—

—

dBm  

dBm  

[2400-2BW to 2400-BW] MHz,  

[2483.5+BW to 2483.5+2BW]  

MHz per ETSI 300.328  

Spurious emissions per ETSI

 

SPUR

ETSI440  

EN300.440  

47-74 MHz,87.5-108 MHz,  

174-230 MHz, 470-862 MHz  

—

-60  

—

dBm  

25-1000 MHz  

1-12 GHz  

—

—

-42  

-36  

—

—

dBm  

dBm  

Note:  

1. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value.  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.9.4 RF

 

Receiver Characteristics for 1Mbps 2GFSK in the 2.4GHz Band  

Unless otherwise indicated, typical conditions are: T

OP

= 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.  

Table 4.15.

 

RF Receiver Characteristics for 1Mbps 2GFSK in the 2.4GHz Band  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Signal is reference signal

1

. Packet  

length is 20 bytes.  

Max usable receiver input  

level, 0.1% BER  

SAT  

—

10  

—

dBm  

Signal is reference signal

1

. Using  

DC-DC converter  

Sensitivity, 0.1% BER  

SENS  

—

-95  

—

dBm  

Signal to co-channel interfer-

 

C/I

CC  

er, 0.1% BER  

Desired signal 3 dB above refer-  

ence sensitivity  

—

—

8.3  

-3  

—

—

dB  

dB  

N+1 adjacent channel (1  

MHz) selectivity, 0.1% BER,  

with allowable exceptions.  

Desired is reference signal at  

-67 dBm  

C/I

1+  

Interferer is reference signal at +1  

MHz offset. Desired frequency  

2402 MHz ≤ Fc ≤ 2480 MHz  

N-1 adjacent channel (1  

MHz) selectivity, 0.1% BER,  

with allowable exceptions.  

Desired is reference signal at  

-67 dBm  

C/I

1-  

Interferer is reference signal at -1  

MHz offset. Desired frequency  

2402 MHz ≤ Fc ≤ 2480 MHz  

—

-0.5  

—

dB  

Alternate (2 MHz) selectivity,

 

C/I

2  

0.1% BER, with allowable  

exceptions. Desired is refer-  

ence signal at -67 dBm  

Interferer is reference signal at ± 2  

MHz offset. Desired frequency  

2402 MHz ≤ Fc ≤ 2480 MHz  

—

—

-43  

—

—

dB  

dB  

Alternate (3 MHz) selectivity,

 

C/I

3  

0.1% BER, with allowable  

exceptions. Desired is refer-  

ence signal at -67 dBm  

Interferer is reference signal at ± 3  

MHz offset. Desired frequency  

2404 MHz ≤ Fc ≤ 2480 MHz  

-46.7  

Selectivity to image frequen-

 

C/I

IM  

cy, 0.1% BER. Desired is ref-  

erence signal at -67 dBm  

Interferer is reference signal at im-  

age frequency with 1 MHz preci-  

sion  

—

—

-38.7  

-48.2  

—

—

dB  

dB  

Selectivity to image frequen-

 

C/I

IM+1  

cy +1 MHz, 0.1% BER. De-  

sired is reference signal at  

-67 dBm  

Interferer is reference signal at im-  

age frequency +1 MHz with 1  

MHz precision  

Blocking, 0.1% BER, Desired

 

BLOCK

OOB  

is reference signal at -67  

dBm. Interferer is CW in  

OOB range.  

Interferer frequency 30 MHz ≤ f ≤  

2000 MHz  

—

—

-27  

-32  

-32  

-27  

—

—

—

—

—

—

dBm  

dBm  

dBm  

dBm  

dBm  

Interferer frequency 2003 MHz ≤ f  

≤ 2399 MHz  

Interferer frequency 2484 MHz ≤ f  

≤ 2997 MHz  

—

Interferer frequency 3 GHz ≤ f ≤  

12.75 GHz  

—

Upper limit of input power  

range over which RSSI reso-  

lution is maintained  

RSSI

MAX  

TBD  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Lower limit of input power  

range over which RSSI reso-  

lution is maintained  

RSSI

MIN  

—

—

TBD  

dBm  

RSSI resolution  

RSSI

RES  

Over RSSI

MIN

to RSSI

MAX  

—

—

TBD  

dB  

Note:  

1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;  

interferer data = PRBS15; frequency accuracy better than 1 ppm  

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EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet  

Electrical Specifications  

4.1.9.5 RF

 

Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band  

Unless otherwise indicated, typical conditions are: T

OP

= 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.  

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.  

Table 4.16.

 

RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band  

Parameter  

Symbol  

Test Condition  

Min  

Typ  

Max  

Unit  

Error vector magnitude (off-

 

EVM  

set EVM), per  

802.15.4-2011, not including  

2415 MHz channel  

Average across frequency. Signal  

is DSSS-OQPSK reference pack-  

et

1  

—

5.5