SKYWORKS-SILICON-LABS-EFR32MG1P232F256IM32-C0R
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EFR32MG1 Mighty Gecko Multi-Protocol
SoC Family Data Sheet
The Mighty Gecko multi-protocol family of SoCs is part of the
Wireless Gecko portfolio. Mighty Gecko SoCs are ideal for ena-
KEY FEATURES
bling energy-friendly multi-protocol, multi-band networking for IoT
devices.
• 32-bit
ARM® Cortex®-M4 core with 40
M
z maximum operating frequency
•
56 kB of flash and 32 kB of RAM
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable power amplifier, and no-compromise MCU features.
• Supports
Zigbee, Thread and Bluetooth
Low Energy
• 12-channel
Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
Mighty Gecko applications include:
• Connected
Home
• Lighting
• Autonomous
Hardware Crypto Accelerator
and Random Number Generator
• Health
and Wellness
• Metering
• Integrated
PA with up to 19 dBm (2.4
GHz) or 20 dBm (Sub-GHz) TX power
• Integrated
balun for 2.4 GHz
• Building
Automation and Security
• Robust
peripheral set and up to 32 GPIO
Core / Memory
Clock Management
Energy Management
Other
High Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Voltage
CRYPTO
Voltage Monitor
Regulator
ARM Cortex
TM
M4 processor
Memo
y
with DSP extensions and FPU
Protection Unit
Auxiliary High
Frequency RC
Oscillator
Low Frequency
RC Oscillator
DC-DC
Power-On Reset
Converter
CRC
Low Frequency
Crystal
Oscillator
Ultra Low
Frequency RC
Oscillator
Flash Program
RAM Memory
Memory
Brown-Out
Detector
Debug Interface
DMA Controller
32-bit bus
Peripheral Reflex System
Radio Transceiver
Serial
I/O Ports
Timers and Triggers
Analog I/F
Interfaces
External
Interrupts
Sub-GHz RF
Frontend:
LNA, PA,
DEMOD
USART
Timer/Counter
Protocol Timer
ADC
I/Q Mixer
Low Energy
UART
TM
General
Purpose I/O
Low Energy
Timer
Analog
Comparator
IFADC
AGC
PGA
Watchdog Timer
RFSENSE
Real Time
Counter and
Calendar
I
2
C
Pin Reset
Pulse Counter
IDAC
2.4 GHz RF
Frontend:
LNA, PA,
I/Q Mixer
Frequency
Synthesizer
BALUN
To RF
Frontend
Circuits
MOD
Pin Wakeup
Cryotimer
Lowest power mode with peripheral operational:
EM0—Active EM1—Sleep
EM2—Deep Sleep
EM3—Stop
EM4—Hibernate
EM4—Shutoff
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Rev. 1.4
EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Feature List
1. Feature
List
The EFR32MG1 highlighted features are listed below.
•
Low Power Wireless System-on-Chip
•
Wide selection of MCU peripherals
High Performance 32-bit 40 MHz ARM Cortex
®
-M4 with
DSP instruction and floating-point unit for efficient signal
processing
•
• 12-bit
1 Msps SAR Analog to Digital Converter (ADC)
• 2
× Analog Comparator (ACMP)
• Digital
to Analog Current Converter (IDAC)
• 256
kB flash program memory
• Up
to 32 pins connected to analog channels (APORT)
shared between analog peripherals
• 32
kB RAM data memory
• 2.4
GHz and Sub-GHz radio operation
• Transmit
power:
• Up
to 32 General Purpose I/O pins with output stat
ten-
tion and asynchronous interrupts
• 8
Channel DMA Controller
• 2.4
GHz radio: Up to 19 dBm
• 12
Channel Peripheral Reflex System (PRS)
• 2
× 16-bit Timer/Counter
• Sub-GHz
radio: Up to 20 dBm
•
Low Energy Consumption
• 3
or 4 Compare/Capture/PW
nels
• 32-bit
Real Time Counter and Cale
r
• 16-bit
Low Energy Timer for waveform generation
• 9.8
mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz
• 8.7
mA RX current at 1 Mbps, GFSK, 2.4 GHz
• 7.6
mA RX current at 38.4 kbps, GFSK, 169 MHz
• 8.2
mA TX current at 0 dBm output power at 2.4 GHz
• 34.5
mA TX current at 14 dBm output power at 868 MHz
• 63
μA/MHz in Active Mode (EM0)
• 32-bit
Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode
• 16-bit
Pulse Counter with asynchronous operation
• Watchdog
T
mer wi
h dedicated RC oscillator
• 2.2
μA EM2 DeepSleep current (4 kB RAM retention and
RTCC running from LFRCO)
• 2
× Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I
2
S)
• Wake
on Radio with signal strength detection, preamble
pattern detection, frame detection and timeout
Low
rgy UART (LEUART
™
)
I
2
C in
face with SMBus support and address recognition
in EM3 Stop
•
•
•
High Receiver Performance
• -92.5
dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz
• -99
dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz
• -126.4
dBm sensitivity at 600 bps, GFSK, 915 MHz
• -121.4
dBm sensitivity at 2.4 kbps, GFSK, 868 MHz
• -107
dBm sensitivity at 4.8 kbps, OOK, 433 MHz
• -111.9
dBm sensitivity at 38.4 kbps, GFSK, 169 M
•
Supported Modulation Formats
• 2/4
(G)FSK with fully configurable shaping
• BPSK
/ DBPSK TX
•
Wide Operating Range
• 1.85
V to 3.8 V single power supply
• Integrated
DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• Standard
(-40 °C to 85 °C) and Extended (-40 °C to 125 °C)
temperature grades available
•
Support for Internet Security
• General
Purpose CRC
• Random
Number Generator
• OOK
/ ASK
• Hardware
Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
• Shaped
OQPSK / (G)MSK
• Configurable
DSSS and FEC
•
QFN32 5×5 mm Package
•
QFN48 7×7 mm Package
•
Supported Protocols
• Zigbee
• Thread
Bluetooth
®
Low Energy
•
• Proprietary
P
tocols
• Wirel
M-Bus
• Select
d IEEE 802.15.4g SUN-FSK PHYs
• Low
Power Wide Area Networks
•
Suitable for Systems Targeting Compliance With:
CC Part 90.210 Mask D, FCC part 15.247, 15.231, 15.249
• ETSI
Category I Operation, EN 300 220, EN 300 328
• ARIB
T-108, T-96
• China
regulatory
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Ordering Information
2. Ordering
Information
Table 2.1.
Ordering Information
Frequency Band
@ Max TX Power
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
Protocol
Stack
Flash RAM
Ordering Code
(kB)
(kB)
GPIO Package Temp
Range
EFR32MG1P233F256GM48-C0
Bluetooth LE
Zigbee
256
32
28
28
31
31
16
16
QFN48
48
QFN48
QFN48
QFN32
QFN32
-40 to +85°C
-40 to +125°C
-40 to +85°C
-40 to +125°C
-40 to +85°C
-40 to +125°C
Thread
Proprietary
Bluetooth LE
Zigbee
EFR32MG1P233F256IM48-C0
EFR32MG1P232F256GM48-C0
EFR32MG1P232F256IM48-C0
EFR32MG1P232F256GM32-C0
EFR32MG1P232F256IM32-C0
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
256
256
256
256
256
32
32
32
32
32
Thread
Proprietary
Bluetooth LE
Zigbee
2.4 GHz @ 19 dBm
2.4 GHz @ 19 dBm
2.4 GHz @ 19 dBm
2.4 GHz @ 19 dBm
Sub-GHz @ 20 dBm
Thread
Proprietary
Bluetooth LE
Zigbee
Thread
Proprietary
Bluetooth LE
Zigbee
Thread
Proprietary
Bluetooth LE
Zigbee
Thread
Proprietary
Zigbee
EFR32MG1
1F256GM48-C0
EFR32MG1P133F256GM48-C0
256
256
32
32
32
28
QFN48
QFN48
-40 to +85°C
-40 to +85°C
Proprietary
Bluetooth LE
Zigbee
2.4 GHz @ 16.5 dBm
Sub-GHz @ 16.5 dBm
Thread
Proprietary
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Ordering Information
Frequency Band
@ Max TX Power
2.4 GHz @ 16.5 dBm
Protocol
Stack
Flash RAM
Ordering Code
(kB)
(kB)
GPIO Package Temp
Range
EFR32MG1P132F256GM48-C0
Bluetooth LE
Zigbee
256
32
31
31
16
16
QFN48
QFN48
32
QFN32
-40 to +85°C
-40 to
25°C
-40 to +85°C
-40 to +125°C
Thread
Proprietary
Bluetooth LE
Zigbee
EFR32MG1P132F256IM48-C0
EFR32MG1P132F256GM32-C0
EFR32MG1P132F256IM32-C0
2.4 GHz @ 16.5 dBm
2.4 GHz @ 16.5 dBm
2.4 GHz @ 16.5 dBm
256
256
256
32
32
32
Thread
Proprietary
Bluetooth LE
Zigbee
Thread
Proprietary
Bluetooth LE
Zigbee
Thread
Proprietary
Zigbee
EFR32MG1P131F256GM48-C0
EFR32MG1B232F256GM48-C0
EFR32MG1B232F256IM48-C0
EFR32MG1B232F256GM32-C0
EFR32MG1B132F256GM48-C0
EFR32MG1B132F256GM32-C0
EFR32MG1
32F256GM48-C0
EF
G1V132F256GM32-C0
Sub-GHz @ 16.5 dBm
2.4 GHz @ 19 dBm
2.4 GHz @ 19 dBm
2.4 GHz @ 19 dBm
2.4 GHz @ 16.5 dBm
2.4 GHz @ 16.5 dBm
2.4 GHz @ 8 dBm
2.4 GHz @ 8 dBm
256
256
256
256
256
256
256
256
32
32
32
32
32
32
32
32
32
31
31
16
31
16
31
16
QFN48
QFN48
QFN48
QFN32
QFN48
QFN32
QFN48
QFN32
-40 to +85°C
-40 to +85°C
-40 to +125°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
Proprietary
Zigbee
Thread
Zigbee
Thread
Zigbee
Thread
Zigbee
Thread
Zigbee
Thread
Zigbee
Thread
Zigbee
Thread
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Rev. 1.4
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Ordering Information
EFR32 X G 1 P 132 F 256 G
M 32
–
C0 R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN), J (CSP)
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
Performance Grade – P (Performance), B (Basic), V (Value)
Series
Gecko
Family – M (Mighty), B (Blue), F (Flex)
Wireless Gecko 32-bit
Figure 2.1.
Ordering Code Key
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Table of Contents
1. Feature
List .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2. Ordering
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3. System
Overview .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3.1 Introduction .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3.2 Radio .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 9
3.2.1 Antenna
Interface .
. . . . . . . . . . . . . . . . . . . . . . . . .
10
3.2.2 Fractional-N
Frequency Synthesizer
. . . . . . . . . . . . . . . . . . . . .10
3.2.3 Receiver
Architecture .
. . . . . . . . . . . . . . . . . . . . . . . . .10
3.2.4 Transmitter
Architecture . . . . . . . . . . . . . . . . . .
. . . . . .10
3.2.5 Wake
on Radio
. . . . . . . . . . . . . . . . . . . . .
. . . . . .11
3.2.6 RFSENSE .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2.7 Flexible
Frame Handling
. . . . . . . . . . . . . . . . . . . . . . . . .11
3.2.8 Packet
and State Trace
. . . . . . . . . . . . . . . . . . . . . . . . .11
3.2.9 Data
Bufferin
g
. . . . . . . . . . . . . . . . . .
. . . . . . . . . .11
3.2.10 Radio
Controller (RAC)
. . . . . . . . . . . . . . . . . . . . . . . . .12
3.2.11 Random
Number Generator
. . . . . . . . . . . . . . . . . . . . . . .12
3.3 Power
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.3.1 Energy
Management Unit (EMU)
. . . . . . .
. . . . . . . . . . . . . .13
3.3.2 DC-DC
Converter .
. . . . . . . . . . . . . . . . . . . . . . . . . .13
3.4 General
Purpose Input/Output (GPIO)
. . .
. . . . . . . . . . . . . . . . . .13
3.5 Clocking .
. . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .13
3.5.1 Clock
Management Unit (CMU) .
. . . . . . . . . . . . . . . . . . . . . .13
3.5.2 Internal
and External Oscillators.
. . . . . . . . . . . . . . . . . . . .13
3.6 Counters/Timers
and PWM .
. . . . . . . . . . . . . . . . . . . . . . . . .14
3.6.1 Timer/Counter
(TIMER) .
. . . . . . . . . . . . . . . . . . . . . . .14
3.6.2 Real
Time Counter and Calendar (RTCC)
. . . . . . . . . . . . . . . . . . .14
3.6.3 Low
Energy Timer (LETIMER)
. . . . . . . . . . . . . . . . . . . . . . .14
3.6.4 Ultra
Low Power Wake-up Timer (CRYOTIMER)
. . . . . . . . . . . . . . . . .14
3.6.5 Pulse
Counter (PCNT) .
. . . . . . . . . . . . . . . . . . . . . . . . .14
3.6.6 Watchdog
Ti
er (WDOG
)
.
. . . . . . . . . . . . . . . . . . . . . . .
.
14
3.7 Communications
and Other Digital Peripherals
. . . . . . . . . . . . . . . . . . .14
3.7.1 Universal
Synchronous/Asynchronous Receiver/Transmitter (USART) .
. . . . . . . . .14
3.7.2
ow
nergy Universal Asynchronous Receiver/Transmitter (LEUART) .
. . . . . . . . .15
2
3.7.3
nter-Integrated Circuit Interface (I
C) .
. . . . . . . . . . . . . . . . . . . .15
3.7.4 Peripheral
Reflex System (PRS)
. . . . . . . . . . . . . . . . . . . . . .15
3
Security Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
8.1 GPCRC
(General Purpose Cyclic Redundancy Check)
. . . . . . . . . . . . . . .15
3.8.2 Crypto
Accelerator (CRYPTO)
. . . . . . . . . . . . . . . . . . . . . . .15
3.9 Analo
g
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.9.1 Analog
Port (APORT)
. . . . . . . . . . . . . . . . . . . . . . . . . .15
3.9.2 Analog
Comparator (ACMP) .
. . . . . . . . . . . . . . . . . . . . . . .15
3.9.3 Analog
to Digital Converter (ADC)
. . . . . . . . . . . . . . . . . . . . . .16
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3.9.4 Digital
to Analog Current Converter (IDAC)
. . . . . . . . . . . . . . . . . . .16
3.10 Reset
Management Unit (RMU) .
. . . . . . . . . . . . . . . . . . . . . . .16
3.11 Core
and Memory
. . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.11.1 Processor
Core .
. . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.11.2 Memory
System Controller (MSC)
. . . . . . . . . . . . . . . . . . . . .16
3.11.3 Linked
Direct Memory Access Controller (LDMA)
. . . . . . . . . . . . . . . .16
3.12 Memory
Map .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.13 Configuration
Summary . . . . . . . . . . . . . . . . . . . . . . . .
.18
4. Electrical
Specifications .
. . . . . . . . . . . . . . . . . . . . . . . . .
19
4.1 Electrical
Characteristics .
. . . . . . . . . . . . . . . . . . . . . . . . .19
4.1.1 Absolute
Maximum Ratings
. . . . . . . . . . . . . . . . .
. . . . . .20
4.1.2 Operating
Conditions . . . . . . . . . . . . . . . . . . .
. . . . . .22
4.1.3 Thermal
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .24
4.1.4 DC-DC
Converter .
. . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1.5 Current
Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.1.6 Wake
Up Times
. . . . . . . . . . . . . . . . .
. . . . . . . . . .33
4.1.7 Brown
Out Detector (BOD)
. . . . . . . . . . . . . . . . . . . . . . . .34
4.1.8 Frequency
Synthesize
r
. . . . . . . . . . . . . . . . . . . . . . . . .
.
35
4.1.9 2.4
GHz RF Transceiver Characteristics .
. . . . . . . . . . . . . . . . . . .36
4.1.10 Sub-GHz
RF Transceiver Characteristics
. . .
. . . . . . . . . . . . . .45
4.1.11 Modem.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.1.12 Oscillators
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.1.13 Flash
Memory Characteristics
. . . .
. . . . . . . . . . . . . . . . . .74
4.1.14 General-Purpose
I/O (GPIO)
. . .
. . . . . . . . . . . . . . . . . . .75
4.1.15 Voltage
Monitor (VMON
)
.
. . . . . . . . . . . . . . . . . . . . . . .
.
77
4.1.16 Analog
to Digital Converter (ADC)
. . . . . . . . . . . . . . . . . . . .78
4.1.17 Analog
Comparator (ACMP)
. . . . . . . . . . . . . . . . . . . . . . .80
4.1.18 Current
Digital to Analog C
verter (IDAC)
. . . . . . . . . . . . . . . . . .82
4.1.19 Pulse
Counter (PCNT)
. . . . . . . . . . . . . . . . . . . . . . . . .84
4.1.20 I2C .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
4.1.21 USART
SPI .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .87
4.2 Typical
Performance Curves
. . . . . . . . . . . . . . . . . . . . . . . . .88
4.2.1 Supply
Curr
. . . . . . . . . . . . . . . . . . . . . . . . . . . .89
4.2.2 DC-DC
Converter .
. . . . . . . . . . . . . . . . . . . . . . . . . .91
4.2.3 Internal
Oscillators .
. . . . . . . . . . . . . . . . . . . . . . . . . .93
4.2.4
.4 GHz Radio
. . . . . . . . . . . . . . . . . . . . . . . . . . . .99
5. Typical
Connection Diagrams
. . . . . . . . . . . . . . . . . . . . . . . .101
5.1 Power
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
101
RF Matching Networks
. . . . . . . . . . . . . . . . . . . . . . . . . .103
5.3 Other
Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . .
104
6. Pin
Definitions .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
6.1 QFN48
2.4 GHz and Sub-GHz Device Pinout.
. . . . . . . . . . . . . . . . . .
105
6.2 QFN48
2.4 GHz Device Pinout
. . . . . . . . . . . . . . . . . . . . . .
1
.
0
7
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6.3 QFN48
Sub-GHz Device Pinout
. . . . . . . . . . . . . . . . . . . . . . .109
6.4 QFN32
2.4 GHz Device Pinout
. . . . . . . . . . . . . . . . . . . . . .
1
.
1
1
. . . . . . . . . . . . . . . . . . . . . . . .
1
.
13
6.5 GPIO
Functionality Table
6.6 Alternate
Functionality Overview
. . . . . . . . . . . . . . . . . . . . . . .
123
6.7 Analog
Port (APORT) Client Maps
. . . . . . . . . . . . . . . . . . . . .
.
130
7. QFN48
Package Specifications.
. . . . . . . . . . . . . . . . . . . . . . .
134
7.1 QFN48
Package Dimensions
. . . . . . . . . . . . . . . . . . . . . .
.
1
34
7.2 QFN48
PCB Land Pattern
. . . . . . . . . . . . . . . . . . . . . . . . .136
7.3 QFN48
Package Marking
. . . . . . . . . . . . . . . . . . . . . . . .
.
138
8. QFN32
Package Specifications.
. . . . . . . . . . . . . . . .
. . . . .
139
8.1 QFN32
Package Dimensions
. . . . . . . . . . . . . . . . . .
. . . .
.
1
39
8.2 QFN32
PCB Land Pattern
. . . . . . . . . . . . . . . . . . . . . . . . .141
8.3 QFN32
Package Marking
. . . . . . . . . . . . . . . . . . . . . . . .
.
143
9. Revision
History .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .144
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
System Overview
3. System
Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG1 Reference Man-
ual.
A block diagram of the EFR32MG1 family is shown in
Figure 3.1 Detailed EFR32MG1 Block Diagram on page 9
. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information
.
Radio Transciever
Port I/O Configuration
Sub-GHz RF
SUBGRF_IP
SUBGRF_IN
SUBGRF_OP
SUBGRF_ON
I
DEMOD
IFADC
AGC
LNA
Digital Peripherals
LETIMER
PA
PGA
Q
IOVDD
TIMER
CRYOTIMER
PCNT
RFSENSE
BALUN
2.4 GHz RF
I
Frequency
Synthesizer
LNA
2G4RF_IOP
2G4RF_ION
To RF
Frontend
Circuits
MOD
Port A
Drivers
PA
PAn
Q
RTC / RTCC
USA
Port
Mapper
Energy Management
ARM Cortex-M4 Core
Port B
Drivers
LEUART
I2C
PAVDD
RFVDD
PBn
PCn
PDn
PFn
Up to 256 KB ISP Flash
Program Memory
IOVDD
AVDD
Up to 32 KB RAM
Memory Protection Unit
Floating Point Unit
DMA Controller
RYPTO
CRC
Voltage
Monitor
A
H
B
A
P
B
Port C
Drivers
DVDD
bypass
Port D
Drivers
VREGVDD
VREGSW
Analog Peripherals
DC-DC
Converter
Voltage
Regulator
Serial Wire Debug /
Programming
Internal
Reference
IDAC
DECOUPLE
Watchdog
Timer
Port F
Drivers
VDD
VREF
VSS
VREGVSS
RFVSS
Brown Out /
Power-On
Reset
Clock Management
VDD
12-bit ADC
PAVSS
ULFRCO
AUXHFRCO
LFRCO
Reset
Management
Unit
RESETn
Temp
Sensor
HFRCO
LFXO
LFXTAL_P / N
+
–
HFXTAL_P
HFXTAL_N
HFXO
Analog Comparator
Figure 3.1.
Detailed EFR32MG1 Block Diagram
3.2 Radio
The Mighty G
cko family features a highly configurable radio transceiver supporting a wide range of wireless protocols, including Zig-
bee, Thread, BLE and proprietary.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
System Overview
3.2.1 Antenna
Interface
The EFR32MG1 family includes devices which support both single-band and dual-band RF communication over separate physical RF
interfaces.
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
The sub-GHz antenna interface consists of a differential transmit interface (pins SUBGRF_OP and SUBGRF_ON) and a differential re-
ceive interface (pinsSUBGRF_IP and SUBGRF_IN).
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
3.2.2 Fractional-N
Frequency Synthesizer
The EFR32MG1 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesiz
The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used
nsmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receive
and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver
Architecture
The EFR32MG1 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer, employing a crystal reference. The I/Q signals are further filtered and amplif
ed before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further
configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. The 2.4 GHz radio is calibrated
oduction to improve image rejection performance. The sub-GHz
radio can be calibrated on-demand by the user for the desired freque
cy band.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High c
frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS) for 2.4 GHz and sub-GHz bands.
A Received Signal Strength Indicator (RSSI) is
ailable for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
The EFR32MG1 features integrated support for antenna diversity to mitigate the problem of frequency-selective fading due to multipath
propagation and improve link budget. Support for antenna diversity is available for specific PHY configurations in 2.4 GHz and sub-GHz
bands. Internal configurable hardware controls an external switch for automatic switching between antennae during RF receive detec-
tion operations.
Note:
Due to the shorter preamble of 802.15.4 and BLE packets, RX diversity is not supported.
3.2.4 Trans
tter Architecture
The EFR32MG1 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filte
shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access – Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32MG1. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
System Overview
3.2.5 Wake
on Radio
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-
ing a subsystem of the EFR32MG1 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-
als.
3.2.6 RFSENSE
The RFSENSE peripheral generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, provid-
ing true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low en
y con-
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup
nt by
enabling normal RF reception.
Various strategies for optimizing power consumption and system response time in presence of false alarms may
e employed using
available timer peripherals.
3.2.7 Flexible
Frame Handling
EFR32MG1 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-
tor:
• Highly
adjustable preamble length
• Up
to 2 simultaneous synchronization words, each up to 32 bits and providing separate inte
rupts
• Frame
disassembly and address matching (filtering) to accept or reject frames
• Automatic
ACK frame assembly and transmission
• Fully
flexible CRC generation and verification:
• Multiple
CRC values can be embedded in a single frame
• 8,
16, 24 or 32-bit CRC value
• Configurable
CRC bit and byte ordering
• Selectable
bit-ordering (least significant or most significant bit fi
• Optional
data whitening
• Optional
Forward Error Correction (FEC), including con
olutional encoding / decoding and block encoding / decoding
• Half
rate convolutional encoder and decoder with cons
t lengths from 2 to 7 and optional puncturing
• Optional
symbol interleaving, typically used in combination with FEC
• Symbol
coding, such as Manchester or DSSS
r biphase space encoding using FEC hardware
• UART
encoding over air, with start and stop b
t insertion / removal
• Test
mode support, such as modulated or unmodulated carrier output
• Received
frame timestamping
3.2.8 Packet
and State Trace
The EFR32MG1 Frame Cont
has a packet and state trace unit that provides valuable information during the development phase. It
features:
• Non-intrusive
trac
of transmit data, receive data and state information
• Data
obse
bilit
on a single-pin UART data output, or on a two-pin SPI data output
• Configur
data output bitrate / baudrate
• Multiplexed
transmitted data, received data and state / meta information in a single serial data stream
3.2.
ta Buffering
Th
EFR32MG1 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
System Overview
3.2.10 Radio
Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32MG1. It performs the following tasks:
• Precisely-timed
control of enabling and disabling of the receiver and transmitter circuitry
• Run-time
calibration of receiver, transmitter and frequency synthesizer
• Detailed
frame transmission timing, including optional LBT or CSMA-CA
3.2.11 Random
Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-
ber generator algorithms such as Fortuna.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
System Overview
3.3 Power
The EFR32MG1 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a
single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator can
be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor.
AVDD and VREGVDD need to be 1.85 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.3.1 Energy
Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is u
to monitor multi-
ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if
sensed supply has
fallen below a chosen threshold.
3.3.2 DC-DC
Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Paten
RF noise mitigation allows operation
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,
short-circuit protection, and dead-time protection. The DC-DC converter may also ente
bypass mode when the input voltage is too low
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-
sients.
3.4 General
Purpose Input/Output (GPIO)
EFR32MG1 has up to 32 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input.
More advanced configurations including open-drain, open-source,
d glitch-filtering can be configured for each individual GPIO pin.
The GPIO pins can be overridden by peripheral connections, like S
ommunication. Each peripheral connection can be routed to sev-
eral GPIO pins on the device. The input value of a GPIO pin
n be routed through the Peripheral Reflex System to other peripherals.
The GPIO subsystem supports asynchronous external pin
nterrupts.
3.5 Clocking
3.5.1 Clock
Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32MG1. Individual enabling and disabling of clocks to all periph-
erals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows
software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscilla-
tors.
3.5.2 Internal
and External Oscillators
The EFR32MG1 sup
rts two crystal oscillators and fully integrates four RC oscillators, listed below.
• A
high fre
ncy crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for
MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A
32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• A
tegrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
H
O employs fast startup at minimal energy consumption combined with a wide frequency range.
• An
integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire Viewer port with a wide frequency range.
• An
integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
• An
integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
System Overview
3.6 Counters/Timers
and PWM
3.6.1 Timer/Counter
(TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Real
Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of
on-board oscilla-
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instan
es. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose
tention, allowing easy
and convenient data storage in all energy modes down to EM4H.
3.6.3 Low
Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in add
n to EM1 Sleep and EM0 Active. This
allows it to be used for timing and output generation when most of the device is powered dow
allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-
figured to start counting on compare matches from the RTCC.
3.6.4 Ultra
Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from a
energy mode. The CRYOTIMER provides a wide range of inter-
rupt periods, facilitating flexible ultra-low energy operation.
3.6.5 Pulse
Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except th
AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep,
EM2 Deep Sleep, and EM3 Stop.
3.6.6 Watchdog
Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous sy
driven by PRS.
3.7 Communication
and Other Digital Peripherals
3.7.1 Unive
l Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
port
• ISO7816
SmartCards
• IrDA
I
2
S
•
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
System Overview
3.7.2 Low
Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUART
TM
provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.7.3 Inter-Integrated
Circuit Interface (I
2
C)
The I
2
C interface enables communication between the MCU and a serial I
2
C bus. It is capable of acting as both a master and a slave
and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates
from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system.
The interface provided to software by the I
2
C peripheral allows precise timing control of the transmission process and highly
ated
transfers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral
Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripherals without so
volvement. Peripher-
als producing Reflex signals are called producers. The PRS routes Reflex signals from producers to cons
peripherals, which in
turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied
by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.
3.8 Security
Features
3.8.1 GPCRC
(General Purpose Cyclic Redundancy Check)
The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The suppor-
ted 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomi
an be programmed to any value, depending on the
needs of the application.
3.8.2 Crypto
Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous
are encryption and decryption accelerator. EFR32 devices sup-
port AES encryption and decryption with 128- or 256-bit key
ECC over both GF(P) and GF(2
m
), SHA-1 and SHA-2 (SHA-224 and
SHA-256).
Supported block cipher modes of operation for AES includ
CB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO block is tightly linked to the Radi
Bu
fer Controller (BUFC) enabling fast and efficient autonomous cipher operations on
data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention.
CRYPTO also provides trigger signals for DMA read and write operations.
3.9 Analog
3.9.1 Analog
Port (APORT)
The Analog P
(A
ORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins.
Each APOR
s consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are
grouped by X/Y pairs.
3.9.2
nalog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
System Overview
3.9.3 Analog
to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
3.9.4 Digital
to Analog Current Converter (IDAC)
The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC
input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with several ranges consisting of
various step sizes.
3.10 Reset
Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32MG1. A wide range of reset sources are available, inc
ding several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.11 Core
and Memory
3.11.1 Processor
Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM
Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory
Protection Unit (MPU) supporting up to 8 memory segments
• Up
to 256 kB flash program memory
• Up
to 32 kB RAM data memory
• Configuration
and event handling of all peripherals
• 2-pin
Serial-Wire debug interface
3.11.2 Memory
System Controller (MSC)
The Memory System Controller (MSC) is the program memo
unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is d
d into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the informa
block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.11.3 Linked
Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-
phisticated operations to be implemented.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
System Overview
3.12 Memory
Map
The EFR32MG1 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2.
EFR32MG1 Memory Map — Core Peripherals and Code Space
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
System Overview
Figure 3.3.
EFR32MG1 Memory Map — Peripherals
3.13 Configuration
Summary
The features of the EFR32MG1 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.1.
Configuration Summary
Module
Configuration
IrDA
Pin Connections
USART0
US0_TX, US0_RX, US0_CLK, US0_CS
SmartCard
I
2
S
USART1
US1_TX, US1_RX, US1_CLK, US1_CS
SmartCard
with DTI
TIMER0
TIMER1
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[3:0]
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4. Electrical
Specifications
4.1 Electrical
Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical
values are based on T
AMB
=25 °C and V
DD
= 3.3 V, by production test and/or technology characterization.
• Radio
performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum
and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to
4.1.2.1 General Operating Conditions
for more details about operational supply and temperature limits.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.1 Absolute
Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at
http://www.silabs.com/support/quality/pages/default.aspx
.
Table 4.1.
Absolute Maximum Ratings
Parameter
Symbol
T
STG
Test Condition
Min
-50
-0.3
—
Typ
—
Max
150
3.8
1
Unit
°C
Storage temperature range
Voltage on any supply pin
V
DDMAX
V
DDRAMPMAX
—
V
Voltage ramp rate on any
supply pin
—
V / µs
5V tolerant GPIO pins
1 2 3
Standard GPIO pins
DC voltage on any GPIO pin
V
DIGPIN
-0.3
—
Min of 5.25
and IOVDD
+2
V
-0.3
-0.3
—
—
—
—
IOVDD+0.3
V
V
Voltage on HFXO pins
V
HFXOPIN
1.4
10
Input RF level on pins
2G4RF_IOP and
2G4RF_ION
P
RFMAX2G4
dBm
Voltage differential between
V
MAXDIFF2G4
RF pins (2G4RF_IOP –
2G4RF_ION)
-50
—
—
50
mV
V
Absolute voltage on RF pins
V
MAX2G4
2G4RF_IOP and
-0.3
3.3
2G4RF_ION
Absolute voltage on Sub-
GHz RF pins
V
MAXSUBG
Pins SU
RF_OP and
SUBGRF_ON
-0.3
-0.3
—
—
—
—
—
3.3
0.3
V
V
Pins SUBGRF_IP and
SUBGRF_IN,
Total current into VDD power
I
VDDMAX
lines
Source
200
200
mA
mA
Total current into VSS
ground lines
I
VSSMAX
Sink
—
Current per I/O pin
IOMAX
Sink
—
—
—
—
—
—
—
—
50
50
mA
mA
mA
mA
°C
Source
Current for
O pins
Junction temperature
I
IOALLMAX
Sink
—
200
200
105
125
Source
—
T
J
-G grade devices
-I grade devices
-40
-40
°C
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.
2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source
below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the
maximum IO current specifications.
3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.
Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.2 Operating
Conditions
When assigning supply sources, the following requirements must be observed:
• VREGVDD
must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies.
• VREGVDD
= AVDD
• DVDD
≤ AVDD
• IOVDD
≤ AVDD
• RFVDD
≤ AVDD
• PAVDD
≤ AVDD
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.2.1 General
Operating Conditions
Table 4.2.
General Operating Conditions
Parameter
Symbol
Test Condition
Min
-40
Typ
25
Max
85
Unit
°C
°C
V
Operating ambient tempera-
T
A
ture range
1
-G temperature grade
-I temperature grade
-40
25
125
3.8
AVDD supply voltage
2
V
AVDD
1.85
3.3
VREGVDD operating supply
V
VREGVDD
voltage
2 3
DCDC in regulation
2.4
3.3
3.3
3.3
3.8
3.8
3.8
V
V
V
DCDC in bypass, 50mA load
1.85
1.85
DCDC not in use. DVDD external-
ly shorted to VREGVDD
VREGVDD current
I
VREGVDD
DCDC in bypass, T ≤ 85 °C
DCDC in bypass, T > 85 °C
—
—
—
—
—
200
100
mA
mA
V
RFVDD operating supply
voltage
V
RFVDD
1.62
V
VREGVDD
DVDD operating supply volt-
V
DVDD
age
1.62
1.62
1.62
0.75
—
—
V
VREGVDD
V
VREGVDD
V
VREGVDD
2.75
V
V
PAVDD operating supply
voltage
V
PAVDD
IOVDD operating supply volt-
V
IOVDD
age
All IOVDD pins
—
V
DECOUPLE output capaci-
tor
4
C
DECOUPLE
1.0
µF
Difference between AVDD
dV
DD
—
—
0.1
V
and VREGVDD, ABS(AVDD-
VREGVDD)
2
HFCORECLK frequency
f
CORE
MODE = WS0
MODE = WS1
MODE = WS0
MODE = WS1
—
—
—
—
—
—
—
—
26
40
26
40
MHz
MHz
MHz
MHz
HFCLK frequency
f
HFCLK
Note:
1. The maximum limit on T
A
may be lower due to device self-heating, which depends on the power dissipation of the specific appli-
cation. T
A
(ma
= T
J
(max) – (THETA
JA
x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal
Charac
ics table for T
J
and THETA
JA
.
2. VREGV
D must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
3. The minimum voltage required in bypass mode is calculated using R
BYP
from the DCDC specification table. Requirements for
other loads can be calculated as V
DVDD_min
+I
LOAD
* R
BYP_max
.
4
system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-
ue stays within the specified bounds across temperature and DC bias.
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Rev. 1.4
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.3 Thermal
Characteristics
Table 4.3.
Thermal Characteristics
Parameter
Symbol
Test Condition
Min
—
—
—
—
—
—
—
—
—
—
—
—
Typ
64.5
51.6
47.7
26.2
23.1
22.
79
Max
—
—
—
—
—
—
—
—
—
—
—
—
Unit
°C/W
°C/W
/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Thermal resistance, QFN48
THETA
JA_QFN48
2-Layer PCB, Air velocity = 0 m/s
Package
2-Layer PCB, Air velocity = 1 m/s
2-Layer PCB, Air velocity = 2 m/s
4-Layer PCB, Air velocity = 0 m/s
4-Layer PCB, Air velocity = 1 m/s
4-Layer PCB, Air velocity = 2 m/s
Thermal resistance, QFN32
THETA
JA_QFN32
2-Layer PCB, Air velocity = 0 m/s
Package
2-Layer PCB, Air velocity = 1 m/s
62
2
54.1
32
2-Layer PCB, Air velocity = 2 m/s
4-Layer PCB, Air velocity = 0 m/s
4-Layer PCB, Air velocity = 1 m/s
4-Layer PCB, Air velocity = 2 m/s
28.1
26.9
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.4 DC-DC
Converter
Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=1.0 µF (Murata GRM188R71A105KA61D), V_DCDC_I=3.3
V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.
Table 4.4.
DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input voltage range
V
DCDC_I
Bypass mode, I
DCDC_LOAD
= 50
mA
1.85
—
V
VREGVDD_
V
MAX
Low noise (LN) mode, 1.8 V out-
put, I
DCDC_LOAD
= 100 mA, or
Low power (LP) mode, 1.8 V out-
put, I
DCDC_LOAD
= 10 mA
2.4
—
V
VREGVDD_
V
MAX
Low noise (LN) mode, 1.8 V out-
put, I
DCDC_LOAD
= 200 mA
2.6
1.8
—
—
VREGVDD_
V
V
MAX
Output voltage programma-
V
DCDC_O
ble range
1
V
VREGVDD
Regulation DC accuracy
ACC
DC
Low Noise (LN) mode, 1.8 V tar-
get output
1.7
—
—
1.9
2.2
V
V
Regulation window
2
WIN
REG
Low Power (LP) mode,
LPCMPBIAS
3
= 0, 1.8 V target
output, I
DCDC_LOAD
≤ 75 µA
1.63
Low Power (LP) mode,
1.63
—
2.1
V
LPCMPBIAS
3
= 3, 1.8 V target
output, I
DCDC_LOA
≤ 10 mA
Steady-state output ripple
V
R
Radio disabled
—
—
3
—
mVpp
mV
CCM M
e (LNFORCECCM
3
=
1), Loa
nges between 0 mA
and 100 mA
Output voltage under/over-
shoot
V
OV
—
150
CM Mode (LNFORCECCM
3
=
0), Load changes between 0 mA
and 10 mA
—
—
150
mV
Overshoot during LP to LN
CCM/DCM mode transitions com-
pared to DC level in LN mode
—
—
200
50
—
—
mV
mV
Undershoot during BYP/LP to LN
CCM (LNFORCECCM
3
= 1) mode
transitions compared to DC level
in LN mode
Undershoot during BYP/LP to LN
—
125
—
mV
DCM (LNFORCECCM
3
= 0) mode
transitions compared to DC level
in LN mode
DC l
regulation
DC load regulation
V
REG
Input changes between
V
VREGVDD_MAX
and 2.4 V
—
—
0.1
0.1
—
—
%
%
I
REG
Load changes between 0 mA and
100 mA in CCM mode
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Max load current
I
LOAD_MAX
Low noise (LN) mode, Heavy
Drive
4
, T ≤ 85 °C
—
—
200
mA
Low noise (LN) mode, Heavy
Drive
4
, T > 85 °C
—
—
—
—
—
—
—
—
—
—
100
100
50
mA
mA
mA
µA
Low noise (LN) mode, Medium
Drive
4
Low noise (LN) mode, Light
Drive
4
Low power (LP) mode,
LPCMPBIAS
3
= 0
75
Low power (LP) mode,
LPCMPBIAS
3
= 3
10
mA
DCDC nominal output ca-
pacitor
C
DCDC
25% tolerance
1
1
4.7
4.7
2.5
µF
µH
Ω
DCDC nominal output induc-
L
DCDC
tor
20% tolerance
4.7
—
4.7
1.2
Resistance in Bypass mode
R
BYP
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its in
t voltage, V
VREGVDD
.
2. LP mode controller is a hysteretic controller that maintains the output volta
ithin the specified limits.
3. In the EMU_DCDCMISCCTRL register.
4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-
um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=
ETCNT=15.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.5 Current
Consumption
4.1.5.1 Current
Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C.
EMU_PWRCFG_PWRCFG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table repre-
sent the worst conditions across process variation at T = 25 °C.
Table 4.5.
Current Consumption 3.3 V without DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
nit
Current consumption in EM0
I
ACTIVE
mode with all peripherals dis-
abled
38.4 MHz crystal, CPU running
while loop from flash
1
—
130
—
µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
—
88
100
112
102
222
65
—
105
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
106
350
—
1 MHz HFRCO, CPU running
while loop from flash
38.4 MHz crystal
1
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFR
O
Current consumption in EM1
I
EM1
mode with all peripherals dis-
abled
—
—
—
—
35
37
38
41
µA/MHz
µA/MHz
µA/MHz
µA
157
3.3
275
—
Current consumption in EM2
I
EM2
mode
Full 32
AM retention and
RTCC running from LFXO
1 bank (4 kB) RAM retention and
RTCC running from LFRCO
—
—
3
6.3
6
µA
µA
Current consumption in EM3
I
EM3
mode
Full 32 kB RAM retention and
CRYOTIMER running from ULFR-
CO
2.8
Current consumption in
EM4H mode
I
EM4H
128 byte RAM retention, RTCC
running from LFXO
—
—
1.1
—
—
µA
µA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
0.65
128 byte RAM retention, no RTCC
No RAM retention, no RTCC
—
—
0.65
0.04
1.3
µA
µA
Current cons
mption in
EM4S mode
I
EM4S
0.11
Not
1.
U_HFXOCTRL_LOWPOWER=0.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.5.2 Current
Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC
output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.6.
Current Consumption 3.3 V using DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0
I
ACTIVE_DCM
mode with all peripherals dis-
abled, DCDC in Low Noise
DCM mode
1
38.4 MHz crystal, CPU running
while loop from flash
2
—
88
—
µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
63
71
78
76
98
—
—
—
—
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM0
I
ACTIVE_CCM
mode with all peripherals dis-
abled, DCDC in Low Noise
CCM mode
3
38.4 MHz crystal, CPU running
while loop from flash
2
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
75
81
88
94
49
—
—
—
—
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
38 MHz HFRCO, CPU runnin
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from fl
26 MHz HF
O, CPU running
while loop fr
m f
ash
38.4 M
ystal
2
38 MHz HFRCO
26 MHz HFRCO
Current consumption in EM1
I
EM1_DCM
mode with all peripherals dis-
abled, DCDC in Low Noise
DCM mode
1
—
—
—
32
38
—
—
—
µA/MHz
µA/MHz
µA
Current consumption in EM2
I
EM2
mode, DCDC in LP mode
4
Full RAM retention and RTCC
running from LFXO
2.5
1 bank (4 kB) RAM retention and
RTCC running from LFRCO
—
—
2.2
2.1
—
—
µA
µA
Current consumption in EM3
M3
mode
Full 32 kB RAM retention and
CRYOTIMER running from ULFR-
CO
Current con
ption in
EM4H mod
I
EM4H
128 byte RAM retention, RTCC
running from LFXO
—
—
0.86
0.58
—
—
µA
µA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
No RAM retention, no RTCC
—
—
0.58
0.04
—
—
µA
µA
Current consumption in
EM4S mode
I
EM4S
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.
2. CMU_HFXOCTRL_LOWPOWER=0.
3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.
4. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPCMPBIAS=0, LPCLIMILIMSEL=1,
ANASW=DVDD.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.5.3 Current
Consumption 1.85 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.85 V. T = 25 °C.
EMU_PWRCFG_PWRCFG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table repre-
sent the worst conditions across process variation at T = 25 °C.
Table 4.7.
Current Consumption 1.85 V without DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0
I
ACTIVE
mode with all peripherals dis-
abled
38.4 MHz crystal, CPU running
while loop from flash
1
—
131
—
A/MHz
38 MHz HFRCO, CPU running
Prime from flash
—
—
—
—
—
—
88
100
112
102
220
65
—
—
—
—
—
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
38.4 MHz crystal
1
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
Current consumption in EM1
I
EM1
mode with all peripherals dis-
abled
—
—
—
—
35
37
—
—
—
—
µA/MHz
µA/MHz
µA/MHz
µA
154
3.2
Current consumption in EM2
I
EM2
mode
Full 32 kB RAM re
ntion and
RTCC runn
g from LFXO
1 bank
) RAM retention and
RTCC running from LFRCO
—
—
2.8
2.7
—
—
µA
µA
Current consumption in EM3
I
EM3
mode
ull 32 kB RAM retention and
CRYOTIMER running from ULFR-
CO
Current consumption in
EM4H mode
I
EM4H
128 byte RAM retention, RTCC
running from LFXO
—
—
1
—
—
µA
µA
128 byte RAM retention, RTCC
running from LFXO, serial flash in
deep power down
0.62
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
—
—
0.62
0.02
—
—
µA
µA
Current con
mption in
EM4S mode
I
EM4S
no RAM retention, no RTCC
Note:
1
U_HFXOCTRL_LOWPOWER=0.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.5.4 Current
Consumption Using Radio 3.3 V with DC-DC
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. T = 25 °C. Mini-
mum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.
Table 4.8.
Current Consumption Using Radio 3.3 V with DC-DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled), T ≤ 85 °C
I
RX_ACTIVE
500 kbit/s, 2GFSK, F = 915 MHz,
Radio clock prescaled by 4
—
8.4
10
mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
Radio clock prescaled by 4
—
—
—
—
—
—
—
—
—
—
—
—
—
8.1
7.9
7.7
7
9
7.6
8.7
9.8
—
10
10
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
Radio clock prescaled by 4
50 kbit/s, 2GFSK, F = 433 MHz,
Radio clock prescaled by 4
10
38.4 kbit/s, 2GFSK, F = 315 MHz,
Radio clock prescaled by 4
10
38.4 kbit/s, 2GFSK, F = 169 MHz,
Radio clock prescaled by 4
10
1 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
—
802.15.4 receiving frame, F
GHz, Radio clock pre
caled by 3
—
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled), T > 85 °C
I
RX_ACTIVE_HT
500 kbit/s, 2GFSK, F = 915 MHz,
Radio clock presc
ed by 4
10.8
10.5
10.8
10.5
10.9
10.2
38.4 kbit/s, 2GFSK
F = 868 MHz,
Radio clock
rescaled by 4
—
38.4 kb
GFSK, F = 490 MHz,
Radio clock prescaled by 4
—
0 kbit/s, 2GFSK, F = 433 MHz,
Radio clock prescaled by 4
—
38.4 kbit/s, 2GFSK, F = 315 MHz,
Radio clock prescaled by 4
—
38.4 kbit/s, 2GFSK, F = 169 MHz,
Radio clock prescaled by 4
—
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled), T ≤ 85 °C
I
TX
F = 915 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
80.2
104
mA
F = 915 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
—
35.5
40.9
mA
F = 868 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
—
84.9
34.5
114
42
mA
A
F = 868 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
F = 490 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
—
82.8
19.5
12
mA
mA
F = 433 MHz, CW, 10 dBm
match, External PA supply con-
nected to DC-DC output
22.1
F = 433 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
—
—
32.3
32.5
37.8
39.4
mA
mA
F = 315 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
F = 169 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
—
—
—
—
—
80.2
8.2
106.9
—
mA
mA
mA
mA
mA
mA
F = 2.4 GHz, CW, 0 dBm output
power, Radio clo
rescaled by 3
F = 2.4 GHz
W, 3 dBm output
power
16.5
23.3
32.7
83.9
—
F = 2.4
, CW, 8 dBm output
power
—
= 2.4 GHz, CW, 10.5 dBm out-
put power
—
F = 2.4 GHz, CW, 16.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
—
F = 2.4 GHz, CW, 19.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
—
126.7
—
mA
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled), T > 85 °C
I
TX_HT
F = 915 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
—
108.5
mA
F = 915 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
—
—
42.9
mA
F = 868 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
—
—
—
118.2
42
mA
A
F = 868 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
F = 490 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
—
—
—
17
23
mA
mA
F = 433 MHz, CW, 10 dBm
match, External PA supply con-
nected to DC-DC output
F = 433 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
—
—
—
—
37.8
39.4
mA
mA
F = 315 MHz, CW, 14 dBm
match, External PA supply con-
nected to DCDC output
F = 169 MHz, CW, 20 dBm
match, External PA supply = 3.3V
—
—
—
110.7
—
mA
nA
RFSENSE current consump-
I
RFSENSE
tion
51
4.1.6 Wake
Up Times
Table 4.9.
Wake Up Times
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
Wake up time from EM1
t
EM1_WU
—
3
—
AHB
Clocks
Wake up from EM2
Wake up from EM3
M2_WU
Code execution from flash
Code execution from RAM
Code execution from flash
Code execution from RAM
Executing from flash
—
—
—
—
—
10.7
3
—
—
—
—
—
µs
µs
µs
µs
µs
t
EM3_WU
10.7
3
Wake up from EM4H
1
t
EM4H_WU
t
EM4S_WU
60
Wa
p from EM4S
1
Executing from flash
—
290
—
µs
Note:
1. Time from wake up request until first instruction is executed. Wakeup results in device reset.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.7 Brown
Out Detector (BOD)
Table 4.10.
Brown Out Detector (BOD)
Parameter
Symbol
Test Condition
DVDD rising
Min
—
Typ
—
Max
1.62
—
Unit
V
DVDD BOD threshold
V
DVDDBOD
DVDD falling
1.35
—
—
V
DVDD BOD hysteresis
DVDD BOD response time
AVDD BOD threshold
V
DVDDBOD_HYST
24
2.4
—
—
mV
µs
V
t
DVDDBOD_DELAY
Supply drops at 0.1V/µs rate
—
—
V
AVDDBOD
AVDD rising
AVDD falling
—
1.85
—
1.62
—
—
V
AVDD BOD hysteresis
AVDD BOD response time
EM4 BOD threshold
V
AVDDBOD_HYST
21
2.4
—
—
mV
µs
V
t
AVDDBOD_DELAY
Supply drops at 0.1V/µs rate
—
—
V
EM4DBOD
AVDD rising
AVDD falling
—
1.7
—
1.45
—
—
V
EM4 BOD hysteresis
V
EM4BOD_HYST
46
300
—
mV
µs
EM4 BOD response time
t
EM4BOD_DELAY
Supply drops at 0.1V/µs rate
—
—
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.8 Frequency
Synthesizer
Table 4.11.
Frequency Synthesizer
Parameter
Symbol
Test Condition
2400 – 2483.5 MHz
779 – 956 MHz
390 – 574 MHz
195 – 358 MHz
110 – 191 MHz
2400 – 2483.5 MHz
779 – 956 MHz
390 – 574 MHz
195 – 358 MHz
110 – 191 MHz
2400 – 2483.5 MHz
779 – 956 MHz
390 – 574 MHz
195 – 358 MHz
110 – 191 MHz
2400 – 2483
MHz
779 – 9
MHz
390 – 574 MHz
95 – 358 MHz
110 – 191 MHz
Min
2400
779
390
195
110
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
2483.5
956
574
358
191
73
Unit
MHz
MHz
Hz
MHz
MHz
Hz
RF synthesizer frequency
range
f
RANGE
LO tuning frequency resolu-
f
RES
tion with 38.4 MHz crystal
—
24
Hz
—
12.2
7.3
Hz
—
Hz
—
4.6
Hz
Frequency deviation resolu-
df
RES
tion with 38.4 MHz crystal
—
73
Hz
—
24
Hz
—
12.2
7.3
Hz
—
Hz
—
4.6
Hz
Maximum frequency devia-
tion with 38.4 MHz crystal
df
MAX
—
1677
559
280
167
105
kHz
kHz
kHz
kHz
kHz
—
—
—
—
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9 2.4
GHz RF Transceiver Characteristics
4.1.9.1 RF
Transmitter General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.
Table 4.12.
RF Transmitter General Characteristics for 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
nit
Maximum TX power
1
POUT
MAX
19 dBm-rated part numbers.
PAVDD connected directly to ex-
ternal 3.3V supply
2
—
19.5
—
dBm
16 dBm-rated part numbers.
PAVDD connected directly to ex-
ternal 3.3V supply
—
—
16.
—
dBm
8 dBm-rated part numbers
CW
-30
1
—
—
—
—
dBm
dBm
dB
Minimum active TX Power
Output power step size
POUT
MIN
POUT
STEP
-5 dBm< Output power < 0 dBm
—
—
0 dBm < output power <
POUT
MAX
0.5
dB
Output power variation vs
supply at POUT
MAX
POUT
VAR_V
1.85 V < V
VREGVDD
< 3.3 V,
PAVDD connected directly to ex-
ternal supply, for output power >
10.5 dBm.
—
4.5
—
dB
1.85 V < V
VREGV
3.3 V using
DC-DC con
ter
—
—
2.2
1.5
2.2
1.5
3.4
0.4
—
—
—
dB
dB
Output power variation vs
temperature at POUT
MAX
POUT
VAR_T
From –
+85 °C, PAVDD con-
nected
C-DC output
From -40 to +125 °C, PAVDD
connected to DC-DC output
—
—
dB
From -40 to +85 °C, PAVDD con-
nected to external supply
—
—
dB
From -40 to +125 °C, PAVDD
connected to external supply
—
—
dB
Output power variation vs R
OUT
VAR_F
frequency at POUT
MAX
Over RF tuning frequency range
—
—
dB
RF tuning frequenc
ange
F
RANGE
2400
2483.5
MHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
2. For Bluetooth, the Maximum TX power on Channel 2456 is limited to +15 dBm to comply with In-band Spurious emissions.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.2 RF
Receiver General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.
Table 4.13.
RF Receiver General Characteristics for 2.4 GHz Band
Parameter
Symbol
F
RANGE
SPUR
RX
Test Condition
Min
2400
—
Typ
—
Max
2483.5
—
Unit
MHz
m
dBm
dBm
RF tuning frequency range
Receive mode maximum
spurious emission
30 MHz to 1 GHz
1 GHz to 12 GHz
-57
—
-47
—
Max spurious emissions dur-
SPUR
RX_FCC
ing active receive mode, per
FCC Part 15.109(a)
216 MHz to 960 MHz, Conducted
Measurement
—
-55.2
—
Above 960 MHz, Conducted
Measurement
—
—
-47.2
-24
—
—
dBm
dBm
Level above which
RFSENSE will trigger
1
RFSENSE
TRIG
CW at 2.45 GHz
Level below which
RFSENSE will not trigger
1
RFSENSE
THRES
CW at 2.45 GHz
—
-50
—
dBm
2 Mbps 2GFSK signal
2
250 kbps 2GFSK signal
1% PER sensitivity
SENS
2GFSK
—
—
-89.2
-99.1
—
—
dBm
dBm
Note:
1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
2. Channel at 2420 MHz will have degraded sensitivity. Sensitivity could be as high as -83 dBm on this channel.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.3 RF
Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Table 4.14.
RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Parameter
Symbol
TXBW
Test Condition
Min
—
Typ
740
-6.5
Max
—
Unit
Transmit 6dB bandwidth
Power spectral density limit
10 dBm
kHz
PSD
LIMIT
Per FCC part 15.247 at 10 dBm
—
—
Bm/
3kHz
Per FCC part 15.247 at 20 dBm
—
—
—
-2.6
10
—
—
—
dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
dBm
Occupied channel bandwidth
OCP
ETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band, 10 dBm
1
1
MHz
In-band spurious emissions,
SPUR
INB
with allowed exceptions
1
At ± 2 MHz, 10 dBm
At ± 3 MHz, 10 dBm
—
—
—
-39.8
-42.1
—
—
—
dBm
dBm
dBm
At ± 2 MHz, 20 dBm
2
At ± 3 MHz, 20 dBm
2
-20
—
—
—
-30
—
dBm
dBm
Emissions of harmonics out-
SPUR
HRM_FCC
2nd,3rd, 5, 6, 8, 9,10 harmonics;
-47
of-band, per FCC part
15.247
continuous transmission of modu-
lated carrier
Spurious emissions out-of-
band, excluding harmonics
captured in SPUR
HARM,FCC
Emissions taken at
POUT
MAX
, PAVDD connec-
ted to external 3.3 V supply
SPUR
OOB_FCC
Per FCC part 15.2
5/15.209,
Above 2.48
GHz or below 2.4
GHz; co
nuous transmission of
—
—
-47
-26
—
—
dBm
dBc
.
CW car
Restricted Bands
3
Per FCC part 15.247, Above
2.483 GHz or below 2.4 GHz;
continuous transmission of CW
carrier, Non-Restricted Bands
Spurious emissions out-of-
band; per ETSI 300.328
SPUR
ETSI328
[2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
—
—
-16
-26
—
—
dBm
dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
Spurious emission
r ETSI
SPUR
ETSI440
EN300.440
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
-60
—
dBm
25-1000 MHz
1-12 GHz
—
—
-42
-36
—
—
dBm
dBm
No
1. Per Bluetooth Core_5.0, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.
2. For 2456 MHz, a maximum output power of 15 dBm is used to achieve this value.
3. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.4 RF
Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4MHz. RF center frequency 2.45 GHz.
Table 4.15.
RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal
1
. Packet
length is 20 bytes.
Max usable receiver input
level, 0.1% BER
SAT
—
10
—
dBm
Sensitivity, 0.1% BER
2
Signal is reference signal
1
. Using
DC-DC converter.
SENS
—
—
-92.5
-92
—
—
dBm
dBm
With non-ideal signals as speci-
fied in RF-PHY.TS.4.2.2, section
4.6.1.
Signal to co-channel interfer-
C/I
CC
er, 0.1% BER
Desired signal 3 dB above refer-
ence sensitivity.
—
—
8.3
-3
—
—
dB
dB
N+1 adjacent channel selec-
C/I
1+
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
Interferer is reference signal at +1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
reference signal at -67 dBm
N-1 adjacent channel selec-
C/I
1-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
Interferer is reference signal at -1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
—
—
—
-0.5
-43
—
—
—
dB
dB
dB
reference signal at -67 dBm
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I
2
Interferer is reference signal at ± 2
MHz offset. Desir
d frequency
2402 MHz ≤ Fc
0 MHz
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I
3
Interfere
s reference signal at ± 3
MHz of
Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
-46.7
Selectivity to image frequen-
C/I
IM
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
—
—
-38.7
-48.2
—
—
dB
dB
Selectivity to image frequen-
C/I
IM+1
cy ± 1 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
Interferer is reference signal at im-
age frequency ± 1 MHz with 1
MHz precision
Blocking, less than 0.1%
BER. Desired is -6
m
BLE referenc
ign
l at
2426MHz.
erer is CW in
BLOCK
OOB
Interferer frequency 30 MHz ≤ f ≤
2000 MHz
-5
—
—
—
—
dBm
dBm
Interferer frequency 2003 MHz ≤ f
≤ 2399 MHz
4
-10
OOB range
3
Interferer frequency 2484 MHz ≤ f
≤ 2997 MHz
-10
-10
-17
—
—
—
—
—
—
—
dBm
dBm
dBm
dBm
Interferer frequency 3 GHz ≤ f ≤ 6
GHz
Interferer frequency 6 GHz ≤ f ≤
12.75 GHz
—
Intermodulation performance
IM
Per Core_4.1, Vol 6, Part A, Sec-
tion 4.4 with n = 3
-25.8
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
2. Receive sensitivity on Bluetooth Low Energy channel 26 is -86 dBm.
3. Interferer max power limited by equipment capabilities and path loss. Minimum specified at 25 °C.
4. Except -13 dBm at Desired Frequency – Crystal Frequency.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.5 RF
Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz. Maximum duty cycle
of 66%.
Table 4.16.
RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Error vector magnitude (off-
EVM
set EVM), per
802.15.4-2011, not including
2415 MHz channel
1
Average across frequency. Signal
is DSSS-OQPSK reference pack-
et
2
—
5.5
—
% rms
Power spectral density limit
PSD
LIMIT
Relative, at carrier ± 3.5 MHz, out-
put power at POUT
MAX
—
—
-26
-36
—
—
dBc/
100kHz
Absolute, at carrier ± 3.5 MHz,
dBm/
100kHz
3
output power at POUT
MAX
Per FCC part 15.247, output pow-
er at POUT
MAX
—
-4.2
—
dBm/
3kHz
ETSI
—
—
12
—
—
dBm
MHz
Occupied channel bandwidth
OCP
ETSI328
per ETSI EN300.328
99% BW at highest and lowest
channels in band
2.25
Spurious emissions of har-
monics in restricted bands
per FCC Part 15.205/15.209,
Emissions taken at
POUT
MAX
, PAVDD connec-
ted to external 3.3 V supply,
Test Frequency is 2450 MHz
SPUR
HRM_FCC_
Continuous transmission of
—
—
-45.8
—
—
dBm
lated carrier
R
Spurious emissions of har-
monics in non-restricted
bands per FCC Part
SPUR
HRM_FCC_
Contin
transmission of modu-
-26
dBc
lated ca
r
NRR
15.247/15.35, Emissions tak-
en at POUT
MAX
, PAVDD
connected to external 3.3 V
supply, Test Frequency is
2450 MHz
Spurious emissions out-of-
band (above 2.483 GHz or
below 2.4 GHz) in restricted
bands, per FCC part
15.205/15.209, Emissions
taken at POUT
MAX
AVDD
connected t
ernal 3.3 V
supply, Tes
equency =
2450 MHz
SPUR
OOB_FCC_
Restricted bands 30-88 MHz; con-
—
—
—
—
-52
-62
-57
-48
—
—
—
—
dBm
dBm
dBm
dBm
tinuous transmission of modulated
carrier
Restricted bands 88-216 MHz;
continuous transmission of modu-
lated carrier
Restricted bands 216-960 MHz;
continuous transmission of modu-
lated carrier
Restricted bands >960 MHz; con-
tinuous transmission of modulated
carrier
4
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Spurious emissions out-of-
band in non-restricted bands
per FCC Part 15.247, Emis-
SPUR
OOB_FCC_
Above 2.483 GHz or below 2.4
—
-26
—
dBc
GHz; continuous transmission of
NR
modulated carrier
sions taken at POUT
MAX
,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency = 2450 MHz
Spurious emissions out-of-
band; per ETSI 300.328
5
SPUR
ETSI328
[2400-BW to 2400], [2483.5 to
2483.5+BW];
—
—
-16
-26
—
—
dBm
dBm
[2400-2BW to 2400-BW],
[2483.5+BW to 2483.5+2BW]; per
ETSI 300.328
Spurious emissions per ETSI
SPUR
ETSI440
EN300.440
5
47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
—
—
—
-60
-42
-36
—
—
—
dBm
dBm
dBm
25-1000 MHz, excluding above
frequencies
1G-14G
Note:
1. Typical EVM for the 2415 MHz channel is 7.9%.
2. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with
pseudo-random packet data content.
3. For 2415 MHz, a maximum duty cycle of 50% is used to achieve this valu
4. For 2480 MHz, a maximum duty cycle of 20% is used to achieve th
s value.
5. Specified at maximum power output level of 10 dBm.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.9.6 RF
Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 2.45 GHz.
Table 4.17.
RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Signal is reference signal
1
. Packet
length is 20 octets.
Max usable receiver input
level, 1% PER
SAT
—
10
—
dBm
Sensitivity, 1% PER
2
SENS
Signal is reference signal. Packet
length is 20 octets. Using DC-DC
converter.
—
—
-99
-99
—
—
dBm
dBm
Signal is reference signal. Packet
length is 20 octets. Without DC-
DC converter.
Co-channel interferer rejec-
CCR
tion, 1% PER
Desired signal 3 dB above sensi-
tivity limit
—
—
—
-2.6
33.75
52.2
—
—
—
dB
dB
dB
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
ACR
P1
Interferer is reference signal at +1
channel-spacing.
Interferer is filtered reference sig-
nal
4
at +1 channel-spacing.
level
3
Interferer is CW at +1 chann
spacing
5
.
—
58.6
—
dB
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
ACR
M1
ACR
2
Interferer is reference signal at -1
channel-spacing.
—
—
35
—
—
dB
dB
Interferer is filtere
ference sig-
nal
4
at -1 ch
nnel-spacing.
54.7
level
3
Interfe
CW at -1 channel-
spacing.
—
—
—
60.1
45.9
56.8
—
—
—
dB
dB
dB
Alternate channel rejection,
1% PER. Desired is refer-
ence signal at 3dB above
reference sensitivity level
3
Interferer is reference signal at ± 2
channel-spacing
Interferer is filtered reference sig-
nal
4
at ± 2 channel-spacing
Interferer is CW at ± 2 channel-
spacing
—
—
65.5
49.3
—
—
dB
dB
Interferer is CW in image band
5
Image rejection , 1% PER,
Desired is reference signal at
3dB above reference sensi-
tivity level
3
Blocking rej
ion of all other
BLOCK
channels. 1% PER, Desired
is reference signal at 3dB
abov
reference sensitivity
lev
terferer is reference
signal
Interferer frequency < Desired fre-
quency – 3 channel-spacing
—
—
57.2
57.9
—
—
dB
dB
Interferer frequency > Desired fre-
quency + 3 channel-spacing
Blocking rejection of 802.11g
BLOCK
80211G
signal centered at +12MHz
or -13MHz
6
Desired is reference signal at 6dB
above reference sensitivity level
3
—
51.6
—
dB
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSI
MAX
—
—
5
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSI
MIN
-98
—
—
dBm
RSSI resolution
RSSI
RES
RSSI
LIN
over RSSI
MIN
to RSSI
MAX
—
—
0.25
+/-1
—
—
dB
B
RSSI accuracy in the linear
region as defined by
802.15.4-2003
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Sy
rate = 62.5 ksym-
bols/s.
2. Receive sensitivity on 802.15.4 channel 14 is -98 dBm
3. Reference sensitivity level is -85 dBm.
4. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-
band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.
5. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ± 5 MHz on th
chan
el raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
6. This is an IEEE 802.11b/g ERP-PBCC 22 MBit/s signal as defined by the IEEE 802.11 specification and IEEE 802.11g adden-
dum.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10 Sub-GHz
RF Transceiver Characteristics
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.1 Sub-GHz
RF Transmitter characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz.
Table 4.18.
Sub-GHz RF Transmitter characteristics for 915 MHz Band
Parameter
Symbol
F
RANGE
Test Condition
Min
902
17.7
Typ
—
Max
930
Unit
MHz
m
RF tuning frequency range
Maximum TX Power
1
POUT
MAX
External PA supply = 3.3V, 20
dBm output power setting
20.3
24.5
External PA supply connected to
DC-DC output, 14 dBm output
power setting
10.4
13.8
17.6
dBm
Minimum active TX Power
Output power step size
POUT
MIN
—
—
—
-45.5
0.5
—
—
—
dBm
dB
POUT
STEP
POUT
VAR_V
output power > 0 dBm
Output power variation vs
supply at POUT
MAX
1.8 V < V
VREGVDD
< 3.3 V, Exter-
nal PA supply = 3.3 V, T = 25 °C
4.8
dB
1.8 V < V
VREGVDD
< 3.3 V, Exter-
nal PA supply connected to DC-
DC output, T = 25 °C
—
1.9
—
dB
Output power variation vs
temperature, peak to peak
POUT
VAR_T
-40 to +85 °C with External P
supply = 3.3 V
—
—
—
0.6
0.8
0.7
1.3
1.6
1.4
dB
dB
dB
-40 to +125 °C with External PA
supply = 3.3 V
-40 to +85 °C wit
ternal PA
supply conn
ted to DC-DC out-
put
-40 to +
°C with External PA
supply connected to DC-DC out-
put
—
1.0
1.9
dB
Output power variation vs RF
POUT
VAR_F
frequency
External PA supply = 3.3 V, T =
25 °C
—
—
—
—
0.2
0.3
0.6
0.6
-47
-42
dB
dB
External PA supply connected to
DC-DC output, T = 25 °C
Spurious emissions of har-
monics at 20 dBm output
power, Conducted measure-
ment, 20dBm match, Exter-
nal PA supply = 3.
, Test
Frequency
5 MHz
PUR
HARM_FCC
In restricted bands, per FCC Part
-64.6
-64.2
dBm
dBc
15.205 / 15.209
0
In non-restricted bands, per FCC
Part 15.231
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Spurious emissions out-of-
band at 20 dBm output pow-
er, Conducted measurement,
20dBm match, External PA
supply = 3.3V, Test Frequen-
cy = 915 MHz
SPUR
OOB_FCC_
In non-restricted bands, per FCC
—
-76.2
-66
dBc
Part 15.231
20
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
—
—
—
-68.8
-67.7
-69.1
-52
-62
-58
dBm
dBm
dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
—
—
-54.6
-75.
-69
-42.4
-60
dBm
dBm
dBc
Spurious emissions of har-
monics at 14 dBm output
power, Conducted measure-
ment, 14dBm match, Exter-
nal PA supply connected to
DC-DC output, Test Fre-
quency = 915 MHz
SPUR
HARM_FCC
In restricted bands, per FCC Part
15.205 / 15.209
_14
In non-restricted bands, per FCC
Part 15.231
-49
Spurious emissions out-of-
band at 14 dBm output pow-
er, Conducted measurement,
14dBm match, External PA
supply connected to DC-DC
output, Test Frequency =
915 MHz
SPUR
OOB_FCC_
In non-restricted bands, per FCC
—
—
—
—
-87.5
-74.2
-73.1
-74.3
-66
-52
-67
-58
dBc
dBm
dBm
dBm
Part 15.231
14
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.20
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
In restricted ban
216-960
MHz), per FCC P
5.205 /
15.209
In restr
bands (>960 MHz),
per FCC
art 15.205 / 15.209
—
-60.2
-49
dBm
Note:
1. Supported transmit power levels are deter
ne
by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.2 Sub-GHz
RF Receiver Characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 915 MHz.
Table 4.19.
Sub-GHz RF Receiver Characteristics for 915 MHz Band
Parameter
Symbol
Test Condition
Min
902
—
Typ
—
Max
930
10
Unit
MHz
m
Tuning frequency range
F
RANGE
Max usable input level, 0.1%
SAT
500K
BER
Desired is reference 500 kbps
GFSK signal
1
—
Sensitivity
SENS
Desired is reference 4.8 kbps
—
—
-104.7
—
-100.7
-99.5
dBm
dBm
OOK signal
2
, 20% PER, T ≤ 85 °C
Desired is reference 4.8 kbps
OOK signal
2
, 20% PER, T > 85
°C
Desired is reference 600 bps
GFSK signal
3
, 0.1% BER
—
—
-126.4
-107.5
—
dBm
dBm
Desired is reference 50 kbps
-104.2
GFSK signal
4
, 0.1% BER, T ≤ 85
°C
Desired is reference 50 kbps
GFSK signal
4
, 0.1% BER, T
°C
—
—
—
—
—
—
—
—
-105.1
—
-103
-101.5
-101.3
-93.2
-93
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Desired is reference 100 kbps
GFSK signal
5
, 0.
BER, T ≤ 85
°C
Desired is re
erence 100 kbps
GFSK
l
5
, 0.1% BER, T > 85
°C
Desired is reference 500 kbps
GFSK signal
1
, 0.1% BER, T ≤ 85
°C
-97.7
—
Desired is reference 500 kbps
GFSK signal
1
, 0.1% BER, T > 85
°C
Desired is reference 400 kbps
4GFSK signal
6
, 1% PER, T ≤ 85
°C
-90.9
—
-87.5
-86.9
Desired is reference 400 kbps
4GFSK signal
6
, 1% PER, T > 85
°C
Level above which
RFSENSE
TRIG
CW at 915 MHz
—
—
-25.8
-50
—
—
dBm
dBm
RF
SE will trigger
7
Level below which
RFSENSE will not trigger
7
RFSENSE
THRES
CW at 915 MHz
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Desired is 4.8 kbps OOK signal
2
at 3dB above sensitivity level,
20% PER
Adjacent channel selectivity,
C/I
1
Interferer is CW at ± 1 ×
channel-spacing
—
43.7
—
dB
Desired is 600 bps GFSK signal
3
at 3dB above sensitivity level,
0.1% BER
—
—
—
—
—
—
—
—
—
—
—
65.76
48.24
51.1
47
—
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Desired is 50 kbps GFSK signal
4
at 3dB above sensitivity level,
0.1% BER
Desired is 100 kbps GFSK signal
5
at 3dB above sensitivity level,
0.1% BER
Desired is 500 kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Desired is 400 kbps 4GFSK sig-
nal
6
at 3dB above sensitivity level,
0.1% BER
35.9
57.2
71.76
53.6
56.9
53.6
44
Desired is 4.8 kbps OOK signal
2
at 3dB above sensitivity level,
20% PER
Alternate channel selectivity,
C/I
2
Interferer is CW at ± 2 ×
channel-spacing
Desired is 600 bps GFSK sign
at 3dB above sensitivity level,
0.1% BER
Desired is 50 kb
FSK signal
4
at 3dB above
ensitivity level,
0.1% BER
Desire
00 kbps GFSK signal
5
at 3dB above sensitivity level,
0.1% BER
Desired is 500 kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Desired is 400 kbps 4GFSK sig-
nal
6
at 3dB above sensitivity level,
0.1% BER
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Desired is 4.8 kbps OOK signal
2
at 3dB above sensitivity level,
20% PER
Image rejection, Interferer is
C/I
IMAGE
CW at image frequency
—
41.2
—
dB
Desired is 50 kbps GFSK signal
4
at 3dB above sensitivity level,
0.1% BER
—
—
—
—
52.4
50.35
46.2
—
—
—
—
dB
dB
dB
dB
Desired is 100 kbps GFSK signal
5
at 3dB above sensitivity level,
0.1% BER
Desired is 500 kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Desired is 400 kbps 4GFSK sig-
nal
6
at 3dB above sensitivity level,
0.1% BER
35.9
Blocking selectivity, 0.1%
BER. Desired is 100 kbps
GFSK signal at 3dB above
sensitivity level
C/I
BLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
—
58.7
60.9
76.4
—
—
—
dB
dB
dB
Interferer CW at Desired ± 10
MHz
Desired is 100 kbps GFSK signal
5
at 3dB above sensitivity leve
Intermod selectivity, 0.1%
BER. CW interferers at 400
kHz and 800 kHz offsets
C/I
IM
—
—
46.1
—
—
5
dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSI
MAX
RSSI
MIN
RSSI
RES
dBm
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
-98
—
—
RSSI resolution
Over RSSI
MIN
to RSSI
MAX
range
216-960 MHz
—
—
—
0.25
-77.7
-62.7
—
dBm
dBm
dBm
Max spurious emissions dur-
SPUR
RX_FCC
ing active receive mode, per
FCC Part 15.109(a)
-49.2
-51.7
Above 960 MHz
Max spurious emissions dur-
SPUR
RX_ARIB
ing active receive mode,per
ARIB STD-T108 Section 3.3
Below 710 MHz, RBW=100kHz
710-900 MHz, RBW=1MHz
900-915 MHz, RBW=100kHz
915-930 MHz, RBW=100kHz
930-1000 MHz, RBW=100kHz
Above 1000 MHz, RBW=1MHz
—
—
—
—
—
—
-77.7
-75.8
-85.4
-85.6
-85.1
-57.9
-60
-61
-61
-55
-60
-47
dBm
dBm
dBm
dBm
dBm
dBm
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 175 kHz, RX channel BW = 2524.8 kHz, channel spacing = 1
MHz.
2. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 315.6 kHz, channel spacing = 500 kHz.
3. Definition of reference signal is 600 bps 2GFSK, BT=0.5, Δf = 0.3 kHz, RX channel BW = 1262 Hz, channel spacing = 300 kHz.
4. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 120.229 kHz, channel spacing = 200
kHz.
5. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 210.4 kHz, channel spacing = 400 kHz.
6. Definition of reference signal is 400 kbps 4GFSK, BT=0.5, inner deviation = 33.3 kHz, RX channel BW = 336.64 kHz, ch
spacing = 600 kHz.
7. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.3 Sub-GHz
RF Transmitter characteristics for 868 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 868 MHz.
Table 4.20.
Sub-GHz RF Transmitter characteristics for 868 MHz Band
Parameter
Symbol
F
RANGE
Test Condition
Min
863
16.6
Typ
—
Max
876
23
Unit
MHz
m
RF tuning frequency range
Maximum TX Power
1
POUT
MAX
External PA supply = 3.3V, 20
dBm output power setting, T ≤ 85
°C
19.6
External PA supply = 3.3V, 20
dBm output power setting, T > 85
°C
—
—
3.7
17.5
dBm
dBm
External PA supply connected to
DC-DC output, 14 dBm output
power setting
10
14.7
Minimum active TX Power
Output power step size
POUT
MIN
—
—
—
-43.5
0.5
5
—
—
—
dBm
dB
POUT
STEP
POUT
VAR_V
output power > 0 dBm
Output power variation vs
supply at POUT
MAX
1.8 V < V
VREGVDD
< 3.3 V, Exter-
nal PA supply = 3.3 V, T = 25 °C
dB
1.8 V < V
VREGVDD
< 3.3 V, E
nal PA supply connected to DC-
DC output, T = 25 °C
—
2
—
dB
Output power variation vs
temperature, peak to peak
POUT
VAR_T
-40 to +85 °C wi
ternal PA
supply = 3.3 V
—
—
—
0.6
0.8
0.5
0.9
1.3
1.2
dB
dB
dB
-40 to +125 °C with External PA
supply
V
-40 to +85 °C with External PA
supply connected to DC-DC out-
pu
-40 to +125 °C with External PA
supply connected to DC-DC out-
put
—
0.7
1.5
dB
Output power variation vs RF
POUT
VAR_F
frequency
External PA supply = 3.3 V, T =
25 °C
—
—
—
0.2
0.2
-44
0.6
0.8
-30
dB
dB
External PA supply connected to
DC-DC output, T = 25 °C
Spurious em
ons of har-
monics, Co
cted meas-
urement, External PA supply
connected to DC-DC output,
Test Frequency = 868 MHz
SPUR
HARM_ETSI
Per ETSI EN 300-220, Section
7.8.2.1
dBm
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Spurious emissions out-of-
band, Conducted measure-
ment, External PA supply
connected to DC-DC output,
Test Frequency = 868 MHz
SPUR
OOB_ETSI
Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
—
-61.7
-55.7
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
—
—
-64.2
-59.9
-43.5
-30
dBm
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings f
all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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Rev. 1.4
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.4 Sub-GHz
RF Receiver Characteristics for 868 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 868 MHz.
Table 4.21.
Sub-GHz RF Receiver Characteristics for 868 MHz Band
Parameter
Symbol
Test Condition
Min
863
—
Typ
—
Max
876
10
Unit
MHz
m
Tuning frequency range
F
RANGE
Max usable input level, 0.1%
SAT
2k4
BER
Desired is reference 2.4 kbps
GFSK signal
1
—
Max usable input level, 0.1%
SAT
38k4
BER
Desired is reference 38.4 kbps
GFSK signal
2
—
—
—
—
10
dBm
dBm
dBm
Sensitivity
SENS
Desired is reference 2.4 kbps
GFSK signal
1
, 0.1% BER
-121
-109.2
-116.5
-105.4
Desired is reference 38.4 kbps
GFSK signal
2
, 0.1% BER, T ≤ 85
°C
Desired is reference 38.4 kbps
—
—
-105.2
dBm
GFSK signal
2
, 0.1% BER, T > 85
°C
Desired is reference 500 kbps
GFSK signal
3
, 0.1% BER
—
—
-95.1
-25.8
-50
—
—
—
—
dBm
dBm
dBm
dB
Level above which
RFSENSE
TRIG
CW at 868 MHz
RFSENSE will trigger
4
Level below which
RFSENSE will not trigger
4
RFSENSE
THRES
CW at 868 MHz
—
Desire
.4 kbps GFSK signal
1
at 3dB a
ve sensitivity level,
0.1% BER
Adjacent channel selectivity,
C/I
1
Interferer is CW at ± 1 ×
channel-spacing
48.5
57.7
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
36.4
—
44.9
59.1
47.7
47.5
47.2
—
—
—
—
—
dB
dB
dB
dB
dB
Desired is 2.4kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Alternate channel selectivity,
C/I
2
Interferer is CW at ± 2 ×
channel-spacing
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
—
Desired is 2.4kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Image rejec
Interferer is
C/I
IMAGE
CW at imag
requency
—
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
—
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal
1
at 3 dB above
sensitivity level
C/I
BLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
—
71.9
77.9
90.9
—
—
—
dB
dB
dB
Interferer CW at Desired ± 10
MHz
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSI
MAX
—
—
5
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSI
MIN
-98
—
—
dBm
RSSI resolution
RSSI
RES
Over RSSI
MIN
to RSSI
MAX
range
30 MHz to 1 GHz
—
—
—
0.25
-77.1
-59.9
—
dBm
m
dBm
Max spurious emissions dur-
SPUR
RX
ing active receive mode
-69
-50
1 GHz to 12 GHz
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 5.05 kHz, ch
el s
acing = 12.5 kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 84.16 kHz,
l spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 841.6 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.5 Sub-GHz
RF Transmitter characteristics for 490 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 490 MHz.
Table 4.22.
Sub-GHz RF Transmitter characteristics for 490 MHz Band
Parameter
Symbol
F
RANGE
Test Condition
Min
470
18.5
Typ
—
Max
510
23
Unit
MHz
m
RF tuning frequency range
Maximum TX Power
1
POUT
MAX
External PA supply = 3.3V
21.1
Minimum active TX Power
Output power step size
POUT
MIN
-44.9
0.5
—
—
—
dBm
dB
POUT
STEP
POUT
VAR_V
output power > 0 dBm
—
—
Output power variation vs
supply, peak to peak
at 20 dBm;1.8 V < V
VREGVDD
<
4.3
dB
3.3 V, External PA supply connec-
ted directly to external supply, T =
25 °C
Output power variation vs
temperature, peak to peak
POUT
VAR_T
-40 to +85 °C at 20 dBm
-40 to +125 °C at 20 dBm
T = 25 °C
—
—
—
0.2
0.3
0.2
0.9
1.3
0.4
dB
dB
dB
Output power variation vs RF
POUT
VAR_F
frequency
Harmonic emissions, 20
dBm output power setting,
490 MHz
SPUR
HARM_CN
Per China SRW Requirement
Section 2.1, frequencies belo
1GHz
—
—
—
-41.3
-47.2
-57.5
-34.9
-36
—
dBm
dBm
dBm
Per China SRW Requirement,
Section 2.1, freq
cies above
1GHz
Spurious emissions, 20 dBm
SPUR
OOB_CN
output power setting, 490
MHz
Per China S
W Requirement,
Sectio
8.5-72.5MHz,
76-108M
, 167-223MHz,
470-556MHz, and 606-798MHz)
Per China SRW Requirement,
Section 2.1 (other frequencies be-
low 1GHz)
—
—
-58.5
-47.9
—
—
dBm
dBm
Per China SRW Requirement,
Section 2.1 (frequencies above
1GHz)
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this dat
heet can be found in the Max TX Power column of the Ordering Information Table.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.6 Sub-GHz
RF Receiver Characteristics for 490 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 490 MHz.
Table 4.23.
Sub-GHz RF Receiver Characteristics for 490 MHz Band
Parameter
Symbol
Test Condition
Min
470
—
Typ
—
Max
510
10
Unit
MHz
m
Tuning frequency range
F
RANGE
Max usable input level, 0.1%
SAT
2k4
BER
Desired is reference 2.4 kbps
GFSK signal
1
—
Max usable input level, 0.1%
SAT
38k4
BER
Desired is reference 38.4 kbps
GFSK signal
2
—
—
—
—
10
—
dBm
dBm
dBm
Sensitivity
SENS
Desired is reference 2.4 kbps
GFSK signal
1
, 0.1% BER
-122
-111.7
Desired is reference 38.4 kbps
-108.9
GFSK signal
2
, 0.1% BER, T ≤ 85
°C
Desired is reference 38.4 kbps
GFSK signal
2
, 0.1% BER, T > 85
°C
—
—
—
—
—
—
-117.5
—
-107.9
-114.8
-113.9
-104.7
-104
dBm
dBm
dBm
dBm
dBm
Desired is reference 10 kbps
GFSK signal
3
, 0.1% BER, T
°C
Desired is reference 10 kbps
GFSK signal
3
, 0.
BER, T > 85
°C
Desired is re
erence 100 kbps
GFSK
l
4
, 0.1% BER, T ≤ 85
°C
-107.6
—
Desired is reference 100 kbps
GFSK signal
4
, 0.1% BER, T > 85
°C
Level above which
RFSENSE
TRIG
Desired is reference 100 kbps
GFSK signal
4
, 0.1% BER
—
—
48
-25.8
-50
—
—
—
dBm
dBm
dB
RFSENSE will trigger
5
Level below which
RFSENSE will not trigger
5
RFSENSE
THRES
CW at 490 MHz
Desired is 2.4 kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Adjacent channel selec
ivity, C/I
1
Interferer is CW at ±
×
channel-spacing
58.4
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
38.3
—
47.5
60.8
51.7
—
—
—
dB
dB
dB
Desired is 2.4kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Alt
channel selectivity,
C/I
2
Interferer is CW at ± 2 ×
channel-spacing
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
—
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Desired is 2.4kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Image rejection, Interferer is
C/I
IMAGE
CW at image frequency
—
60.9
—
dB
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
—
53
—
dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal
1
at 3 dB above
sensitivity level
C/I
BLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
—
71.9
74.1
87.9
—
—
—
dB
B
dB
Interferer CW at Desired ± 10
MHz
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSI
MAX
RSSI
MIN
RSSI
RES
—
—
—
5
dBm
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
-98
—
RSSI resolution
Over RSSI
MIN
to RSSI
MAX
range
30 MHz to 1 GHz
—
—
—
0.25
-84.7
-66.8
—
dBm
dBm
dBm
Max spurious emissions dur-
SPUR
RX
ing active receive mode
-54
-54
1 GHz to 12 GHz
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 5.05 kHz, channel spacing = 12.5 kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 84.16 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 10 kbps 2GFSK, BT=0.5, Δf =
z, RX channel BW = 21.04 kHz.
4. Definition of reference signal is 100 kbps 2GFSK, BT=0.
Δf = 50 kHz, RX channel BW = 210.4 kHz.
5. RFSENSE performance is only valid from 0 to 85 °C.
FSENSE should be disabled outside this temperature range.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.7 Sub-GHz
RF Transmitter characteristics for 433 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 433 MHz.
Table 4.24.
Sub-GHz RF Transmitter characteristics for 433 MHz Band
Parameter
Symbol
F
RANGE
Test Condition
Min
426
11
Typ
—
Max
445
18
Unit
MHz
m
RF tuning frequency range
Maximum TX Power
1
POUT
MAX
External PA supply connected to
DC-DC output, 14dBm output
power
14.3
External PA supply connected to
DC-DC output, 10dBm output
power
7
10.7
14
dBm
Minimum active TX Power
Output power step size
POUT
MIN
—
—
—
-42
0
5
1.7
—
—
—
dBm
dB
POUT
STEP
POUT
VAR_V
output power > 0 dBm
Output power variation vs
supply, peak to peak, Pout =
10dBm
At 10 dBm;1.8 V < V
VREGVDD
3.3 V, External PA supply = DC-
DC output, T = 25 °C
<
dB
Output power variation vs
temperature, peak to peak,
Pout= 10dBm
POUT
VAR_T
-40 to +85C at 10dBm
-40 to +125C at 10dBm
—
—
0.5
0.7
1.2
1.7
dB
dB
Output power variation vs RF
POUT
VAR_F
frequency, Pout = 10dBm
T = 25 °C
—
—
—
0.2
0.6
-47
-26
dB
Spurious emissions of har-
monics FCC, Conducted
measurement, 14dBm
SPUR
HARM_FCC
In restricted ban
er FCC Part
15.205 / 15.209
-61.2
-68.5
dBm
dBc
In non-r
stri
ted bands, per FCC
Part 15
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
Spurious emissions out-of-
band FCC, Conducted
measurement, 14dBm
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
SPUR
OOB_FCC
n non-restricted bands, per FCC
Part 15.231
—
—
—
—
-86.2
-71.9
-70.2
-60.5
-26
-52
dBc
dBm
dBm
dBm
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
-62
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
-54.5
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
—
—
-57.7
-57.3
-84.5
-46
-36
-36
dBm
dBm
dBm
Spurious emissions of har-
monics ETSI, Conducted
me
ment, 14dBm
matc
External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
SPUR
HARM_ETSI
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies below 1Ghz)
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1Ghz)
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Spurious emissions out-of-
band ETSI, Conducted
measurement, 14dBm
match, External PA supply
connected to DC-DC output,
Test Frequency = 434 MHz
SPUR
OOB_ETSI
Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
—
-65.1
-60
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
—
—
-63.9
-56.8
-42
-36
dBm
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings f
all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.8 Sub-GHz
RF Receiver Characteristics for 433 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 433 MHz.
Table 4.25.
Sub-GHz RF Receiver Characteristics for 433 MHz Band
Parameter
Symbol
Test Condition
Min
426
—
Typ
—
Max
445
10
Unit
MHz
m
Tuning frequency range
F
RANGE
Max usable input level, 0.1%
SAT
2k4
BER
Desired is reference 2.4 kbps
GFSK signal
1
—
Max usable input level, 0.1%
SAT
50k
BER
Desired is reference 50 kbps
GFSK signal
2
—
—
—
—
10
—
dBm
dBm
dBm
Sensitivity
SENS
Desired is reference 4.8 kbps
OOK signal
3
, 20% PER
-10
Desired is reference 100 kbps
-107.5
-105
GFSK signal
4
, 0.1% BER, T ≤ 85
°C
Desired is reference 100 kbps
GFSK signal
4
, 0.1% BER, T > 85
°C
—
—
—
—
-110
—
-104
dBm
dBm
dBm
Desired is reference 50 kbps
GFSK signal
2
, 0.1% BER, T
°C
-107.2
-106.6
Desired is reference 50 kbps
GFSK signal
2
, 0.
BER, T > 85
°C
Desired is re
erence 2.4 kbps
GFSK
l
1
, 0.1% BER
—
—
—
—
—
-122.3
-109.4
—
—
-106.2
-105.7
—
dBm
dBm
dBm
dBm
dBm
Desired is reference 9.6 kbps
GFSK signal
5
, 1% PER, T ≤ 85 °C
Desired is reference 9.6 kbps
GFSK signal
5
, 1% PER, T > 85 °C
Level above which
RFSENSE will trigger
6
RFSENSE
TRIG
CW at 433 MHz
-25.8
-50
Level below which
RFSENSE will not trigger
6
FSENSE
THRES
CW at 433 MHz
—
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Desired is 4.8 kbps OOK signal
3
at 3dB above sensitivity level,
20% PER
Adjacent channel selectivity,
C/I
1
Interferer is CW at ± 1 ×
channel-spacing
—
46
—
dB
Desired is 100 kbps GFSK signal
4
at 3dB above sensitivity level,
0.1% BER
24.8
47
45.6
—
33.4
59.1
50.7
31.2
56.8
56.2
62.2
57.4
47.8
42.2
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Desired is 2.4 kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Desired is 50 kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
Desired is 9.6 kbps 4GFSK sig-
nal
5
at 3dB above sensitivity level,
1% PER
Desired is 4.8 kbps OOK signal
3
at 3dB above sensitivity level,
20% PER
Alternate channel selectivity,
C/I
2
Interferer is CW at ± 2 ×
channel-spacing
—
Desired is 100 kbps GFSK signal
4
at 3dB above sensitivity level,
0.1% BER
—
Desired is 2.4 kbps GFSK sig
at 3dB above sensitivity level,
0.1% BER
—
Desired is 50 kb
FSK signal
2
at 3dB above
ensitivity level,
0.1% BER
—
Desire
.6 kbps 4GFSK sig-
nal
5
at 3dB above sensitivity level,
1% PER
—
Desired is 4.8 kbps OOK signal
3
at 3dB above sensitivity level,
20% PER
Image rejection, Interferer is
C/I
IMAGE
CW at image frequency
—
Desired is 100 kbps GFSK signal
4
at 3dB above sensitivity level,
0.1% BER
—
Desired is 2.4 kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
—
52.3
53
Desired is 50 kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
—
Desired is 9.6 kbps 4GFSK sig-
—
45
nal
5
at 3dB above sensitivity level,
1% PER
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal
1
at 3dB above
sensitivity level
C/I
BLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
—
73.8
75.7
89.9
—
—
—
dB
dB
dB
Interferer CW at Desired ± 10
MHz
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Desired is 2.4 kbps GFSK signal
1
at 3dB above sensitivity level
Intermod selectivity, 0.1%
BER. CW interferers at 12.5
kHz and 25 kHz offsets
C/I
IM
—
59.1
—
dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSI
MAX
RSSI
MIN
RSSI
RES
—
—
—
5
dBm
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
-98
—
RSSI resolution
Over RSSI
MIN
to RSSI
MAX
range
216-960 MHz
—
—
—
0.25
-83.5
-62
—
dBm
dBm
dBm
Max spurious emissions dur-
SPUR
RX_FCC
ing active receive mode, per
FCC Part 15.109(a)
57
-52
Above 960 MHz
Max spurious emissions dur-
SPUR
RX_ETSI
ing active receive mode, per
ETSI 300-220 Section 8.6
Below 1000 MHz
Above 1000 MHz
—
—
-84.6
-5
.7
-57
-52
dBm
dBm
Max spurious emissions dur-
SPUR
RX_ARIB
ing active receive mode, per
ARIB STD T67 Section
Below 710 MHz, RBW=100kHz
—
-83.6
-57
dBm
3.3(5)
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, R
nnel BW = 5.05 kHz, channel spacing = 12.5 kHz.
2. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 120.229 kHz, channel spacing = 200
kHz.
3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 315.6 kHz, channel spacing = 500 kHz.
4. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf
kHz, RX channel BW = 210.4 kHz, channel spacing = 200 kHz.
5. Definition of reference signal is 9.6 kbps 4GFSK, BT=0.5
ner deviation = 0.8 kHz, RX channel BW = 9.989 kHz, channel spac-
ing = 12.5 kHz.
6. RFSENSE performance is only valid from 0 to 85 °C
SENSE should be disabled outside this temperature range.
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Rev. 1.4
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.9 Sub-GHz
RF Transmitter characteristics for 315 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 315 MHz.
Table 4.26.
Sub-GHz RF Transmitter characteristics for 315 MHz Band
Parameter
Symbol
F
RANGE
Test Condition
Min
195
10.8
Typ
—
Max
358
17
Unit
MHz
m
RF tuning frequency range
Maximum TX Power
1
POUT
MAX
External PA supply connected to
DC-DC output, T ≤ 85 °C
15.3
External PA supply connected to
DC-DC output, T > 85 °C
10.5
—
—
dBm
Minimum active TX Power
Output power step size
POUT
MIN
-43
0.5
—
—
—
dBm
dB
POUT
STEP
POUT
VAR_V
output power > 0 dBm
—
—
Output power variation vs
supply
1.8 V < V
VREGVDD
< 3.3 V, Exter-
nal PA supply = DC-DC output, T
= 25 °C
1
8
dB
Output power variation vs
temperature
POUT
VAR_T
-40 to +85C
-40 to +125C
T = 25 °C
—
—
—
0.5
0.7
0.1
1.2
1.5
0.7
dB
dB
dB
Output power variation vs RF
POUT
VAR_F
frequency
Spurious emissions of har-
monics at 14 dBm output
power, Conducted measure-
ment, 14dBm match, Exter-
nal PA supply connected to
DC-DC output, Test Fre-
quency = 303 MHz
SPUR
HARM_FCC
In restricted bands, per FCC Part
15.205 / 15.209
—
—
-53.8
-63.4
-47
-26
dBm
dBc
In non-restricted
s, per FCC
Part 15.231
Spurious emissions out-of-
band at 14 dBm output pow-
er, Conducted measurement,
14dBm match, External PA
supply connected to DC-DC
output, Test Frequency =
303 MHz
SPUR
OOB_FCC
In non-restricted bands, per FCC
Part 15.231
—
—
—
—
-76.6
-71.8
-70.2
-68.2
-26
-51
-61
-57
dBc
dBm
dBm
dBm
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
—
-57.5
-46
dBm
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.10 Sub-GHz
RF Receiver Characteristics for 315 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 315 MHz.
Table 4.27.
Sub-GHz RF Receiver Characteristics for 315 MHz Band
Parameter
Symbol
Test Condition
Min
195
—
Typ
—
Max
358
10
Unit
MHz
m
Tuning frequency range
F
RANGE
Max usable input level, 0.1%
SAT
2k4
BER
Desired is reference 2.4 kbps
GFSK signal
1
—
Max usable input level, 0.1%
SAT
38k4
BER
Desired is reference 38.4 kbps
GFSK signal
2
—
—
—
10
dBm
dBm
Sensitivity
SENS
Desired is reference 2.4 kbps
-123
-120.7
GFSK signal
1
, 0.1% BER, T ≤ 85
°C
Desired is reference 2.4 kbps
GFSK signal
1
, 0.1% BER, T > 85
°C
—
—
—
—
—
—
-111.4
—
-120
-108.6
-107.9
-94.6
dBm
dBm
dBm
dBm
dBm
Desired is reference 38.4 kbps
GFSK signal
2
, 0.1% BER, T ≤ 85
°C
Desired is reference 38.4 kb
GFSK signal
2
, 0.1% BER, T > 85
°C
Desired is referen
500 kbps
GFSK signal
3
, 0.
BER, T ≤ 85
°C
-97.2
—
Desire
eference 500 kbps
-93.9
GFSK si
al
3
, 0.1% BER, T > 85
°C
Level above which
RFSENSE
TRIG
CW at 315 MHz
—
—
-25.8
-50
—
—
—
dBm
dBm
dB
RFSENSE will trigger
4
Level below which
RFSENSE will not trigger
4
RFSENSE
THRES
CW at 315 MHz
Desired is 2.4 kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Adjacent channel selectivity,
C/I
1
Interferer is CW at ± 1 ×
channel-spacing
54.1
64.2
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
46
—
—
50
66
54
—
—
—
dB
dB
dB
Desired is 2.4kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Alternate channel selectivity,
C/I
2
Interferer is CW at ± 2 ×
cha
l-spacing
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level
2
,
0.1% BER
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Desired is 2.4kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Image rejection, Interferer is
C/I
IMAGE
CW at image frequency
—
54.4
—
dB
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
—
51.9
—
dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal
1
at 3 dB above
sensitivity level
C/I
BLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
—
—
74.9
76.7
93.1
—
—
—
dB
B
dB
Interferer CW at Desired ± 10
MHz
72.6
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSI
MAX
RSSI
MIN
RSSI
RES
—
—
—
5
dBm
dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
-98
—
RSSI resolution
Over RSSI
MIN
to RSSI
MAX
range
216-960 MHz
—
—
—
0.25
-87.4
-76.7
—
dBm
dBm
dBm
Max spurious emissions dur-
SPUR
RX_FCC
ing active receive mode, per
FCC Part 15.109(a)
-55
-47
Above 960MHz
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 5.05 kHz, channel spacing = 12.5 kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 84.16 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf =
5 kHz, RX channel BW = 841.6 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RF
ENSE should be disabled outside this temperature range.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.11 Sub-GHz
RF Transmitter Characteristics for 169 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 169 MHz.
Table 4.28.
Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Parameter
Symbol
F
RANGE
Test Condition
Min
169
18.4
Typ
—
Max
170
Unit
MHz
m
RF tuning frequency range
Maximum TX Power
1
POUT
MAX
External PA supply = 3.3 V
20.4
23.3
Minimum active TX Power
Output power step size
POUT
MIN
-42.6
0.5
—
—
—
dBm
dB
POUT
STEP
POUT
VAR_V
output power > 0 dBm
—
—
Output power variation vs
supply, peak to peak
1.8 V < V
VREGVDD
< 3.3 V, Exter-
nal PA supply = 3.3 V, T = 25 °C
4.8
dB
Output power variation vs
temperature, peak to peak
POUT
VAR_T
-40 to +85 °C at 20 dBm
-40 to +125 °C at 20 dBm
—
—
—
0.6
0.8
1.2
1.5
-36
dB
dB
Spurious emissions of har-
monics, Conducted meas-
urement, External PA supply
= 3.3 V, Test Frequency =
169 MHz
SPUR
HARM_ETSI
Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
-49.3
dBm
Per ETSI EN 300-220, Sectio
7.8.2.1 (other frequencies be
GHz)
—
—
—
-58.2
-38.9
-61.8
-53
25.4
-36
dBm
dBm
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequenc
above 1
GHz)
Spurious emissions out-of-
band, Conducted measure-
ment, External PA supply =
3.3 V, Test Frequency = 169
MHz
SPUR
OOB_ETSI
Per ETSI EN 300-220, Section
7.8.2.1
74 MHz, 87.5-118
MHz, 17
30 MHz, and 470-862
MHz)
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
—
—
-62
-54
dBm
dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
-47.6
-41.1
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this dat
heet can be found in the Max TX Power column of the Ordering Information Table.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.10.12 Sub-GHz
RF Receiver Characteristics for 169 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = External PA
Supply. RFVDD and external PA supply paths filtered using ferrites. Crystal frequency = 38.4 MHz. RF center frequency 169 MHz.
Table 4.29.
Sub-GHz RF Receiver Characteristics for 169 MHz Band
Parameter
Symbol
Test Condition
Min
169
—
Typ
—
Max
170
10
Unit
MHz
m
Tuning frequency range
F
RANGE
Max usable input level, 0.1%
SAT
2k4
BER
Desired is reference 2.4 kbps
GFSK signal
1
—
Max usable input level, 0.1%
SAT
38k4
BER
Desired is reference 38.4 kbps
GFSK signal
2
—
—
—
—
10
—
dBm
dBm
dBm
Sensitivity
SENS
Desired is reference 2.4 kbps
GFSK signal
1
, 0.1% BER
-12
Desired is reference 38.4 kbps
-111.9
-108
GFSK signal
2
, 0.1% BER, T ≤ 85
°C
Desired is reference 38.4 kbps
GFSK signal
2
, 0.1% BER, T > 85
°C
—
—
—
—
-97.7
—
-108.5
-94.6
-94
dBm
dBm
dBm
Desired is reference 500 kbps
GFSK signal
3
, 0.1% BER, T
°C
Desired is reference 500 kbps
GFSK signal
3
, 0.
BER, T > 85
°C
Level above which
RFSENSE
TRIG
CW at 169 MHz
—
—
—
-25.8
-50
—
—
—
dBm
dBm
dB
RFSENSE will trigger
4
Level below which
RFSENSE will not trigger
4
RFSENSE
THRES
CW at 169 MHz
Desired is 2.4 kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Adjacent channel selectivity,
C/I
1
Interferer is CW at ± 1 x
channel-spacing
65
Desired is 38.4kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
43.3
—
50.4
67.9
55.5
54.6
51
—
—
—
—
—
dB
dB
dB
dB
dB
Desired is 2.4kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Alternate channel selec
ivity, C/I
2
Interferer is CW at ±
x
channel-spacing
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
—
Desired is 2.4kbps GFSK signal
1
at 3dB above sensitivity level,
0.1% BER
Ima
jection, Interferer is
C/I
IMAGE
CW at image frequency
—
Desired is 38.4kbps GFSK signal
2
at 3dB above sensitivity level,
0.1% BER
—
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
74.2
76
Max
—
Unit
dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal
1
at 3 dB above
sensitivity level
C/I
BLOCKER
Interferer CW at Desired ± 1 MHz
Interferer CW at Desired ± 2 MHz
68.7
80
—
dB
Interferer CW at Desired ± 10
MHz
90.6
—
dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSI
MAX
RSSI
MIN
RSSI
RES
—
—
—
5
dBm
Bm
Lower limit of input power
range over which RSSI reso-
lution is maintained
-98
—
RSSI resolution
Over RSSI
MIN
to RSSI
MAX
range
30 MHz to 1 GHz
—
—
—
0.25
-83.7
-58.8
—
dBm
dBm
dBm
Max spurious emissions dur-
SPUR
RX
ing active receive mode
-63
-50
1 GHz to 12 GHz
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW =
5 kHz, channel spacing = 12.5 kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 84.16 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 841.6 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
4.1.11 Modem
Tab
4.30. Modem
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Receive bandwidth
BW
RX
onfigurable range with 38.4 MHz
crystal
0.1
—
2530
kHz
IF frequency
f
IF
Configurable range with 38.4 MHz
crystal. Selected steps available.
150
—
1371
kHz
DSSS symbol length
DSSS bits per symbol
SL
DSSS
Configurable in steps of 1 chip
Configurable
2
1
—
—
32
4
chips
PS
DSSS
bits/
symbol
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.12 Oscillators
4.1.12.1 Low-Frequency
Crystal Oscillator (LFXO)
Table 4.31.
Low-Frequency Crystal Oscillator (LFXO)
Parameter
Symbol
Test Condition
Min
—
Typ
32.768
—
Max
—
Unit
Hz
kΩ
Crystal frequency
f
LFXO
Supported crystal equivalent
ESR
LFXO
series resistance (ESR)
—
70
Supported range of crystal
load capacitance
1
C
LFXO_CL
6
8
—
—
18
40
pF
pF
On-chip tuning cap range
2
C
LFXO_T
On each of LFXTAL_N and
LFXTAL_P pins
On-chip tuning cap step size
SS
LFXO
—
—
0.25
273
—
—
pF
nA
Current consumption after
startup
3
I
LFXO
ESR = 70 kOhm, C
L
= 7 pF,
GAIN
4
= 2, AGC
4
= 1
Start- up time
t
LFXO
ESR = 70 kOhm, C
L
= 7 pF,
GAIN
4
= 2
—
308
—
ms
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be C
LFXO_T
/2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW
in EMU_PWRCTRL register.
4. In CMU_LFXOCTRL register.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.12.2 High-Frequency
Crystal Oscillator (HFXO)
Table 4.32.
High-Frequency Crystal Oscillator (HFXO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Crystal frequency
f
HFXO
38.4 MHz required for radio trans-
ciever operation
38
38.4
40
MHz
Supported crystal equivalent
ESR
HFXO_38M4
Crystal frequency 38.4 MHz
series resistance (ESR)
—
6
—
—
60
12
Ω
Supported range of crystal
load capacitance
1
C
HFXO_CL
pF
On-chip tuning cap range
2
C
HFXO_T
SS
HFXO
t
HFXO
On each of HFXTAL_N and
HFXTAL_P pins
9
20
0.04
300
—
25
—
—
40
pF
pF
On-chip tuning capacitance
step
—
Startup time
38.4 MHz, ESR = 50 Ohm, C
L
=
10 pF
—
µs
Frequency tolerance for the
FT
HFXO
crystal
38.4 MHz, ESR = 50 Ohm, C
L
=
10 pF
-40
ppm
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be C
HFXO_T
/2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
4.1.12.3 Low-Frequency
RC Oscillator (LFRCO)
Table 4
3. Low-Frequency
RC Oscillator (LFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
ENVREF
1
= 1, T ≤ 85 °C
ENVREF
1
= 1, T > 85 °C
ENVREF
1
= 0, T ≤ 85 °C
Oscillation frequency
f
LFRCO
30.474
32.768
34.243
kHz
30.474
30.474
—
—
32.768
500
39.7
33.915
—
kHz
kHz
µs
Startup time
t
LFRCO
I
LFRCO
Current con
ption
2
ENVREF = 1 in
CMU_LFRCOCTRL
—
342
—
nA
ENVREF = 0 in
—
494
—
nA
CMU_LFRCOCTRL
Not
. In CMU_LFRCOCTRL register.
2. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.12.4 High-Frequency
RC Oscillator (HFRCO)
Table 4.34.
High-Frequency RC Oscillator (HFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency accuracy
f
HFRCO_ACC
At production calibrated frequen-
cies, across supply voltage and
temperature
-2.5
—
2.5
%
Start-up time
t
HFRCO
f
HFRCO
≥ 19 MHz
4 < f
HFRCO
< 19 MHz
f
HFRCO
≤ 4 MHz
f
HFRCO
= 38 MHz
f
HFRCO
= 32 MHz
f
HFRCO
= 26 MHz
f
HFRCO
= 19 MHz
f
HFRCO
= 16 MHz
f
HFRCO
= 13 MHz
f
HFRCO
= 7 MHz
f
HFRCO
= 4 MHz
f
HFRCO
= 2 MHz
f
HFRCO
= 1
z
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
1
—
—
ns
µs
2.5
204
171
147
126
110
100
81
—
µs
Current consumption on all
supplies
I
HFRCO
228
190
164
138
120
110
91
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
%
33
35
31
35
30
35
Coarse trim step size (% of
period)
SS
HFRCO_COARS
0.8
—
E
Fine trim step size (% of pe-
SS
HFRCO_FINE
riod)
—
—
0.1
0.2
—
—
%
Period jitter
PJ
HFRCO
% RMS
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.12.5 Auxiliary
High-Frequency RC Oscillator (AUXHFRCO)
Table 4.35.
Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Parameter
Symbol
Test Condition
Min
-2.5
Typ
Max
Unit
Frequency accuracy
f
AUXHFRCO_ACC
At production calibrated frequen-
—
2.5
%
cies, across supply voltage and
temperature
Start-up time
t
AUXHFRCO
f
AUXHFRCO
≥ 19 MHz
4 < f
AUXHFRCO
< 19 MHz
f
AUXHFRCO
≤ 4 MHz
f
AUXHFRCO
= 38 MHz
f
AUXHFRCO
= 32 MHz
f
AUXHFRCO
= 26 MHz
f
AUXHFRCO
= 19 MHz
f
AUXHFRCO
= 16 MHz
f
AUXHFRCO
= 13 MHz
f
AUXHFRCO
= 7 MHz
f
AUXHFRCO
= 4 MHz
f
AUXHFRCO
= 2 M
f
AUXHFRCO
=
MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
µs
2.5
204
171
147
126
110
100
81
µs
Current consumption on all
supplies
I
AUXHFRCO
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
%
33
31
30
Coarse trim step size (% of
period)
SS
AUXHFR-
0.8
CO_COARSE
Fine trim step size (% of pe-
SS
AUXHFR-
—
—
0.1
0.2
—
—
%
riod)
CO_FINE
Period jitter
PJ
AUXHFRCO
% RMS
4.1.12.6 Ultra-low
Frequency RC Oscillator (ULFRCO)
Table 4.36.
Ultra-low Frequency RC Oscillator (ULFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
f
ULFRCO
0.95
1
1.07
kHz
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.13 Flash
Memory Characteristics
1
Table 4.37.
Flash Memory Characteristics
1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Flash erase cycles before
failure
EC
FLASH
10000
—
—
cycles
Flash data retention
RET
FLASH
T ≤ 85 °C
10
10
20
—
—
26
—
—
40
ars
years
µs
T ≤ 125 °C
Word (32-bit) programming
time
t
W_PROG
Burst write, 128 words, average
time per word
Single word
57
20
68
27
82
40
µs
Page erase time
2
Mass erase time
3
Device erase time
4 5
t
PERASE
t
MERASE
t
DERASE
ms
20
27
40
ms
T ≤ 85 °C
—
—
—
—
—
60
60
—
—
—
74
78
3
ms
ms
mA
mA
mA
T ≤ 125 °C
Erase current
6
I
ERASE
Page Erase
Mass or Device Erase
5
Write current
6
I
WRITE
3
Note:
1. Flash data retention information is published in the Quarterly
ty and Reliability Report.
2. From setting the ERASEPAGE bit in MSC_WRITECMD t
until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
3. Mass erase is issued by the CPU and erases all fla
4. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW).
5. From setting the DEVICEERASE bit in AA
CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
6. Measured at 25 °C.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.14 General-Purpose
I/O (GPIO)
Table 4.38.
General-Purpose I/O (GPIO)
Parameter
Symbol
Test Condition
GPIO pins
Min
—
Typ
—
Max
IOVDD*0.3
—
Unit
V
Input low voltage
Input high voltage
V
IL
V
IH
GPIO pins
IOVDD*0.7
IOVDD*0.8
—
V
Output high voltage relative
V
OH
to IOVDD
Sourcing 3 mA, IOVDD ≥ 3 V,
—
—
V
DRIVESTRENGTH
1
= WEAK
Sourcing 1.2 mA, IOVDD ≥ 1.62
V,
IOVDD*0.6
—
—
V
DRIVESTRENGTH
1
= WEAK
Sourcing 20 mA, IOVDD ≥ 3 V,
IOVDD*0.8
—
—
—
—
—
—
—
V
V
V
V
V
V
DRIVESTRENGTH
1
= STRONG
Sourcing 8 mA, IOVDD ≥ 1.62 V,
IOVDD*0.6
—
DRIVESTRENGTH
1
= STRONG
Sinking 3 mA, IOVDD ≥ 3 V,
Output low voltage relative to
V
OL
IOVDD
—
—
—
—
IOVDD*0.2
IOVDD*0.4
IOVDD*0.2
IOVDD*0.4
DRIVESTRENGTH
1
= WEAK
Sinking 1.2 mA, IOVDD ≥ 1.62 V,
DRIVESTRENG
= WEAK
Sinking 20
, IOVDD ≥ 3 V,
DRIVE
ENGTH
1
= STRONG
Sinking 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH
1
= STRONG
Input leakage current
I
IOLEAK
All GPIO except LFXO pins, GPIO
≤ IOVDD, T ≤ 85 °C
—
—
—
—
—
30
20
0.1
0.1
—
30
50
nA
nA
nA
nA
µA
kΩ
ns
LFXO Pins, GPIO ≤ IOVDD, T ≤
85 °C
All GPIO except LFXO pins, GPIO
≤ IOVDD, T > 85 °C
110
250
15
LFXO Pins, GPIO ≤ IOVDD, T >
85 °C
—
Input leakag
current on
5VTOL pads above IOVDD
I
5VTOLLEAK
IOVDD < GPIO ≤ IOVDD + 2 V
3.3
43
25
I/O
pull-up/pull-down re-
R
PUD
sist
65
Pulse width of pulses re-
moved by the glitch suppres-
sion filter
t
IOGLITCH
35
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output fall time, From 70%
to 30% of V
IO
t
IOOF
C
L
= 50 pF,
—
1.8
—
ns
DRIVESTRENGTH
1
= STRONG,
SLEWRATE
1
= 0x6
C
L
= 50 pF,
—
—
—
4.5
2.2
7.4
—
—
—
ns
ns
ns
DRIVESTRENGTH
1
= WEAK,
SLEWRATE
1
= 0x6
C
L
= 50 pF,
Output rise time, From 30%
t
IOOR
to 70% of V
IO
DRIVESTRENGTH
1
= STRONG,
SLEWRATE = 0x6
1
C
L
= 50 pF,
DRIVESTRENGTH
1
= WEAK,
SLEWRATE
1
= 0x6
Note:
1. In GPIO_Pn_CTRL register.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.15 Voltage
Monitor (VMON)
Table 4.39.
Voltage Monitor (VMON)
Parameter
Symbol
I
VMON
Test Condition
Min
Typ
Max
Unit
Supply current (including
I_SENSE)
In EM0 or EM1, 1 supply moni-
tored
—
5.8
8.26
µA
In EM0 or EM1, 4 supplies moni-
tored
—
—
—
—
—
11.8
62
16.8
—
A
nA
nA
nA
nA
In EM2, EM3 or EM4, 1 channel
active and above threshold
In EM2, EM3 or EM4, 1 channel
active and below threshold
62
—
In EM2, EM3 or EM4, All channels
active and above threshold
99
—
In EM2, EM3 or EM4, All channels
active and below threshold
99
—
Loading of monitored supply
I
SENSE
In EM0 or EM1
—
—
2
2
—
—
3.4
—
—
—
—
µA
nA
V
In EM2, EM3 or EM4
Threshold range
V
VMON_RANGE
1.62
—
—
Threshold step size
N
VMON_STESP
Coarse
200
20
460
26
mV
mV
ns
Fine
—
Response time
Hysteresis
t
VMON_RES
Supply drops at
s rate
—
V
VMON_HYST
—
mV
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.16 Analog
to Digital Converter (ADC)
Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated.
Table 4.40.
Analog to Digital Converter (ADC)
Parameter
Symbol
Test Condition
Min
Typ
—
Max
12
Unit
Bits
V
Resolution
V
RESOLUTION
V
ADCIN
6
—
Input voltage range
1
Single ended
Differential
—
V
FS
-V
FS
/2
1
—
V
FS
/2
V
AVDD
V
Input range of external refer-
V
ADCREFIN_P
ence voltage, single ended
and differential
—
V
Power supply rejection
2
PSRR
ADC
At DC
At DC
—
—
80
80
—
—
dB
dB
Analog input common mode
CMRR
ADC
rejection ratio
Current from all supplies, us-
I
ADC_CONTINU-
1 Msps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1
4
—
—
—
—
—
—
—
301
149
91
350
—
—
—
—
—
—
µA
µA
µA
µA
µA
µA
µA
ing internal reference buffer.
OUS_LP
Continuous operation. WAR-
MUPMODE
3
= KEEPADC-
WARM
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 1
4
62.5 ksps / 1 MHz ADCCLK,
SPROG = 15, GPBIASACC =
Current from all supplies, us-
I
ADC_NORMAL_LP
35 ksps / 16 MHz ADCCLK, BIA-
51
SPROG = 0, GPB
ASACC = 1
4
ing internal reference buffer.
Duty-cycled operation. WAR-
MUPMODE
3
= NORMAL
5 ksps / 16 MHz
CLK BIA-
SPROG = 0
GPBIASACC = 1
4
9
Current from all supplies, us-
I
ADC_STAND-
125 ks
6 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1
4
117
79
ing internal reference buffer.
BY_LP
Duty-cycled operation.
5 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1
4
AWARMUPMODE
3
= KEEP-
INSTANDBY or KEEPIN-
SLOWACC
Current from all supplies, us-
I
ADC_CONTINU-
1 Msps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0
4
—
—
—
—
—
—
—
345
191
132
102
17
—
—
—
—
—
—
—
µA
µA
µA
µA
µA
µA
µA
ing internal reference buffer.
OUS_HP
Continuous operation. WAR-
MUPMODE
3
= KEEPADC-
WARM
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 0
4
62.5 ksps / 1 MHz ADCCLK, BIA-
SPROG = 15, GPBIASACC = 0
4
Current fro
supplies, us-
I
ADC_NORMAL_HP
35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0
4
ing internal re
erence buffer.
Duty-cycled operation. WAR-
MUPMODE
3
= NORMAL
5 ksps / 16 MHz ADCCLK BIA-
SPROG = 0, GPBIASACC = 0
4
Current from all supplies, us-
I
ADC_STAND-
125 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0
4
162
123
ing internal reference buffer.
BY_HP
Duty-cycled operation.
35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0
4
AWARMUPMODE
3
= KEEP-
INSTANDBY or KEEPIN-
SLOWACC
Current from HFPERCLK
I
ADC_CLK
HFPERCLK = 16 MHz
—
140
—
µA
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
f
ADCCLK
Test Condition
Min
—
Typ
—
—
7
Max
16
1
Unit
MHz
ADC clock frequency
Throughput rate
f
ADCRATE
t
ADCCONV
—
Msps
cycles
cycles
cycles
µs
Conversion time
5
6 bit
8 bit
12 bit
—
—
—
—
5
—
9
—
13
—
WARMUPMODE
3
= NORMAL
Startup time of reference
generator and ADC core
t
ADCSTART
—
WARMUPMODE
3
= KEEPIN-
STANDBY
—
—
58
—
—
—
67
68
2
µs
µs
dB
dB
WARMUPMODE
3
= KEEPINSLO-
WACC
1
Internal reference
6
, differential
measurement
SNDR at 1Msps and f
IN
10kHz
=
SNDR
ADC
—
—
External reference
7
, differential
measurement
Spurious-free dynamic range
SFDR
ADC
(SFDR)
1 MSamples/s, 10 kHz full-scale
sine wave
—
-1
-6
75
—
—
—
2
dB
Differential non-linearity
(DNL)
DNL
ADC
12 bit resolution, No missing co-
des
LSB
LSB
Integral non-linearity (INL),
End point method
INL
ADC
12 bit resolution
6
Offset error
V
ADCOFFSETERR
V
ADCGAIN
-3
—
—
—
0.25
-0.2
-1
3
LSB
%
Gain error in ADC
Using intern
eference
Using e
rnal reference
3.5
—
—
%
Temperature sensor slope
V
TS_SLOPE
-1.84
mV/°C
Note:
1. The absolute voltage allowed at any ADC i
put is dictated by the power rail supplied to on-chip circuitry, and may be lower than
the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on
EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin.
2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.
3. In ADCn_CNTL register.
4. In ADCn_BIASPROG re
ter.
5. Derived from ADCCLK.
6. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The
differential inp
ange with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum
value is
duc
on-tested using sine wave input at 1.5 dB lower than full scale.
7. Extern
ference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or
SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential
input range with this configuration is ± 1.25 V.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.17 Analog
Comparator (ACMP)
Table 4.41.
Analog Comparator (ACMP)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input voltage range
V
ACMPIN
ACMPVDD =
ACMPn_CTRL_PWRSEL
1
0
—
V
ACMPVDD
V
BIASPROG
2
≤ 0x10 or FULL-
BIAS
2
= 0
Supply voltage
V
ACMPVDD
1.85
2.1
—
—
V
VREGVDD_
V
V
MAX
0x10 < BIASPROG
2
≤ 0x20 and
FULLBIAS
2
= 1
V
V
EGVDD_
MAX
BIASPROG
2
= 1, FULLBIAS
2
= 0
Active current not including
voltage reference
3
I
ACMP
—
—
50
—
—
nA
nA
BIASPROG
2
= 0x10, FULLBIAS
2
= 0
306
BIASPROG
2
= 0x20, FULLBIAS
2
= 1
—
—
74
50
95
—
µA
nA
Current consumption of inter-
I
ACMPREF
nal voltage reference
3
VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
VLP selected as input using VDD
—
—
20
—
—
nA
µA
VBDIV selected as input using
1.25 V reference / 1
4.1
VADIV selected a
input using
VDD/1
—
2.4
—
µA
HYSTSEL
4
HYST0
HYSTS
= HYST1
HYSTSEL
4
= HYST2
HYSTSEL
4
= HYST3
HYSTSEL
4
= HYST4
HYSTSEL
4
= HYST5
HYSTSEL
4
= HYST6
HYSTSEL
4
= HYST7
HYSTSEL
4
= HYST8
HYSTSEL
4
= HYST9
HYSTSEL
4
= HYST10
HYSTSEL
4
= HYST11
HYSTSEL
4
= HYST12
HYSTSEL
4
= HYST13
HYSTSEL
4
= HYST14
HYSTSEL
4
= HYST15
Hysteresis (V
CM
= 1.25 V,
BIASPROG
2
= 0x10, FULL-
BIAS
2
= 1)
V
ACMPHYST
-1.75
10
0
1.75
26
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
18
32
44
55
65
77
86
0
21
46
27
63
32
80
38
100
121
148
4
43
47
-4
-27
-47
-64
-78
-93
-113
-135
-18
-32
-43
-54
-64
-74
-85
-10
-18
-27
-32
-37
-42
-47
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Comparator delay
5
BIASPROG
2
= 1, FULLBIAS
2
= 0
t
ACMPDELAY
—
30
—
µs
BIASPROG
2
= 0x10, FULLBIAS
2
= 0
—
3.7
35
—
—
—
35
µs
BIASPROG
2
= 0x20, FULLBIAS
2
= 1
—
ns
BIASPROG
2
=0x10, FULLBIAS
2
= 1
Offset voltage
V
ACMPOFFSET
-35
mV
Reference voltage
V
ACMPREF
Internal 1.25 V reference
Internal 2.5 V reference
1
2
1.25
2.5
1.47
2.8
—
V
V
CSRESSEL
6
= 0
CSRESSEL
6
= 1
CSRESSEL
6
= 2
CSRESSEL
6
= 3
CSRESSEL
6
= 4
CSRESSEL
6
= 5
CSRESSEL
6
= 6
CSRESSEL
6
= 7
Capacitive sense internal re-
R
CSRES
sistance
—
infinite
kΩ
—
—
—
—
—
—
—
15
27
—
—
—
—
—
—
—
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
39
51
102
164
239
Note:
1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL
PWRSEL and may be IOVDD, AVDD or DVDD.
2. In ACMPn_CTRL register.
3. The total ACMP current is the sum of the contributions fr
the ACMP and its internal voltage reference. I
ACMPTOTAL
= I
ACMP
I
ACMPREF
+
.
4. In ACMPn_HYSTERESIS registers.
5. ± 100 mV differential drive.
6. In ACMPn_INPUTSEL register.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.18 Current
Digital to Analog Converter (IDAC)
Table 4.42.
Current Digital to Analog Converter (IDAC)
Parameter
Symbol
Test Condition
Min
—
Typ
4
Max
—
Unit
ranges
µA
Number of ranges
Output current
N
IDAC_RANGES
I
IDAC_OUT
RANGSEL
1
= RANGE0
RANGSEL
1
= RANGE1
RANGSEL
1
= RANGE2
RANGSEL
1
= RANGE3
0.05
—
1.6
1.6
0.5
2
—
—
—
32
4.7
16
64
—
A
µA
µA
Linear steps within each
range
N
IDAC_STEPS
—
steps
RANGSEL
1
= RANGE0
RANGSEL
1
= RANGE1
RANGSEL
1
= RANGE2
RANGSEL
1
= RANGE3
Step size
SS
IDAC
—
—
—
—
-2
50
100
500
2
—
—
—
—
2
nA
nA
nA
µA
%
Total accuracy, STEPSEL
1
=
0x10
ACC
IDAC
EM0 or EM1, AVDD=3.3 V, T = 25
°C
—
EM0 or EM1, Across
perating
temperature range
-18
—
—
-2
22
—
%
%
EM2 or EM3, Sou
e mode,
RANGSEL
1
= R
E0,
AVDD=3.3
= 25 °C
EM2 or
3, Source mode,
RANGS
= RANGE1,
AVDD=3.3 V, T = 25 °C
—
—
—
—
—
—
—
—
-1.7
-0.8
-0.5
-0.7
-0.6
-0.5
-0.5
5
—
—
—
—
—
—
—
—
%
EM2 or EM3, Source mode,
RANGSEL
1
= RANGE2,
AVDD=3.3 V, T = 25 °C
%
EM2 or EM3, Source mode,
RANGSEL
1
= RANGE3,
AVDD=3.3 V, T = 25 °C
%
EM2 or EM3, Sink mode, RANG-
SEL
1
= RANGE0, AVDD=3.3 V, T
= 25 °C
%
EM2 or EM3, Sink mode, RANG-
SEL
1
= RANGE1, AVDD=3.3 V, T
= 25 °C
%
EM2 or EM3, Sink mode, RANG-
SEL
1
= RANGE2, AVDD=3.3 V, T
= 25 °C
%
EM2 or EM3, Sink mode, RANG-
SEL
1
= RANGE3, AVDD=3.3 V, T
= 25 °C
%
µs
Start up time
t
IDAC_SU
Output within 1% of steady state
value
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
5
Max
—
Unit
µs
Settling time, (output settled
t
IDAC_SETTLE
within 1% of steady state val-
ue),
Range setting is changed
Step value is changed
—
1
—
µs
Current consumption
2
I
IDAC
EM0 or EM1 Source mode, ex-
cluding output current, Across op-
erating temperature range
—
—
8.9
12
13
16
µA
µA
EM0 or EM1 Sink mode, exclud-
ing output current, Across operat-
ing temperature range
EM2 or EM3 Source mode, ex-
cluding output current, T = 25 °C
—
—
—
—
—
1.04
1.08
8.9
—
—
—
—
—
µA
µA
µA
µA
%
EM2 or EM3 Sink mode, exclud-
ing output current, T = 25 °C
EM2 or EM3 Source mode, ex-
cluding output current, T ≥ 85 °C
EM2 or EM3 Sink mode, exclud-
ing output current, T ≥ 85 °C
12
Output voltage compliance in
I
COMP_SRC
source mode, source current
change relative to current
sourced at 0 V
RANGESEL1=0, output voltage =
min(V
IOVDD
, V
AVDD
2
-100 mV)
0.04
RANGESEL1=1, output voltage =
min(V
IOVDD
, V
AVDD
2
-100 mV
—
—
—
0.02
0.02
0.02
—
—
—
%
%
%
RANGESEL1=2, output voltage =
min(V
IOVDD
, V
AVDD
2
-150 mV)
RANGESEL1=3
ut voltage =
min(V
IOVDD
,
VDD
-250 mV)
Output voltage compliance in
I
COMP_SINK
sink mode, sink current
change relative to current
sunk at IOVDD
RANGE
L1=0, output voltage =
100 mV
—
—
—
—
0.18
0.12
0.08
0.02
—
—
—
—
%
%
%
%
RANGESEL1=1, output voltage =
00 mV
RANGESEL1=2, output voltage =
150 mV
RANGESEL1=3, output voltage =
250 mV
Note:
1. In IDAC_CURPROG register.
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in th
IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-
tween
D (0) and DVDD (1).
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Electrical Specifications
4.1.19 Pulse
Counter (PCNT)
Table 4.43.
Pulse Counter (PCNT)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input frequency
F
IN
Asynchronous Single and Quad-
rature Modes
—
—
10
MHz
Sampled Modes with Debounce
filter set to 0.
—
—
8
Hz
4.1.20 I2C
4.1.20.1 I2C
Standard-mode (Sm)
1
Table 4.44.
I2C Standard-mode (Sm)
1
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
SCL clock frequency
2
SCL clock low time
SCL clock high time
SDA set-up time
f
SCL
0
—
100
kHz
t
LOW
4.7
4
—
—
—
—
—
—
—
µs
µs
ns
ns
µs
t
HIGH
t
SU_DAT
t
HD_DAT
250
100
4.7
—
SDA hold time
3
3450
—
Repeated START condition
t
SU_STA
set-up time
(Repeated) START condition
t
HD_STA
hold time
4
—
—
µs
STOP condition set-up time
t
SU_STO
4
—
—
—
—
µs
µs
Bus free time between a
t
BUF
4.7
STOP and START condition
Note:
1. For CLHR set to 0 in th
n_CTRL register.
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (t
HD_DAT
) needs to be met only when the device does not stretch the low time of SCL (t
LOW
).
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Electrical Specifications
4.1.20.2 I2C
Fast-mode (Fm)
1
Table 4.45.
I2C Fast-mode (Fm)
1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency
2
SCL clock low time
SCL clock high time
SDA set-up time
f
SCL
0
—
400
kHz
t
LOW
1.3
0.6
—
—
—
—
—
—
—
µs
µs
ns
ns
µs
t
HIGH
t
SU_DAT
t
HD_DAT
100
100
0.6
—
SDA hold time
3
900
—
Repeated START condition
t
SU_STA
set-up time
(Repeated) START condition
t
HD_STA
hold time
0.6
—
—
µs
STOP condition set-up time
t
SU_STO
0.6
1.3
—
—
—
—
µs
µs
Bus free time between a
t
BUF
STOP and START condition
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (t
HD,DAT
) needs to be met only when the device does not stretch the low time of SCL (t
LOW
).
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Electrical Specifications
4.1.20.3 I2C
Fast-mode Plus (Fm+)
1
Table 4.46.
I2C Fast-mode Plus (Fm+)
1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency
2
SCL clock low time
SCL clock high time
SDA set-up time
f
SCL
0
—
1000
kHz
t
LOW
0.5
0.26
50
—
—
—
—
—
—
—
—
—
—
µs
µs
ns
ns
µs
t
HIGH
t
SU_DAT
t
HD_DAT
SDA hold time
100
0.26
Repeated START condition
t
SU_STA
set-up time
(Repeated) START condition
t
HD_STA
hold time
0.26
—
—
µs
STOP condition set-up time
t
SU_STO
0.26
0.5
—
—
—
—
µs
µs
Bus free time between a
t
BUF
STOP and START condition
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.1.21 USART
SPI
SPI Master Timing
Table 4.47.
SPI Master Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period
1 2 3
t
SCLK
2 *
t
HFPERCLK
—
—
ns
CS to MOSI
1 2
t
CS_MO
t
SCLK_MO
t
SU_MI
-9
-6
—
—
10
ns
ns
SCLK to MOSI
1 2
MISO setup time
1 2
6.5
IOVDD = 1.62 V
IOVDD = 3.0 V
60
40
—
—
—
—
—
—
ns
ns
ns
MISO hold time
1 2
t
H_MI
-13
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of V
DD
(figure shows 50% of V
DD
).
3. t
HFPERCLK
is one period of the selected HFPERCLK.
t
CS_MO
CS
CKL_MO
SCLK
CLKPOL = 0
t
SCLK
SCLK
CLKPOL = 1
MOSI
MISO
t
SU_MI
t
H_MI
Figure 4.1.
SPI Master Timing Diagram
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Electrical Specifications
SPI Slave Timing
Table 4.48.
SPI Slave Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period
1 2 3
t
SCLK
6 *
t
HFPERCLK
—
—
ns
SCLK high time
1 2 3
SCLK low time
1 2 3
t
SCLK_HI
2.5 *
t
HFPERCLK
—
—
—
—
s
ns
t
SCLK_LO
2.5 *
t
HFPERCLK
CS active to MISO
1 2
CS disable to MISO
1 2
MOSI setup time
1 2
MOSI hold time
1 2 3
SCLK to MISO
1 2 3
t
CS_ACT_MI
t
CS_DIS_MI
t
SU_MO
4
4
8
7
—
—
—
—
—
70
50
—
—
ns
ns
ns
ns
ns
t
H_MO
t
SCLK_MI
0 + 1.
*
t
HFPERCLK
65 + 2.5 *
t
HFPERCLK
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPH
0).
2. Measurement done with 8 pF output loading at 10% and 90% of V
DD
(figure shows 50% of V
DD
).
3. t
HFPERCLK
is one period of the selected HFPERCLK.
t
CS_ACT_MI
CS
t
CS_DIS_MI
SCLK
CLKPOL = 0
t
SCLK_HI
t
SCLK_LO
SCLK
t
U_MO
CLKPOL = 1
t
SCLK
t
H_MO
MOSI
MISO
t
SCLK_MI
Figure 4.2.
SPI Slave Timing Diagram
4.2 Typical
Performance Curves
Typi
performance curves indicate typical characterized performance under the stated conditions.
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Electrical Specifications
4.2.1 Supply
Current
Figure 4.3.
EM0 Active Mode Typical Supply Current
s. Temperature
Figure 4.4.
EM1 Sleep Mode Typical Supply Current vs. Temperature
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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Electrical Specifications
Figure 4.5.
EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature
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Electrical Specifications
4.2.2 DC-DC
Converter
Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 1.0 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.6.
DC-DC Converter Typical Performance Characteristics
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Electrical Specifications
Load Step Response in LN (CCM) mode
(Heavy Drive)
LN (CCM) and LP mode transition (load: 5mA)
DVDD
DVDD
60mV/div
offset:1.8V
50mV/div
offset:1.8V
100mA
I
LOAD
1mA
V
SW
2V/div
offset:1.8V
10μ
100μs/div
Figure 4.7.
DC-DC Converter Transition Waveforms
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
4.2.3 Internal
Oscillators
Figure 4.8.
HFRCO and AUXHFRCO Typical Performance at 38 MHz
Figure 4.9.
HFRCO and AUXHFRCO Typical Performance at 32 MHz
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Figure 4.10.
HFRCO and AUXHFRCO Typical Performance at 26 MHz
Figure 4.11.
HFRCO and AUXHFRCO Typical Performance at 19 MHz
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Figure 4.12.
HFRCO and AUXHFRCO Typical Performance at 16 MHz
Figure 4.13.
HFRCO and AUXHFRCO Typical Performance at 13 MHz
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Electrical Specifications
Figure 4.14.
HFRCO and AUXHFRCO Typical Performance at 7 MHz
Figure 4.15.
HFRCO and AUXHFRCO Typical Performance at 4 MHz
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Electrical Specifications
Figure 4.16.
HFRCO and AUXHFRCO Typical Performance at 2 MHz
Figure 4.17.
HFRCO and AUXHFRCO Typical Performance at 1 MHz
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Electrical Specifications
Figure 4.18.
LFRCO Typical Performance at 32.768 kHz
Figure 4.19.
ULFRCO Typical Performance at 1 kHz
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Electrical Specifications
4.2.4 2.4
GHz Radio
Figure 4.20.
2.4 GHz RF Transmitter Output Power
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Electrical Specifications
Figure 4.21.
2.4 GHz RF Receiver Sensitivity
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Typical Connection Diagrams
5. Typical
Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure.
V
DD
Main
Supply
+
–
VREGVDD
AVDD
IOVDD
VREGSW
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
VREGVSS
DVDD
DECOUPLE
RFVDD
PAVDD
Figure 5.1.
EFR32MG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter
Typical power supply circuits using the internal DC-DC converter are shown be
The MCU operates from the DC-DC converter sup-
ply. For low RF transmit power applications less than 13dBm, the RF PA may b
upplied by the DC-DC converter. For OPNs support-
ing high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm.
V
DD
Main
Supply
+
–
GVDD
AVDD
IOVDD
V
DCDC
VREGSW
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
VREGVSS
DVDD
DECOUPLE
RFVDD
PAVDD
Figur
5.2. EFR32MG1
Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC)
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Typical Connection Diagrams
V
DD
Main
Supply
+
–
VREGVDD
AVDD
IOVDD
V
DCDC
VREGSW
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
VREGVSS
DVDD
DECOUPLE
RFVDD
PAVDD
Figure 5.3.
EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD)
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Typical Connection Diagrams
5.2 RF
Matching Networks
Typical RF matching network circuit diagrams are shown in
Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on
page 103
for applications in the 2.4GHz band, and in
Figure 5.5 Typical Sub-GHz RF impedance-matching network circuits on page
103
for applications in the sub-GHz band. Application-specific component values can be found in the EFR32xG1 Reference Manual.
For low RF transmit power applications less than 13dBm, the two-element match is recommended. For OPNs supporting high power
RF transmission, the four-element match is recommended for high RF transmit power (> 13dBm).
4-Element Match for 2.4GHz Band
2-Element Match for 2.4GHz Band
PAVDD
PAVDD
PAVDD
PAVDD
2G4RF_IOP
2G4RF_ION
L0
L0
L
2G4RF_IOP
2G4RF_ION
50Ω
50Ω
C0
C0
C1
Figure 5.4.
Typical 2.4 GHz RF impedance-matching networ
circuits
Sub-GHz Match Topology I (169-500 MHz)
PAVDD
L1
L2
C0
L3
C5
L5
L6
L7
SUBGRF_IN
SUBGRF_IP
50Ω
C2
C3
C4
C7
C8
C9
C10
L0
C1
L4
BAL1
SUBGRF_ON
SUBGRF_OP
Sub-GHz Match Topology 2 (500-915 MHz)
C0
L3
PAVDD
L5
L6
SUBGRF_IN
50Ω
L0
C4
C7
C8
C9
S
BGRF_IP
L4
BAL1
C1
SUBGRF_ON
SUBGRF_OP
Figure 5.5.
Typical Sub-GHz RF impedance-matching network circuits
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Typical Connection Diagrams
5.3 Other
Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002: “Hardware De-
sign Considerations” contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
6. Pin
Definitions
6.1 QFN48
2.4 GHz and Sub-GHz Device Pinout
Figure 6.1.
QFN48 2.4 GHz and Sub-GHz Device Pinout
The following table prov
des package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see
6.5 GPIO Functionality Table
or
6.6 Alternate Functionality Overview
.
Table 6.1.
QFN48 2.4 GHz and Sub-GHz Device Pinout
Pin Name
S
Pin(s) Description
Pin Name
PF0
Pin(s) Description
0
2
Ground
1
3
GPIO (5V)
PF1
GPIO (5V)
PF2
GPIO (5V)
PF3
4
GPIO (5V)
PF4
5
GPIO (5V)
PF5
6
GPIO (5V)
PF6
7
GPIO (5V)
PF7
8
GPIO (5V)
RFVDD
HFXTAL_P
9
Radio power supply
High Frequency Crystal output pin.
HFXTAL_N
10
High Frequency Crystal input pin.
11
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Pin Definitions
Pin Name
Pin(s) Description
Reset input, active low. To apply an ex-
Pin Name
Pin(s) Description
ternal reset source to this pin, it is re-
quired to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
Sub GHz Differential RF output, positive
path.
RESETn
12
SUBGRF_OP
13
Sub GHz Differential RF output, nega-
tive path.
Sub GHz Differential RF input, positive
path.
SUBGRF_ON
SUBGRF_IN
14
16
SUBGRF_IP
RFVSS
15
17
Sub GHz Differential RF input, negative
path.
Radio Ground
2.4 GHz Differential RF input/output,
negative path. This pin should be exter-
nally grounded.
Power Amplifier (PA) voltage regulator
VSS
PAVSS
18
20
2G4RF_ION
PAVDD
19
21
2.4 GHz Differential RF input/output,
positive path.
Power Amp
A) voltage regulator
VDD input
2G4RF_IOP
PD13
PD15
PA1
22
24
26
28
30
32
34
36
38
GPIO (5V)
PD14
PA0
23
25
27
29
31
33
35
37
39
GPIO (5V)
GPIO (5V)
GPIO
GPIO
PA2
GPIO (5V)
PA3
GPIO (5V)
PA4
GPIO (5V)
PA5
GPIO (5V)
PB11
GPIO (5V)
PB12
AVDD
PB15
VREGSW
GPIO (5V)
PB13
GPIO (5V)
Analog power supply.
GPIO
PB14
GPIO
VREGVSS
REGVDD
Voltage regulator VSS
Voltage regulator VDD input
DCDC regulator switching node
Decouple output for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin.
DVDD
40
Digital power supply.
DECOUPLE
41
IOVDD
PC7
42
44
46
48
Digital IO power supply.
GPIO (5V)
PC6
PC8
43
45
47
GPIO (5V)
GPIO (5V)
GPIO (5V)
PC9
GPIO (5V)
PC10
PC11
Note:
GPIO (5V)
1. GPIO with 5V tolerance
ndicated by (5V).
2. The pins PA2, PA3, PA4, PB11, PB12, PB13, PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to
preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
6.2 QFN48
2.4 GHz Device Pinout
Figure 6.2.
QFN48 2.4 GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPI
n, see
6.5 GPIO Functionality Table
or
6.6 Alternate Functionality Overview
.
Table 6.2.
QFN48 2.4 GHz Device Pinout
Pin Name
VSS
Pin(s) Description
Pin Name
PF0
Pin(s) Description
0
2
Ground
1
3
GPIO (5V)
PF1
GPIO (5V)
PF2
GPIO (5V)
3
4
GPIO (5V)
PF4
5
GPIO (5V)
PF5
6
GPIO (5V)
PF6
7
GPIO (5V)
PF7
8
GPIO (5V)
RFVDD
HFXTAL_P
9
Radio power supply
High Frequency Crystal output pin.
HFXTAL_N
10
High Frequency Crystal input pin.
11
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Reset input, active low. To apply an ex-
Pin Name
Pin(s) Description
ternal reset source to this pin, it is re-
quired to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
RESETn
12
NC
13
No Connect.
Power Amplifier (PA) voltage regulator
VSS
RFVSS
2G4RF_ION
PAVDD
14
16
18
Radio Ground
PAVSS
2G4RF_IOP
PD10
15
17
19
2.4 GHz Differential RF input/output,
negative path. This pin should be exter-
nally grounded.
2.4 GHz Differential RF input/o
t,
positive path.
Power Amplifier (PA) voltage regulator
VDD input
GPIO (5V)
PD11
PD13
PD15
PA1
20
22
24
26
28
30
32
34
36
38
GPIO (5V)
PD12
PD14
21
23
25
27
29
31
33
35
37
39
GPIO (5V)
GPIO (5V)
GPIO (5V)
GPIO (5V)
PA0
GPIO
GPIO
PA2
IO (5V)
PA3
GPIO (5V)
PA4
GPIO (5V)
PA5
GPIO (5V)
PB11
GPIO (5V)
PB12
AVDD
PB15
VREGSW
GPIO (5V)
PB13
GPIO (5V)
Analog power supply.
GPIO
PB14
GPIO
VREGVSS
VREGVDD
Voltage regulator VSS
Voltage regulator VDD input
DCDC regulator switching node
Decouple output for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin.
DVDD
40
Digital power supply.
DECOUPLE
41
IOVDD
PC7
42
44
46
48
Digital IO power supply.
GPIO (5V)
PC6
PC8
43
45
47
GPIO (5V)
GPIO (5V)
GPIO (5V)
PC9
GPIO (5V)
PC10
PC11
Note:
GPIO (5V)
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PA2, PA3, PA
11, PB12, PB13, PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to
preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
6.3 QFN48
Sub-GHz Device Pinout
Figure 6.3.
QFN48 Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPI
n, see
6.5 GPIO Functionality Table
or
6.6 Alternate Functionality Overview
.
Table 6.3.
QFN48 Sub-GHz Device Pinout
Pin Name
VSS
Pin(s) Description
Pin Name
PF0
Pin(s) Description
0
2
Ground
1
3
GPIO (5V)
PF1
GPIO (5V)
PF2
GPIO (5V)
3
4
GPIO (5V)
PF4
5
GPIO (5V)
PF5
6
GPIO (5V)
PF6
7
GPIO (5V)
PF7
8
GPIO (5V)
RFVDD
HFXTAL_P
9
Radio power supply
High Frequency Crystal output pin.
HFXTAL_N
10
High Frequency Crystal input pin.
11
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Reset input, active low. To apply an ex-
Pin Name
Pin(s) Description
ternal reset source to this pin, it is re-
quired to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
Sub GHz Differential RF output, positive
path.
RESETn
12
SUBGRF_OP
13
Sub GHz Differential RF output, nega-
tive path.
Sub GHz Differential RF input, positive
path.
SUBGRF_ON
SUBGRF_IN
14
16
SUBGRF_IP
RFVSS
15
17
Sub GHz Differential RF input, negative
path.
Radio Ground
PD9
PD11
PD13
PD15
PA1
18
20
22
24
26
28
30
32
34
36
38
GPIO (5V)
PD10
PD12
19
21
23
25
27
29
31
33
35
37
39
GPIO (5V)
GPIO (5V)
GPIO (5V)
GPIO (5V)
PD14
GPIO (5V)
GPIO (5V)
PA0
GPIO
GPIO
PA2
GPIO
5V)
PA3
GPIO (5V)
PA4
G
O (5V)
PA5
GPIO (5V)
PB11
GPIO (5V)
PB12
AVDD
PB15
VREGSW
GPIO (5V)
PB13
GPIO (5V)
Analog power supply.
GPIO
PB14
GPIO
VREGV
VREGVDD
Voltage regulator VSS
Voltage regulator VDD input
DCDC regulator switching node
Decouple output for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin.
DVDD
40
Digital power supply.
ECOUPLE
41
IOVDD
PC7
42
44
46
48
Digital IO power supply.
GPIO (5V)
PC6
PC8
43
45
47
GPIO (5V)
GPIO (5V)
GPIO (5V)
PC9
GPIO (5V)
PC10
PC11
Note:
GPIO (5V)
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PA2, PA3, PA4, PB11, PB12, PB13, PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to
preserve upgrade option
with full hardware compatibility, do not use these pins with 5V domains.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
6.4 QFN32
2.4 GHz Device Pinout
Figure 6.4.
QFN32 2.4 GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPI
n, see
6.5 GPIO Functionality Table
or
6.6 Alternate Functionality Overview
.
Table 6.4.
QFN32 2.4 GHz Device Pinout
Pin Name
VSS
Pin(s) Description
Pin Name
PF0
Pin(s) Description
0
2
4
6
Ground
1
3
5
7
GPIO (5V)
PF1
GPIO (5V)
PF2
GPIO (5V)
3
GPIO (5V)
RFVDD
HFXTAL_P
Radio power supply
High Frequency Crystal output pin.
HFXTAL_N
High Frequency Crystal input pin.
Reset input, active low. To apply an ex-
ternal reset source to this pin, it is re-
quired to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
RESETn
8
RFVSS
9
Radio Ground
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Pin Name
Pin(s) Description
2.4 GHz Differential RF input/output,
Power Amplifier (PA) voltage regulator
PAVSS
10
12
2G4RF_ION
PAVDD
11
negative path. This pin should be exter-
nally grounded.
VSS
2.4 GHz Differential RF input/output,
positive path.
Power Amplifier (PA) voltage regulator
VDD input
2G4RF_IOP
13
PD13
PD15
14
16
18
20
22
24
26
GPIO (5V)
PD14
PA0
15
17
19
21
23
25
27
GPIO (5V)
GPIO (5V)
GPIO
PA1
GPIO
PB11
GPIO (5V)
PB12
GPIO (5V)
PB13
GPIO (5V)
AVDD
PB15
Analog power supply.
GPIO
PB14
GPIO
VREGVSS
VREGVDD
Voltage reg
SS
Voltage regulator VDD input
VREGSW
DCDC regulator switching node
Decouple
utput for on-chip voltage
regulato
. An external decoupling ca-
citor is required at this pin.
DVDD
28
Digital power supply.
DECOUPLE
PC10
29
31
IOVDD
PC11
30
32
Digital IO power supply.
GPIO (5V)
GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PB11, PB12, PB13, PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade
options with full hardware compatibility, do not use these pins with 5V domains.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
6.5 GPIO
Functionality Table
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO
pin, followed by the functionality available on that pin. Refer to
6.6 Alternate Functionality Overview
for a list of GPIO locations available
for each function.
Table 6.5.
GPIO Functionality Table
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29 LE-
TIM0_OUT0 #0 LE-
TIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
US0_TX #0 US0_RX
#31 US0_CLK #30
US0_CS #29
US0_CTS #28
US0_RTS #27
US1_TX #0 US1_RX
FRC_DFRAME
#31 US1_CLK #30
US1_CS #29
FRC_DCLK #0
FRC_DOUT #3
CMU_CLK1 #0
PRS_CH6 #0
PRS_CH7 #10
PRS_CH8 #9
PRS_CH9 #8
ACMP0_O #0
ACMP1_O #0
BUSDY BUSCX
ADC0_EXTN
MODEM_DCLK #0
MODEM_DIN #31
MODEM_DOUT #30
MODEM_ANT0 #29
MOD
M_ANT1 #28
PA0
US1_CTS #28
US1_RTS #27
LEU0_TX #0
LEU0_RX #31
I2C0_SDA #0
I2C0_SCL #31
TIM0_CC0 #1
TIM0_CC1 #0
US0_TX #1 US0_RX
#0 US0_C
31
US0_CS
US0_CTS #29
US0_RTS #28
US1_TX #1 US1_RX
FRC_DFRAME #31
US1_CLK #31
US1_CS #30
US1_CTS #29
US1_RTS #28
LEU0_TX #1
LEU0_RX #0
I2C0_SDA #1
I2C0_SCL #0
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
FRC_DCLK #1
FRC_DOUT #0
CMU_CLK0 #0
PRS_CH6 #1
PRS_CH7 #0
PRS_CH8 #10
PRS_CH9 #9
ACMP0_O #1
ACMP1_O #1
BUSCY BUSDX
ADC0_EXTP
MODEM_DCLK #1
MODEM_DIN #0
MODEM_DOUT #31
MODEM_ANT0 #30
MODEM_ANT1 #29
PA1
TIM1_CC1 #0
TIM1_CC2 #31
TIM1_CC3 #3
E-
TIM0_OUT0
E-
TIM0_OUT1 #0
PCNT0_S0IN #1
P
T0_S1IN #0
TIM0_CC0 #2
TIM0_CC1 #1
TIM0_CC2 #0
US0_TX #2 US0_RX
#1 US0_CLK #0
US0_CS #31
TIM0_CDTI0 #31
TIM0_CDTI1 #30
TIM0_CDTI2 #29
TIM1_CC0 #2
TIM1_CC1 #1
TIM1_CC2 #0
TIM1_CC3 #31 LE-
TIM0_OUT0 #2 LE-
TIM0_OUT1 #1
PCNT0_S0IN #2
PCNT0_S1IN #1
US0_CTS #30
US0_RTS #29
US1_TX #2 US1_RX
#1 US1_CLK #0
US1_CS #31
FRC_DCLK #2
FRC_DOUT #1
PRS_CH6 #2
PRS_CH7 #1
PRS_CH8 #0
PRS_CH9 #10
ACMP0_O #2
ACMP1_O #2
FRC_DFRAME #0
MODEM_DCLK #2
MODEM_DIN #1
MODEM_DOUT #0
MODEM_ANT0 #31
MODEM_ANT1 #30
PA2
BUSDY BUSCX
US1_CTS #30
US1_RTS #29
LEU0_TX #2
LEU0_RX #1
I2C0_SDA #2
I2C0_SCL #1
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #3
TIM0_CC1 #2
TIM0_CC2 #1
US0_TX #3 US0_RX
#2 US0_CLK #1
US0_CS #0
TIM0_CDTI0 #0
TIM0_CDTI1 #31
TIM0_CDTI2 #30
TIM1_CC0 #3
TIM1_CC1 #2
TIM1_CC2 #1
TIM1_CC3 #0 LE-
TIM0_OUT0 #3 LE-
TIM0_OUT1 #2
PCNT0_S0IN #3
PCNT0_S1IN #2
US0_CTS #31
US0_RTS #30
US1_TX #3 US1_RX
#2 US1_CLK #1
US1_CS #0
FRC_DCLK #3
FRC_DOUT #2
PRS_CH6 #3
PRS_CH7 #2
PRS_CH8 #1
PRS_CH9 #0
ACMP0
ACMP1_O #3
GPIO_EM4WU8
FRC_DFRAME #1
MODEM_DCLK #3
MODEM_DIN #2
MODEM_DOUT #1
MODEM_ANT0 #0
MODEM_ANT1 #31
PA3
BUSCY BUSDX
US1_CTS #31
US1_RTS #30
LEU0_TX #3
LEU0_RX #2
I2C0_SDA #3
I2C0_SCL #2
TIM0_CC0 #4
TIM0_CC1 #3
TIM0_CC2 #2
US0_TX #4 US0_RX
#3 US0_CLK #2
US0_CS #1
TIM0_CDTI0 #1
TIM0_CDTI1 #0
TIM0_CDTI2 #31
TIM1_CC0 #4
TIM1_CC1 #3
TIM1_CC2 #2
TIM1_CC3 #1 LE-
TIM0_OUT0 #4 LE-
TIM0_OUT1 #3
PCNT0_S0IN #4
PCNT0_S1IN #3
US0_CTS #0
FRC_DCLK #4
F
_DOUT #3
US0_RTS #31
US1_TX #4 US1_RX
#3 US1_CLK #2
US1_CS #1
PRS_CH6 #4
PRS_CH7 #3
PRS_CH8 #2
PRS_CH9 #1
ACMP0_O #4
ACMP1_O #4
FRC_DFRAME #2
MODEM_DCLK #4
MODEM_DIN #3
MODEM_DOUT #2
MODEM_ANT0 #1
MODEM_ANT1 #0
PA4
BUSDY BUSCX
BUSCY BUSDX
BUSCY BUSDX
US1_CTS #0
US1_RTS #31
LEU0_T
LEU0_RX #3
I2C0_SDA #4
I2C0_SCL #3
TIM0_CC0 #5
TIM0_CC1 #4
TIM0_CC2 #3
TIM0_CDT
TIM0_CDTI1
TIM0_CDTI2 #0
TI
1_CC0 #5
TX #5 US0_RX
#4 US0_CLK #3
US0_CS #2
US0_CTS #1
US0_RTS #0
US1_TX #5 US1_RX
#4 US1_CLK #3
US1_CS #2
FRC_DCLK #5
FRC_DOUT #4
PRS_CH6 #5
PRS_CH7 #4
PRS_CH8 #3
PRS_CH9 #2
ACMP0_O #5
ACMP1_O #5
FRC_DFRAME #3
MODEM_DCLK #5
MODEM_DIN #4
MODEM_DOUT #3
MODEM_ANT0 #2
MODEM_ANT1 #1
PA5
T
M1_CC1 #4
TIM1_CC2 #3
US1_CTS #1
US1_RTS #0
LEU0_TX #5
LEU0_RX #4
I2C0_SDA #5
I2C0_SCL #4
TIM1_CC3 #2 LE-
TIM0_OUT0 #5 LE-
TIM0_OUT1 #4
PCNT0_S0IN #5
PCNT0_S1IN #4
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
US0_TX #6 US0_RX
#5 US0_CLK #4
US0_CS #3
US0_CTS #2
US0_RTS #1
US1_TX #6 US1_RX
#5 US1_CLK #4
US1_CS #3
FRC_DCLK #6
FRC_DOUT #5
PRS_CH6 #6
PRS_CH7 #5
PRS_CH8 #4
PRS_CH9 #3
ACMP0_O #6
ACMP1_O #6
FRC_DFRAME #4
MODEM_DCLK #6
MODEM_DIN #5
MODEM_DOUT #4
MODEM_ANT0 #3
MODEM_ANT1 #2
PB11
TIM1_CC1 #5
TIM1_CC2 #4
US1_CTS #2
US1_RTS #1
LEU0_TX #6
LEU0_RX #5
I2C0_SDA #6
I2C0_SCL #5
TIM1_CC3 #3 LE-
TIM0_OUT0 #6 LE-
TIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CC2 #5
US0_TX #7 US0_RX
#6 US0_CLK #5
US0_CS #4
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7
TIM1_CC1 #6
TIM1_CC2 #5
TIM1_CC3 #4 LE-
TIM0_OUT0 #7 LE-
TIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
US0_CTS #3
US0_RTS #2
US1_TX #7 US1_RX
#6 US1_CLK #5
US1_CS #4
FRC_DCLK #7
FRC_DOUT #6
PRS_CH6 #7
PRS_CH7 #6
PRS_CH8 #5
PRS_CH
4
ACMP0_
7
ACMP1_O #7
FRC_DFRAME #5
MODEM_DCLK #7
MODEM_DIN #6
MODEM_DOUT #5
MODEM_ANT0 #4
MODEM_ANT1 #3
PB12
BUSDY BUSCX
US1_CTS #3
US1_RTS #2
LEU0_TX #7
LEU0_RX #6
I2C0_SDA #7
I2C0_SCL #6
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
US0_TX #8 US0_RX
#7 US0_CLK #6
US0_CS #5
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
TIM1_CC1 #7
TIM1_CC2 #6
TIM1_CC3 #5 LE-
TIM0_OUT0 #8 LE-
TIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
US0_CTS #4
US0_RTS #3
US1_TX #8 US1_RX
#7 US1_CLK #6
US1_CS #5
FRC_DCLK #8
F
_DOUT #7
PRS_CH6 #8
PRS_CH7 #7
PRS_CH8 #6
PRS_CH9 #5
ACMP0_O #8
ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
FRC_DFRAME #6
MODEM_DCLK #8
MODEM_DIN #7
MODEM_DOUT #6
MODEM_ANT0 #5
MODEM_ANT1 #4
PB13
BUSCY BUSDX
US1_CTS #4
US1_RTS #3
LEU0_T
LEU0_RX #7
I2C0_SDA #8
I2C0_SCL #7
TIM0_CC0 #9
TIM0_CC1 #8
TIM0_CC2 #7
TX #9 US0_RX
#8 US0_CLK #7
US0_CS #6
TIM0_CDT
TIM0_CDTI1
TIM0_CDTI2 #4
TI
1_CC0 #9
T
M1_CC1 #8
TIM1_CC2 #7
TIM1_CC3 #6 LE-
TIM0_OUT0 #9 LE-
TIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
US0_CTS #5
US0_RTS #4
US1_TX #9 US1_RX
#8 US1_CLK #7
US1_CS #6
FRC_DCLK #9
FRC_DOUT #8
CMU_CLK1 #1
PRS_CH6 #9
PRS_CH7 #8
PRS_CH8 #7
PRS_CH9 #6
ACMP0_O #9
ACMP1_O #9
FRC_DFRAME #7
MODEM_DCLK #9
MODEM_DIN #8
MODEM_DOUT #7
MODEM_ANT0 #6
MODEM_ANT1 #5
BUSDY BUSCX
LFXTAL_N
PB14
US1_CTS #5
US1_RTS #4
LEU0_TX #9
LEU0_RX #8
I2C0_SDA #9
I2C0_SCL #8
US0_TX #10
US0_RX #9
US0_CLK #8
US0_CS #7
TIM0_CC0 #10
TIM0_CC1 #9
TIM0_CC2 #8
TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9
US0_CTS #6
US0_RTS #5
US1_TX #10
US1_RX #9
US1_CLK #8
US1_CS #7
US1_CTS #6
US1_RTS #5
LEU0_TX #10
LEU0_RX #9
I2C0_SDA #10
I2C0_SCL #9
FRC_DCLK #10
FRC_DOUT #9
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9
PRS_CH8 #8
PRS_CH9 #7
ACMP0_O #10
ACMP1_O #10
FRC_DFRAME #8
MODEM_DCLK #10
MODEM_DIN #9
MODEM_DOUT #8
MODEM_ANT0 #7
MODEM_ANT1 #6
BUSCY BUSDX
LFXTAL_P
B15
TIM1_CC2 #8
TIM1_CC3 #7 LE-
TIM0_OUT0 #10 LE-
TIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #11
US0_RX #10
US0_CLK #9
US0_CS #8
TIM0_CC0 #11
TIM0_CC1 #10
TIM0_CC2 #9
TIM0_CDTI0 #8
TIM0_CDTI1 #7
TIM0_CDTI2 #6
TIM1_CC0 #11
TIM1_CC1 #10
TIM1_CC2 #9
TIM1_CC3 #8 LE-
TIM0_OUT0 #11 LE-
TIM0_OUT1 #10
PCNT0_S0IN #11
PCNT0_S1IN #10
US0_CTS #7
US0_RTS #6
US1_TX #11
US1_RX #10
US1_CLK #9
US1_CS #8
US1_CTS #7
US1_RTS #6
LEU0_TX #11
LEU0_RX #10
I2C0_SDA #11
I2C0_SCL #10
FRC_DCLK #11
FRC_DOUT #10
CMU_CLK0 #2
PRS_CH0 #8
PRS_CH9 #11
PRS_CH
0
PRS_CH11 #5
ACMP0_O #11
ACMP1_O #11
FRC_DFRAME #9
MODEM_DCLK #11
MODEM_DIN #10
MODEM_DOUT #9
MODEM_ANT0 #8
MODEM_ANT1 #7
PC6
BUSBY BUSAX
US0_TX #12
US0_RX #11
US0_CLK #10
US0_CS #9
US0_CTS #8
US0_RTS #7
US1_TX #12
US1_RX #11
US1_CL
US1_CS #9
US1_CTS #8
US1_RTS #7
LEU0_TX #12
EU0_RX #11
I2C0_SDA #12
I2C0_SCL #11
TIM0_CC0 #12
TIM0_CC1 #11
TIM0_CC2 #10
TIM0_CDTI0 #9
TIM0_CDTI1 #8
TIM0_CDTI2 #7
TIM1_CC0 #12
TIM1_CC1 #11
TIM1_CC2 #10
TIM1_CC3 #9 LE-
TIM0_OUT0 #12 LE-
TIM0_OUT1 #11
PCNT0_S0IN #12
PCNT0_S1IN #1
FRC_DCLK #12
FRC_DOUT #11
CMU_CLK1 #2
PRS_CH0 #9
PRS_CH9 #12
PRS_CH10 #1
PRS_CH11 #0
ACMP0_O #12
ACMP1_O #12
FRC_DFRAME #10
MODEM_DCLK #12
MODEM_DIN #11
MODEM_DOUT #10
MODEM_ANT0 #9
MODEM_ANT1 #8
PC7
BUSAY BUSBX
US0_TX #13
US0_RX #12
US0_CLK #11
US0_CS #10
US0_CTS #9
US0_RTS #8
US1_TX #13
US1_RX #12
US1_CLK #11
US1_CS #10
US1_CTS #9
US1_RTS #8
LEU0_TX #13
LEU0_RX #12
I2C0_SDA #13
I2C0_SCL #12
TIM0_CC0 #13
TI
_CC1 #12
T
0_CC2 #11
TIM0_CDTI0 #10
TIM0_CDTI1 #9
TIM0_CDTI2 #8
TIM1_CC0 #13
FRC_DCLK #13
FRC_DOUT #12
PRS_CH0 #10
PRS_CH9 #13
PRS_CH10 #2
PRS_CH11 #1
ACMP0_O #13
ACMP1_O #13
FRC_DFRAME #11
MODEM_DCLK #13
MODEM_DIN #12
MODEM_DOUT #11
MODEM_ANT0 #10
MODEM_ANT1 #9
PC8
BUSBY BUSAX
TIM1_CC1 #12
TIM1_CC2 #11
TIM1_CC3 #10 LE-
TIM0_OUT0 #13 LE-
TIM0_OUT1 #12
PCNT0_S0IN #13
PCNT0_S1IN #12
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #14
US0_RX #13
US0_CLK #12
US0_CS #11
US0_CTS #10
US0_RTS #9
US1_TX #14
US1_RX #13
US1_CLK #12
US1_CS #11
US1_CTS #10
US1_RTS #9
LEU0_TX #14
LEU0_RX #13
I2C0_SDA #14
I2C0_SCL #13
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CC2 #12
TIM0_CDTI0 #11
TIM0_CDTI1 #10
TIM0_CDTI2 #9
TIM1_CC0 #14
FRC_DCLK #14
FRC_DOUT #13
PRS_CH0 #11
PRS_CH9 #14
PRS_CH
#3
PRS_CH
2
ACMP0_O #14
ACMP1_O #14
FRC_DFRAME #12
MODEM_DCLK #14
MODEM_DIN #13
MODEM_DOUT #12
MODEM_ANT0 #11
MODEM_ANT1 #10
PC9
BUSAY BUSBX
TIM1_CC1 #13
TIM1_CC2 #12
TIM1_CC3 #11 LE-
TIM0_OUT0 #14 LE-
TIM0_OUT1 #13
PCNT0_S0IN #14
PCNT0_S1IN #13
US0_TX #15
US0_RX #14
US0_CLK #13
US0_CS #12
US0_CTS #11
US0_RTS #10
US1_TX #15
US1_RX #14
US1_CL
US1_CS #12
US1_CTS #11
US1_RTS #10
LEU0_TX #15
EU0_RX #14
I2C0_SDA #15
I2C0_SCL #14
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
FRC_DCLK #15
FRC_DOUT #14
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
GPIO_EM4WU12
FRC_DFRAME #13
MODEM_DCLK #15
MODEM_DIN #14
MODEM_DOUT #13
MODEM_ANT0 #12
MODEM_ANT1 #11
PC10
BUSBY BUSAX
TIM1_CC1 #14
TIM1_CC2 #13
TIM1_CC3 #12 LE-
TIM0_OUT0 #15 LE-
TIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #1
US0_TX #16
US0_RX #15
US0_CLK #14
US0_CS #13
US0_CTS #12
US0_RTS #11
US1_TX #16
US1_RX #15
US1_CLK #14
US1_CS #13
US1_CTS #12
US1_RTS #11
LEU0_TX #16
LEU0_RX #15
I2C0_SDA #16
I2C0_SCL #15
TIM0_CC0 #16
TI
_CC1 #15
T
0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
FRC_DCLK #16
FRC_DOUT #15
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
FRC_DFRAME #14
MODEM_DCLK #16
MODEM_DIN #15
MODEM_DOUT #14
MODEM_ANT0 #13
MODEM_ANT1 #12
PC11
BUSAY BUSBX
TIM1_CC1 #15
TIM1_CC2 #14
TIM1_CC3 #13 LE-
TIM0_OUT0 #16 LE-
TIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #17
US0_RX #16
US0_CLK #15
US0_CS #14
US0_CTS #13
US0_RTS #12
US1_TX #17
US1_RX #16
US1_CLK #15
US1_CS #14
US1_CTS #13
US1_RTS #12
LEU0_TX #17
LEU0_RX #16
I2C0_SDA #17
I2C0_SCL #16
TIM0_CC0 #17
TIM0_CC1 #16
TIM0_CC2 #15
TIM0_CDTI0 #14
TIM0_CDTI1 #13
TIM0_CDTI2 #12
TIM1_CC0 #17
FRC_DCLK #17
FRC_DOUT #16
CMU_CLK0 #4
PRS_CH3 #8
PRS_CH4 #0
PRS_C
PRS_CH6 #11
ACMP0_O #17
ACMP1_O #17
FRC_DFRAME #15
MODEM_DCLK #17
MODEM_DIN #16
MODEM_DOUT #15
MODEM_ANT0 #14
MODEM_ANT1 #13
PD9
BUSCY BUSDX
TIM1_CC1 #16
TIM1_CC2 #15
TIM1_CC3 #14 LE-
TIM0_OUT0 #17 LE-
TIM0_OUT1 #16
PCNT0_S0IN #17
PCNT0_S1IN #16
US0_TX #18
US0_RX #17
US0_CLK #16
US0_CS #15
US0_CTS #14
US0_RTS #13
US1_TX #18
US1_RX #17
US1_CL
US1_CS #15
US1_CTS #14
US1_RTS #13
LEU0_TX #18
EU0_RX #17
I2C0_SDA #18
I2C0_SCL #17
TIM0_CC0 #18
TIM0_CC1 #17
TIM0_CC2 #16
TIM0_CDTI0 #15
TIM0_CDTI1 #14
TIM0_CDTI2 #13
TIM1_CC0 #18
FRC_DCLK #18
FRC_DOUT #17
CMU_CLK1 #4
PRS_CH3 #9
PRS_CH4 #1
PRS_CH5 #0
PRS_CH6 #12
ACMP0_O #18
ACMP1_O #18
FRC_DFRAME #16
MODEM_DCLK #18
MODEM_DIN #17
MODEM_DOUT #16
MODEM_ANT0 #15
MODEM_ANT1 #14
PD10
BUSDY BUSCX
TIM1_CC1 #17
TIM1_CC2 #16
TIM1_CC3 #15 LE-
TIM0_OUT0 #18 LE-
TIM0_OUT1 #17
PCNT0_S0IN #18
PCNT0_S1IN #1
US0_TX #19
US0_RX #18
US0_CLK #17
US0_CS #16
US0_CTS #15
US0_RTS #14
US1_TX #19
US1_RX #18
US1_CLK #17
US1_CS #16
US1_CTS #15
US1_RTS #14
LEU0_TX #19
LEU0_RX #18
I2C0_SDA #19
I2C0_SCL #18
TIM0_CC0 #19
TI
_CC1 #18
T
0_CC2 #17
TIM0_CDTI0 #16
TIM0_CDTI1 #15
TIM0_CDTI2 #14
TIM1_CC0 #19
FRC_DCLK #19
FRC_DOUT #18
PRS_CH3 #10
PRS_CH4 #2
PRS_CH5 #1
PRS_CH6 #13
ACMP0_O #19
ACMP1_O #19
FRC_DFRAME #17
MODEM_DCLK #19
MODEM_DIN #18
MODEM_DOUT #17
MODEM_ANT0 #16
MODEM_ANT1 #15
PD11
BUSCY BUSDX
TIM1_CC1 #18
TIM1_CC2 #17
TIM1_CC3 #16 LE-
TIM0_OUT0 #19 LE-
TIM0_OUT1 #18
PCNT0_S0IN #19
PCNT0_S1IN #18
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #20
US0_RX #19
US0_CLK #18
US0_CS #17
US0_CTS #16
US0_RTS #15
US1_TX #20
US1_RX #19
US1_CLK #18
US1_CS #17
US1_CTS #16
US1_RTS #15
LEU0_TX #20
LEU0_RX #19
I2C0_SDA #20
I2C0_SCL #19
TIM0_CC0 #20
TIM0_CC1 #19
TIM0_CC2 #18
TIM0_CDTI0 #17
TIM0_CDTI1 #16
TIM0_CDTI2 #15
TIM1_CC0 #20
FRC_DCLK #20
FRC_DOUT #19
PRS_CH3 #11
PRS_CH4 #3
PRS_CH
2
PRS_CH
4
ACMP0_O #20
ACMP1_O #20
FRC_DFRAME #18
MODEM_DCLK #20
MODEM_DIN #19
MODEM_DOUT #18
MODEM_ANT0 #17
MODEM_ANT1 #16
PD12
BUSDY BUSCX
TIM1_CC1 #19
TIM1_CC2 #18
TIM1_CC3 #17 LE-
TIM0_OUT0 #20 LE-
TIM0_OUT1 #19
PCNT0_S0IN #20
PCNT0_S1IN #19
US0_TX #21
US0_RX #20
US0_CLK #19
US0_CS #18
US0_CTS #17
US0_RTS #16
US1_TX #21
US1_RX #20
US1_CL
US1_CS #18
US1_CTS #17
US1_RTS #16
LEU0_TX #21
EU0_RX #20
I2C0_SDA #21
I2C0_SCL #20
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
FRC_DCLK #21
FRC_DOUT #20
PRS_CH3 #12
PRS_CH4 #4
PRS_CH5 #3
PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
FRC_DFRAME #19
MODEM_DCLK #21
MODEM_DIN #20
MODEM_DOUT #19
MODEM_ANT0 #18
MODEM_ANT1 #17
PD13
BUSCY BUSDX
TIM1_CC1 #20
TIM1_CC2 #19
TIM1_CC3 #18 LE-
TIM0_OUT0 #21 LE-
TIM0_OUT1 #20
PCNT0_S0IN #21
PCNT0_S1IN #2
US0_TX #22
US0_RX #21
US0_CLK #20
US0_CS #19
US0_CTS #18
US0_RTS #17
US1_TX #22
US1_RX #21
US1_CLK #20
US1_CS #19
US1_CTS #18
US1_RTS #17
LEU0_TX #22
LEU0_RX #21
I2C0_SDA #22
I2C0_SCL #21
TIM0_CC0 #22
TI
_CC1 #21
T
0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
FRC_DCLK #22
FRC_DOUT #21
CMU_CLK0 #5
PRS_CH3 #13
PRS_CH4 #5
FRC_DFRAME #20
MODEM_DCLK #22
MODEM_DIN #21
MODEM_DOUT #20
MODEM_ANT0 #19
MODEM_ANT1 #18
PRS_CH5 #4
PD14
BUSDY BUSCX
TIM1_CC1 #21
TIM1_CC2 #20
PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
GPIO_EM4WU4
TIM1_CC3 #19 LE-
TIM0_OUT0 #22 LE-
TIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #23
US0_RX #22
US0_CLK #21
US0_CS #20
US0_CTS #19
US0_RTS #18
US1_TX #23
US1_RX #22
US1_CLK #21
US1_CS #20
US1_CTS #19
US1_RTS #18
LEU0_TX #23
LEU0_RX #22
I2C0_SDA #23
I2C0_SCL #22
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
FRC_DCLK #23
FRC_DOUT #22
CMU_CLK1 #5
PRS_CH3 #14
PRS_CH4 #6
PRS_CH
5
PRS_CH
7
ACMP0_O #23
ACMP1_O #23
BG_SWO #2
FRC_DFRAME #21
MODEM_DCLK #23
MODEM_DIN #22
MODEM_DOUT #21
MODEM_ANT0 #20
MODEM_ANT1 #19
PD15
BUSCY BUSDX
TIM1_CC1 #22
TIM1_CC2 #21
TIM1_CC3 #20 LE-
TIM0_OUT0 #23 LE-
TIM0_OUT1 #22
PCNT0_S0IN #23
PCNT0_S1IN #22
US0_TX #24
US0_RX #23
US0_CLK #22
US0_CS #21
US0_CTS #20
US0_RTS #19
US1_TX #24
US1_RX #23
US1_CL
US1_CS #21
US1_CTS #20
US1_RTS #19
LEU0_TX #24
EU0_RX #23
I2C0_SDA #24
I2C0_SCL #23
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
FRC_DCLK #24
FRC_DOUT #23
PRS_CH0 #0
PRS_CH1 #7
PRS_CH2 #6
FRC_DFRAME #22
MODEM_DCLK #24
MODEM_DIN #23
MODEM_DOUT #22
MODEM_ANT0 #21
MODEM_ANT1 #20
PF0
BUSBY BUSAX
PRS_CH3 #5
TIM1_CC1 #23
TIM1_CC2 #22
ACMP0_O #24
ACMP1_O #24
DBG_SWCLKTCK
TIM1_CC3 #21 LE-
TIM0_OUT0 #24 LE-
TIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #2
US0_TX #25
US0_RX #24
US0_CLK #23
US0_CS #22
US0_CTS #21
US0_RTS #20
US1_TX #25
US1_RX #24
US1_CLK #23
US1_CS #22
US1_CTS #21
US1_RTS #20
LEU0_TX #25
LEU0_RX #24
I2C0_SDA #25
I2C0_SCL #24
TIM0_CC0 #25
TI
_CC1 #24
T
0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
FRC_DCLK #25
FRC_DOUT #24
PRS_CH0 #1
PRS_CH1 #0
PRS_CH2 #7
FRC_DFRAME #23
MODEM_DCLK #25
MODEM_DIN #24
MODEM_DOUT #23
MODEM_ANT0 #22
MODEM_ANT1 #21
PF1
BUSAY BUSBX
PRS_CH3 #6
TIM1_CC1 #24
TIM1_CC2 #23
ACMP0_O #25
ACMP1_O #25
DBG_SWDIOTMS
TIM1_CC3 #22 LE-
TIM0_OUT0 #25 LE-
TIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #26
US0_RX #25
US0_CLK #24
US0_CS #23
US0_CTS #22
US0_RTS #21
US1_TX #26
US1_RX #25
US1_CLK #24
US1_CS #23
US1_CTS #22
US1_RTS #21
LEU0_TX #26
LEU0_RX #25
I2C0_SDA #26
I2C0_SCL #25
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
CMU_CLK0 #6
PRS_CH0 #2
PRS_CH1 #1
PRS_CH2 #0
PRS_CH
7
ACMP0_
6
ACMP1_O #26
DBG_TDO
FRC_DCLK #26
FRC_DOUT #25
FRC_DFRAME #24
MODEM_DCLK #26
MODEM_DIN #25
MODEM_DOUT #24
MODEM_ANT0 #23
MODEM_ANT1 #22
PF2
BUSBY BUSAX
TIM1_CC1 #25
TIM1_CC2 #24
TIM1_CC3 #23 LE-
TIM0_OUT0 #26 LE-
TIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
BG_SWO #0
GPIO_EM4WU0
US0_TX #27
US0_RX #26
US0_CLK #25
US0_CS #24
US0_CTS #23
US0_RTS #22
US1_TX #27
US1_RX #26
US1_CL
US1_CS #24
US1_CTS #23
US1_RTS #22
LEU0_TX #27
EU0_RX #26
I2C0_SDA #27
I2C0_SCL #26
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
FRC_DCLK #27
FRC_DOUT #26
CMU_CLK1 #6
PRS_CH0 #3
PRS_CH1 #2
PRS_CH2 #1
PRS_CH3 #0
ACMP0_O #27
ACMP1_O #27
DBG_TDI
FRC_DFRAME #25
MODEM_DCLK #27
MODEM_DIN #26
MODEM_DOUT #25
MODEM_ANT0 #24
MODEM_ANT1 #23
PF3
BUSAY BUSBX
TIM1_CC1 #26
TIM1_CC2 #25
TIM1_CC3 #24 LE-
TIM0_OUT0 #27 LE-
TIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #2
US0_TX #28
US0_RX #27
US0_CLK #26
US0_CS #25
US0_CTS #24
US0_RTS #23
US1_TX #28
US1_RX #27
US1_CLK #26
US1_CS #25
US1_CTS #24
US1_RTS #23
LEU0_TX #28
LEU0_RX #27
I2C0_SDA #28
I2C0_SCL #27
TIM0_CC0 #28
TI
_CC1 #27
T
0_CC2 #26
TIM0_CDTI0 #25
TIM0_CDTI1 #24
TIM0_CDTI2 #23
TIM1_CC0 #28
FRC_DCLK #28
FRC_DOUT #27
PRS_CH0 #4
PRS_CH1 #3
PRS_CH2 #2
PRS_CH3 #1
ACMP0_O #28
ACMP1_O #28
FRC_DFRAME #26
MODEM_DCLK #28
MODEM_DIN #27
MODEM_DOUT #26
MODEM_ANT0 #25
MODEM_ANT1 #24
PF4
BUSBY BUSAX
TIM1_CC1 #27
TIM1_CC2 #26
TIM1_CC3 #25 LE-
TIM0_OUT0 #28 LE-
TIM0_OUT1 #27
PCNT0_S0IN #28
PCNT0_S1IN #27
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
GPIO Name
Pin Alternate Functionality / Description
Analog
Timers
Communication
Radio
Other
US0_TX #29
US0_RX #28
US0_CLK #27
US0_CS #26
US0_CTS #25
US0_RTS #24
US1_TX #29
US1_RX #28
US1_CLK #27
US1_CS #26
US1_CTS #25
US1_RTS #24
LEU0_TX #29
LEU0_RX #28
I2C0_SDA #29
I2C0_SCL #28
TIM0_CC0 #29
TIM0_CC1 #28
TIM0_CC2 #27
TIM0_CDTI0 #26
TIM0_CDTI1 #25
TIM0_CDTI2 #24
TIM1_CC0 #29
FRC_DCLK #29
FRC_DOUT #28
PRS_CH0 #5
PRS_CH1 #4
PRS_CH
3
PRS_CH
2
ACMP0_O #29
ACMP1_O #29
FRC_DFRAME #27
MODEM_DCLK #29
MODEM_DIN #28
MODEM_DOUT #27
MODEM_ANT0 #26
MODEM_ANT1 #25
PF5
BUSAY BUSBX
TIM1_CC1 #28
TIM1_CC2 #27
TIM1_CC3 #26 LE-
TIM0_OUT0 #29 LE-
TIM0_OUT1 #28
PCNT0_S0IN #29
PCNT0_S1IN #28
US0_TX #30
US0_RX #29
US0_CLK #28
US0_CS #27
US0_CTS #26
US0_RTS #25
US1_TX #30
US1_RX #29
US1_CL
US1_CS #27
US1_CTS #26
US1_RTS #25
LEU0_TX #30
EU0_RX #29
I2C0_SDA #30
I2C0_SCL #29
TIM0_CC0 #30
TIM0_CC1 #29
TIM0_CC2 #28
TIM0_CDTI0 #27
TIM0_CDTI1 #26
TIM0_CDTI2 #25
TIM1_CC0 #30
FRC_DCLK #30
FRC_DOUT #29
CMU_CLK1 #7
PRS_CH0 #6
PRS_CH1 #5
PRS_CH2 #4
PRS_CH3 #3
ACMP0_O #30
ACMP1_O #30
FRC_DFRAME #28
MODEM_DCLK #30
MODEM_DIN #29
MODEM_DOUT #28
MODEM_ANT0 #27
MODEM_ANT1 #26
PF6
BUSBY BUSAX
TIM1_CC1 #29
TIM1_CC2 #28
TIM1_CC3 #27 LE-
TIM0_OUT0 #30 LE-
TIM0_OUT1 #29
PCNT0_S0IN #30
PCNT0_S1IN #2
US0_TX #31
US0_RX #30
US0_CLK #29
US0_CS #28
US0_CTS #27
US0_RTS #26
US1_TX #31
US1_RX #30
US1_CLK #29
US1_CS #28
US1_CTS #27
US1_RTS #26
LEU0_TX #31
LEU0_RX #30
I2C0_SDA #31
I2C0_SCL #30
TIM0_CC0 #31
TI
_CC1 #30
T
0_CC2 #29
TIM0_CDTI0 #28
TIM0_CDTI1 #27
TIM0_CDTI2 #26
TIM1_CC0 #31
FRC_DCLK #31
FRC_DOUT #30
CMU_CLK0 #7
PRS_CH0 #7
PRS_CH1 #6
PRS_CH2 #5
PRS_CH3 #4
ACMP0_O #31
ACMP1_O #31
GPIO_EM4WU1
FRC_DFRAME #29
MODEM_DCLK #31
MODEM_DIN #30
MODEM_DOUT #29
MODEM_ANT0 #28
MODEM_ANT1 #27
PF7
BUSAY BUSBX
TIM1_CC1 #30
TIM1_CC2 #29
TIM1_CC3 #28 LE-
TIM0_OUT0 #31 LE-
TIM0_OUT1 #30
PCNT0_S0IN #31
PCNT0_S1IN #30
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
6.6 Alternate
Functionality Overview
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-
nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO
pin. Refer to
6.5 GPIO Functionality Table
for a list of functions available on each GPIO pin.
Note:
Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 6.6.
Alternate Functionality Overview
Alternate
LOCATION
12 – 15
16 – 19
16: PC11
20: PD12
24: PF0
Functionality
0 – 3
4 – 7
8 – 11
20 – 23
24 – 27
28 – 31
Description
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
12: PC7
13: PC8
28:
29:
30: PF
31: PF7
Analog comparator
ACMP0, digital out-
put.
17: PD9
21: PD13
25: PF1
18: PD10
22: PD14
26: PF2
15: PC10
19: PD11
23: PD15
27: PF3
ACMP0_O
10: PB15
14: PC9
11: PC6
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PC9
11: PC6
12: PC7
13: PC8
16: PC11
20: PD12
24: PF0
17: PD9
21: PD13
25:
1
18: PD10
22: PD14
26: PF2
15: PC10
19: PD11
23: PD
5 27
PF3
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP1, digital out-
put.
ACMP1_O
0: PA0
Analog to digital
converter ADC0 ex-
ternal reference in-
put negative pin.
ADC0_EXTN
ADC0_EXTP
CMU_CLK0
CMU_CLK1
0: PA1
Analog to digital
converter ADC0 ex-
ternal reference in-
put positive pin.
0: PA1
4: PD9
5: PD14
6: PF2
7: PF7
Clock Management
Unit, clock output
number 0.
1: PB15
2: PC6
3: PC11
0: PA0
4: PD10
5: PD15
6: PF3
Clock Management
Unit, clock output
number 1.
1: PB14
2: PC7
3: PC10
7: PF6
0: PF0
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
DBG_SWCLKTCK
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull down.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 – 15
16 – 19
Functionality
0 – 3
4 – 7
8 – 11
20 – 23
24 – 27
28 – 31
Description
0: PF1
Debug-interface
Serial Wire data in-
put / output and
JTAG Test Mode
Select.
DBG_SWDIOTMS
Note that this func-
tion is enab
d to
the pin ou
set,
and has a built-in
pull up.
0: PF2
ebug-interface
Serial Wire viewer
Output.
1: PB13
2: PD15
3: PC11
Note that this func-
tion is not enabled
after reset, and
must be enabled by
software to be
used.
DBG_SWO
0: PF3
Debug-interface
JTAG Test Data In.
Note that this func-
tion becomes avail-
able after the first
valid JTAG com-
mand is received,
and has a built-in
pull up when JTAG
is active.
DBG_TDI
0: PF2
Debug-interface
JTAG Test Data
Out.
Note that this func-
tion becomes avail-
able after the first
valid JTAG com-
mand is received.
DBG_TDO
0: PA0
1: PA1
2: PA2
PA3
: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PC9
12: PC7
13: PC8
16: PC11
20: PD12
24: PF0
17: PD9
21: PD13
25: PF1
18: PD10
22: PD14
26: PF2
15: PC10
19: PD11
23: PD15
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Frame Controller,
Data Sniffer Clock.
FRC_DCLK
11: PC6
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10
20: PD14
24: PF2
13: PC10
17: PD11
21: PD15
25: PF3
28: PF6
29: PF7
30: PA0
31: PA1
Frame Controller,
Data Sniffer Frame
active
FRC_DFRAME
FRC_DOUT
14: PC11
18: PD12
22: PF0
26: PF4
27: PF5
15: PD9
19: PD13
23: PF1
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
20: PD13
24: PF1
17: PD10
21: PD14
25: PF2
28: PF5
29: PF6
30: PF7
31: PA0
Frame Controller,
Data Sniffer Out-
put.
5: PB11
6: PB12
7: PB13
14: PC10
18: PD11
22: PD15
26: PF3
15: PC11
19: PD12
23: PF0
27: PF4
0: PF2
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU0
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 – 3
4 – 7
8 – 11
12 – 15
16 – 19
20 – 23
24 – 27
28 – 31
Description
0: PF7
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU1
GPIO_EM4WU4
GPIO_EM4WU8
GPIO_EM4WU9
GPIO_EM4WU12
I2C0_SCL
0: PD14
0: PA3
Pin can be used to
wake the system
up from E
Pin can be used to
ke the system
p from EM4
0: PB13
0: PC10
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10
PD14 25:
PF2
20: PD13
24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
I2C0 Serial Clock
Line input / output.
14: PC10
18: PD11
22: PD15
26: PF3
15: PC11
19: PD12
23: PF0
27: PF4
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PC
12: PC7
13: PC8
6: PC11
20: PD12
24: PF0
PD9 21:
PD13 25:
PF1
18: PD10
22: PD14
26: PF2
15: P
10 19:
PD11 23:
PD15 27:
PF3
28: PF4
29: PF5
30: PF6
31: PF7
I2C0 Serial Data in-
put / output.
I2C0_SDA
11: PC6
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PC9
1
C7
13: PC8
16: PC11
20: PD12
24: PF0
17: PD9
21: PD13
25: PF1
18: PD10
22: PD14
26: PF2
15: PC10
19: PD11
23: PD15
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Low Energy Timer
LETIM0, output
channel 0.
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
11
C6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
20: PD13
24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Low Energy Timer
LETIM0, output
channel 1.
5: PB11
6: PB12
7: PB13
17: PD10
21: PD14
25: PF2
14: PC10
18: PD11
22: PD15
26: PF3
15: PC11
19: PD12
23: PF0
27: PF4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
20: PD13
24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
: PB11
6: PB12
7: PB13
17: PD10
21: PD14
25: PF2
LEUART0 Receive
input.
14: PC10
18: PD11
22: PD15
26: PF3
15: PC11
19: PD12
23: PF0
27: PF4
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PC9
11: PC6
12: PC7
13: PC8
16: PC11
20: PD12
24: PF0
17: PD9
21: PD13
25: PF1
18: PD10
22: PD14
26: PF2
15: PC10
19: PD11
23: PD15
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
LEUART0 Transmit
output. Also used
as receive input in
half duplex commu-
nication.
LEU0_TX
0: PB14
Low Frequency
Crystal (typically
32.768 kHz) nega-
tive pin. Also used
as an optional ex-
ternal clock input
pin.
LFXTAL_N
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 – 15
16 – 19
Functionality
0 – 3
4 – 7
8 – 11
20 – 23
24 – 27
28 – 31
Description
0: PB15
Low Frequency
Crystal (typically
32.768 kHz) posi-
tive pin.
LFXTAL_P
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
16: PD11
20: PD15
24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
MODEM antenna
control output
,
used for ant
nna
diversity.
13: PC11
17: PD12
21: PF0
14: PD9
18: PD13
22: PF1
15: PD10
19: PD14
23: PF2
25: PF4
26: PF5
27: PF6
MODEM_ANT0
MODEM_ANT1
MODEM_DCLK
MODEM_DIN
MODEM_DOUT
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11
16: PD12
20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31:
MODEM antenna
control output 1,
ed for antenna
diversity.
13: PD9
17: PD13
21: PF1
14: PD10
18: PD14
22: PF2
11: PC10
15: PD11
19: PD15
23: PF3
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PC9
12: PC7
16: PC11
20: PD12
24: PF0
17: PD9
21: PD13
25: PF1
18: PD10
22: PD14
26: PF2
15: PC10
19: PD11
23: PD15
27: PF3
28: P
29: PF5
30: PF6
31: PF7
13: PC8
MODEM data clock
out.
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10
21: PD14
25: PF2
20: PD13
24:
F1
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
MODEM data in.
MODEM data out.
14: PC10
18: PD11
22: PD15
26: PF3
15: PC11
19: PD12
23: PF0
27: PF4
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10
20: PD14
24: PF2
13: PC10
17: PD11
PD15 25:
PF3
28: PF6
29: PF7
30: PA0
31: PA1
14: PC11
18: PD12
22: PF0
26: PF4
27: PF5
15: PD9
19: PD13
23: PF1
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PC
12: PC7
6: PC11
20: PD12
24: PF0
PD9 21:
PD13 25:
PF1
18: PD10
22: PD14
26: PF2
15: P
10 19:
PD11 23:
PD15 27:
PF3
28: PF4
29: PF5
30: PF6
31: PF7
Pulse Counter
PCNT0 input num-
ber 0.
13: PC8
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11
C7
1
C8
13: PC9
16: PD9
17: PD10
21: PD14
25: PF2
20: PD13
24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Pulse Counter
PCNT0 input num-
ber 1.
5: PB11
6: PB12
7: PB13
14: PC10
18: PD11
22: PD15
26: PF3
15: PC11
19: PD12
23: PF0
27: PF4
0: PF0
1: PF1
2: PF2
3: PF3
4: PF4
5: PF5
6: PF6
7: PF7
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
Peripheral Reflex
System PRS, chan-
nel 0.
0: PF1
1: PF2
2: PF3
3: PF4
4: PF5
: PF6
6: PF7
7: PF0
Peripheral Reflex
System PRS, chan-
nel 1.
PRS_CH1
0: PF2
1: PF3
2: PF4
3: PF5
4: PF6
5: PF7
6: PF0
7: PF1
Peripheral Reflex
System PRS, chan-
nel 2.
PRS_CH2
0: PF3
1: PF4
2: PF5
3: PF6
4: PF7
5: PF0
6: PF1
7: PF2
8: PD9
9: PD10
10: PD11
14: PD15
11: PD12
12: PD13
13: PD14
Peripheral Reflex
System PRS, chan-
nel 3.
PRS_CH3
0: PD9
4: PD13
5: PD14
6: PD15
Peripheral Reflex
System PRS, chan-
nel 4.
1: PD10
2: PD11
3: PD12
PRS_CH4
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 – 15
16 – 19
Functionality
0 – 3
4 – 7
8 – 11
20 – 23
24 – 27
28 – 31
Description
0: PD10
1: PD11
2: PD12
3: PD13
4: PD14
5: PD15
6: PD9
Peripheral Reflex
System PRS, chan-
nel 5.
PRS_CH5
PRS_CH6
PRS_CH7
PRS_CH8
PRS_CH9
PRS_CH10
PRS_CH11
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM0_CDTI
TIM0_CDTI1
TIM0_CDTI2
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PD12
12: PD10
16: PD14
13: PD11
17: PD15
Peripheral Reflex
System PRS, chan-
nel 6.
11: PD9
15: PD13
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PA0
Peripheral Reflex
stem PRS, chan-
el 7.
5: PB11
6: PB12
7: PB13
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PA0
10: PA1
Peripheral Reflex
System PRS, chan-
nel 8.
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PA0
9: PA1
10: PA2
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
Peripheral Reflex
System PRS, chan-
nel 9.
0: PC6
1: PC7
2: PC8
3: PC9
4: PC10
5: PC11
Peripheral Reflex
System PRS, chan-
nel 10.
0: PC7
1: PC8
2: PC9
3: PC10
4: PC11
5: PC6
Peripheral Reflex
System PRS, chan-
nel 11.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PC9
1
C7
16: PC11
20: PD12
24: PF0
17: PD9
21: PD13
25: PF1
18: PD10
22: PD14
26: PF2
15: PC10
19: PD11
23: PD15
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Timer 0 Capture
Compare input /
output channel 0.
13: PC8
11
C6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10
21: PD14
25: PF2
20: PD13
24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Timer 0 Capture
Compare input /
output channel 1.
5: PB11
6: PB12
7: PB13
14: PC10
18: PD11
22: PD15
26: PF3
15: PC11
19: PD12
23: PF0
27: PF4
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10
20: PD14
24: PF2
13: PC10
17: PD11
21: PD15
25: PF3
14: PC11
18: PD12
22: PF0
15: PD9
19: PD13
23: PF1
28: PF6
29: PF7
30: PA0
31: PA1
Timer 0 Capture
Compare input /
output channel 2.
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
16: PD11
20: PD15
24: PF3
13: PC11
17: PD12
21: PF0
14: PD9
18: PD13
22: PF1
28: PF7
29: PA0
30: PA1
31: PA2
Timer 0 Compli-
mentary Dead Time
Insertion channel 0.
25: PF4
26: PF5
27: PF6
15: PD10
19: PD14
23: PF2
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11
16: PD12
20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
Timer 0 Compli-
mentary Dead Time
Insertion channel 1.
13: PD9
17: PD13
21: PF1
14: PD10
18: PD14
22: PF2
11: PC10
15: PD11
19: PD15
23: PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
12: PD9
16: PD13
20: PF1
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
Timer 0 Compli-
mentary Dead Time
Insertion channel 2.
1: PB11
2: PB12
3: PB13
13: PD10
17: PD14
21: PF2
10: PC10
14: PD11
18: PD15
22: PF3
11: PC11
15: PD12
19: PF0
23: PF4
silabs.com
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Rev. 1.4
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
Alternate
LOCATION
12 – 15
16 – 19
16: PC11
20: PD12
24: PF0
Functionality
0 – 3
4 – 7
8 – 11
20 – 23
24 – 27
28 – 31
Description
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
12: PC7
13: PC8
28: PF4
29: PF5
30: PF6
31: PF7
Timer 1 Capture
Compare input /
output channel 0.
17: PD9
21: PD13
25: PF1
18: PD10
22: PD14
26: PF2
15: PC10
19: PD11
23: PD15
27: PF3
TIM1_CC0
TIM1_CC1
TIM1_CC2
TIM1_CC3
US0_CLK
US0_CS
10: PB15
14: PC9
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10
21: PD14
25: PF2
20: PD13
24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Timer 1 Capture
Compare input /
output cha
1.
5: PB11
6: PB12
7: PB13
14: PC10
18: PD11
22: PD15
26: PF3
15: PC11
19: PD12
23: PF0
27: PF4
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10
20: PD14
24: PF2
13: PC10
17: PD11
21: PD15
25: PF3
28: PF6
29: PF7
30: PA0
31:
Timer 1 Capture
mpare input /
utput channel 2.
14: PC11
18: PD12
22: PF0
15: PD9
19: PD13
23: PF1
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
16: PD11
20: PD15
24: PF3
28: P
29: PA0
30: PA1
31: PA2
Timer 1 Capture
Compare input /
output channel 3.
13: PC11
17: PD12
21: PF0
14: PD9
18: PD13
22: PF1
15: PD10
19: PD14
23: PF2
25: PF4
26: PF5
27: PF6
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10
20: PD14
24:
F2
28: PF6
29: PF7
30: PA0
31: PA1
13: PC10
17: PD11
21: PD15
25: PF3
USART0 clock in-
put / output.
14: PC11
18: PD12
22: PF0
15: PD9
19: PD13
23: PF1
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
16: PD11
20: PD15
24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
13: PC11
17: PD12
PF0
14: PD9
18: PD13
22: PF1
15: PD10
19: PD14
23: PF2
25: PF4
26: PF5
27: PF6
USART0 chip se-
lect input / output.
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11
6: PD12
20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART0 Clear To
Send hardware
flow control input.
13: PD9
PD13 21:
PF1
US0_CTS
US0_RTS
14: PD
18: PD14
22: PF2
11: PC10
15: P
11 19:
PD15 23:
PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
1
D9
16: PD13
20: PF1
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART0 Request
To Send hardware
flow control output.
1: PB11
2: PB12
3: PB13
13: PD10
17: PD14
21: PF2
10: PC10
14: PD11
18: PD15
22: PF3
11
C11 15:
PD12 19:
PF0 23:
PF4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10
21: PD14
25: PF2
20: PD13
24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
USART0 Asynchro-
nous Receive.
5: PB11
6: PB12
7: PB13
14: PC10
18: PD11
22: PD15
26: PF3
15: PC11
19: PD12
23: PF0
27: PF4
USART0 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US0_RX
0: PA0
: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PC9
12: PC7
13: PC8
16: PC11
20: PD12
24: PF0
17: PD9
21: PD13
25: PF1
18: PD10
22: PD14
26: PF2
15: PC10
19: PD11
23: PD15
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
USART0 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
11: PC6
US0_TX
USART0 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10
20: PD14
24: PF2
28: PF6
29: PF7
30: PA0
31: PA1
13: PC10
17: PD11
21: PD15
25: PF3
14: PC11
18: PD12
22: PF0
15: PD9
19: PD13
23: PF1
USART1 clock in-
put / output.
US1_CLK
26: PF4
27: PF5
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Pin Definitions
Alternate
LOCATION
12 – 15
16 – 19
12: PC10
16: PD11
20: PD15
24: PF3
Functionality
0 – 3
4 – 7
8 – 11
20 – 23
24 – 27
28 – 31
Description
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
28: PF7
29: PA0
30: PA1
31: PA2
13: PC11
17: PD12
21: PF0
14: PD9
18: PD13
22: PF1
25: PF4
26: PF5
27: PF6
USART1 chip se-
lect input / output.
US1_CS
15: PD10
19: PD14
23: PF2
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11
16: PD12
20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART1 Clear To
Send hardware
flow contr
ut.
13: PD9
17: PD13
21: PF1
US1_CTS
US1_RTS
14: PD10
18: PD14
22: PF2
11: PC10
15: PD11
19: PD15
23: PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
12: PD9
16: PD13
20: PF1
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31:
USART1 Request
Send hardware
ow control output.
1: PB11
2: PB12
3: PB13
13: PD10
17: PD14
21: PF2
10: PC10
14: PD11
18: PD15
22: PF3
11: PC11
15: PD12
19: PF0
23: PF4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10
21: PD14
25: PF2
20: PD13
24: PF1
28: P
29: PF6
30: PF7
31: PA0
USART1 Asynchro-
nous Receive.
5: PB11
6: PB12
7: PB13
14: PC10
18: PD11
22: PD15
26: PF3
15: PC11
19: PD12
23: PF0
27: PF4
USART1 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US1_RX
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
14: PC9
11: PC6
12: PC7
13: PC8
16: PC11
20: PD12
24: PF0
17: PD9
21: PD13
25: PF1
18: PD10
22: PD14
26: PF2
15: PC10
19: PD11
PD15 27:
PF3
28: PF4
29: PF5
30: PF6
31: PF7
USART1 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
US1_TX
USART1 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
6.7 Analog
Port (APORT) Client Maps
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal rout-
ing.
Figure 6.5 APORT Connection Diagram on page 130
shows the APORT routing for this device family (note that available features
may vary by part number). A complete description of APORT functionality can be found in the Reference Manual.
PF0
PB15
PF1
1X
2X
3X
4X
PB14
PB13
POS
NE
PF2
1X
2X
3X
4X
POS
NEG
PF3
PF4
ACMP1
1Y
2Y
3Y
4
ACMP0
PB12
1Y
2Y
3Y
4Y
PF5
PF6
PF7
PB11
PA5
PA4
1X
2X
3X
4X
POS
NEG
PA3
PA2
ADC0
1Y
2Y
3Y
4Y
ADC_EXTP
ADC_EXTN
PA1
PA0
EXTP
EXT
PD15
1X
1Y
IDAC0
n
X,
n
Y
ORT
n
X, APORT
n
Y
A
…
BUSAX, BUSB
Y
,
.
..
Figure 6.5.
APORT Connection Diagram
Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the
peripheral’s port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.
In general, enumerations for the pin selection field in an analog peripheral’s register can be determined by finding the desired pin con-
nection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared
bus used by this connection is indicated in the Bus column.
Table 6.7.
ACMP0 Bus and Pin Mapping
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
Table 6.8.
ACMP1 Bus and Pin Mapping
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Pin Definitions
Table 6.9.
ADC0 Bus and Pin Mapping
Table 6.10.
IDAC0 Bus and Pin Mapping
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
QFN48 Package Specifications
7. QFN48
Package Specifications
7.1 QFN48
Package Dimensions
Figure 7.1.
QFN48 Package Drawing
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
QFN48 Package Specifications
Table 7.1.
QFN48 Package Dimensions
Dimension
Min
0.80
0.00
Typ
0.85
Max
0.90
0.05
A
A1
A3
b
0.02
0.20 REF
0.25
0.18
6.90
6.90
4.60
4.60
0.30
7.10
7.10
4.80
4.80
D
7.00
E
7.00
D2
E2
e
4.70
4.70
0.50 BSC
0.40
L
0.30
0.20
0.09
0.50
—
K
—
R
—
0.14
aaa
bbb
ccc
ddd
eee
fff
0.15
.10
0.10
0.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
QFN48 Package Specifications
7.2 QFN48
PCB Land Pattern
Figure 7.2.
QFN48 PCB Land Pattern Drawing
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
QFN48 Package Specifications
Table 7.2.
QFN48 PCB Land Pattern Dimensions
Dimension
Typ
6.01
6.01
4.70
4.70
0.50
0.26
0.86
S1
S
L1
W1
e
W
L
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask a
d the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 4×4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
QFN48 Package Specifications
7.3 QFN48
Package Marking
EFR32
PPPPPPPPP
YYWWTTTTTT #
Figure 7.3.
QFN4
ckage Marking
The package marking consists of:
• PPPPPPPPP
– The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,…)
4. Performance Grade (P | B | V)
5. Feature Code (1 to 7)
6. TRX Code (3 = TXRX | 2= RX | 1 = TX)
7. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
8. Flash (J = 1024K | H
2K | G = 256K | F = 128K | E = 64K | D = 32K)
9. Temperature Grade (
-40 to 85 | I = -40 to 125)
• YY
– The last 2 digits of the assembly year.
• WW
– The 2-dig
orkweek when the device was assembled.
• TTTTTT
ace or manufacturing code. The first letter is the device revision.
• #
– Bootlo
der revision number.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
QFN32 Package Specifications
8. QFN32
Package Specifications
8.1 QFN32
Package Dimensions
Figure 8.1.
QFN32 Package Drawing
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
QFN32 Package Specifications
Table 8.1.
QFN32 Package Dimensions
Dimension
Min
0.80
0.00
Typ
0.85
Max
0.90
0.05
A
A1
A3
b
0.02
0.20 REF
0.25
0.18
4.90
3.40
0.30
5.10
3.60
D/E
D2/E2
E
5.00
3.50
0.50 BSC
0.40
L
0.30
0.20
0.09
0.50
—
K
—
R
—
0.14
aaa
bbb
ccc
ddd
eee
fff
0.15
0.10
0.10
.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless oth
ise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-199
.
3. This drawing conforms to the JEDEC Solid State Ou
MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
QFN32 Package Specifications
8.2 QFN32
PCB Land Pattern
Figure 8.2.
Q
2 PCB Land Pattern Drawing
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
QFN32 Package Specifications
Table 8.2.
QFN32 PCB Land Pattern Dimensions
Dimension
Typ
4.01
4.01
3.50
3.50
0.50
0.26
0.86
S1
S
L1
W1
e
W
L
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask a
d the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 3×3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
QFN32 Package Specifications
8.3 QFN32
Package Marking
EFR32
PPPPPPPPP
YYWWTTTTTT
Figure 8.3.
QFN32 Package Marking
The package marking consists of:
• PPPPPPPPP
– The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,…)
4. Performance Grade (P | B | V)
5. Feature Code (1 to 7)
6. TRX Code (3 = TXRX | 2= RX | 1 = TX)
7. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
8. Flash (J = 1024K | H = 512k | G = 256K | F = 128K | E = 64K | D = 32K)
9. Temperature Grade (G = -40 to 85 | I = –
0 to 125)
• YY
– The last 2 digits of the assembly year.
• WW
– The 2-digit workweek when the device was assembled.
• TTTTTT
– A trace or manufacturing code. The first letter is the device revision.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Revision History
9. Revision
History
Revision 1.4
October, 2018
•
2. Ordering Information
– Added OPN for QFN48 sub-GHz devices.
•
4.1.2.1 General Operating Conditions
– Removed voltage scaling footnote from DECOUPLE output capacitor specification.
•
4.1.5 Current Consumption
– Removed “across supply voltage” from header.
•
4.1.10 Sub-GHz RF Transceiver Characteristics
– Replaced “PAVDD” with “External PA Supply”.
•
4.1.10.10 Sub-GHz RF Receiver Characteristics for 315 MHz Band
&
4.1.10.6 Sub-GHz RF Receiver Characteristics fo
MHz
Band
– Corrected tuning frequency range units from “dBM” to “MHz”.
•
4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band
– Replaced “GFSK” with “4GFSK” for 400 kbps test condition.
•
4.1.15 Voltage Monitor (VMON)
– Replaced “1 supply monitored” with “1 channel active” and replaced “4 sup
s monitored” with
“all channels active” in VMON supply current test conditions.
•
Table 4.40 Analog to Digital Converter (ADC) on page 78
– Minor wording and typographical error fixes.
•
Table 4.41 Analog Comparator (ACMP) on page 80
– Minor wording and typographical error fixes.
•
6.3 QFN48 Sub-GHz Device Pinout
– Added GPIO pinout information for QFN48 sub-GHz devices.
Revision 1.3
April, 2018
•
Table 3.1 Configuration Summary on page 18
: Corrected USART1 features (removed IrDA).
•
Table 4.6 Current Consumption 3.3 V using DC-DC Converter on page 28
:
• Typical
values for I
EM2
updated to 2.5 and 2.2 uA per errata CUR_E201.
• Typical
value for I
EM3
updated to 2.1 uA per errata CUR_E201.
•
Table 4.15 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate on page 39
: typical value
for SENS updated to -92.5 dBm per errata RADIO_E206.
•
Table 4.17 RF Receiver Characteristics for 802.15.4 DSSS-OQ
in the 2.4 GHz Band on page 43
: Typical values for SENS up-
dated to -99 dBm per errata RADIO_E201.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Revision History
Revision 1.2
November, 2017
• Applied
latest formatting, style, and sequence guidelines.
• Updated
front page with new title and messaging.
• “Bluetooth
Smart” changed to “Bluetooth Low Energy”
• Added
high-temperature (-I grade) part numbers and associated sections / specifications.
• Parameter
Names, Symbol Names, and Test Conditions throughout electrical specification tables updated for consistency across all
EFR32xG1x product families.
• Electrical
specification changes not related to formatting consistency, typographical errors, or the addition of high-temper
re part
numbers are listed below.
•
4.1.1 Absolute Maximum Ratings
:
• V
DDMAX
: Min value changed from 0 to -0.3 V.
• Removed
P
RFMAXSUBG
, V
MAXDIFFSUBG
, and DeltaV
DD
specifications.
• Split
V
MAXSUBG
into separate line items for SUBGRF_OP/SUBGRF_ON and SUBGRF_IP/SUBG
• V
MAXSUBG
for SUBGRF_IP/SUBGRF_IN: Min = -0.3 V, Max = +0.3 V.
• Added
footnotes to clarify V
DIGPIN
specification for 5V tolerant GPIO.
•
Table 4.2 General Operating Conditions on page 23
:
• Added
C
DECOUPLE
and f
HFCLK
specifications.
• Added
footnote for additional information on peak current during voltage scaling operations.
•
Table 4.6 Current Consumption 3.3 V using DC-DC Converter on page 28
:
• I
EM1
: CCM Mode specifications removed from table.
• Low
Power Mode footnote corrected from “LPBIAS=3” to “LPCMPBIAS=0”, and “LPCILIMSEL” to “LPCLIMILIMSEL”.
•
4.1.9.3 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.
z Band, 1 Mbps Data Rate
:
• TXBW:
Test Condition at 10 dBm added.
• Footnote
referring to Bluetooth Core specification updated to “Bluetooth Core_5.0…” from “Bluetooth Core_4.2…”
•
Table 4.17 RF Receiver Characteristics for 802.15.4 DSSS-
PSK in the 2.4 GHz Band on page 43
: RSSI
MAX
value placed in
Max column and RSSI
MIN
value placed in Min column.
•
Table 4.19 Sub-GHz RF Receiver Characteristics for 9
MHz Band on page 48
: 100kbps reference signal footnote corrected to
show 400 kHz channel spacing instead of 200 kHz.
•
Table 4.34 HFRCO on page 72
and
Table 4.35 A
FRCO on page 73
tables separated (specifications are identical for this
product).
Table 4.37 Flash Memory Characteristics
1
page 74
:
•
• Added
single-word programming time and clarified existing specification as per-word timing for a 128-word burst write.
• Added
footnotes to clarify mass, device, and page erase timing conditions.
•
Table 4.39 Voltage Monitor (VMON) on page 77
: I
VMON
specifications for EM2/3/4 separated into above threshold and below
threshold conditions.
•
Table 4.40 Analog to Digital Converter (ADC) on page 78
• V
ADCIN
specificatio
nged to reference V
FS
instead of V
REF
• Input
referred ADC noise specification removed.
.
• Footnotes
a
ded to clarify internal and external reference configurations.
•
Table 4.
An
log Comparator (ACMP) on page 80
: Text explaining total ACMP current calculation brought into table as a foot-
note.
•
4.1.21 USART SPI
:
• SPI
Master Timing: Updated with relaxed values.
SPI Slave Timing: Corrected t
SCLK
Min value to “6 * t
HFPERCLK
” from “2 * t
HFPERCLK
“.
Updated remainder of specifications to match formatting and common specs in all EFR32xG1x product families.
• Added
PCNT electrical specifications table:
Table 4.43 Pulse Counter (PCNT) on page 84
.
•
4.2 Typical Performance Curves
: Added data for >85C operation.
•
5.2 RF Matching Networks
: Removed redundant paragraph in introduction.
• Added
section
5.3 Other Connections
.
• Condensed
pinout tables and moved detailed GPIO functionality information to .
• Added
Figure 6.5 APORT Connection Diagram on page 130
.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Revision History
• Corrected
flash designator description in Package Marking sections.
Revision 1.1
2016-Oct-26
• Ordering
Information: Removed Encryption column. All products in family include full encryption capabilites. Previously EFR32MG1V
devices listed as “AES only”.
• System
Overview Sections: Minor wording and typographical error fixes.
• Electrical
Characteristics: Minor wording and typographical error fixes.
• “Sub-GHz
Receiver Characteristics for 433 MHz Band” table in Electrical Characteristics: Corrected Sensitivity spec error
re da-
ta for 50 kbps and 2.4 kbps were swapped.
• “HFRCO
and AUXHFRCO” table in Electrical Characteristics: f_HFRCO symbol changed to f_HFRCO_ACC.
• Pinout
tables: APORT channel details removed from “Analog” column. This information is now found in the APORT client map sec-
tions.
• Updated
APORT client map sections.
Revision 1.0
2016-Jul-22
• Electrical
Characteristics: Minimum and maximum value statement changed to cover full op
ating temperature range.
• Finalized
Specification Tables. Tables with condition/min/typ/max or footnote changes include:
• Absolute
Maximum Ratings
• General
Operating Conditions
• DC-DC
Converter
• Current
Consumption Using Radio 3.3V with DC-DC
• RF
Transmitter General Characteristics for 2.4 GHz Band
• RF
Receiver General Characteristics for 2.4 GHz Band
• RF
Receiver Characteristics for Bluetooth Smart in the 2.4 G
Band
• RF
Transmitter Characteristics for 802.15.4 DSSS-OQPSK in
e 2.4 GHz Band
• RF
Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
• Sub-GHz
RF Transmitter characteristics for 868 M
and
• Sub-GHz
RF Transmitter characteristics for 490 MHz Band
• Sub-GHz
RF Receiver characteristics for 490 MHz Band
• Sub-GHz
RF Receiver characteristics for
3 MHz Band
• HFRCO
and AUXHFRCO
• ADC
• IDAC
• Updated
Typical Performance Graphs.
• Added
external ground not
o 2G4RF_ION pin descriptions.
• Added
note for 5V toleran
pinout GPIO Overview sections.
• Updated
OPN decoder with latest revision.
• Updated
Packag
Marking text with latest descriptions.
Revision 0.9
2016-06-06
• A
dual-band and sub-GHz OPNs.
Revision 0.951
2016-06-03
• Electrical
specification tables updated with additional characterization data.
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Revision History
Revision 0.95
2016-04-11
• All
OPNs changed to rev C0. Note the following:
• All
OPNs ending in -B0 are Engineering Samples based on an older revision of silicon and are being removed from the OPN
table. These older revisions should be used for evaluation only and will not be supported for production.
• OPNs
ending in -C0 are the Current Revision of Silicon and are intended for production.
• Electrical
specification tables updated with latest characterization data and production test limits.
Revision 0.9
2016-01-12
• Updated
electrical specifications with latest characterization data.
• Added
thermal characteristics table.
• Updated
OPN decoder figure to include extended family options.
Revision 0.8
2015-12-01
• Engineering
samples note added to ordering information table.
• Updated
electrcal specifications with latest available data.
Revision 0.75
2015-11-3
• Consolidated
individual device datasheets into single-family document.
• Re-formatted
ordering information table and OPN decoder.
• Updated
block diagrams for front page and system overview.
• Removed
extraneous sections from DC-DC and wake-on-radio from system overview.
• Updated
table formatting for electrical specifications to tech pubs standards.
• Updated
electrcal specifications with latest available d
• Added
I2C and USART SPI timing tables.
• Moved
DC-DC graph to typical performance curves.
• Updated
APORT tables and APORT referen
s to correct nomenclature.
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Rev. 1.4
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EFR32MG1 Mighty Gecko Multi-Protocol SoC Family Data Sheet
Revision History
Revision 0.7
2015-08-31
Outcome of comprehensive review cycle of EFR32BG Datasheets. Major changes div the following sections
• Section
2: Ordering Information
• Section
3.3.4: Receiver Architecture
• Section
3.3.5: Transmitter Architecture
• Section
4: Electrical Characteristics
• Section
4.3.1: General Operating Conditions
• Section
4.4: DC-DC Converter
• Section
4.5: Current Consumption
• Section
4.9.1: RF Transmitter Characteristics for 2.4 GHz Band
• Section
4.9.2: RF Receiver General Characteristics for 2.4 GHz Band
• Section
4.9.3: RF Transmitter Characteristics for Bluetooth Smart in 2.4 GHz Band
• Section
4.9.4: RF Receiver Characteristics for Bluetooth Smart in 2.4 GHz Band
• Section
4.11.1: LFXO
• Section
4.11.2: HFXO
• Section
4.12: GPIO
• Section
4.13: VMON
• Section
4.14: ADC
• Section
4.15: IDAC
• Section
4.16: Analog Comparator
• Section
5: Application Circuits
• Section
6.5: QFNxx Package
• Section
6.7: QFNxx Package Marking
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