SKYWORKS-SILICON-LABS-EM3586-RT
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EM358x
High-Performance, Integrated ZigBee/802.15.4 System-on-Chip Family
Complete System-on-Chip
Exceptional RF Performance
–
32-bit ARM® Cortex -M3 processor
–
Normal mode link budget up to 103 dB; configurable up
to 110 dB
–
2.4 GHz IEEE 802.15.4-2003 transceiver & lower MAC
–
256 or 512 kB flash, with optional read protection
–
32 or
64 kB RAM memory
–
AES128 encryption accelerator
–
Flexible ADC, UART/SPI/TWI serial communications,
and general purpose timers
–
–100 dBm normal RX sensitivity; configurable to
–102 dBm (1% PER, 20 byte packet)
–
+3 dB normal mode output power; configurable up to
+8 dBm
–
Robust Wi-Fi and Bluetooth coexistence
–
Optional USB serial communications
–
24 highly configurable GPIOs with Schmitt trigger inputs
Innovative network and processor debug
–
Packet Trace Port for non-intrusive packe
ace with
Ember development tools
Industry-leading ARM® Cortex -M3 processor
–
Leading 32-bit processing performance
–
Highly efficient Thumb-2 instruction set
–
Operation at 6, 12, or 24 MHz
–
Serial Wire/JTAG interface
–
Standard ARM debug capabilities:
Patch & Break-
point; Data Watchpoint & Trace; Instrumentation Trace
Macrocell
–
Flexible Nested Vectored Interrupt Controller
Application Flexibility
–
Single voltage operat
n: 2.1–3.6 V with internal 1.8 and
1.25 V regulators
–
Optional 32.768 kHz crystal for higher timer accuracy
–
Low external component count with single 24 MHz
crystal
–
Sup
or external power amplifier
–
Small
7 mm 48-pin QFN package
Low power consumption, advanced management
–
RX Current (w/ CPU): 27 mA
–
TX Current (w/ CPU, +3 dBm TX): 31 mA
–
Low deep sleep current, with retained RAM and GPIO:
1.0
A without/1.25
A with sleep timer
–
Low-frequency internal RC oscillator for low-power sleep
timing
–
High-frequency internal RC oscillator for fast (110 µs)
processor start-up from sleep
TX_ACTIVE
Data
RAM
64 kB
Program
Flash
512 kB
PA select
PA
RF_TX_ALT_P,N
RF_P,N
SYNTH
DAC
ADC
MAC
+
Baseband
PA
LNA
ARM
®
Cortex
TM
-M3
CPU with NVIC
and MPU
2
nd
level
Interrupt
controller
IF
Packet Trace
Bias
CPU debug
TPIU/ITM/FPB/
DWT/ETM
Encryption
acclerator
OSCA
OSCB
HF crystal
OSC
Internal HF
RC-OSC
Calibration
ADC
General
purpose
timers
Always
Powered
Domain
25V
Regulator
VDD_CORE
VREG_O
USB
Device
Serial
Wire and
JTAG
SWCLK, JTCK
1.8V
Regulator
GPIO
registers
Watchdog
debug
General
Purpose
ADC
nRESET
POR
UART/
SPI/TWI
Chip
manager
Sleep
timer
LF crystal
OSC
Internal LF
RC-OSC
GPIO multiplexor switch
PA[7:0], PB[7:0], PC[7:0]
Rev 1.1
1
/
23
Copyright © 20
23
by Silicon Laboratories
EM358x
EM358x
General Description
The Ember EM358x is a fully integrated System-on-Chip that integrates a 2.4 GHz, IEEE 802.15.4-2003-compliant
®
transceiver, 32-bit ARM
Cortex
TM
-M3 microprocessor, flash and RAM memory, and peripherals of use to
designers of ZigBee-based systems.
The transceiver uses an efficient architecture that exceeds the dynamic range requirements imposed by the IEEE
802.15.4-2003 standard by over 15 dB. The integrated receive channel filtering allows for robust co-existence w
th
other communication standards in the 2.4 GHz spectrum, such as IEEE 802.11-2007 and Bluetooth. The integ
ted
regulator, VCO, loop filter, and power amplifier keep the external component count low. An optiona
gh
performance radio mode (boost mode) is software-selectable to boost dynamic range.
®
The integrated 32-bit ARM
Cortex
TM
-M3 microprocessor is highly optimized for high performance, low power
consumption, and efficient memory utilization. Including an integrated MPU, it supports two dif
rent modes of
operation—privileged mode and user mode. This architecture could allow for separation o
networking stack
from the application code, and prevents unwanted modification of restricted areas of
ry and registers
resulting in increased stability and reliability of deployed solutions.
The EM358x has either 256 or 512 kB of embedded flash memory and either 32
or 64 kB of integrated RAM for
data and program storage. The Ember software for the EM358x employs an effective wear-leveling algorithm that
optimizes the lifetime of the embedded flash.
To
m
aintain the strict timing requirements imposed by the ZigBee and IEEE 802.15.4-2003 standards, the EM358x
integrates a number of MAC functions, AES128 encryption accelerator, and automatic CRC handling into the
hardware. The MAC hardware handles automatic ACK transmission and reception, automatic backoff delay, and
clear channel assessment for transmission, as well as automatic filtering of received packets. The Ember Packet
Trace Interface is also integrated with the MAC, allowing complete
n-intrusive capture of all packets to and from
the EM358x with Ember development tools.
The EM358x offers a number of advanced power management features that enable long battery life. A high-
frequency internal RC oscillator allows the processor co
begin code execution quickly upon waking. Various
deep sleep modes are available with less than 2 µA power consumption while retaining RAM contents.
T
o
s
upport
user-defined applications, on-chip peripherals includ
op
ional USB, UAR
T
,
S
PI, TWI, ADC, and general-purpose
timers, as well as up to 24 GPIOs. Additionally,
ntegrated voltage regulator, power-on-reset circuit, and sleep
timer are available.
Finally, the EM358x utilizes standard Serial Wire and JTAG interfaces for powerful software debugging and
®
programming of the ARM Cortex
TM
-M
core. The EM358x integrates the standard ARM
system debug
components: Flash Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT), and Instrumentation Trace
Macrocell (ITM) as well as the advanced Embedded Trace Macrocell (ETM).
T
a
rget applications for the EM358x include:
Smart Energy
Building automation and control
Home automation a
ontrol
Security and monitoring
General ZigBee wireless sensor networking
This technical
ta sheet details the EM358x features available to customers using it with Ember software.
2
Rev 1.1
EM358x
Table of Contents
1. Related
Documents and Conventions ……………………………………………………………………
.
5
1.1. Related Documents………………………………………………………………………………………….
.
5
1.1.1. Ember
EM358x Reference Manual……………………………………………………………..
.
5
1.1.2. ZigBee
Specificatio
n
.
………………………………………………………………………………..
.
5
1.1.3. ZigBee
PRO Stack Profile …………………………………………………………………………
.
5
1.1.4. ZigBee
Stack Profile …………………………………………………………………………….
5
1.1.5. Bluetooth
Core Specification ……………………………………………………………………..
.
5
1.1.6. EEE
802.15.4-2003 ………………………………………………………………………………….
.
5
1.1.7. EEE
802.11g……………………………………………………………………………
…………….
.
5
1.1.8. USB
2.0 Specificatio
n
.
……………………………………………………..
……………….
.
5
1.1.9. ARM®
Cortex™-M3 Reference Manual …………………………………
………………..
.
5
1.2. Conventions
……………………………………………………………………………………………………
.
6
2. Typical
Connection Diagrams ……………………………………………………………………………….
.
9
3. Electrical
Specifications……………………………………………………
………………………………
.
1
3
3.1. Absolute Maximum Ratings……………………………………………………………………………..
.
1
3
3.2. Recommended Operating Conditions ……………………………………………………………….
.
1
3
3.3. Environmental Characteristics………………………………………………………………………….
.
1
4
3.4. DC Electrical Characteristics……………………………………………………………………………
.
1
4
3.5. Digital I/O Specifications …………………………….
……………………………………………..
.
1
9
3.6. Non-RF System Electrical Characteristics …………………………………………………………
.
2
0
3.7. RF Electrical Characteristics ……………………………………………………………………………
.
2
1
3.7.1. Receive…………………………………..
……………………………………………………….
.
2
1
3.7.2. Transmit…………………………….
……………………………………………………………….
.
2
4
3.7.3. Synthesize
r
.
……………………
…………………………………………………………………..
.
2
6
4. EM358x
System Overview…………….
………………………………………………………………….
.
2
7
4.1. Microprocessor and Memory……………………………………………………………………………
.
2
8
4.1.1. ARM®
Cortex™-M3 Microprocessor …………………………………………………………
.
2
8
4.1.2. Embedded
Memory ………………………………………………………………………………..
.
2
9
4.2. Interrupt Syste
m
.
……………………………………………………………………………………………
.
2
9
4.2.1. Nested
Vectored Interrupt Controller (NVIC
)
.
……………………………………………..
.
2
9
4.2.2. Event
Manager ………………………………………………………………………………………
.
2
9
4.2.3.
emory Protection Unit …………………………………………………………………
.
2
9
4.3. Radio Modu
………………………………………………………………………………………………..
.
2
9
4.3.1. Receive
(Rx) Path…………………………………………………………………………………..
.
2
9
4.3.2. Transmit
(Tx) Pat
h
.
…………………………………………………………………………………
.
3
0
3. Integrated
MAC Module…………………………………………………………………………..
.
3
0
4
3.4. Packet
Trace Interface (PTI)…………………………………………………………………….
.
3
0
4.3.5. Random
Number Generator …………………………………………………………………….
.
3
0
4.4. System Modules…………………………………………………………………………………………….
.
3
0
4.4.1. Power
domain
s
.
……………………………………………………………………………………..
.
3
0
4.4.2. Resets…………………………………………………………………………………………………..
.
3
1
4.4.3. Clock
s
.
………………………………………………………………………………………………….
.
3
1
4.4.4. System
Timers……………………………………………………………………………………….
.
3
1
4.4.5. Power
Management………………………………………………………………………………..
.
3
1
Rev 1.1
3
EM358x
4.5. Integrated Voltage Regulator …………………………………………………………………………..
.
3
2
4.6. Peripherals
……………………………………………………………………………………………………
.
3
2
4.6.1. GPIO …………………………………………………………………………………………………..
.
3
2
4.6.2. Serial
Controllers ……………………………………………………………………………………
.
3
2
4.6.3. USB
…………………………………………………………………………………………………..
.
3
3
4.6.4. General
Purpose Timers………………………………………………………………………….
.
3
3
4.6.5. Analog-to-Digital
Converter (ADC) …………………………………………………………..
.
3
4
4.7. Debuggin
g
.
…………………………………………………………………………………………………
34
4.7.1. Trace
Port Interface Unit (TPIU
)
.
………………………………………………………………
.
3
4
4.7.2. Instrumentation
Trace Macrocell (ITM)………………………………………………………
.
3
4
4.7.3. Embedded
Trace Macrocell (ETM)……………………………………………..
…………..
.
3
4
4.7.4.
Data Watchpoint and Trace (DWT)…………………………..
…………….
.
3
4
4.7.5. Flash
Patch and Breakpoint (FPB) ………………………………………..
……………….
.
3
5
4.7.6. Serial
Wire and JTAG (SWJ) Interfac
e
.
……………………………………………………..
.
3
5
5. Ordering
Informatio
n
.
………………………………………………………………………………………….
.
3
6
6. Pin
Assignments………………………………………………………………
………………………………
.
3
7
6.1. Mechanical Details
…………………………………………………………………………………………
.
5
0
6.1.1. QFN48
Footprint Recommendation
s
.
………………………………………………………..
.
5
2
6.1.2. Solder
Temperature Profile………………………………………………………………………
.
5
4
6.2. Part Markin
g
.
…………………………………………………………………………………………………
.
5
6
Document Change List ……………………………………
….
…………………………………………….
.
5
8
Contact Information …………………………………………………………………………………………………
.
5
9
4
Rev 1.1
EM358x
1. Related
Documents and Conventions
1.1. Related
Documents
This data sheet accompanies several documents to provide the complete description of the Ember EM358x
devices.
1.1.1. Ember EM358x Reference Manual
The Silicon Laboratories Ember EM358x Reference Manual provides the detailed description for each perip
eral
on the EM358x devices.
1.1.2. ZigBee Specification
The core ZigBee specification (Document 053474) defines ZigBee’s smart, cost-effective and energy-efficient
mesh network. It can be downloaded from the ZigBee website (www.zigbee.org). ZigBee Allianc
membership is
required.
1.1.3. ZigBee PRO Stack Profile
The ZigBee PRO Stack Profile specification (Document 074855) is optimized for low power consumption and to
support large networks with thousands of devices. It can be downloaded from the ZigBee website (111.zigbee.org).
ZigBee Alliance membership is required.
1.1.4. ZigBee Stack Profile
The ZigBee Stack Profile specification (Document 064321) is designed to support smaller networks with hundreds
of devices in a single network. It can be downloaded from the ZigBee website (111.zigbee.org). ZigBee Alliance
membership is required.
1.1.5. Bluetooth Core Specification
The Bluetooth specification is the global short-range wireless stand
rd enabling connectivity for a broad range of
electronic devices. Version 2.1 + EDR (Enhanced Data Rate) can be found here:
1.1.6. EEE 802.15.4-2003
This standard defines the protocol and compatible
nterconnection for data communication devices using low data
rate, low power and low complexity, short-range
io frequency (RF) transmissions in a wireless personal area
network (WPAN). It can be found here:
1.1.7. EEE 802.11g
This version provides changes and additions to support the further higher data rate extension for operation in the
2.4 GHz band. It can be found here:
1.1.8. USB 2.0 Specification
The Universal Serial Bu
evision 2.0 specification provides the technical details to understand USB requirements
and design USB compatible products. The main specification (usb_20.pdf) is part of the zipfile found here:
1.1.9. A
Cortex™-M3 Reference Manual
®
ARM-spe
ific features like the Nested Vector Interrupt Controller are described in the ARM
Cortex™-M3
reference documentation. The online reference manual can be found here:
Rev 1.1
5
EM358x
1.2. Conventions
Abbreviations and acronyms used in this data sheet are explained in
Table 1.1. Acronyms and Abbreviations
Acronym/Abbreviation
Meaning
ACK
Acknowledgement
ADC
Analog to Digital Converter
Advanced Encryption Standard
Automatic Gain Control
AES
AGC
AHB
Advanced High Speed Bus
Advanced Peripheral Bus
APB
CBC-MAC
CCA
Cipher Block Chaining—Message Authentication Code
Clear Channel Assessment
Counter with CBC-MAC Mode for AES encryption
Improved Counter with CBC-MAC Mode for AES encryption
Customer Information Block
1 kHz Clock
CCM
CCM*
CIB
CLK1K
CLK32K
CPU
32.768 kHz Crystal Clock
Central Processing Unit
CRC
Cyclic Redundancy
ck
Carrier Sense Multiple Access-Collision Avoidance
Counter Mo
CSMA-CA
CTR
CTS
Clear to Send
DNL
Differential Non-Linearity
DMA
Direct Memory Access
DWT
EEPROM
EM
Data Watchpoint and Trace
Electrically Erasable Programmable Read Only Memory
Event Manager
ENOB
ESD
effective number of bits
Electro Static Discharge
E
Equivalent Series Resistance
External Trigger Input
ETR
®
TM
FCLK
FIB
ARM Cortex
-M3 CPU Clock
Fixed Information Block
First-in, First-out
FIFO
6
Rev 1.1
EM358x
Table 1.1. Acronyms and Abbreviations
FPB
GPIO
HF
Flash Patch and Breakpoint
General Purpose I/O (pins)
High Frequency
2
I C
Inter-Integrated Circuit
IDE
Integrated Development Environment
Intermediate Frequency
IF
IEEE
INL
Institute of Electrical and Electronics Engineers
Integral Non-linearity
ITM
Instrumentation Trace Macrocell
Joint
T
e
st Action Group
JTAG
LF
Low Frequency
LNA
Low Noise Amplifier
LQI
Link Quality Indicator
LSB
Least significant bit
MAC
MFB
MISO
MOS
MOSI
MPU
MSB
MSL
Medium Access Control
Main Flash Block
Master in, slave out
Metal Oxide Semicon
uctor (P-channel or N-channel)
Master out, slave in
Memory Pro
ction Unit
Most significant bit
Moisture Sensitivity Level
Negative Acknowledge
NACK
NIST
NMI
National Institute of Standards and
T
e
chnology
Non-Maskable Interrupt
NVIC
OPM
O-QPSK
OSC24M
OSC32K
OSCHF
OSCRC
PA
Nested Vectored Interrupt Controller
One-Pulse Mode
Offset-Quadrature Phase Shift Keying
High Frequency Crystal Oscillator
Low-Frequency 32.768 kHz Oscillator
High-Frequency Internal RC Oscillator
Low-Frequency RC Oscillator
Power Amplifier
Rev 1.1
7
EM358x
Table 1.1. Acronyms and Abbreviations
PCLK
PER
PHY
PLL
Peripheral clock
Packet Error Rate
Physical Layer
Phase-Locked Loop
POR
PRNG
PSD
PTI
Power-On-Reset
Pseudo Random Number Generator
Power Spectral Density
Packet Trace Interface
Pulse Width Modulation
Quad Flat Pack
PWM
QFN
RAM
RC
Random Access Memory
Resistive/Capacitive
RF
Radio Frequency
RMS
RoHS
RSSI
RTS
Rx
Root Mean Square
Restriction of Hazardous Substances
Receive Signal Strength Indic
or
Request to Send
Receive
SYSCLK
SDFR
SFD
SINAD
SPI
System clock
Spurious Fre
Dynamic Range
Start Frame Delimiter
Signal-to-noise and distortion ratio
Serial Peripheral Interface
Serial Wire and JTAG Interface
T
o
tal Harmonic Distortion
True random number generator
Two Wire serial interface
Transmit
SWJ
THD
TRNG
TWI
Tx
UART
UEV
USB
VCO
Universal Asynchronous Receiver/Transmitter
Update event
Universal Serial Bus
Voltage Controlled Oscillator
8
Rev 1.1
EM358x
2. Typical
Connection Diagrams
Figure 2.1 illustrates the typical application circuit.
Note:
The circuit shown in
Figure 2.1
is for example purposes only. For a complete reference design, please download one of
the latest Ember Hardware Reference Designs from the Silicon Labs website (
www.silabs.com/zigbee-support
).
The Balun provides an impedance transformation from the antenna to the EM358x for both TX and RX modes.
L4, along with the PCB trace parasitics and the ceramic balun impedence, provide the optimal RF path for
maximum transmit power and receive sensitivity for the EM358x system.
The harmonic filter (L5, L6, C7, C8 and C9) provides additional suppression of the second harmonic, which
increases the margin over the FCC limit.
The 24 MHz crystal, Y2, with loading capacitors is required and provides the high-frequency
stal oscillator
source for the EM358x’s main system clock. The optional 32.768 kHz crystal, Y1, w
oading capacitors
generates a highly accurate low-frequency crystal oscillator for use with peripherals, but it i
mandatory as the
low-frequency internal RC oscillator can be used.
Loading capacitance and ESR (C3 and R3) provides proper loading for the internal 1.8 V regulator.
Loading capacitance C4 provides proper loading for the internal 1.25 V regulator, no ESR is required because it is
contained within the chip.
Resistor R7 reduces the operating voltage of the flash memory. This reduces current consumption and improves
sensitivity by 1 dB when compared to not using it.
Various decoupling capacitors, C12 – C21, are required, these should be placed as close to their corresponding
pins as possible. For values and locations see one of the Silicon Labs reference designs.
An antenna impedance matched to 50
is required.
Rev 1.1
9
EM358x
Figure 2.1. Typical Application Circuit
10
Rev 1.1
EM358x
Table 2.1. Bill of Materials for Figure 2.1
Item Qty Reference
Description
Manufacturer
1
2
1
1
ANT1
BLN1
ANTENNA, <not specified>
<not specified>
BALUN, CHIP MULTILAYER CERAMIC, 2.4
GHZ. 50/100 OHM, -40C TO 85C, 0805
Wurth 748421245
Johanson 2450BL15B100E
Murata LDB212G4010C
TDK HHM1520
3
1
1
1
1
1
3
2
1
1
1
C1
CAPACITOR, <not specified>
<not specified>
<not sp
d>
<not spec
d>
<not specified>
<not specified>
<not specified>
<not specified>
4
C2
CAPACITOR, <not specified>
5
C3
CAPACITOR, 2.2 µ
F
,
1
0 V, X5R, 10%, 0603
CAPACITOR, 1 µ
F
,
6
.3
V
,
X
5R, 10%, 0402
CAPACITOR, 33 p
F
,
±
5%, 50 V, NPO, 0402
CAPACITOR, 22 p
F
,
±
5%, 50 V, NPO, 0402
CAPACITOR, 1 p
F
,
±
0.25 p
F
,
5
0 V, 0402, NPO
6
C4
7
C5
8
C6, C10, C11
9
C7, C9
C8
10
11
12
CAPACITOR, 1.8p
F
,
±
0.25 p
F
,
5
0 V, 0402, NPO
<not specified>
FB1
J1
FERRITE BEAD, 60 OHM, 500M
603
Murata BLM18PG600SN1
CONNECTOR, USB, END LAUNCH, THROUGH
Molex 67068-8110
HOLE
13
1
J2
CONNECTOR, HEA
R, SHROUDED, 10
POSITION, DUA
ROW, VERTICAL, 0.050″
Samtec FTSH-105-01-L-DV-K
14
15
4
2
L1, L2, L3, L4
L5, L6
INDUCTOR, <no
pecified>
<not specified>
INDUCTOR, 2.7 nH, ±0.3 nH, 0402, MULTI-
LAYER
Murata LQG15HS2N7
16
17
18
19
20
21
22
23
1
1
1
1
2
1
4
1
R1
RESISTOR, 15K OHM, 5%, 1/10W, 0402
RESISTOR, 10K OHM, 5%, 1/16W, 0402
RESISTOR, 1 OHM, 5%, 1/16W, 0402
RESISTOR, 1.5K OHM, 1%, 1/16W, 0402
RESISTOR, 26.1 OHM, 1%, 1/10W, 0402
RESISTOR, 10 OHM, 5%, 1/16W, 0402
RESISTOR, 100K OHM, 5%, 1/16W, 0402
<not specified>
R2
<not specified>
R3
<not specified>
R4
<not specified>
R5, R6
<not specified>
R7
<not specified>
R8, R9, R10, R11
Q1
<not specified>
MOSFE
T
,
2
N7002, 300MA, 830MW, 60V, TO-
236-3, SC-59, SOT-23-3
NXP Semiconductor 2N7002
24
25
1
1
U1
U2
IC, VOLTAGE REGULATOR, <not specified>
<not specified>
EM358x, ZIGBEE/802.15.4 RF
EM3581-RTR/EM3582-RTR/
TRANSCEIVER, ARM CORTEX-M3, 32
or 64 kB
EM3585-RTR/
RAM, 256 or 512 kB FLASH, 48-QFN
EM3586-RTR/EM3587-RTR/
EM3588-RTR
Rev 1.1
11
EM358x
Table 2.1. Bill of Materials for Figure 2.1
26
1
U3
IC – PROGRAMMABLE MEMORY – BLANK,
SERIAL FLASH, 8M (256K X 32), 2.7 V – 3.6 V, –
40 to 85 ºC, 8-SOIC (0.154″, 3.90MM WIDTH)
WinBond W25Q80BVSNIG
27
28
1
1
Y1
Y2
CRYSTAL, 32.768 kHz, ±20 ppm INITIAL TOL-
ERANCE AT +25ºC, 12.5 pF
Abracon ABS07-32.768KHZ-T
OSCILLATOR, CRYSTAL, 24.000 MHz, 18 pF
LOAD, ±10 PPM TOLERANCE, ±25 PPM STA-
BILIT
Y
,
–
40 TO 85 ºC, AT49
Abracon ABLS-24.000M
D1X-T
ILSI HC49USM-24.000000M-
2435
AEL X2
0000S067
12
Rev 1.1
EM358x
3. Electrical
Specifications
3.1. Absolute
Maximum Ratings
T
a
ble 3.1 lists the absolute maximum ratings for the EM358x.
Table 3.1. Absolute Maximum Ratings
Parameter
Test Condition
Min
–0.3
–0.3
Max
U
V
Regulator input voltage (VDD_PADS)
+3.6
+2.0
Analog, Memory and Core voltage (VDD_24MHZ,
VDD_VCO, VDD_R
F
,
V
DD_I
F
,
V
DD_PADSA,
VDD_MEM, VDD_PRE, VDD_SYNTH, VDD_CORE)
V
Voltage on RF_
P
,
N; RF_TX_ALT_
P
,
N
–0.3
—
3.6
+15
V
RF Input Power
(for max level for correct packet reception see
RX signal into a
loss-less balun
dBm
T
a
ble 3.7)
Voltage on any GPIO (PA[7:0], PB[7:0], PC[7:0]),
SWCLK, nRESE
T
,
V
REG_OUT
–0.3 VDD_PADS
+0.3
V
V
Voltage on any GPIO pin (PA4, PA5, PB5, PB6, PB7,
PC1), when used as an input to the general purpose
ADC
–0.3
2.0
Voltage on OSCA, OSCB, NC
–0.3 VDD_PADSA
+0.3
V
Storage temperature
–40
+140
°C
3.2. Recommended
Operating Conditi
s
T
a
ble 3.2 lists the rated operating conditions of the EM358x.
Table 3.2. Operating Conditions
Parameter
Test Condition
Min
Typ
—
Max
Unit
V
Regulator input voltage (VDD_PADS)
2.1
1.7
3.6
1.9
Analog and memory in
voltage
(VDD_24MHZ, VDD_V
, VDD_R
F
,
V
DD_I
F
,
VDD_PADSA, VDD_MEM, VDD_PRE,
VDD_SYNTH)
1.8
V
Core in
oltage when supplied from internal
regulator
VDD_CORE)
1.18
–40
1.25
—
1.32
+85
V
Operating temperature range
°C
Rev 1.1
13
EM358x
3.3. Environmental
Characteristics
T
a
ble 3.3 lists the rated environmental characteristics of the EM358x.
Table 3.3. Environmental Characteristics
Parameter
ESD (human body model)
ESD (charged device model)
ESD (charged device model)
Test Condition
On any pin
Non-RF pins
RF pins
Min
—
Typ
—
Max
±2
Unit
kV
V
—
—
±400
±225
—
—
V
3.4. DC
Electrical Characteristics
T
a
ble 3.4 lists the DC electrical characteristics of the EM358x.
Table 3.4. DC Characteristics
Parameter
Test Condition
n
Typ
Max
Unit
Regulator input voltage
(VDD_PADS)
2.1
—
3.6
V
Power supply range (VDD_MEM)
Power supply range (VDD_CORE)
Deep Sleep Current
Regulator output or external input
Regulator output
1.7
1.8
1.9
V
V
1.18
1.25
1.32
Quiescent current, internal oscilla-
tor disabled, 4 kB RAM retained
–40 °C, VDD_PADS=3.6 V
+25 °C, VDD
S=3.6 V
+85 °C, V
D_PADS=3.6 V
–40
DD_PADS=3.6 V
+25 °C, VDD_PADS=3.6 V
+85°C, VDD_PADS=3.6 V
–40 °C, VDD_PADS=3.6 V
+25 °C, VDD_PADS=3.6 V
+85 °C, VDD_PADS=3.6 V
–40 °C, VDD_PADS=3.6 V
+25 °C, VDD_PADS=3.6 V
+85 °C, VDD_PADS=3.6 V
–40 °C, VDD_PADS=3.6 V
+25 °C, VDD_PADS=3.6 V
+85 °C, VDD_PADS=3.6 V
–40 °C, VDD_PADS=3.6 V
+25 °C, VDD_PADS=3.6 V
+85 °C, VDD_PADS=3.6 V
With no debugger activity
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.9
1.0
2.2
1.2
1.25
2.5
1.3
1.6
2.9
1.6
1.9
3.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Quiescent current, including
internal RC oscillator, 4 kB RAM
retained
Quiescent current, including
32.768 kHz oscillator, 4 kB RAM
retained
Quiescent current, including
internal RC oscillator
32.768 kHz oscillator, 4 kB RAM
retained
Additional qui
cent current per
4 kB b
of RAM retained
0.007
0.067
0.76
0.57
0.67
2.0
A
ditional quiescent current when
ned RAM exceeds 32 kB
Simulated deep sleep (debug
mode) current
500
14
Rev 1.1
EM358x
Table 3.4. DC Characteristics (Continued)
Parameter
Test Condition
Min
Typ
Max
Unit
Reset Current
Quiescent current, nRESET
asserted
Typ at 25 °C/3.0 V
Max at 85 °C/3.6 V
—
2
3
mA
Processor and Peripheral Currents
®
TM
ARM Cortex
-M3, RAM, and
flash memory
25 °C, 1.8 V memory and
—
—
—
7.5
8.5
4.0
—
—
—
mA
mA
mA
1.25 V core
®
TM
ARM Cortex
-M3 running at 12 MHz
from crystal oscillator
Radio and all peripherals off
®
TM
ARM Cortex
-M3, RAM, and
flash memory
25 °C, 1.8 V memory and
1.25 V core
®
TM
ARM Cortex
-M3 running at 24 MHz
from crystal oscillator
Radio and all peripherals off
®
TM
ARM Cortex
-M3, RAM, and
flash memory sleep current
25 °C, 1.8 V memory and
1.25 V core
®
TM
ARM Cortex
-M3 sleeping, CPU
clock set to 12 MHz from t
rystal
oscillator
Radio and all peripherals off
®
TM
ARM Cortex
-M3, RAM, and
flash memory sleep current
25 °C, 1.8 V
ory and
1.
V core
ARM Cortex
-M3 sleeping, CPU
clock set
MHz from the high fre-
quency RC oscillator
—
—
2.5
0.2
—
—
mA
mA
®
M
Radio and all peripherals off
Serial controller current
F
r each controller at maximum data
rate
General purpose timer current
General purpose ADC current
USB active current
For each timer at maximum clock rate
At maximum sample rate, DMA enabled
—
—
0.25
1.1
1
—
—
mA
mA
mA
mA
USB suspended mode
rrent
1.8 V memory and 1.25 V core
2.5
®
TM
ARM Cortex
-M3 sleeping, CPU
clock set to 3 MHz from the high fre-
quency RC oscillator.
Radio and all peripherals off
RX Current
®
TM
dio receiver, MAC, and base-
d
ARM Cortex
-M3 sleeping, CPU
clock set to 12 MHz
—
—
—
23.5
27.0
28.0
—
—
—
mA
mA
mA
T
o
tal RX current ( = I
receiver,
25 °C, VDD_PADS=3.0 V
ARM Cortex
-M3 running at 12 MHz
Radio
®
TM
MAC and baseband, CPU + IRAM,
and Flash memory )
25 °C, VDD_PADS=3.0 V
ARM Cortex
-M3 running at 24 MHz
®
TM
Rev 1.1
15
EM358x
Table 3.4. DC Characteristics (Continued)
Parameter
Test Condition
25 °C, VDD_PADS=3.0 V
Min
Typ
Max
Unit
Boost mode total RX current ( =
receiver, MAC and base-
—
29.0
—
mA
®
TM
I
ARM Cortex
-M3 running at 12 MHz
Radio
band, CPU+ IRAM, and flash
memory )
25 °C, VDD_PADS=3.0 V
ARM Cortex
-M3 running at 24 MHz
—
—
30.0
27.5
—
—
mA
mA
®
TM
TX Current
Radio transmitter, MAC, and base-
25 °C and 1.8 V core; max. power out
band
(+3 dBm typical)
ARM Cortex
-M3 sleeping, CPU
clock set to 12 MHz
®
TM
T
o
tal TX current ( = I
ter, MAC and baseband, CPU +
IRAM, and flash memory)
transmit- 25
°C, VDD_PADS=3.0 V; maximum
—
—
—
—
—
—
—
44
31.5
29
—
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
mA
Radio
®
power setting (+8 dBm); ARM
TM
Cortex -M3
running at 12 MHz
25 °C, VDD_PADS=3.0 V; +3 dBm
®
TM
power setting; ARM
Cortex -M3
running at 12 MHz
25 °C, VDD_PADS=3.0 V; 0 dBm power
®
TM
setting; ARM
Cortex -M3
running at
12 MHz
25 °C, VDD_PADS=3.0 V; minimum
24
®
TM
power setting; ARM
Cortex -M3
running a
MHz
25 °C, VDD_P
DS=3.0 V; maximum
45
®
power sett
g (+8 dBm); ARM
Cor-
TM
tex –
running at 24 MHz
25 °C, VDD_PADS=3.0 V; +3 dBm
33.5
30
®
TM
wer setting; ARM
Cortex -M3
running at 24 MHz
25 °C, VDD_PADS=3.0 V; 0 dBm power
®
TM
setting; ARM
Cortex -M3
running at
24 MHz
25 °C, VDD_PADS=3.0 V; minimum
24
®
TM
power setting; ARM
Cortex -M3
running at 24 MHz
16
Rev 1.1
EM358x
®
TM
Figure 3.1 shows the variation of current in transmit mode (with the ARM
Cortex -M3
running at 12 MHz).
Figure 3.1. Tra
mit Power Consumption
Rev 1.1
17
EM358x
Figure 3.2 shows typical output power against power setting on the Silicon Labs reference design.
Figure 3.2.
ansmit Output Power
18
Rev 1.1
EM358x
3.5. Digital
I/O Specifications
T
a
ble 3.5 lists the digital I/O specifications for the EM358x. The digital I/O power (named VDD_PADS) comes from
three dedicated pins (Pins 23, 28, and 37). The voltage applied to these pins sets the I/O voltage.
Table 3.5. Digital I/O Specifications
Parameter
Test Condition
Min
Typ
—
Max
Unit
V
Voltage supply (regulator input voltage)
Low Schmitt switching threshold
2.1
3.6
V
0.42 x
—
0.50 x
SWIL
VDD_PADS
VDD_PADS
Schmitt input threshold going
from high to low
High Schmitt switching threshold
V
0.62 x
—
0
0 x
V
SWIH
VDD_PADS
D_PADS
Schmitt input threshold going
from low to high
Input current for logic 0
I
—
—
2
24
0
—
—
29
29
—
–0.5
+0.5
34
μ
A
μ
A
k
k
V
IL
Input current for logic 1
I
IH
Input pull-up resistor value
Input pull-down resistor value
Output voltage for logic 0
R
IPU
IPD
R
34
V
0.18 x
OL
VDD_PADS
(I =
4 mA for standard pads,
OL
8 mA for high current pads)
Output voltage for logic 1
V
0.82 x
—
VDD_PADS
V
OH
VDD_PADS
(I =
4 mA for standard pads,
OH
8 mA for high c
rent pads)
Output source current
(standard current pad)
I
—
—
—
—
—
—
4
4
8
mA
mA
mA
HS
Output sink current
(standard current pad)
I
OLS
Output source current
high current pad: PA6, PA7, PB6, PB7,
PC0
I
OHH
Output sink current
high current pad: PA6, PA7, PB6, PB7,
PC0
I
—
—
—
—
8
mA
mA
OLH
T
o
tal output current (fo
Pads)
I
+ I
40
OH
OL
Rev 1.1
19
EM358x
T
a
ble 3.6 lists the nRESET pin specifications for the EM358x. The digital I/O power (named VDD_PADS) comes
from three dedicated pins (Pins 23, 28, and 37). The voltage applied to these pins sets the I/O voltage.
Table 3.6. nReset Pin Specifications
Parameter
Test Condition
Min
Typ
Max
Unit
Low Schmitt switching threshold
V
0.42 x
—
0.50 x
V
SWIL
VDD_PADS
VDD_PADS
Schmitt input threshold going from
high to low
High Schmitt switching threshold
V
0.62 x
—
0.80 x
V
SWIH
VDD_PADS
VDD
ADS
Schmitt input threshold going from
low to high
0.5
+0.5
34
Input current for logic 0
Input current for logic 1
Input pull-up resistor value
I
—
—
24
—
—
29
μ
A
μ
A
k
IL
I
IH
R
IPU
Pull-up value while the chip is not
reset
Input pull-up resistor value
R
12
14.5
17
k
IPURESET
Pull-up value while the chip is
reset
3.6. Non-RF
System Electrical Characteristics
T
a
ble 3.7 lists the non-RF system level characteristics for
EM358x.
Table 3.7. Non-RF System Electrical Characte
stics
Parameter
est Condition
Min
Typ
110
Max
Unit
®
System wake time from deep
sleep
From wakeup event to first ARM
Cor-
te
-M3 instruction running from 6 MHz
—
—
µs
M
internal RC clock
Includes supply ramp time and oscillator
startup time
®
TM
Shutdown time going into deep
sleep
From last ARM
Cortex -M3
instruction
to deep sleep mode
—
5
—
µs
20
Rev 1.1
EM358x
3.7. RF
Electrical Characteristics
3.7.1. Receive
T
a
ble 3.8 lists the key parameters of the integrated IEEE 802.15.4-2003 receiver on the EM358x.
Receive measurements were collected with the Silicon Labs EM358x Ceramic Balun Reference Design (Version
A0) at 2440
MHz. The typical number indicates one standard deviation above the mean, measured at room
temperature (25
C). The Min and Max numbers were measured over process corners at room temperature.
Table 3.8. Receive Characteristics
Parameter
Frequency range
Test Condition
Min
2400
—
Typ
—
Max
00
–96
Unit
MHz
dBm
Sensitivity (boost mode)
1% PER, 20 byte packet defined by
IEEE 802.15.4-2003;
–1
Sensitivity
1% PER, 20 byte packet defined by
IEEE 802.15.4-2003;
—
—
–100
35
–94
—
dBm
dB
High-side adjacent channel rejection
IEEE 802.15.4-2003 interferer signal,
wanted IEEE 802.15.4-2003 signal
at –82 dBm
Low-side adjacent channel rejection
IEEE 802.15.4-2003 interferer signal,
wanted IEEE 802.15.4
3 signal
at –82 dBm
—
—
—
—
—
—
—
35
46
46
39
47
49
49
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
nd
2
high-side adjacent channel rejec-
IEEE 802.15.4-2
03 interferer signal,
wanted IEEE 8
5.4-2003 signal
–82 dBm
tion
nd
2
low-side adjacent channel rejection
IEEE 8
15.4-2003 interferer signal,
wanted
EE 802.15.4-2003 signal
at –82 dBm
High-side adjacent channel rejection
F
ltered IEEE 802.15.4-2003 inter-
ferer signal, wanted IEEE 802.15.4-
2003 signal at –82 dBm
Low-side adjacent channel rejection
Filtered IEEE 802.15.4-2003 inter-
ferer signal, wanted IEEE 802.15.4-
2003 signal at –82 dBm
nd
2
high-side adjacent channel
Filtered IEEE 802.15.4-2003 inter-
ferer signal, wanted IEEE 802.15.4-
2003 signal at –82 dBm
rejection
nd
2
low
e adjacent channel rejection
Filtered IEEE 802.15.4-2003 inter-
ferer signal, wanted IEEE 802.15.4-
2003 signal at –82 dBm
-side adjacent channel rejection
Low-side adjacent channel rejection
CW interferer signal, wanted IEEE
802.15.4-2003 signal at –82 dBm
—
—
44
47
—
—
dB
dB
CW interferer signal, wanted IEEE
802.15.4-2003 signal at –82 dBm
Rev 1.1
21
EM358x
Table 3.8. Receive Characteristics (Continued)
Parameter
Test Condition
Min
Typ
Max
Unit
nd
2
high-side adjacent channel
CW interferer signal, wanted IEEE
802.15.4-2003 signal at –82 dBm
—
59
—
dB
rejection
nd
2
low-side adjacent channel rejection
CW interferer signal, wanted IEEE
802.15.4-2003 signal at –82 dBm
—
—
59
40
—
—
dB
dB
Channel rejection for all other channels
IEEE 802.15.4-2003 interferer signal,
wanted IEEE 802.15.4-2003 signal
at –82 dBm
802.11g rejection centered at +12 MHz
IEEE 802.15.4-2003 interferer signal,
—
3
—
dB
or –13 MHz
wanted IEEE 802.15.4-2003 signal
at –82 dBm
Maximum input signal level for correct
operation
0
—
—
—
dBm
dBc
Co-channel rejection
IEEE 802.15.4-2003 interferer signal,
wanted IEEE 802.15.4-2003 signal
at –82 dBm
—
–6
Relative frequency error tolerance
(50% greater than the 2×40 ppm
required by IEEE 802.15.4-2003)
–120
–120
—
—
+120
+120
ppm
ppm
Relative timing error tolerance
(50% greater than the 2×40 ppm
required by IEEE 802.15.4-2003)
Linear RSSI range
RSSI Range
As defi
ed by IEEE 802.15.4-2003
40
—
—
—
dB
–90
–40
dBm
22
Rev 1.1
EM358x
Figure 3.3 shows the variation of receive sensitivity with temperature for boost mode and normal mode for a typical
chip.
Figure 3.3. Receive Sensitivity vs. Temperature
Rev 1.1
23
EM358x
3.7.2. Transmit
T
a
ble 3.9 lists the key parameters of the integrated IEEE 802.15.4-2003 transmitter on the EM358x.
Transmit measurements were collected with the Silicon Labs EM358x Ceramic Balun Reference Design (Version
A0) at 2440
MHz. The Typical number indicates one standard deviation below the mean, measured at room
temperature (25
C). The Min and Max numbers were measured over process corners at room temperature. In
terms of impedance, this reference design presents a 3n3 inductor in parallel with a 100:50
Ω
balun to the RF pins.
Table 3.9. Transmit Characteristics
Parameter
Test Condition
Min
Typ
Max
Unit
Maximum output power
At highest boost mode power setting (+8)
—
8
dBm
(boost mode)
Maximum output power
Minimum output power
At highest normal mode power setting (+3)
At lowest power setting
1
–55
5
—
—
15
dBm
dBm
%
—
—
Error vector magnitude
(Offset-EVM)
As defined by IEEE 802.15.4-2003,
which sets a 35% maximum
Carrier frequency error
PSD mask relative
PSD mask absolute
–40
–20
–30
—
—
—
+40
—
ppm
dB
3.5 MHz away
3.5 MHz away
—
dBm
24
Rev 1.1
EM358x
Figure 3.4 shows the variation of transmit power with temperature for maximum boost mode power, and normal
mode for a typical chip.
Figure 3.4. Transmit Power vs. Temperature
Rev 1.1
25
EM358x
3.7.3. Synthesizer
T
a
ble 3.10 lists the key parameters of the integrated synthesizer on the EM358x.
Table 3.10. Synthesizer Characteristics
Parameter
Frequency range
Test Condition
Min
2400
—
Typ
—
Max
2500
—
Unit
MHz
k
μ
s
Frequency resolution
Lock time
11.7
—
From off
—
100
0
Relock time
Channel change or RX/TX turnaround
(IEEE 802.15.4-2003 defines 192
μ
s
turnaround time)
—
—
μ
s
Phase noise at 100 kHz offset
Phase noise at 1 MHz offset
Phase noise at 4 MHz offset
Phase noise at 10 MHz offset
—
—
—
—
–75
–100
–108
–114
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
26
Rev 1.1
EM358x
4. EM358x
System Overview
Figure 4.1 shows a detailed block diagram of the EM358x.
TX_ACTIVE
Data
RAM
64 kB
Program
Flash
512 kB
PA select
PA
RF_TX_ALT_P,N
RF_P,N
SYNTH
DAC
ADC
MAC
+
Baseband
PA
LNA
ARM
®
Cortex
TM
-M3
CPU with NVIC
and MPU
2
nd
level
Interrupt
controller
IF
Packet Trace
Bias
CPU debug
TPIU/ITM/FPB/
DWT/ETM
En
accle
OSCA
OSCB
Calibration
ADC
HF crystal
OSC
Internal HF
RC-OSC
General
purpose
timers
Always
Powered
Domain
1.25V
Regulator
VDD_CORE
VREG_OUT
USB
Device
Serial
Wire and
JTAG
SWCLK, JTCK
1.8V
Regulator
GPIO
registers
Watchdog
debug
General
Purpose
ADC
nRESET
POR
UART/
SPI/TWI
Chip
manager
Sleep
timer
LF crystal
OSC
Internal LF
RC-OSC
GPIO multiplexor switch
PA[7
], PB[7:0], PC[7:0]
Figure 4.1
358x Block Diagram
The EM358x radio receiver is a low-I
F
,
s
uper-heterodyne receiver. The architecture has been chosen to optimize
co-existence with other devices in the
4 GHz band (namely Wi-Fi and Bluetooth), and to minimize power
consumption. The receiver uses differen
ial signal paths to reduce sensitivity to noise interference. Following RF
amplification, the signal is downconverted by an image-rejecting mixer, filtered, and then digitized by an ADC.
The digital section of the receiver uses a coherent demodulator to generate symbols for the hardware-based MAC.
The digital receiver also contains the analog radio calibration routines, and controls the gain within the receiver
path.
The radio transmitter u
an efficient architecture in which the data stream directly modulates the VCO frequency.
An integrated PA provi
the output power. Digital logic controls Tx path and output power calibration. If the
EM358x is to be used with an external PA, use the TX_ACTIVE or nTX_ACTIVE signal to control the timing of the
external switch
logic.
The inte
ed 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24 MHz crystal with its loading
capacito
is required to establish the PLL local oscillator signal.
The MAC interfaces the on-chip RAM to the Rx and Tx baseband modules. The MAC provides hardware-based
IEEE 802.15.4-2003 packet-level filtering. It supplies an accurate symbol time base that minimizes the
s
ronization effort of the Ember software and meets the protocol timing requirements. In addition, it provides
timer and synchronization assistance for the IEEE 802.15.4-2003 CSMA-CA algorithm.
The EM358x integrates hardware support for a packet trace module, which allows robust packet-based debug.
This element is a critical component of Ember Desktop, the Ember development environment, and provides
advanced network debug capability when used with the Ember Debug Adapter (ISA3).
®
TM
The EM358
ntegrates an ARM
Cortex -M3
microprocessor, revision r1p1. This industry-leading core provides
Rev 1.1
27
EM358x
®
32-bit performance and is very power-efficient. It has excellent code density using the ARM
Thumb-2 instruction
set. The processor can be operated at 12 or 24 MHz when using the high-frequency crystal oscillator, or at 6 MHz
or 12 MHz when using the high-frequency internal RC oscillator.
EM358x parts have either 256 or 512 kB of flash memory and either 32
or 64 kB of RAM on-chip, and the ARM
configurable memory protection unit (MPU).
The EM358x implements both the ARM Serial Wire and JTAG debug interfaces. These interfaces provide real
time, non-intrusive programming and debugging capabilities. Serial Wire and JTAG provide the same functionality,
but are mutually exclusive. The Serial Wire interface uses two pins; the JTAG interface uses five. Serial
is
preferred, since it uses fewer pins.
®
The EM358x contains the ARM
Embedded Trace Macrocell (ETM) to provide advanced real time software
debugging features for complex systems.
The EM358x contains 24 GPIO pins shared with other peripheral or alternate functions. Beca
e of flexible routing
within the EM358x, external devices can use the alternate functions on a variety of different
s. The integrated
serial controller SC1 can be configured for SPI (master or slave), TWI (master-only), or UAR
peration, and the
serial controller SC2 can be configured for SPI (master or slave) or TWI (master-only) operation.
The EM358x has an optional integrated USB 2.0-compliant, full-speed (12 Mbps) device peripheral, with an on-
chip transceiver. It is available on GPIO pins.
The EM358x has a general purpose ADC which can sample analog signals from six GPIO pins in single-ended or
differential modes. It can also sample the 1.8 V regulated supply VDD_PADSA
the voltage reference VRE
F
,
a
nd
GND. The ADC has one voltage range: 0 V to 1.2 V (normal). The ADC has a DMA mode to capture samples and
automatically transfer them into RAM. The integrated voltage reference for the ADC, VRE
F
,
c
an be made available
to external circuitry. An external voltage reference can also be dri
en into the ADC. The regulator input voltage,
VDD_PADS, cannot be measured using the general purpose
, but it can be measured through Ember
software.
The EM358x contains four oscillators: a high-frequency
MHz external crystal oscillator, a high-frequency 12
MHz internal RC oscillator, an optional low-frequency 32
kHz external crystal oscillator, and a low-frequency
10 kHz internal RC oscillator.
The EM358x has an ultra low power, deep slee
tate with a choice of clocking modes. The sleep timer can be
clocked with either the external 32.768 kHz crysta
cillator or with a 1 kHz clock derived from the internal 10 kHz
RC oscillator. Alternatively, all clocks can be disabled for the lowest power mode. In the lowest power mode, only
external events on GPIO pins will wake
p the chip. The EM358x has a fast startup time (typically 110 µs) from
®
TM
deep sleep to the execution of the first A
M Cortex
-M3 instruction.
The EM358x contains three power domains. The always-on high voltage supply powers the GPIO pads and critical
chip functions. Regulated low voltage supplies power the rest of the chip. The low voltage supplies are disabled
during deep sleep to reduce power consumption. Integrated voltage regulators generate regulated 1.25 V and 1.8
V voltages from an unregu
ated supply voltage. The 1.8 V regulator output is decoupled and routed externally to
supply analog blocks, R
M, and flash memories. The 1.25 V regulator output is decoupled externally and supplies
the core logic.
EM358x parts are pin-compatible with the Ember EM351 and EM357 chips.
Note:
The EM3
x is not pin-compatible with the previous generation of Ember chip, the EM250, except for the RF section of
the
p. Pins 1-11 and 45-48 are compatible, to ease migration to the EM358x.
The follo
ng sections summarize features of the EM358x that are addressed in more detail in the
Ember EM358x
Reference Manual
.
4.1. Microprocessor
and Memory
Re
er to chapter 2 in the
Ember EM358x Reference Manual
for more information.
®
4.1.1. ARM
Cortex™-M3 Microprocessor
®
TM
The EM358x integrates the ARM
Cortex -M3
microprocessor, revision r1p1, developed by ARM Ltd., making
®
TM
the EM358x a true System-on-Chip solution. The ARM
Cortex -M3
is an advanced 32-bit modified Harvard
architectur
ocessor that has separate internal program and data buses, but presents a unified program and data
28
Rev 1.1
EM358x
address space to software.
4.1.2. Embedded Memory
Embedded memory consists of flash memory and RAM.
The EM358x provides a total of either 256 or 512 kB of flash memory. The flash memory is provided in three
separate blocks:
Main Flash Block (MFB)
Fixed Information Block (FIB)
Customer Information Block (CIB)
®
TM
The EM358x has either 32
or 64 kB of static RAM on-chip. Although the ARM
Cortex -M3
allows bit band
accesses to this address region, the standard MPU configuration does not permit use of the bit-band feature. The
RAM is physically connected to the AHB System bus and is therefore accessible to both the ARM
Cortex -M3
microprocessor and the debugger. The radio (802.15.4-2003 MAC), general purpose ADC,
device controller,
and the two serial controllers are equipped with DMA controllers, which allow them to transf
a into and out of
RAM autonomously.
TM
4.2. Interrupt
System
®
TM
The EM358x’s interrupt system is composed of two parts: a standard ARM
Cortex -M3
Nested Vectored
Interrupt Controller (NVIC) that provides top-level interrupts, and a proprietary Event Manager (EM) that provides
second-level interrupts. The NVIC and EM provide a simple hierarchy. All
econd-level interrupts from the EM feed
into top-level interrupts in the NVIC. This two-level hierarchy allows for both fine granular control of interrupt
sources and coarse granular control over entire peripherals, while allowing peripherals to have their own interrupt
vector.
Refer to chapter 3 in the
Ember EM358x Reference Manual
fo
mo
nformation.
4.2.1. Nested Vectored Interrupt Controller (NVIC)
®
TM
The ARM
Cortex -M3
Nested Vectored Interrupt Contr
(NVIC) facilitates low-latency exception and interrupt
handling. The NVIC and the processor core interfac
are closely coupled, which enables low-latency interrupt
processing and efficient processing of late-arriving
nterrupts. The NVIC maintains knowledge of the stacked
(nested) interrupts to enable tail-chaining of inte
ts. The NVIC also contains a software-configurable interrupt
prioritization mechanism.
4.2.2. Event Manager
The proprietary Event Manager provid
second-level interrupts. The Event Manager takes a large variety of
hardware interrupt sources from the peripherals and merges them into a smaller group of interrupts in the NVIC.
Effectively, all second-level interrupts from a peripheral are “OR’d” together into a single interrupt in the NVIC. In
addition, the Event Manager provides missed indicators for the top-level peripheral interrupts with the register
INT_MISS.
4.2.3. Memory Protection Unit
®
TM
The EM358x includes t
RM Cortex
-M3 Memory Protection Unit, or MPU. The MPU controls access rights
and characteristics of up to eight address regions, each of which may be divided into eight equal sub-regions.
®
TM
Refer to the AR
Cortex -M3
T
e
chnical Reference Manual (DDI 0337A) for a detailed description of the MPU.
4.3. Ra
o Module
The radio module consists of an analog front end and digital baseband.
Refer to chapter 4 in the
Ember EM358x Reference Manual
for more information.
4
. Receive (Rx) Path
The EM358x Rx path uses a low-I
F
,
s
uper-heterodyne receiver that rejects the image frequency using complex
mixing and polyphase filtering. The filtering within the Rx path improves the EM358x’s co-existence with other 2.4
GHz transceivers such as Zigbee/ 802.15.4-2003, IEEE 802.11-2007, and Bluetooth radios. The digital baseband
also provides gain control of the Rx path, both to enable the reception of small and large wanted signals and to
tolerate lar
nterferers.
Rev 1.1
29
EM358x
4.3.2. Transmit (Tx) Path
The EM358x Tx path produces an O-QPSK-modulated signal using the analog front end and digital baseband. The
area- and power-efficient Tx architecture uses a two-point modulation scheme to modulate the RF signal
generated by the synthesizer. The modulated RF signal is fed to the integrated PA and then out of the EM358x.
4.3.3. Integrated MAC Module
®
The EM358x integrates most of the IEEE 802.15.4-2003 MAC requirements in hardware. This allows the ARM
TM
Cortex -M3
CPU to provide greater bandwidth to application and network operations. In addition, the hardware
acts as a first-line filter for unwanted packets. The EM358x MAC uses a DMA interface to RAM to further
ce
®
TM
the overall ARM
Cortex -M3
CPU interaction when transmitting or receiving packets.
The primary features of the MAC are:
CRC generation, appending, and checking
Hardware timers and interrupts to achieve the MAC symbol timing
Automatic preamble and SFD pre-pending on Tx packets
Address recognition and packet filtering on Rx packets
Automatic acknowledgement transmission
Automatic transmission of packets from memory
Automatic transmission after backoff time if channel is clear (CCA)
Automatic acknowledgement checking
Time stamping received and transmitted messages
Attaching packet information to received packets (LQI, RSSI, gain, time stamp, and packet status)
EEE 802.15.4-2003 timing and slotted/unslotted timing
4.3.4. Packet Trace Interface (PTI)
The EM358x integrates a true PHY-level PTI with the MAC
allowing complete, non-intrusive capture of all packets
to and from the EM358x with Ember development tools.
4.3.5. Random Number Generator
Thermal noise in the analog circuitry is digitized t
provide entropy for a true random number generator (TRNG).
Ember software uses the TRNG to seed a pseu
andom number generator (PRNG). The TRNG is also used
directly for cryptographic key generation.
4.4. System
Modules
System modules encompass power domains, resets, clocks, system timers, power management, and encryption.
Refer to chapter 5 in the
Ember EM358x Reference Manual
for more information.
4.4.1. Power domains
The EM358x contains three power domains:
An “always-on
ain” containing all logic and analog cells required to manage the EM358x’s power
modes, including the GPIO controller and sleep timer. This domain must remain powered.
A “core domain” containing the CPU, Nested Vectored Interrupt Controller (NVIC), and peripherals.
T
o
s
ave
power,
is domain can be powered down using a mode called deep sleep. In the EM358x the core domain
includes the RAM, which by default is powered down in deep sleep. An additional feature of the RAM
is
hat blocks of RAM cells can optionally be retained in deep sleep. This is configured using a register,
which must be written before entering deep sleep.
A “flash domain” containing the flash memory. This domain is managed by the power management
controller. During deep sleep the flash portion is completely powered down.
The preferred and recommended power configuration is to use the internal regulated power supplies to provide
power to the core and memory domains. Optionally, the on-chip regulators may be left unused, and the core and
memory domains may instead be powered from external supplies.
Refer to chapter 6 in the
Ember EM358x Reference Manual
for more information.
30
Rev 1.1
EM358x
4.4.2. Resets
The EM358x resets are generated from a number of sources. Each of these reset sources feeds into central reset
detection logic that causes various parts of the system to be reset depending on the state of the system and the
nature of the reset event. Reset sources include:
Power-On-Resets (POR HV and POR LV)
nRESET Pin
Watchdog Reset
Software Reset
Option Byte Error
Debug Reset
JRST
Deep Sleep Reset
The EM358x records the last reset condition that generated a restart to the system. The Rese
eneration module
responds to reset sources and generates reset signals, which vary based on the reset source and cause.
4.4.3. Clocks
The EM358x integrates four oscillators:
12 MHz RC oscillator: Used as the default system clock source when power is applied to the core domain.
24 MHz crystal oscillator: Requires an external 24 MHz crystal. Used as the system clock source when all
peripherals, including the radio peripheral, require the most accurate clock.
10 kHz RC oscillator: Provided as an internal timing reference
32.768 kHz crystal oscillator: Provided as an optional
imi
ference for on-chip timers.
4.4.4. System Timers
The EM358x contains three system timers:
®
TM
Watchdog Timer: Can be enabled to provide protec
on against software crashes and ARM
Cortex -M3
CPU lockup.
Sleep Timer: 32-bit timer dedicated to sy
m timing and waking from sleep at specific times.
®
Event Timer: An ARM
standard system timer in the NVIC.
4.4.5. Power Management
The EM358x’s power management sys
em is designed to achieve the lowest deep sleep current consumption
possible while still providing flexible wakeup sources, timer activity, and debugger operation. The EM358x has four
main sleep modes:
Idle Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All
power domains remain fully powered and nothing is reset.
Deep Sleep 1:
primary deep sleep state. In this state, the core power domain is fully powered down
and the sleep ti
is active.
Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this
mode t
sleep timer cannot wake up the EM358x.
p Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep sleep without
p
wering down the core domain. Instead, the core domain remains powered and all peripherals except the
system debug components (ITM, DW
T
,
F
PB, NVIC) are held in reset. The purpose of this sleep state is to
allow EM358x software to perform a deep sleep cycle while maintaining debug configuration such as
breakpoints.
The deep sleep modes consume less than 2 µA power. When in deep sleep the EM358x can be returned to the
running state in a number of ways. The wake sources are split depending on deep sleep 1 or deep sleep 2.
The RAM can optionally be configured to select banks of locations to be non-volatile. In deep sleep those banks
selected are powered by a low leakage internal regulator that remains on during deep sleep, powered from the
always-on
ply.
Rev 1.1
31
EM358x
4.5. Integrated
Voltage Regulator
The EM358x integrates two low dropout regulators to provide 1.8 V and 1.25 V power supplies. The 1V8 regulator
supplies the analog and memories, and the 1V25 regulator supplies the digital core. In deep sleep the voltage
regulators are disabled. An external 1.8 V regulator may replace both internal regulators. The always-on domain
needs to be minimally powered at 2.1 V, and cannot be powered from the external 1.8 V regulator.
Refer to chapter 6 in the Ember EM358x Reference Manual for more information.
4.6. Peripherals
4.6.1. GPIO
The EM358x has 24 multi-purpose GPIO pins, which may be individually configured as:
General purpose output
General purpose open-drain output
Alternate output controlled by a peripheral device
Alternate open-drain output controlled by a peripheral device
Analog
General purpose input
General purpose input with pull-up or pull-down resistor
The 24 GPIO pins are grouped into three ports. Each pin has a 4-bit co
figura
ion value in its GPIO_PxCFGH/L
register. If a GPIO has two peripherals that can be the source of alternate output mode data, then other registers in
addition to GPIO_PxCFGH/L determine which peripheral cont
ols the output. For some GPIOs the
GPIO_PxCFGH/L configuration will be overridden. These functions are forced when the EM358x is reset and
remain forced until software or an external debugger overrides the
ed functions.
Refer to chapter 7 in the
Ember EM358x Reference Manual
for more information.
4.6.2. Serial Controllers
The EM358x has two serial controllers, SC1 and SC2, which provide several options for full-duplex synchronous
and asynchronous serial communications.
SPI (Serial Peripheral Interface), master
ave
TWI (Two Wire serial Interface), master only
UART (Universal Asynchronous Receiver/Transmitter), SC1 only
Receive and transmit FIFOs and DMA channels, SPI and UART modes
Both SC1 and SC2 SPI controllers include an SPI master controller with the following features:
Full duplex operation
Programmable clock frequency (12 MHz max.)
Programmable clock polarity and phase
Selectable dat
t direction (either LSB or MSB first)
Receive and transmit FIFOs
Receive and transmit DMA channels
Both SC1
nd
C2 SPI controllers include a SPI slave controller with these features:
l duplex operation
Up to 5 Mbps data transfer rate
Programmable clock polarity and clock phase
Selectable data shift direction (either LSB or MSB first)
Slave select input
Both SC1 and SC2 include a Two Wire serial Interface (TWI) master controller with the following features:
Uses only two bidirectional GPIO pins
Pro
ammable clock frequency (up to 400 kHz)
Supports both 7-bit and 10-bit addressing
32
Rev 1.1
EM358x
Compatible with Philips’ I2C-bus slave devices
The SC1 UART supports the following features:
Flexible baud rate clock (300 bps to 921.6 kbps)
Data bits (7 or 8)
Parity bits (none, odd, or even)
Stop bits (1 or 2)
False start bit and noise filtering
Receive and transmit FIFOs
Optional RTS/CTS flow control
Receive and transmit DMA channels
Receive and transmit FIFOs allow faster data speeds using byte-at-a-time interrupts. For the h
ghest SPI and
UART speeds, dedicated receive and transmit DMA channels reduce CPU loading and ex
e allowable time
to service a serial controller interrupt.
Refer to chapter 8 in the
Ember EM358x Reference Manual
for more information.
4.6.3. USB
EM3582, EM3586 and EM3588 variants have a USB 2.0-compliant full-speed
Mbps) device peripheral, with
on-chip transceiver.
It supports up to six endpoints (in addition to the control endpoint 0). There are five endpoints that can be used as
either interrupt or bulk and one isochronous endpoint.
The USB peripheral is interfaced to the CPU through memory mapped registers for control, and DMA for data. The
USB device generates its own 48 MHz internal clock from the mai
MHz crystal clock.
The EM358x, where applicable, fully supports USB suspend and resume modes, and meets the USB specification
suspend current of <2.5mA. It achieves this by switching the chip to run from a divided down version of the system
clock.
Refer to chapter 9 in the Ember EM358x Reference M
ual for more information.
4.6.4. General Purpose Timers
Each of the EM358x’s two general-purpose t
rs consists of a 16-bit auto-reload counter driven by a
programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of
input signals (input capture) or generat
g output waveforms (output compare and PWM). Pulse lengths and
waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler.
The timers are completely independent, and do not share any resources. They can be synchronized together.
The two general-purpose timers, TIM1 and TIM2, have the following features:
16-bit up, down, or up/down auto-reload counter.
Programmable prescaler to divide the counter clock by any power of two from 1 through 32768.
4 independent
nels for:
Input capture
Output compare
PW
generation (edge- and center-aligned mode)
One-pulse mode output
S
nchronization circuit to control the timer with external signals and to interconnect the timers.
Flexible clock source selection:
Peripheral clock (PCLK at 6 or 12 MHz)
32.768 kHz external clock (if available)
1 kHz clock
GPIO input
Interrupt generation on the following events:
Update: counter overflow/underflow, counter initialization (software or internal/external trigger)
gger event (counter start, stop, initialization or count by internal/external trigger)
Rev 1.1
33
EM358x
Input capture
Output compare
Supports incremental (quadrature) encoders and Hall sensors for positioning applications.
Trigger input for external clock or cycle-by-cycle current management.
Refer to chapter 10 in the
Ember EM358x Reference Manual
for more information.
4.6.5. Analog-to-Digital Converter (ADC)
The EM358x ADC is a first-order sigma-delta converter with the following features:
Resolution of up to 14 bits
Sample times as fast as 5.33 µs (188 kHz)
Differential and single-ended conversions from six external and four internal sources
One voltage range (differential): -VREF to +VREF
Choice of internal or external VREF
internal VREF may be output to PB0 or external VREF may be derived from PB0
Digital offset and gain correction
Dedicated DMA channel with one-shot and continuous operating modes
Refer to chapter 11 in the
Ember EM358x Reference Manua
l for more informatio
4.7. Debugging
The EM358x utilizes standard Serial Wire and JTAG interfaces for powerful software debugging and programming
®
TM
®
of the ARM
Cortex -M3
core. The EM358x integrates the standa
d ARM
system debug components: Flash
Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT), and Instrumentation Trace Macrocell (ITM) as
well as the advanced Embedded Trace Macrocell (ETM).
4.7.1. Trace Port Interface Unit (TPIU)
The EM358x integrates the standard ARM® Trace Port
rface Unit (TPIU). The TPIU receives a data stream
®
from the on-chip trace data generated by the standard
RM Instrument
Trace Macrocell (ITM) and ARM®
Embedded Trace Macrocell (ETM), buffers the data i
a FIFO for the ITM and FIFO for the ETM, formats the data,
and serializes the data to be sent off chip through
ternate functions of the GPIO.
Refer to chapter 12 in the
Ember EM358x Referen
Manual
for more information.
4.7.2. Instrumentation Trace Macrocell (ITM)
®
The EM358x integrates the standard A
M Instrumentation
Trace Macrocell (ITM). The ITM is an application-
driven trace source that supports printf style debugging to trace software events and emits diagnostic system
®
information from the ARM
Data Watchpoint and Trace (DWT). Software using the ITM generates Software
Instrumentation Trace (SWIT). In addition, the ITM provides coarse-grained timestamp functionality.
Refer to chapter 13 in the
Ember EM358x Reference Manual
for more information.
4.7.3. Embedded Trace Macrocell (ETM)
®
The EM358x integrates
standard ARM
Embedded Trace Macrocell (ETM) version 3.4. The ETM is a powerful
debug component that enables reconstruction of program execution. It is designed as a high-speed, low-power
debug tool that
ly supports instruction trace.
Refer to
pter 14 in the
Ember EM358x Reference Manual
for more information.
4.7.4. Da
Watchpoint and Trace (DWT)
The EM358x integrates the standard ARM® Data Watchpoint and Trace (DWT). The DWT provides hardware
support for profiling and debugging functionality. The DWT offers the following features:
PC sampling
Comparators to support:
Watchpoints – enters debug state
Data tracing
Cycle count matched PC sampling
Exception trace support
34
Rev 1.1
EM358x
Instruction cycle count calculation support
Refer to chapter 15 in the
Ember EM358x Reference Manual
for more information.
4.7.5. Flash Patch and Breakpoint (FPB)
®
The EM358x integrates the standard ARM
Flash Patch and Breakpoint (FPB). The FPB implements hardware
breakpoints. The FPB also provides support for remapping of specific instruction or literal locations from flash
memory to an address in RAM memory. The FPB contains:
Two literal comparators for matching against literal loads from flash space, and remapping to a
corresponding RAM space.
Six instruction comparators for matching against instruction fetches from flash space, and remapping to a
corresponding RAM space. Alternatively, the comparators can be individually configured to return a
breakpoint instruction to the processor core on a match, implementing hardware breakpoi
apability.
Refer to chapter 16 in the
Ember EM358x Reference Manual
for more information.
4.7.6. Serial Wire and JTAG (SWJ) Interface
The EM358x includes a standard Serial Wire and JTAG (SWJ) Interface. The SWJ is the primary debug and
programming interface of the EM358x. The SWJ gives debug tools access to the internal buses of the EM358x,
and allows for non-intrusive memory and register access as well as CPU halt-step style debugging. Therefore, any
design implementing the EM358x should make the SWJ signals readily available
®
Serial Wire is an ARM
standard, bi-directional, two-wire protocol designed to replace JTA
G
,
a
nd provides all the
normal JTAG debug and test functionality. JTAG is a standard five-wire protocol providing debug and test
functionality. In addition, the two Serial Wire signals (SWDIO and SWCLK) are overlaid on two of the JTAG signals
(JTMS and JTCK). This keeps the design compact and allows debug tools to switch between Serial Wire and JTAG
as needed, without changing pin connections.
While Serial Wire and JTAG offer the same debug and test functionality, Silicon Labs recommends Serial Wire.
Serial Wire uses only two pins instead of five, and offers a simple communication protocol, high performance data
rates, low power, built-in error detection, and protection fr
glitches.
The SWJ pins are forced functions, and their corresp
ding GPIO_PxCFGH/L configurations are overridden when
the EM358x resets.
Refer to chapter 17 in the
Ember EM358x Refere
Manual
for more information.
Rev 1.1
35
EM358x
5. Ordering
Information
Use the following part number to order the EM358x:
Orderable Part
Number
Package materials / quantity
Flash (kB)
RAM (kB)
USB
EM3581-RTR
EM3582-RTR
*
EM3585-RTR
EM3586-RTR
EM3587-RTR
EM3588-RTR
T
a
pe & Reel, contains 2000 units/reel
T
a
pe & Reel, contains 2000 units/reel
T
a
pe & Reel, contains 2000 units/reel
T
a
pe & Reel, contains 2000 units/reel
T
a
pe & Reel, contains 2000 units/reel
T
a
pe & Reel, contains 2000 units/reel
256
256
512
512
512
51
32
32
3
64
64
No
Yes
No
Yes
No
Yes
*Note
: This part is EOL.
To
o
rder parts, contact Silicon Labs at 1+(877) 444-3032, or find a sales office or distributor on our website,
36
Rev 1.1
EM358x
6. Pin
Assignments
48 47 46 45 44 43 42 41 40 39 38 37
VDD_24MHZ
VDD_VCO
RF_P
1
2
36
35
34
33
32
31
30
29
28
27
26
25
PB0, VREF, IRQA, TRACEDATA2, TIM1CLK, TIM2MSK
PC4, JTMS, SWDIO
49
GND
3
PC3, JTDI, TRACEC
RF_N
4
PC2, JTDO, SWO, TRACEDATA0
SWCLK, JTCK
VDD_RF
5
RF_TX_ALT_P
RF_TX_ALT_N
VDD_IF
6
P
2, SC1MISO, SC1MOSI, SC1SCL, SC1RXD, TIM2C2
B1, SC1MISO, SC1MOSI, SC1SDA, SC1TXD, TIM2C1
PA6, TIM1C3
EM358x
7
8
NC
9
VDD_PADS
VDD_PADSA
PC5, TX_ACTIVE
nRESET
10
11
12
PA5, ADC5, PTI_DATA, nBOOTMODE, TRACEDATA3
PA4, ADC4, PTI_EN, TRACEDATA2
PA3, SC2nSSEL, TIM2C2
13 14 15 16 17 18 19 20 21 22 23 24
Figure 6.1. EM358x Pin Definitions
Refer to Chapter 7, GPIO, in the
Ember EM358x Reference Manual
for details about selecting GPIO pin
functions.
Rev 1.1
37
EM358x
Table 6.1. EM358x Pin Descriptions
Pin #
Signal
Direction
Description
1
2
VDD_24MHZ
VDD_VCO
RF_P
Power
Power
I/O
1.8 V high-frequency oscillator supply
1.8 V VCO supply
3
Differential (with RF_N) receiver input/transmitter output
Differential (with RF_P) receiver input/transmitter output
1.8 V RF supply (LNA and PA)
4
RF_N
I/O
5
VDD_RF
RF_TX_ALT_P
RF_TX_ALT_N
VDD_IF
Power
O
6
Differential (with RF_TX_ALT_N) transmitter output (
al)
Differential (with RF_TX_ALT_P) transmitter output (optional)
1.8 V IF supply (mixers and filters)
Do not connect
7
O
8
Power
9
NC
10
11
VDD_PADSA
PC5
Power
I/O
Analog pad supply (1.8 V)
Digital I/O
TX_ACTIVE
O
Logic-level control for exter
RX/TX switch. The EM358x baseband con-
trols TX_ACTIVE and drives it high (VDD_PADS) when in TX mode.
Select alternate out
ut function with GPIO_PCCFGH[7:4]
12
13
nRESET
PC6
I
Active low chip
set (internal pull-up)
Digital I/O
I/O
I/O
OSC32B
32.768 kHz crystal oscillator
Select analog function with GPIO_PCCFGH[11:8]
nTX_ACTIVE
O
Inverted TX_ACTIVE signal (see PC5)
Select alternate output function with GPIO_PCCFGH[11:8]
14
PC7
I/O
I/O
Digital I/O
OSC32A
32.768 kHz crystal oscillator
Select analog function with GPIO_PCCFGH[15:12]
OSC32_EXT
VRE
_OUT
VDD_PADS
VDD_CORE
I
Digital 32.768 kHz clock input source
Regulator output (1.8 V while awake, 0 V during deep sleep)
Pads supply (2.1–3.6 V)
15
16
Power
Power
Power
17
1.25 V digital core supply decoupling
:
1.
IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.
38
Rev 1.1
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
Direction
Description
18
PA7
I/O
Digital I/O
High
Disable REG_EN with GPIO_DBGCFG[4]
current
TIM1C4
O
Timer 1 Channel 4 output
Enable timer output with TIM1_CCER
Select alternate output function with GPIO_PACFGH[15:12]
Disable REG_EN with GPIO_DBGCFG[4]
TIM1C4
REG_EN
PB3
I
Timer 1 Channel 4 input
Cannot be remapped
O
External regulator open drain output
Enabled after reset
19
I/O
O
Digital I/O
TIM2C3
Timer 2 channel 3 output
(see also Pin 22)
Enable remap with TIM2_OR[6]
Enable timer output in TIM2_CCER
Select alternate output func
with GPIO_PBCFGL[15:12]
TIM2C3
(see also Pin 22)
I
I
Timer 2 channel 3 input
Enable remap with TIM2_OR[6]
SC1nCTS
UART CTS handshake of Serial Controller 1
Enable with SC1_UARTCFG[5]
Select UA
with SC1_MODE
SC1SCLK
O
SPI master clock of Serial Controller 1
Eit
er disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[6]
Enable master with SC1_SPICFG[4]
Select SPI with SC1_MODE
Select alternate output function with GPIO_PBCFGL[15:12]
SC1SCLK
I
SPI slave clock of Serial Controller 1
Enable slave with SC1_SPICFG[4]
Select SPI with SC1_MODE
Note:
1.
IR
an
IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
_IRQDSEL registers.
Rev 1.1
39
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
Direction
Description
20
PB4
I/O
O
Digital I/O
TIM2C4
Timer 2 channel 4 output
(see also Pin 24)
Enable remap with TIM2_OR[7]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PBCFGH[3:0]
TIM2C4
I
Timer 2 channel 4 input
(see also Pin 24)
Enable remap with TIM2_OR[7]
SC1nRTS
O
UART RTS handshake of Serial Controller 1
Either disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[7]
Enable with SC1_UARTCFG[5]
Select UART with SC1_MODE
Select alternate output function with GPIO_PBCFGH[3:0]
SC1nSSEL
PA0
I
SPI slave select of Serial Controller 1
Enable slave with SC1_SPICFG[4]
Select SPI with SC1_MODE
21
I/O
I/O
Digital I/O
USBDM (where
applicable)
USB D- signal
Select analog func
with GPIO_PACFGL[3:0]
TIM2C1
O
Timer 2 chann
1 output
(see also Pin 30)
Disable re
with TIM2_OR[4]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[3:0]
TIM2C1
I
Timer 2 channel 1 input
(see also Pin 30)
Disable remap with TIM2_OR[4]
SC2MOSI
O
SPI master data out of Serial Controller 2
Either disable timer output in TIM2_CCER,
or enable remap with TIM2_OR[4]
Enable master with SC2_SPICFG[4]
Select SPI with SC2_MODE
Select alternate output function with GPIO_PACFGL[3:0]
C2MOSI
I
SPI slave data in of Serial Controller 2
Enable slave with SC2_SPICFG[4]
Select SPI with SC2_MODE
:
.
IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.
40
Rev 1.1
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
Direction
I/O
Description
22
PA1
Digital I/O
USBDP (where
applicable)
I/O
USB D+ signal
Select analog function with GPIO_PACFGL[7:4]
TIM2C3
O
Timer 2 channel 3 output
(see also Pin 19)
Disable remap with TIM2_OR[6]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[7:4]
TIM2C3
I
Timer 2 channel 3 input
(see also Pin 19)
Disable remap with TIM2_OR[6]
SC2SDA
I/O
TWI data of Serial Controller 2
Either disable timer output in TIM2_CCER,
or enable remap with TIM2_OR[6]
Select TWI with SC2_MODE
Select alternate open-drain output function with GPIO_PACFGL[7:4]
SC2MISO
O
SPI slave data out of Serial Controller 2
Either disable timer output
M2_CCER,
or enable remap with TIM2_
[6]
Enable slave with SC2_SPICFG[4]
Select SPI with SC
MODE
Select alternate outp
t function with GPIO_PACFGL[7:4]
SC2MISO
I
SPI master data in of Serial Controller 2
Enable sla
ith SC2_SPICFG[4]
Selec
SPI with SC2_MODE
23
VDD_PADS
Power
P
s supply (2.1–3.6 V)
Note:
1.
IRQC and IRQD external inte
rupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.
Rev 1.1
41
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
Direction
Description
24
PA2
I/O
O
Digital I/O
TIM2C4
Timer 2 channel 4 output
(see also Pin 20)
Disable remap with TIM2_OR[7]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[11:8]
TIM2C4
I
Timer 2 channel 4 input
(see also Pin 20)
Disable remap with TIM2_OR[7]
SC2SCL
I/O
TWI clock of Serial Controller 2
Either disable timer output in TIM2_CCER,
or enable remap with TIM2_OR[7]
Select TWI with SC2_MODE
Select alternate open-drain output functio
ith GPIO_PACFGL[11:8]
SC2SCLK
O
SPI master clock of Serial Controller 2
Either disable timer output in TIM2_CCER,
or enable remap with TIM2_OR[7]
Enable master with SC2_SPICFG[4]
Select SPI with SC2_MOD
Select alternate output function with GPIO_PACFGL[11:8]
SC2SCLK
I
SPI slave clock of
ial Controller 2
Enable slave with S
_SPICFG[4]
Select SPI wit
SC2_MODE
25
PA3
I/O
I
Digital I/O
SC2nSSEL
SPI slave select of Serial Controller 2
E
ble slave with SC2_SPICFG[4]
Select SPI with SC2_MODE
TIM2C2
(see also Pin 31)
O
I
Timer 2 channel 2 output
Disable remap with TIM2_OR[5]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[15:12]
TIM2C2
Timer 2 channel 2 input
(see also Pin 31)
Disable remap with TIM2_OR[5]
Note:
1.
I
C and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.
42
Rev 1.1
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
PA4
Direction
Description
26
I/O
Digital I/O
ADC4
Analog ADC
Input 4
Select analog function with GPIO_PACFGH[3:0]
PTI_EN
O
O
Frame signal of Packet Trace Interface (PTI)
Disable trace interface in ARM core
Enable PTI in Ember software
Select alternate output function with GPIO_PACFGH[3:0]
TRACEDATA2
Synchronous CPU trace data bit 2
(see also Pin 36)
Select 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PACFGH[3:0]
27
PA5
I/O
Digital I/O
ADC5
Analog ADC
Input 5
Select analog function with GPIO_PACFGH[7:4]
PTI_DATA
O
I
Data signal of Packet Trace Interface (PTI)
Disable trace interface
n A
ore
Enable PTI in Ember software
Select alternate out
ut function with GPIO_PACFGH[7:4]
nBOOTMODE
Activate FIB monitor
nstead of main program or bootloader when coming
out of reset.
Signal is a
e during and immediately after a reset on nRESE
T
.
R
efer to
section 7.5,
oot Configuration, in Chapter 7, GPIO, of the
Ember EM358x
Reference Manual
for details.
TRACEDATA3
O
S
nchronous CPU trace data bit 3
(see also Pin 38)
Select 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PACFGH[7:4]
28
29
VDD_PADS
PA6
Power
Pads supply (2.1–3.6 V)
Digital I/O
I/O
High cur-
rent
TIM1C3
TIM1C3
O
Timer 1 channel 3 output
Enable timer output in TIM1_CCER
Select alternate output function with GPIO_PACFGH[11:8]
I
Timer 1 channel 3 input
Cannot be remapped
Note:
1.
IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.
Rev 1.1
43
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
Direction
Description
30
PB1
I/O
O
Digital I/O
SC1MISO
SPI slave data out of Serial Controller 1
Either disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[4]
Select SPI with SC1_MODE
Select slave with SC1_SPICFG
Select alternate output function with GPIO_PBCFGL[7:4]
SC1MOSI
O
SPI master data out of Serial Controller 1
Either disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[4]
Select SPI with SC1_MODE
Select master with SC1_SPICFG
Select alternate output function with GPIO
PBCFGL[7:4]
SC1SDA
SC1TXD
I/O
O
TWI data of Serial Controller 1
Either disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[4]
Select TWI with SC1_MOD
Select alternate open-d
ain
put function with GPIO_PBCFGL[7:4]
UART transmit data of Serial Controller 1
Either disable time
put in TIM2_CCER,
or disable rem
with TIM2_OR[4]
Select UART w
th SC1_MODE
Select alte
e output function with GPIO_PBCFGL[7:4]
TIM2C1
(see also Pin 21)
O
I
Timer 2 channel 1 output
E
ble remap with TIM2_OR[4]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[7:4]
TIM2C1
Timer 2 channel 1 input
(see also Pin 21)
Disable remap with TIM2_OR[4]
Note:
1.
IRQC and IRQD ex
rnal interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.
44
Rev 1.1
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
PB2
Direction
Description
31
I/O
I
Digital I/O
SC1MISO
SPI master data in of Serial Controller 1
Select SPI with SC1_MODE
Select master with SC1_SPICFG
SC1MOSI
SC1SCL
I
SPI slave data in of Serial Controller 1
Select SPI with SC1_MODE
Select slave with SC1_SPICFG
I/O
TWI clock of Serial Controller 1
Either disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[5]
Select TWI with SC1_MODE
Select alternate open-drain output function
ith GPIO_PBCFGL[11:8]
SC1RXD
I
UART receive data of Serial Controller 1
Select UART with SC1_MODE
TIM2C2
O
Timer 2 channel 2 output
(see also Pin 25)
Enable remap with TIM2_O
5]
Enable timer output in TIM2
CER
Select alternate output function with GPIO_PBCFGL[11:8]
TIM2C2
I
Timer 2 channel 2
t
(see also Pin 25)
Enable remap
h TIM2_OR[5]
32
SWCLK
I/O
I
Serial Wir
ock input/output with debugger
Selected wh
n in Serial Wire mode (see JTMS description, Pin 35)
JTCK
JTAG clock input from debugger
S
ec
ed when in JTAG mode (default mode, see JTMS description,
Pin 35)
Internal pull-down is enabled
Note:
1.
IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL r
sters.
Rev 1.1
45
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
Direction
Description
33
PC2
I/O
Digital I/O
Enable with GPIO_DBGCFG[5] and GPIO_PCCFGH[1] clear
JTDO
O
O
JTAG data out to debugger
Selected when in JTAG mode (default mode, see JTMS description,
Pin 35)
SWO
Serial Wire Output asynchronous trace output to debugger
Select asynchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[
Enable Serial Wire mode (see JTMS description, Pin 35
Internal pull-up is enabled
TRACEDATA0
O
Synchronous CPU trace data bit 3
Select 4-wire synchronous trace interface
n ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PACFGL[11:8]
34
PC3
JTDI
I/O
I
Digital I/O
Either Enable with GPIO_D
CFG[5],
or enable Serial Wire mode (
ee JTMS description)
JTAG data in from d
bugger
Selected when in J
mode (default mode, see JTMS description,
Pin 35)
Internal pul
up is enabled
TRACECLK
O
Synchronous CPU trace clock
Enable trace interface in ARM core
S
ect alternate output function with GPIO_PCCFGL[15:12]
35
PC4
I/O
I
Digital I/O
Enable with GPIO_DBGCFG[5]
JTMS
JTAG mode select from debugger
Selected when in JTAG mode (default mode)
JTAG mode is enabled after power-up or by forcing nRESET low
Select Serial Wire mode using the ARM-defined protocol through a debug-
ger
Internal pull-up is enabled
SWDIO
I/O
Serial Wire bidirectional data to/from debugger
Enable Serial Wire mode (see JTMS description)
Select Serial Wire mode using the ARM-defined protocol through a debug-
ger
Internal pull-up is enabled
Note:
1.
IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.
46
Rev 1.1
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
PB0
Direction
Description
36
I/O
Digital I/O
VREF
Analog O
ADC reference output
Enable analog function with GPIO_PBCFGL[3:0]
VREF
Analog I
ADC reference input
Enable analog function with GPIO_PBCFGL[3:0]
Enable reference output with an Ember system function
IRQA
I
External interrupt source A
TRACEDATA2
O
Synchronous CPU trace data bit 2
(see also Pin 26)
Select 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PBCFGL[3:0]
TIM1CLK
TIM2MSK
VDD_PADS
PC1
I
I
Timer 1 external clock input
Timer 2 external clock mask input
Pads supply (2.1–3.6 V)
Digital I/O
37
38
Power
I/O
ADC3
Analog ADC
Input 3
Enable analog fun
with GPIO_PCCFGL[7:4]
TRACEDATA3
O
Synchronous
PU trace data bit 3
(see also Pin 27)
Select 1-,
r 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[7:4]
39
40
VDD_MEM
PC0
Power
1.
V supply (flash, RAM)
I/O
Digital I/O
High
Either enable with GPIO_DBGCFG[5],
current or
enable Serial Wire mode (see JTMS description, Pin 35) and disable
TRACEDATA1
JRST
I
JTAG reset input from debugger
Selected when in JTAG mode (default mode, see JTMS description) and
TRACEDATA1 is disabled
Internal pull-up is enabled
1
IRQD
I
Default external interrupt source D.
TRACEDATA1
O
Synchronous CPU trace data bit 1
Select 2- or 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[3:0]
Note:
1.
IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPI
RQDSEL registers.
Rev 1.1
47
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
Direction
Description
41
PB7
I/O
Digital I/O
High
current
ADC2
Analog ADC
Input 2
Enable analog function with GPIO_PBCFGH[15:12]
1
IRQC
I
Default external interrupt source C.
TIM1C2
O
Timer 1 channel 2 output
Enable timer output in TIM1_CCER
Select alternate output function with GPIO_PBCFGH[15
2]
TIM1C2
PB6
I
Timer 1 channel 2 input
Cannot be remapped
42
I/O
Digital I/O
High
current
ADC1
Analog ADC
Input 1
Enable analog function with
O_PBCFGH[11:8]
IRQB
I
External interrupt source B
TIM1C1
O
Timer 1 channel 1
ut
Enable timer o
put in TIM1_CCER
Select alter
ate output function with GPIO_PBCFGH[11:8]
TIM1C1
I
Timer 1 channel 1 input
Cannot be remapped
43
PB5
I/O
Di
ital I/O
ADC0
Analog ADC
Input 0
Enable analog function with GPIO_PBCFGH[7:4]
TIM2CLK
TIM1MSK
VDD_CORE
DD_PRE
VDD_SYNTH
OSCB
I
Timer 2 external clock input
Timer 1 external clock mask input
1.25 V digital core supply decoupling
1.8 V prescaler supply
I
44
45
46
47
Power
Power
Power
I/O
1.8 V synthesizer supply
24 MHz crystal oscillator or left open when using external clock input on
OSCA
Note:
1.
IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.
48
Rev 1.1
EM358x
Table 6.1. EM358x Pin Descriptions (Continued)
Pin #
Signal
Direction
Description
48
OSCA
I/O
24 MHz crystal oscillator or external clock input.
(An external clock input should only be used for test and debug purposes.
If used in this manner, the external clock input should be a 1.8 V, 50% duty
cycle, square wave.)
49
GND
Ground Ground
supply pad in the bottom center of the package forms Pin 49.
e
the various Ember
EM358x Reference Design
documentation for PCB con-
siderations.
Note:
1.
IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQ
and
GPIO_IRQDSEL registers.
Rev 1.1
49
EM358x
6.1. Mechanical
Details
The EM358x package is a plastic 48-pin QFN that is 7 mm x 7 mm x 0.90 mm. Figure 6.2 illustrates the package
drawing.
Figure 6.2. Package Drawing
50
Rev 1.1
EM358x
Table 6.2. Package Dimensions
Dimension
Min
0.80
0
Nom
0.85
Max
0.90
0.05
0.67
A
A1
A2
A3
b
0.035
0.65
—
0.203 REF
0.25
0.2
0.3
D
7 BSC
7 BSC
0.5 BSC
5.3
E
e
J
5.2
5.2
5.4
5.4
K
5.3
L
0.35
0.40
0.45
aaa
bbb
ccc
ddd
eee
0.10
0.1
0.08
0.1
0.1
Notes:
1.
All dimensions shown are in mi
ime
mm) unless
otherwise noted.
2.
Dimensioning and
T
o
lerancing per ANSI Y14.5M-1994.
3.
This drawing conforms to
JEDEC Solid State Outline
MO-220, Variation VKKD-4
4.
Recommended card
ow profile is per the JEDEC/IPC J-
STD-020 specifica
on for Small Body Components.
Rev 1.1
51
EM358x
6.1.1. QFN48 Footprint Recommendations
Figure 6.3 demonstrates the IPC-7351 recommended PCB Footprint for the EM358x (QFN50P700X700X90-49N).
A ground pad in the bottom center of the package forms a 49th pin.
A 3 x 3 array of non-thermal vias should connect the EM358x decal center shown in Figure 6.3 to the PCB ground
plane through the ground pad. In order to properly solder the EM358x to the footprint, the Paste Mask layer should
have a 3 x 3 array of circular openings at 1.015 mm diameter spaced approximately 1.625 mm (center to center)
apart, as shown in Figure 6.4. This will cause an evenly distributed solder flow and coplanar attachment to the
PCB. The solder mask layer (illustrated in Figure 6.5) should be the same as the copper layer for the E
8x
footprint.
For more information on the package footprint, please refer to the appropriate
EM358x Reference Design
.
X2
Via Drill DIA = 0.254mm
b2
b0
MIN
P
MAX
a1
C1
C2
1
X2
Y1
Y2
E
a0
a1
a2
6.85
6.85
E
0.30
5.35
0.90
5.35
0.50
1.80
1.625
0.75
b1
C2
Y2
b0
b1
b2
1.80
1.625
0.75
* Dimensions in mm
* Dimensions are for
Figures 19-2, 19-3
and 19-4
a2
X1
a0
C1
Figure 6.3. PCB Footprint for the EM358x
a1
a0
DIA = 1.01mm
b0
b1
C2
Y1
E
X1
C1
Figure 6.4. Paste Mask
52
Rev 1.1
EM358x
Figure 6.5. Solder Mask Dimensions
Rev 1.1
53
EM358x
Table 6.3. PCB Land Pattern
Dimension
Min
6.80
6.80
Max
6.90
6.90
C1
C2
E
0.50 BSC
X1
X2
Y1
Y2
0.20
5.20
0.75
5.20
0.30
5.40
0.85
5.4
Notes:
General
1. All
dimensions shown are in millimeters (mm) unless otherwise noted.
2. This
Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All
metal pads are to be non-solder mask defined (NSMD). Clearance between t
e solder mask and the metal pad is
to be 60mm minimum, all the way around the pad.
Stencil Design
1. A
stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
2. The
stencil thickness should be 0.125 mm (5 mils).
3. The
ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A
4×4 array of 1.1 mm square openings on 1.3 mm pitch should be used for the center ground pad.
Card Assembly
1. A
No-Clean, Type-3 solder paste is recommended.
2. The
recommended card reflow profile is per the J
DEC/IPC J-STD-020C specification for Small Body Components.
6.1.2. Solder Temperature Profile
Figure 6-6 illustrates the solder temperature profile for the EM358x. This temperature profile is similar for other
RoHS compliant packages, but manufa
ring lines should be programmed with this profile in order to guarantee
proper solder connection to the PCB.
54
Rev 1.1
EM358x
Temperature
Tpeak
Ramp-up
Ramp-down
T
L
Tsoak
max
Tsoak
Tsoak
min
t
soak
25C
time
t
peak
t
25C t
o
t
peak
Figure 6.6. EM358x Reflow Profile
Rev 1.1
55
EM358x
T
a
ble 6.4 contains the temperature profile parameters.
Table 6.4. Solder Reflow Parameters
Parameter
Value
Average Ramp Up Rate (from
T
s
oakmax to Tpeak)
Minimum Soak
T
e
mperature (
T
s
oakmin)
Maximum Soak
T
e
mperature (
T
s
oakmax)
TL
3°C per second max
150°C
200°C
217°C
Time above TL
60 – 150 seconds
260 + 0°C
Tpeak
Time within 5°C of Tpeak
Ramp Down Rate
20 – 40 seconds
6°C per sec
d max
8 minutes, max
Time from 25°C to Tpeak
6.2. Part
Marking
Figure 6.7 shows the part marking for the EM358x Series. The c
in the top corner indicates Pin 1. Pins are
numbered counter-clockwise from Pin 1 with 12 pins per package e
e.
Figure 6.7. Part Marking for EM358x
Table 6.5. 48-Pin QFN Top Marking Explanation
Mark Method:
1 Marking:
Laser
Circle = 0.40 mm Diameter
(
T
o
p-Left Justified)
Line 1 Marking:
Device Part Number
Right Justified
EM358x
EM358x is the Orderable Part Number variant
(EM3581/2/5/6/7/8)
56
Rev 1.1
EM358x
Table 6.5. 48-Pin QFN Top Marking Explanation
Line 2 Marking:
Line 3 Marking:
TTTTTT = Mfg Code
YY=Year
WW-Work Week
Manufacturing Code from the Assembly Purchase
form. Assigned by the Assembly House. Corre-
sponds to the year and work week.
Right Justified
Circle = 1.3 mm Diameter
Center Justified
“e3” indicates Lead-Free terminal finish
Country of Origin
ISO abbreviation
Right Justified
TW
Rev 1.1
57
EM358x
D
OCUMENT
C
HANGE
L
IST
Revision 0.1 to Revision 0.2
Some information moved to new Ember EM358x Reference Manual
Typical application circuit updated (chapter 2)
Revision 0.2 to Revision 0.3
Complete review of data sheet to reflect change of part numbering to EM358x and introducing variants.
Revision 0.3 to Revision 0.4
Addition of EM3587 variant
Correction of some references to EM358
Addition of Part Marking section.
Revision 0.4 to Revision 1.0
Update to 1.0 with characterization data for Full Production
Revision
1.0
to Revision 1.
1
Update
d Ordering Information.
58
Rev 1.1
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Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software imple-
menters using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each
specific device, and “Typical” parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon
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