SKYWORKS-SILICON-LABS-SI1021-B-GM3
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Si102x/3x
Ultra Low Power, 64/32 kB, 10-Bit ADC
®
MCU with Integrated 240–960 MHz EZRadioPRO
Transceiver
Ultra Low Power at 3.6V
–
RF power consumption
18.5 mA receive
–
–
–
–
–
130 µA/MHz IBA
T
;
d
c-dc enabled
18 mA @ +1 dBm transmit
110 nA sleep current with data retention; POR monitor enabled
400 nA sleep current with smaRTClock (internal LFO)
700 nA sleep current with smaRTClock (external XTAL)
2 µs wake-up from any sleep mode
30 mA @ +13 dBm transmit
85 mA @ +20 dBm transmit
Data rate = 0.123 to 256 kbps
Auto-frequency calibration (AFC)
Antenna diversity and transmit/receive switch control
Programmable packet handler
TX and RX 64-byte FIFOs
12-Bit; 16 Ch. Analog-to-Digital Converter
–
–
–
Up to 75 ksps 12-bit mode or 300 ksps 10-bit mode
Frequency hopping capability
On-chip crystal tuning
External pin or internal VREF (no external capacitor required)
High-Speed 8051 µC Core
–
On-chip PGA allows measuring voltages up to twice the reference
voltage
Pipelined instruction architecture; executes 70% o
tructions in 1
or 2 system clocks
–
–
Autonomous burst mode with 16-bit automatic averaging
accumulator
Integrated temperature sensor
Memory
–
Up to 128 kB Flash; In-system programm
read/write/erase
functionality over the entire supply range
Up to 8 kB internal data RAM
Two Low Current Comparators
–
–
Programmable hysteresis and response time
Digital Peripherals
–
Configurable as interrupt or reset source
–
53 port I/O; All 5 V tolerant with high s
nk
current and programmable drive st
ength
Hardware SMBus™ (I2C
ompatible), 2 x SPI™, and UART
serial ports available con
urrently
Internal 6-Bit Current Reference
–
Up to ±500 µA; source and sink capability
–
–
Enhanced resolution via PWM interpolation
Integrated LCD Controller (Si102x Only)
–
–
Four general-purpose 16-bit counter/timers
–
Supports up to 128 segments (32×4)
Programmable 16-bit counter/timer array with six capture/compare
modules and watchdog timer
–
Integrated charge pump for contrast control
Metering-Specific Peripherals
Clock Sources
–
–
DC-DC buck converter allows dynamic voltage scaling for
maximum efficiency (250 mW output)
Precision internal oscillators: 24.5 MHz with ±2% accuracy sup-
port
RT operation; spread-spectrum mode for reduced EMI
–
Sleep-mode pulse accumulator with programmable switch
de-bounce and pull-up control interfaces directly to metering sen-
sor
Dedicated Packet Processing Engine (DPPE) includes hardware
AES, DMA, CRC, and encoding blocks for acceleration of wireless
protocols
–
–
–
Low
internal oscillator: 20 MHz
External oscillator: Crystal, RC, C, CMOS clock
smaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz internal
LFO with three independent alarms
–
–
-Chip Debug
–
On-chip debug circuitry facilitates full-speed, non-intrusive, in-sys-
tem debug (no emulator required)
Provides 4 breakpoints, single stepping
Manchester and 3 out of 6 encoder hardware for power efficient
implementation of the wireless M-bus specification
–
EZRadioPRO
®
Transceiver
Packages
–
–
–
–
Frequency range = 240–960 MHz
–
–85 pin LGA (6 x 8 mm)
Sensitivity = –121 dBm
FSK, GFSK, and OOK modulation
Max output power = +20 dBm or +13 dBm
Port I/O Configuration
CIP-51 8051
Controller Core
128/64/32/16 kByte
ISP Flash Program
Memory
Pow
r On
Rese
PMU
16
4
Port 0-1
Drivers
P0.0…P1.7
P2.4…P2.7
P3.0…P6.7
P7.0/C2D
Digital Peripherals
UART
ake
Reset
Port 2
Drivers
Timers
32
Port 3-6
Drivers
ebug /
Programming
Hardware
0/1/2/3
C2CK/RST
256 Byte SRAM
Priority
Crossbar
PCA/
8192/4096 Byte XRAM
Port 7
Driver
Decoder
WDT
C2D
VBAT
VDD
DMA
SMBus
SPI 0
Analog
Power
CRC
Engine
VBAT
VDC
RF XCVR
(240-960 MHz,
+20/+13 dBm)
Digital
Power
Crossbar Control
LCD (4×32)
VREG
AES
Engine
PA
VCO
TX
Encoder
EMIF
SFR
Bus
VBATDC
IND
AGC
LNA
DC/DC Buck
Converter
SYSCLK
RXp
RXn
Pulse Counter
EZRadioPro SPI 1
Precision
24.5 MHz
Oscillator
GNDDC
Mixer
PGA
ADC
Low Power
20 MHz
Oscillator
Analog Peripherals
LCD Charge
Pump
CAP
Digital
Modem
External
VREF
Internal
VREF
External
Oscillator
Circuit
Delta
Sigma
Modulator
XTAL1
XTAL2
VDD
VREF
A
M
U
X
12-bit
Temp
Sensor
SDN
75ksps
ADC
Digital
Logic
Enhanced
smaRTClock
Oscillator
nIRQ
GPIOx
XTAL3
XTAL4
3
GND
GND
CP0, CP0A
+
–
30 MHz
XOUT
XIN
System Clock
Configuration
CP1, CP1A
+
–
Comparators
Rev. 1.0 2/13
Copyright © 2013 by Silicon Laboratories
Si102x/3x
2
Rev. 1.0
Si102x/3x
Table of Contents
1. System Overview ……………………………………………………………………………………….. 25
1.1. Typical Connection Diagram ………………………………………………………………….. 28
1.2. CIP-51™ Microcontroller Core ……………………………………………………………….. 29
1.2.1. Fully 8051 Compatible …………………………………………………………………… 29
1.2.2. Improved Throughput…………………………………………………………………….. 2
1.2.3. Additional Features ……………………………………………………………………….. 29
1.3. Port Input/Output ………………………………………………………………………………….. 30
1.4. Serial Port
s
.
………………………………………………………………………………..
……… 31
1.5. Programmable Counter Array……………………………………………….
………… 31
1.6. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomou
Low Power
Burst Mode……………………………………………………………………………………………. 32
1.7. Programmable Current Reference (IREF0)………………………………………………. 33
1.8. Comparators…………………………………………………………..
…………………………. 33
2. Ordering Informatio
n
.
…………………………………………………………………………………. 35
3. Pinout and Package Definitions ………………………………………………………………….. 36
3.1. LGA-85 Package Specification
s
.
…………………………………………………………….. 45
3.1.1. Package Drawin
g
.
…………………………………………………………………………. 45
3.1.2. Land Pattern……………………………..
….
……………………………………….. 47
4. Electrical Characteristic
s
.
…………………………………………………………………………… 48
4.1. Absolute Maximum Specifications…..
…………………………………………………….. 48
4.2. MCU Electrical Characteristic
s
.
………
………………………………………………….. 49
®
4.3. EZRadioPRO
Peripheral Electri
al Characteristics………………………………….. 70
5. SAR ADC with 16-bit Auto-Avera
g Accumulator and Autonomous Low Power
Burst Mode ……………………………………………………………………………………………………. 77
5.1. Output Code Formattin
g
.
……………………………………………………………………….. 77
5.2. Modes of Operatio
n
.
..
…………………………………………………………………………. 79
5.2.1. Starting a Conversion…………………………………………………………………….. 79
5.2.2. Tracking Modes…………………………………………………………………………….. 79
5.2.3. Burst Mode…………………………………………………………………………………… 81
5.2.4. Settling Time Requirements……………………………………………………………. 82
5.2.5. Ga
Setting …………………………………………………………………………………. 82
5.3. 8-Bit Mo
…………………………………………………………………………………………… 83
5.4. 12-Bit Mode …………………………………………………………………………………………. 83
5.5. L
w Power Mode………………………………………………………………………………….. 84
Programmable Window Detector…………………………………………………………….. 90
5.6.1. Window Detector In Single-Ended Mode ………………………………………….. 92
5.6.2. ADC0 Specifications ……………………………………………………………………… 93
5.7. ADC0 Analog Multiplexer ………………………………………………………………………. 94
5.8. Temperature Sensor……………………………………………………………………………… 96
5.8.1. Calibratio
n
.
…………………………………………………………………………………… 96
5.9. Voltage and Ground Reference Options ………………………………………………….. 99
5.10. External Voltage Reference………………………………………………………………… 100
5.11. Internal Voltage Reference…………………………………………………………………. 100
Rev. 1.0
3
Si102x/3x
5.12. Analog Ground Reference………………………………………………………………….. 100
5.13. Temperature Sensor Enable ………………………………………………………………. 100
5.14. Voltage Reference Electrical Specification
s
.
…………………………………………. 101
6. Programmable Current Reference (IREF0)…………………………………………………. 102
6.1. PWM Enhanced Mode…………………………………………………………………………. 102
6.2. IREF0 Specifications …………………………………………………………………………… 10
7. Comparators…………………………………………………………………………………………….. 104
7.1. Comparator Inputs………………………………………………………………………………. 104
7.2. Comparator Output
s
.
……………………………………………………………………
…… 105
7.3. Comparator Response Time …………………………………………………..
………… 106
7.4. Comparator Hysterisi
s
.
…………………………………………………………
……… 106
7.5. Comparator Register Descriptions ………………………………………………………… 107
7.6. Comparator0 and Comparator1 Analog Multiplexers ……………………………….. 111
8. CIP-51 Microcontroller………………………………………………………………………………. 114
8.1. Instruction Set………………………………………………………..
………………………… 115
8.1.1. Instruction and CPU Timing ………………………………………………………….. 115
8.2. CIP-51 Register Descriptions ……………………………………………………………….. 120
9. Memory Organization ……………………………………………………………………………….. 123
9.1. Program Memory…………………………………….
………………………………………… 123
9.1.1. MOVX Instruction and Program Memor
………………………………………. 126
9.2. Data Memor
y
.
…………………………………………………………………………………….. 126
9.2.1. Internal RAM ……………………….
…………………………………………………. 127
9.2.2. External RA
M
.
…………………………………………………………………………….. 127
10. External Data Memory Interface an
On-Chip XRA
M
.
……………………………….. 128
10.1. Accessing XRAM…………….
………………………………………………………….. 128
10.1.1. 16-Bit MOVX Example ……………………………………………………………….. 128
10.1.2. 8-Bit MOVX Example …………………………………………………………………. 128
10.2. Configuring the Exter
al Memory Interface (EMIF
)
.
……………………………….. 129
10.3. Port Configuration……………………………………………………………………………… 129
10.4. Multiplexed and Non-Multiplexed Selection…………………………………………… 133
10.4.1. Multiplexed Configuration……………………………………………………………. 133
10.4.2. Non-Multiplexed Configuration…………………………………………………….. 133
10.5. Memo
ode Selection…………………………………………………………………….. 134
10.5.1. Internal XRAM Only …………………………………………………………………… 135
10.5.2. Split Mode without Bank Select……………………………………………………. 135
10.5.3. Split Mode with Bank Select………………………………………………………… 135
10.5.4. External Only…………………………………………………………………………….. 135
10.6. Timing
……………………………………………………………………………………………. 136
10.6.1. Non-Multiplexed Mode ……………………………………………………………….. 138
10.6.2. Multiplexed Mod
e
.
……………………………………………………………………… 141
11. Direct Memory Access (DMA0)………………………………………………………………… 145
11.1. DMA0 Architecture ……………………………………………………………………………. 146
11.2. DMA0 Arbitration ………………………………………………………………………………. 147
11.2.1. DMA0 Memory Access Arbitration ……………………………………………….. 147
11.2.2. DMA0 Channel Arbitration ………………………………………………………….. 147
4
Rev. 1.0
Si102x/3x
11.3. DMA0 Operation in Low Power Modes ………………………………………………… 147
11.4. Transfer Configuration……………………………………………………………………….. 148
12. Cyclic Redundancy Check Unit (CRC0)……………………………………………………. 159
12.1. 16-bit CRC Algorithm…………………………………………………………………………. 159
12.3. Preparing for a CRC Calculation …………………………………………………………. 162
12.4. Performing a CRC Calculation ……………………………………………………………. 16
12.5. Accessing the CRC0 Result ……………………………………………………………….. 162
12.6. CRC0 Bit Reverse Feature…………………………………………………………………. 166
13. DMA-Enabled Cyclic Redundancy Check Module (CRC1)………………….
…… 167
13.1. Polynomial Specification……………………………………………………….
…………. 167
13.2. Endianness……………………………………………………………………….
……… 168
13.3. CRC Seed Value ………………………………………………………………………………. 169
13.4. Inverting the Final Value…………………………………………………………………….. 169
13.5. Flipping the Final Valu
e
.
…………………………………………………………………….. 169
13.6. Using CRC1 with SFR Access ……………………………….
………………………… 170
13.7. Using the CRC1 module with the DMA ………………………………………………… 170
14. Advanced Encryption Standard (AES) Periphera
l
.
……………………………………. 174
14.1. Hardware Descriptio
n
.
……………………………………………………………………….. 175
14.1.1. AES Encryption/Decryption Cor
e
.
…….
………………………………………… 176
14.1.2. Data SFRs……………………………………
………………………………………. 176
14.1.3. Configuration SFRs……………………………………………………………………. 177
14.1.4. Input Multiplexer…………………
…………………………………………………. 177
14.1.5. Output Multiplexe
r
.
…………………………………………………………………….. 177
14.1.6. Internal State Machine ……
………………………………………………………… 177
14.2. Key Inversion………………….
………………………………………………………….. 178
14.2.1. Key Inversion using DMA……………………………………………………………. 179
14.2.2. Key Inversion using SFRs…………………………………………………………… 180
14.2.3. Extended Key Output Byte Order…………………………………………………. 181
14.2.4. Using the DMA to unwrap the extended Key …………………………………. 182
14.3. AES Block Ciphe
r
.
…………………………………………………………………………….. 183
14.4. AES Block Cipher Data Flow………………………………………………………………. 184
14.4.1. AES Block Cipher Encryption using DM
A
.
…………………………………….. 185
14.4.2. A
Block Cipher Encryption using SFR
s
.
……………………………………. 186
14.5. AES Block Cipher Decryption……………………………………………………………… 187
14.5.1. AES Block Cipher Decryption using DMA……………………………………… 187
14.5.2. AES Block Cipher Decryption using SFRs…………………………………….. 188
.6. Block Cipher Modes ………………………………………………………………………….. 189
14.6.1. Cipher Block Chaining Mode……………………………………………………….. 189
14.6.2. CBC Encryption Initialization Vector Location………………………………… 191
14.6.3. CBC Encryption using DM
A
.
……………………………………………………….. 191
14.6.4. CBC Decryption ………………………………………………………………………… 194
14.6.5. Counter Mode …………………………………………………………………………… 197
14.6.6. CTR Encryption using DMA ………………………………………………………… 199
15. Encoder/Decoder ……………………………………………………………………………………. 206
15.1. Manchester Encoding………………………………………………………………………… 207
Rev. 1.0
5
Si102x/3x
15.2. Manchester Decoding………………………………………………………………………… 208
15.3. Three-out-of-Six
Encoding…………………………………………………………………. 209
15.4. Three-out-of-Six Decoding …………………………………………………………………. 210
15.5. Encoding/Decoding with SFR Access ………………………………………………….. 211
15.6. Decoder Error Interrupt………………………………………………………………………. 211
15.7. Using the ENC0 module with the DMA…………………………………………………. 21
16. Special Function Registers……………………………………………………………………… 215
16.1. SFR Paging ……………………………………………………………………………………… 215
16.2. Interrupts and SFR Pagin
g
.
…………………………………………………………
…… 215
17. Interrupt Handler……………………………………………………………………….
…………. 231
17.1. Enabling Interrupt Source
s
.
…………………………………………………
……… 231
17.2. MCU Interrupt Sources and Vectors…………………………………………………….. 231
17.3. Interrupt Priorities ……………………………………………………………………………… 232
17.4. Interrupt Latency……………………………………………………………………………….. 232
17.5. Interrupt Register Description
s
.
………………………………
………………………… 234
17.6. External Interrupts INT0 and INT1……………………………………………………….. 241
18. Flash Memory…………………………………………………………………………………………. 243
18.1. Programming the Flash Memory …………………………………………………………. 243
18.1.1. Flash Lock and Key Function
s
.
………..
………………………………………… 243
18.1.2. Flash Erase Procedure …………………..
………………………………………. 243
18.1.3. Flash Write Procedure ……………………………………………………………….. 244
18.1.4. Flash Write Optimizatio
n
.
…….
…………………………………………………. 245
18.2. Non-volatile Data Storage ………………………………………………………………….. 246
18.3. Security Options ……………………
………………………………………………………… 246
18.4. Determining the Device Par
mber at Run Time ………………………………… 248
18.5. Flash Write and Erase Guideline
s
.
………………………………………………………. 249
18.5.1. VDD Maintenance and the VDD Monitor ………………………………………. 249
18.5.2. PSWE Maintenanc
e
.
………………………………………………………………….. 251
18.5.3. System Clock ……………………………………………………………………………. 251
18.6. Minimizing Flash Read Current …………………………………………………………… 252
19. Power Management ………………………………………………………………………………… 257
19.1. Normal Mod
e
.
…………………………………………………………………………………… 258
19.2. Idle M
………………………………………………………………………………………… 258
19.3. Stop Mode ……………………………………………………………………………………….. 259
19.4. Low Power Idle Mod
e
.
……………………………………………………………………….. 259
1
5. Suspend Mode …………………………………………………………………………………. 263
.6. Sleep Mode ……………………………………………………………………………………… 263
19.7. Configuring Wakeup Sources……………………………………………………………… 264
19.8. Determining the Event that Caused the Last Wakeup…………………………….. 264
19.9. Power Management Specifications ……………………………………………………… 268
20. On-Chip DC-DC Buck Converter (DC0)…………………………………………………….. 269
20.1. Startup Behavior……………………………………………………………………………….. 270
20.4. Optimizing Board Layout ……………………………………………………………………. 271
20.5. Selecting the Optimum Switch Size……………………………………………………… 271
20.6.
DC-DC Converter Clocking Options …………………………………………………. 271
6
Rev. 1.0
Si102x/3x
20.7. Bypass Mode……………………………………………………………………………………. 272
20.8. DC-DC Converter Register Description
s
.
……………………………………………… 272
20.9. DC-DC Converter Specification
s
.
………………………………………………………… 276
21. Voltage Regulator (VREG0)……………………………………………………………………… 277
21.1. Voltage Regulator Electrical Specification
s
.
………………………………………….. 277
22. Reset Source
s
.
……………………………………………………………………………………….. 27
22.1. Power-On Rese
t
.
………………………………………………………………………………. 279
22.2. Power-Fail Rese
t
.
……………………………………………………………………………… 280
22.3. External Rese
t
.
………………………………………………………………………….
…… 283
22.4. Missing Clock Detector Reset ……………………………………………….
…………. 283
22.5. Comparator0 Reset ……………………………………………………………
……… 283
22.6. PCA Watchdog Timer Reset ………………………………………………………………. 283
22.7. Flash Error Reset ……………………………………………………………………………… 284
22.8. SmaRTClock (Real Time Clock) Reset ………………………………………………… 284
22.9. Software Rese
t
.
……………………………………………………
………………………… 284
23. Clocking Sources……………………………………………………………………………………. 286
23.1. Programmable Precision Internal Oscillator ………………………………………….. 287
23.2. Low Power Internal Oscillator……………………………………………………………… 287
23.3. External Oscillator Drive Circuit……………….
………………………………………… 287
23.3.1. External Crystal Mode…………………….
………………………………………. 287
23.3.2. External RC Mode……………………………………………………………………… 289
23.3.3. External Capacitor Mode……..
…………………………………………………. 290
23.3.4. External CMOS Clock Mode ……………………………………………………….. 290
23.4. Special Function Registers for Selecting and Configuring the System Clock 291
24. SmaRTClock (Real Time Clock)
………………………………………………………….. 295
24.1. SmaRTClock Interface ………………………………………………………………………. 296
24.1.1. SmaRTClock Lock and Key Functions………………………………………….. 297
24.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
……………………………………………………………………………………….. 297
24.1.3. SmaRTClock Interface Autoread Featur
e
.
…………………………………….. 297
24.1.4. RTC0ADR Autoincrement Feature……………………………………………….. 297
24.2. SmaRTClock Clocking Sources ………………………………………………………….. 300
24.2.1. U
the SmaRTClock Oscillator with a Crystal or External CMOS Clock
……………………………………………………………………………………….. 300
24.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode………………… 301
24.2.3. Using the Low Frequency Oscillator (LFO
)
.
…………………………………… 301
24.2.4. Programmable Load Capacitance………………………………………………… 301
24.2.5. Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias
Doubling
……………………………………………………………………………………….. 302
24.2.6. Missing SmaRTClock Detector ……………………………………………………. 304
24.2.7. SmaRTClock Oscillator Crystal Valid Detector ………………………………. 304
24.3. SmaRTClock Timer and Alarm Functio
n
.
……………………………………………… 304
24.3.1. Setting and Reading the SmaRTClock Timer Valu
e
.
………………………. 304
24.3.2. Setting a SmaRTClock Alarm ……………………………………………………… 305
24.3.3. Software Considerations for using the SmaRTClock Timer and Alarm
305
Rev. 1.0
7
Si102x/3x
25. Low-Power Pulse Counter ………………………………………………………………………. 312
25.1. Counting Modes ……………………………………………………………………………….. 313
25.2. Reed Switch Types……………………………………………………………………………. 314
25.3. Programmable Pull-Up Resistors ………………………………………………………… 315
25.4. Automatic Pull-Up Resistor Calibration ………………………………………………… 317
25.5. Sample Rate…………………………………………………………………………………….. 31
25.6. Debounce ………………………………………………………………………………………… 317
25.7. Reset Behavio
r
.
………………………………………………………………………………… 318
25.8. Wake up and Interrupt Sources……………………………………………………
…… 318
25.9. Real-Time Register Acces
s
.
………………………………………………….
………… 319
25.10. Advanced Features ………………………………………………………….
……… 319
25.10.1. Quadrature Erro
r
.
…………………………………………………………………….. 319
25.10.2. Flutter Detection………………………………………………………………………. 320
26. LCD Segment Driver (Si102x Only) ………………………………………………………….. 334
26.1. Configuring the LCD Segment Drive
r
.
……………………..
………………………… 334
26.2. Mapping Data Registers to LCD Pins…………………………………………………… 335
26.3. LCD Contrast Adjustment…………………………………………………………………… 338
26.3.1. Contrast Control Mode 1 (Bypass Mode)………………………………………. 338
26.3.2. Contrast Control Mode 2 (Minimum Contrast Mode) ………………………. 339
26.3.3. Contrast Control Mode 3 (Constant C
rast Mode)……………………….. 339
26.3.4. Contrast Control Mode 4 (Auto-Bypass Mode) ………………………………. 340
26.4. Adjusting the VBAT Monitor Thresh
………………………………………………… 344
26.5. Setting the LCD Refresh Rat
e
.
……………………………………………………………. 345
26.6. Blinking LCD Segments………….
………………………………………………………… 346
26.7. Advanced LCD Optimization
………………………………………………………….. 348
27. Port Input/Output ……………………………………………………………………………………. 351
27.1. Port I/O Modes of Operation……………………………………………………………….. 352
27.1.1. Port Pins Config
red for Analog I/O……………………………………………… 352
27.1.2. Port Pins Configured For Digital I/O……………………………………………… 352
27.1.3. Interfacing Port I/O to High Voltage Logic……………………………………… 353
27.1.4. Increasing Port I/O Drive Strength ……………………………………………….. 353
27.2. Assigning Port I/O Pins to Analog and Digital Functions…………………………. 353
27.2.1. A
ning Port I/O Pins to Analog Functions …………………………………. 353
27.2.2. Assigning Port I/O Pins to Digital Functions…………………………………… 354
27.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions … 354
2
3. Priority Crossbar Decoder ………………………………………………………………….. 355
.4. Port Match ……………………………………………………………………………………….. 361
27.5. Special Function Registers for Accessing and Configuring Port I/O …………. 363
28. SMBus……………………………………………………………………………………………………. 381
28.1. Supporting Document
s
.
……………………………………………………………………… 382
28.2. SMBus Configuration…………………………………………………………………………. 382
28.3. SMBus Operation ……………………………………………………………………………… 382
28.3.1. Transmitter Vs. Receiver…………………………………………………………….. 383
28.3.2. Arbitration…………………………………………………………………………………. 383
28.3.3. Clock Low Extension………………………………………………………………….. 383
8
Rev. 1.0
Si102x/3x
28.3.4. SCL Low Timeout………………………………………………………………………. 383
28.3.5. SCL High (SMBus Free) Timeout ………………………………………………… 384
28.4. Using the SMBus………………………………………………………………………………. 384
28.4.1. SMBus Configuration Register…………………………………………………….. 384
28.4.2. SMB0CN Control Register ………………………………………………………….. 388
28.4.3. Hardware Slave Address Recognition ………………………………………….. 39
28.4.4. Data Register ……………………………………………………………………………. 393
28.5. SMBus Transfer Modes……………………………………………………………………… 393
28.5.1. Write Sequence (Master) …………………………………………………….
…… 393
28.5.2. Read Sequence (Master
)
.
……………………………………………..
…………. 394
28.5.3. Write Sequence (Slave) ………………………………………………
……… 395
28.5.4. Read Sequence (Slave
)
.
…………………………………………………………….. 396
28.6. SMBus Status Decoding…………………………………………………………………….. 397
29. UART
0
.
…………………………………………………………………………………………………… 402
29.1. Enhanced Baud Rate Generation……………………………
………………………… 403
29.2. Operational Modes ……………………………………………………………………………. 404
29.2.1. 8-Bit UAR
T
.
………………………………………………………………………………. 404
29.2.2. 9-Bit UAR
T
.
………………………………………………………………………………. 404
29.3. Multiprocessor Communications ……………..
………………………………………… 405
30. Enhanced Serial Peripheral Interface (SPI0) …
………………………………………. 411
30.1. Signal Descriptions……………………………………………………………………………. 412
30.1.1. Master Out, Slave In (MOSI)..
…………………………………………………. 412
30.1.2. Master In, Slave Out (MISO)……………………………………………………….. 412
30.1.3. Serial Clock (SCK) …………
………………………………………………………… 412
30.1.4. Slave Select (NSS) ….
………………………………………………………….. 412
30.2. SPI0 Master Mode Operatio
n
.
…………………………………………………………….. 412
30.3. SPI0 Slave Mode Operatio
n
.
………………………………………………………………. 414
30.4. SPI0 Interrupt Sources ………………………………………………………………………. 415
30.5. Serial Clock Phase and Polarity ………………………………………………………….. 415
30.6. SPI Special Function Register
s
.
………………………………………………………….. 417
31. EZRadioPRO® Serial Interfac
e
.
……………………………………………………………….. 424
31.1. Signal Descriptions……………………………………………………………………………. 425
31.1.1. M
er Out, Slave In (MOSI)……………………………………………………….. 425
31.1.2. Master In, Slave Out (MISO)……………………………………………………….. 425
31.1.3. Serial Clock (SCK) …………………………………………………………………….. 425
31.1.4. Slave Select (NSS) ……………………………………………………………………. 425
.2. SPI1 Master Mode Operatio
n
.
…………………………………………………………….. 426
31.3. SPI Slave Operation on the EZRadioPRO Peripheral Side……………………… 426
31.4. SPI1 Interrupt Sources ………………………………………………………………………. 426
31.5. Serial Clock Phase and Polarity ………………………………………………………….. 427
31.6. Using SPI1 with the DMA …………………………………………………………………… 428
31.7. Master Mode SPI1 DMA Transfers………………………………………………………. 428
31.8. Master Mode Bidirectional Data Transfe
r
.
…………………………………………….. 428
31.9. Master Mode Unidirectional Data Transfer……………………………………………. 430
31.10. SPI Special Function Register
s
.
………………………………………………………… 430
Rev. 1.0
9
Si102x/3x
®
32. EZRadioPRO
240–960 MHz Transceiver…………………………………………………. 435
32.1. EZRadioPRO Operating Modes ………………………………………………………….. 436
32.1.1. Operating Mode Control …………………………………………………………….. 437
32.2. Interrupts
………………………………………………………………………………………… 440
32.3. System Timing………………………………………………………………………………….. 440
32.3.1. Frequency Control……………………………………………………………………… 44
32.3.2. Frequency Programming…………………………………………………………….. 441
32.3.3. Easy Frequency Programming for FHSS………………………………………. 443
32.3.4. Automatic State Transition for Frequency Change ………………….
…… 444
32.3.5. Frequency Deviation …………………………………………………….
…………. 444
32.3.6. Frequency Offset Adjustment……………………………………….
……… 445
32.3.7. Automatic Frequency Control (AFC
)
.
……………………………………………. 446
32.3.8. TX Data Rate Generator …………………………………………………………….. 447
32.4. Modulation Options……………………………………………………………………………. 447
32.4.1. Modulation Type……………………………………………
………………………… 447
32.4.2. Modulation Data Source……………………………………………………………… 448
32.4.3. PN9 Mode ………………………………………………………………………………… 452
32.5. Internal Functional Blocks ………………………………………………………………….. 452
32.5.1. RX LNA ………………………………………..
………………………………………… 452
32.5.2. Programmable Gain Amplifie
r
.
………..
………………………………………. 453
32.5.3. Digital Modem …………………………………………………………………………… 453
32.5.4. Synthesizer ……………………….
…………………………………………………. 454
32.5.5. Crystal Oscillato
r
.
………………………………………………………………………. 457
32.5.6. Regulators…………………….
………………………………………………………… 457
32.6. Data Handling and Packet H
ler ……………………………………………………… 458
32.6.1. RX and TX FIFOs………………………………………………………………………. 458
32.6.2. Packet Configuration………………………………………………………………….. 459
32.6.3. Packet Handler
X Mod
e
.
…………………………………………………………… 460
32.6.4. Packet Handler RX Mode……………………………………………………………. 460
32.6.5. Data Whitening, Manchester Encoding, and CR
C
.
…………………………. 462
32.6.6. Preamble Detector …………………………………………………………………….. 463
32.6.7. Preamble Length……………………………………………………………………….. 463
32.6.8. In
d Preamble Detector…………………………………………………………… 464
32.6.9. Synchronization Word Configuration…………………………………………….. 464
32.6.10. Receive Header Check …………………………………………………………….. 465
32.6.11. TX Retransmission and Auto TX………………………………………………… 465
.7. RX Modem Configuration …………………………………………………………………… 466
32.7.1. Modem Settings for FSK and GFSK …………………………………………….. 466
32.8. Auxiliary Functions ……………………………………………………………………………. 466
32.8.1. Smart Reset ……………………………………………………………………………… 466
32.8.2. Output Clock …………………………………………………………………………….. 467
32.8.3. General Purpose ADC ……………………………………………………………….. 468
32.8.4. Temperature Sensor ………………………………………………………………….. 469
32.8.5. Low Battery Detector………………………………………………………………….. 471
32.8.6. Wake-Up Timer and 32 kHz Clock Source ……………………………………. 471
10
Rev. 1.0
Si102x/3x
32.8.7. Low Duty Cycle Mode ………………………………………………………………… 473
32.8.8. GPIO Configuration……………………………………………………………………. 474
32.8.9. Antenna Diversit
y
.
……………………………………………………………………… 475
32.8.10. RSSI and Clear Channel Assessment ………………………………………… 475
32.9. Reference Design……………………………………………………………………………… 476
32.10. Application Notes and Reference Design
s
.
…………………………………………. 47
32.11. Customer Support …………………………………………………………………………… 479
32.12. Register Table and Descriptions ……………………………………………………….. 480
32.13. Required Changes to Default Register Values………………………………
…… 482
33. Timers ………………………………………………………………………………………
…………. 483
33.1. Timer 0 and Timer 1 …………………………………………………………..
……… 485
33.1.1. Mode 0: 13-bit Counter/Timer ……………………………………………………… 485
33.1.2. Mode 1: 16-bit Counter/Timer ……………………………………………………… 486
33.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload………………………………. 486
33.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
………………………… 487
33.2. Timer 2 ……………………………………………………………………………………………. 493
33.2.1. 16-bit Timer with Auto-Reload……………………………………………………… 493
33.2.2. 8-bit Timers with Auto-Reload……………………………………………………… 494
33.2.3. Comparator 0/SmaRTClock Capture Mode …………………………………… 494
33.3. Timer 3 ………………………………………………..
………………………………………. 499
33.3.1. 16-bit Timer with Auto-Reload……………………………………………………… 499
33.3.2. 8-Bit Timers with Auto-Reload
…………………………………………………. 500
33.3.3. SmaRTClock/External Oscil
ator Capture Mod
e
.
……………………………. 500
34. Programmable Counter Array………
………………………………………………………… 505
34.1. PCA Counter/Timer …………
………………………………………………………….. 506
34.2. PCA0 Interrupt Sources……………………………………………………………………… 507
34.3. Capture/Compare Modules ………………………………………………………………… 508
34.3.1. Edge-triggered
apture Mode……………………………………………………… 509
34.3.2. Software Timer (Compare) Mode…………………………………………………. 510
34.3.3. High-Speed Output Mode …………………………………………………………… 511
34.3.4. Frequency Output Mode …………………………………………………………….. 512
34.3.5. 8-Bit,
9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes………….. 513
34.3.6. 1
it Pulse Width Modulator Mode…………………………………………….. 515
34.4. Watchdog Timer Mode ………………………………………………………………………. 516
34.4.1. Watchdog Timer Operatio
n
.
………………………………………………………… 516
34.4.2. Watchdog Timer Usage ……………………………………………………………… 517
.5. Register Descriptions for PCA0…………………………………………………………… 519
35. C2 Interface ……………………………………………………………………………………………. 525
35.1. C2 Interface Registers……………………………………………………………………….. 525
35.2. C2 Pin Sharing …………………………………………………………………………………. 528
Document Change List 529
Contact Information 530
Rev. 1.0
11
Si102x/3x
List of Figures
Figure 1.1. Si102x Block Diagram ………………………………………………………………… 27
Figure 1.2. Si103x Block Diagram ………………………………………………………………… 27
Figure 1.3. Si102x/3x RX/TX Direct-tie Application Example ……………………………. 28
Figure 1.4. Si102x/3x Antenna Diversity Application Example ………………………….. 28
Figure 1.5. Port I/O Functional Block Diagram ……………………………………………….. 3
Figure 1.6. PCA Block Diagram ……………………………………………………………………. 31
Figure 1.7. ADC0 Functional Block Diagram ………………………………………………….. 32
Figure 1.8. ADC0 Multiplexer Block Diagram ………………………………………..
……… 33
Figure 1.9. Comparator 0 Functional Block Diagram
…………………….
………… 34
Figure 1.10. Comparator 1 Functional Block Diagram
………………………
…………. 34
Figure 3.1. LGA-85 Pinout Diagram (Top View) ……………………………………………… 44
Figure 3.2. LGA-85 Package Drawing …………………………………………………………… 45
Figure 3.3. LGA-85 Land Pattern
……………………………………
…………………………. 47
Figure 4.1. Frequency Sensitivity (External CMOS Clock, 25°C) ………………………. 56
Figure 4.2. Typical VOH Curves, 1.8–3.6 V
…………………………………………………… 58
Figure 4.3. Typical VOL Curves, 1.8–3.6 V ……………………………………………………. 59
Figure 5.1. ADC0 Functional Block Diagram ………………………………………………….. 77
Figure 5.2. 10-Bit ADC Track and Conversion E
ple Timing (BURSTEN = 0) … 80
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4
……………… 81
Figure 5.4. ADC0 Equivalent Input Circuit
……………………………………………………. 82
Figure 5.5. ADC Window Compare Exam
Right-Justified Single-Ended Data
.. 93
Figure 5.6. ADC Window Compare E
mple: Left-Justified Single-Ended Data ….. 93
Figure 5.7. ADC0 Multiplexer Bloc
Diagram …………………………………………………. 94
Figure 5.8. Temperature Sensor Tr
nsfer Function
………………………………………… 96
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (V
= 1.68 V)
…. 97
REF
Figure 5.10. Voltage Refer
nce Functional Block Diagram ………………………………. 99
Figure 7.1. Comparator 0 Functional Block Diagram
…………………………………….. 104
Figure 7.2. Comparator 1 Functional Block Diagram
…………………………………….. 105
Figure 7.3. Comparator Hysteresis Plot
………………………………………………………. 106
Figure 7.4. CPn Multiplexer Block Diagram ………………………………………………….. 111
Figure 8.1. C
-51 Block Diagram ………………………………………………………………. 114
Figure 9.1. Si
2x/3x Memory Map …………………………………………………………….. 123
Figure 9.2. Flash Program Memory Map ……………………………………………………… 124
Figur
9.3. Address Memory Map for Instruction Fetches ………………………………. 125
ure 10.1. Multiplexed Configuration Example …………………………………………… 133
Figure 10.2. Non-Multiplexed Configuration Example ……………………………………. 134
Figure 10.3. EMIF Operating Modes
…………………………………………………………… 134
Figure 10.4. Non-Multiplexed 16-bit MOVX Timing ……………………………………….. 138
Figure 10.5. Non-Multiplexed 8-bit MOVX without Bank Select Timing
……………. 139
Figure 10.6. Non-Multiplexed 8-bit MOVX with Bank Select Timing
………………… 140
Figure 10.7. Multiplexed 16-bit MOVX Timing ………………………………………………. 141
Figure 10.8. Multiplexed 8-bit MOVX without Bank Select Timing
…………………… 142
Figure 10.9. Multiplexed 8-bit MOVX with Bank Select Timing
……………………….. 143
Rev. 1.0
12
Si102x/3x
Figure 11.1. DMA0 Block Diagram ……………………………………………………………… 146
Figure 12.1. CRC0 Block Diagram
……………………………………………………………… 159
Figure 12.2. Bit Reverse Register
………………………………………………………………. 166
Figure 13.1. Polynomial Representation
……………………………………………………… 167
Figure 14.1. AES Peripheral Block Diagram
………………………………………………… 175
Figure 14.2. Key Inversion Data Flow
…………………………………………………………. 17
Figure 14.3. AES Block Cipher Data Flow ……………………………………………………. 184
Figure 14.4. Cipher Block Chaining Mode ……………………………………………………. 189
Figure 14.5. CBC Encryption Data Flow ………………………………………………..
…… 190
Figure 14.6. CBC Decryption Data Flow
………………………………………..
………… 194
Figure 14.7. Counter Mode …………………………………………………………
……… 197
Figure 14.8. Counter Mode Data Flow
………………………………………………………… 198
Figure 16.1. SFR Page Stack …………………………………………………………………….. 216
Figure 18.1. Flash Security Example …………………………………………………………… 246
Figure 19.1. Si102x/3x Power Distribution
………………………
………………………… 258
Figure 19.2. Clock Tree Distribution ……………………………………………………………. 259
Figure 20.1. Step Down DC-DC Buck Converter Block Diagram …………………….. 269
Figure 22.1. Reset Sources ……………………………………………………………………….. 278
Figure 22.2. Power-On Reset Timing Diagram
…
………………………………………… 279
Figure 23.1. Clocking Sources Block Diagram ….
………………………………………. 286
Figure 23.2. 25 MHz External Crystal Example …………………………………………….. 288
Figure 24.1. SmaRTClock Block Diagram
…………………………………………………. 295
Figure 24.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ……… 303
Figure 25.1. Pulse Counter Block Diagram
………………………………………………….. 312
Figure 25.2. Mode Examples ……
………………………………………………………….. 313
Figure 25.3. Reed Switch Configurations …………………………………………………….. 314
Figure 25.4. Debounce Timing
…………………………………………………………………… 318
Figure 25.5. Flutter Examp
……………………………………………………………………… 320
Figure 26.1. LCD Segment Driver Block Diagram …………………………………………. 334
Figure 26.2. LCD Data Register to LCD Pin Mapping ……………………………………. 336
Figure 26.3. Contrast Control Mode 1
…………………………………………………………. 338
Figure 26.4. Contrast Control Mode 2
…………………………………………………………. 339
Figure 26.5.
ntrast Control Mode 3
…………………………………………………………. 339
Figure 26.6. Contrast Control Mode 4
…………………………………………………………. 340
Figure 27.1. Port I/O Functional Block Diagram ……………………………………………. 351
Fi
ure 27.2. Port I/O Cell Block Diagram
…………………………………………………….. 352
gure 27.3. Crossbar Priority Decoder with No Pins Skipped ………………………… 356
Figure 27.4. Crossbar Priority Decoder with Crystal Pins Skipped
………………….. 357
Figure 28.1. SMBus Block Diagram
……………………………………………………………. 381
Figure 28.2. Typical SMBus Configuration …………………………………………………… 382
Figure 28.3. SMBus Transaction ………………………………………………………………… 383
Figure 28.4. Typical SMBus SCL Generation ……………………………………………….. 385
Figure 28.5. Typical Master Write Sequence
……………………………………………….. 394
Figure 28.6. Typical Master Read Sequence
……………………………………………….. 395
Figure 28.7. Typical Slave Write Sequence
…………………………………………………. 396
13
Rev. 1.0
Si102x/3x
Figure 28.8. Typical Slave Read Sequence
…………………………………………………. 397
Figure 29.1. UART0 Block Diagram
……………………………………………………………. 402
Figure 29.2. UART0 Baud Rate Logic …………………………………………………………. 403
Figure 29.3. UART Interconnect Diagram
……………………………………………………. 404
Figure 29.4. 8-Bit UART Timing Diagram …………………………………………………….. 404
Figure 29.5. 9-Bit UART Timing Diagram …………………………………………………….. 40
Figure 29.6. UART Multi-Processor Mode Interconnect Diagram
……………………. 406
Figure 30.1. SPI Block Diagram
…………………………………………………………………. 411
Figure 30.2. Multiple-Master Mode Connection Diagram …………………………
…… 414
Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave Mode Conne
on Diagram
……………………………………………………………………………….
……… 414
Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connect
on Diagram
………………………………………………………………………………………………. 414
Figure 30.5. Master Mode Data/Clock Timing ………………………………………………. 416
Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0) ..
………………………… 416
Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1) …………………………….. 417
Figure 30.8. SPI Master Timing (CKPHA = 0) ………………………………………………. 421
Figure 30.9. SPI Master Timing (CKPHA = 1) ………………………………………………. 421
Figure 30.10. SPI Slave Timing (CKPHA = 0) …..
………………………………………… 422
Figure 30.11. SPI Slave Timing (CKPHA = 1) ….
………………………………………. 422
Figure 31.1. SPI Block Diagram
…………………………………………………………………. 424
Figure 31.2. Master Mode Data/Clock Tim
g ………………………………………………. 427
Figure 31.3. SPI Master Timing (CKPHA = 0) ………………………………………………. 434
Figure 32.1. State Machine Diagram .
………………………………………………………… 437
Figure 32.2. TX Timing ……………
………………………………………………………….. 441
Figure 32.3. RX Timing ……………………………………………………………………………… 441
Figure 32.4. Frequency Deviation
………………………………………………………………. 445
Figure 32.5. Sensitivity at 1% PER vs. Carrier Frequency Offset
……………………. 446
Figure 32.6. FSK vs. GFSK Spectrums ……………………………………………………….. 448
Figure 32.7. Direct Synchronous Mode Example ………………………………………….. 451
Figure 32.8. Direct Asynchronous Mode Example
………………………………………… 451
Figure 32.9. Microcontroller Connections …………………………………………………….. 452
Figure 32.10
L Synthesizer Block Diagram ……………………………………………… 454
Figure 32.11. FIFO Thresholds
………………………………………………………………….. 458
Figure 32.12. Packet Structure …………………………………………………………………… 459
Fi
ure 32.13. Multiple Packets in TX Packet Handler
……………………………………. 460
gure 32.14. Required RX Packet Structure with Packet Handler Disabled
…….. 460
Figure 32.15. Multiple Packets in RX Packet Handler ……………………………………. 461
Figure 32.16. Multiple Packets in RX with CRC or Header Error
…………………….. 461
Figure 32.17. Operation of Data Whitening, Manchester Encoding, and CRC
….. 463
Figure 32.18. Manchester Coding Example
…………………………………………………. 463
Figure 32.19. Header ………………………………………………………………………………… 465
Figure 32.20. POR Glitch Parameters …………………………………………………………. 466
Figure 32.21. General Purpose ADC Architecture
………………………………………… 469
Figure 32.22. Temperature Ranges using ADC8
………………………………………….. 471
Rev. 1.0
14
Si102x/3x
Figure 32.23. WUT Interrupt and WUT Operation …………………………………………. 473
Figure 32.24. Low Duty Cycle Mode
…………………………………………………………… 474
Figure 32.25. RSSI Value vs. Input Power …………………………………………………… 476
Figure 32.26. Si1024 Split RF TX/RX Direct-Tie Reference Design—Schematic . 477
Figure 32.27. Si1020 Switch Matching Reference Design—Schematic ……………. 478
Figure 33.1. T0 Mode 0 Block Diagram ……………………………………………………….. 48
Figure 33.2. T0 Mode 2 Block Diagram ……………………………………………………….. 487
Figure 33.3. T0 Mode 3 Block Diagram ……………………………………………………….. 488
Figure 33.4. Timer 2 16-Bit Mode Block Diagram
………………………………….
…… 493
Figure 33.5. Timer 2 8-Bit Mode Block Diagram
……………………………..
…………. 494
Figure 33.6. Timer 2 Capture Mode Block Diagram ……………………….
……… 495
Figure 33.7. Timer 3 16-Bit Mode Block Diagram
…………………………………………. 499
Figure 33.8. Timer 3 8-Bit Mode Block Diagram
…………………………………………… 500
Figure 33.9. Timer 3 Capture Mode Block Diagram ………………………………………. 501
Figure 34.1. PCA Block Diagram ……………………………………
………………………… 505
Figure 34.2. PCA Counter/Timer Block Diagram …………………………………………… 507
Figure 34.3. PCA Interrupt Block Diagram
…………………………………………………… 508
Figure 34.4. PCA Capture Mode Diagram ……………………………………………………. 510
Figure 34.5. PCA Software Timer Mode Diagram
………………………………………… 511
Figure 34.6. PCA High-Speed Output Mode Diag
m ……………………………………. 512
Figure 34.7. PCA Frequency Output Mode
………………………………………………….. 513
Figure 34.8. PCA 8-Bit PWM Mode Diagr
……………………………………………….. 514
Figure 34.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
……………………………….. 515
Figure 34.10. PCA 16-Bit PWM Mode
………………………………………………………… 516
Figure 34.11. PCA Module 5 with
tchdog Timer Enabled
………………………….. 517
Figure 35.1. Typical C2 Pin Sharing ……………………………………………………………. 528
15
Rev. 1.0
Si102x/3x
List of Tables
Table 2.1. Product Selection Guide ………………………………………………………………. 35
Table 3.1. Pin Definitions for the Si102x/3x ……………………………………………………. 36
Table 3.2. LGA-85 Package Dimensions
………………………………………………………. 46
Table 3.3. LGA-85 Land Pattern Dimensions …………………………………………………. 47
Table 4.1. Absolute Maximum Ratings ………………………………………………………….. 4
Table 4.2. Global Electrical Characteristics1,2 ……………………………………………….. 49
Table 4.3. Digital Supply Current at VBAT pin with DC-DC Converter Enabled
….. 49
Table 4.4. Digital Supply Current with DC-DC Converter Disabled …………..
……… 50
Table 4.5. Port I/O DC Electrical Characteristics …………………………..
………… 57
Table 4.6. Reset Electrical Characteristics ………………………………………
…………. 60
Table 4.7. Power Management Electrical Specifications ………………………………….. 61
Table 4.8. Flash Electrical Characteristics
…………………………………………………….. 61
Table 4.9. Internal Precision Oscillator Electrical Characteris
s ………………………
61
Table 4.10. Internal Low-Power Oscillator Electrical Characteristics
…………………. 61
Table 4.11. SmaRTClock Characteristics ………………………………………………………. 62
Table 4.12. ADC0 Electrical Characteristics …………………………………………………… 62
Table 4.13. Temperature Sensor Electrical Characteristics
……………………………… 63
Table 4.14. Voltage Reference Electrical Charac
stics …………………………………
64
Table 4.15. IREF0 Electrical Characteristics ………………………………………………….. 65
Table 4.16. Comparator Electrical Charac
eristics …………………………………………..
66
Table 4.17. VREG0 Electrical Characteris
s ………………………………………………… 67
Table 4.18. LCD0 Electrical Characte
stics …………………………………………………… 68
Table 4.19. PC0 Electrical Charac
istics ……………………………………………………..
68
Table 4.20. DC0 (Buck Converter) Electrical Characteristics ……………………………. 69
Table 4.21. DC Characteristics …………………………………………………………………….. 70
Table 4.22. Synthesizer AC Electrical Characteristics
…………………………………….. 71
Table 4.23. Receiver AC Electrical Characteristics …………………………………………. 72
Table 4.24. Transmitter AC Electrical Characteristics ……………………………………… 73
Table 4.25. Auxiliary Block Specifications ……………………………………………………… 74
………………………………………………………………….
.
7
5
Table 4.26. Digi
al IO Specifications (nIRQ)
…………………………
.
7
5
Table 4.27. G
IO Specifications (GPIO_0, GPIO_1, and GPIO_2)
Table 4.28. A
olute Maximum Ratings ………………………………………………………… 76
Table 4.29. Thermal Properties ……………………………………………………………………. 76
Table
.1. Representative Conversion Times and Energy Consumption for the SAR
ADC with 1.65 V High-Speed VREF …………………………………………….. 84
Table 8.1. CIP-51 Instruction Set Summary …………………………………………………. 116
Table 10.1. EMIF Pinout ……………………………………………………………………………. 130
Table 10.2. AC Parameters for External Memory Interface …………………………….. 144
Table 12.1. Example 16-bit CRC Outputs
……………………………………………………. 160
Table 12.2. Example 32-bit CRC Outputs
……………………………………………………. 162
Table 14.1. Extended Key Output Byte Order ………………………………………………. 181
Table 14.2. 192-Bit Key DMA Usage …………………………………………………………… 182
Table 14.3. 256-bit Key DMA Usage …………………………………………………………… 182
Rev. 1.0
16
Si102x/3x
Table 15.1. Encoder Input and Output Data Sizes ………………………………………… 206
Table 15.2. Manchester Encoding ………………………………………………………………. 207
Table 15.3. Manchester Decoding ………………………………………………………………. 208
Table 15.4. Three-out-of-Six Encoding Nibble
……………………………………………… 209
Table 15.5. Three-out-of-Six Decoding
……………………………………………………….. 210
Table 16.1. SFR Map (0xC0–0xFF)
……………………………………………………………. 22
Table 16.2. SFR Map (0x80–0xBF) …………………………………………………………….. 222
Table 16.3. Special Function Registers ……………………………………………………….. 223
Table 17.1. Interrupt Summary ……………………………………………………………
…… 233
Table 18.1. Flash Security Summary
…………………………………………….
………… 247
Table 19.1. Power Modes …………………………………………………………..
……… 257
Table 20.1. IPeak Inductor Current Limit Settings …………………………………………. 270
Table 23.1. Recommended XFCN Settings for Crystal Mode …………………………. 288
Table 23.2. Recommended XFCN Settings for RC and C modes ……………………. 289
Table 24.1. SmaRTClock Internal Registers
……………………
………………………… 296
Table 24.2. SmaRTClock Load Capacitance Settings
…………………………………… 302
Table 24.3. SmaRTClock Bias Settings
………………………………………………………. 303
Table 25.1. Pull-Up Resistor Current …………………………………………………………… 315
Table 25.2. Sample Rate Duty-Cycle Multiplier …
………………………………………… 315
Table 25.3. Pull-Up Duty-Cycle Multiplier …………
………………………………………. 315
Table 25.4. Average Pull-Up Current (Sample Rate = 250 µs)
……………………….. 316
Table 25.5. Average Pull-Up Current (Sa
le Rate = 500 µs)
……………………….. 316
Table 25.6.
Average Pull-Up Current (Sample Rate = 1 ms)
…………………………. 316
Table 25.7. Average Pull-Up Current (Sample Rate = 2 ms)
………………………….. 316
Table 26.1. Bit Configurations to s
ct Contrast Control Modes …………………….. 338
Table 27.1. Port I/O Assignment for Analog Functions
………………………………….. 353
Table 27.2. Port I/O Assignment for Digital Functions ……………………………………. 354
Table 27.3. Port I/O Assignment for External Digital Event Capture Functions
…. 354
Table 28.1. SMBus Clock Source Selection …………………………………………………. 385
Table 28.2. Minimum SDA Setup and Hold Times ………………………………………… 386
Table 28.3. Sources for Hardware Changes to SMB0CN
………………………………. 390
Table 28.4. Hardware Address Recognition Examples (EHACK = 1) ………………. 391
Table 28.5.
Bus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) …………………………………………………………………………… 398
Table 28.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) …………………………………………………………………………… 400
ble 29.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator ………………………………………. 409
Table 29.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ………………………………….. 409
Table 30.1. SPI Slave Timing Parameters
…………………………………………………… 423
Table 31.1. SPI Timing Parameters
……………………………………………………………. 434
Table 32.1. EZRadioPRO Operating Modes
………………………………………………… 436
Table 32.2. EZRadioPRO Operating Modes Response Time …………………………. 437
Table 32.3. Frequency Band Selection
……………………………………………………….. 443
17
Rev. 1.0
Si102x/3x
Table 32.4. Packet Handler Registers …………………………………………………………. 462
Table 32.5. Minimum Receiver Settling Time ……………………………………………….. 464
Table 32.6. POR Parameters
…………………………………………………………………….. 467
Table 32.7. Temperature Sensor Range ……………………………………………………… 470
Table 32.8. Antenna Diversity Control …………………………………………………………. 475
Table 32.9. EZRadioPRO Internal Register Descriptions ……………………………….. 48
Table 33.1. Timer 0 Running Modes
…………………………………………………………… 485
Table 34.1. PCA Timebase Input Options ……………………………………………………. 506
Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Comp
e
Modules ……………………………………………………………………
…………. 508
Table 34.3. Watchdog Timer Timeout Intervals1 ……………………………
……… 518
Rev. 1.0
18
Si102x/3x
List of Registers
SFR Definition 5.1. ADC0CN: ADC0 Control ………………………………………………………. 85
SFR Definition 5.2. ADC0CF: ADC0 Configuration
……………………………………………… 86
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration
…………………………… 87
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ………………………. 88
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ………………………………… 8
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte
…………………………………….. 90
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte ………………………………………. 90
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ……………………
……… 91
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte
……………
………… 91
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte
…………………
…………. 92
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte …………………………………. 92
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select …………………………………. 95
SFR Definition 5.13. TOFFH: Temperature Sensor Offset High B
te ……………………… 98
SFR Definition 5.14. TOFFL: Temperature Sensor Offset Low Byte ………………………. 98
SFR Definition 5.15. REF0CN: Voltage Reference Control …………………………………. 101
SFR Definition 6.1. IREF0CN: Current Reference Control
………………………………….. 102
SFR Definition 6.2. IREF0CF: Current Reference Configuration ………………………….. 103
SFR Definition 7.1. CPT0CN: Comparator 0 Contro
……………………………………… 107
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection
……………………………… 108
SFR Definition 7.3. CPT1CN: Comparator 1 Control ………………………………………….. 109
SFR Definition 7.4. CPT1MD: Comparator 1
de Selection
……………………………… 110
SFR Definition 7.5. CPT0MX: Comparato
0 Input Channel Select ……………………….. 112
SFR Definition 7.6. CPT1MX: Compa
or1 Input Channel Select ……………………….. 113
SFR Definition 8.1. DPL: Data Pointer
ow Byte ……………………………………………….. 120
SFR Definition 8.2. DPH: Data Pointer High Byte ………………………………………………. 120
SFR Definition 8.3. SP: Stack
ointer ………………………………………………………………. 121
SFR Definition 8.4. ACC: Accumulator
…………………………………………………………….. 121
SFR Definition 8.5. B: B Register …………………………………………………………………….. 121
SFR Definition 8.6. PSW: Program Status Word ……………………………………………….. 122
SFR Definition 9.1. PSBANK: Program Space Bank Select ………………………………… 126
SFR Definition 1
1. EMI0CN: External Memory Interface Control
………………………. 131
SFR Definition 1
2. EMI0CF: External Memory Configuration ……………………………. 132
SFR Definition 10.3. EMI0TC: External Memory Timing Control ………………………….. 137
SFR Def
ition 11.1. DMA0EN: DMA0 Channel Enable
……………………………………… 149
SF
efinition 11.2. DMA0INT: DMA0 Full-Length Interrupt ……………………………….. 150
SFR Definition 11.3. DMA0MINT: DMA0 Mid-Point Interrupt
………………………………. 151
SFR Definition 11.4. DMA0BUSY: DMA0 Busy …………………………………………………. 152
SFR Definition 11.5. DMA0SEL: DMA0 Channel Select for Configuration …………….. 153
SFR Definition 11.6. DMA0NMD: DMA Channel Mode
………………………………………. 153
SFR Definition 11.7. DMA0NCF: DMA Channel Configuration …………………………….. 155
SFR Definition 11.8. DMA0NBAH: Memory Base Address High Byte …………………… 156
SFR Definition 11.9. DMA0NBAL: Memory Base Address Low Byte
……………………. 156
SFR Definition 11.10. DMA0NAOH: Memory Address Offset High Byte ……………….. 157
Rev. 1.0
19
Si102x/3x
SFR Definition 11.11. DMA0NAOL: Memory Address Offset Low Byte
………………… 157
SFR Definition 11.12. DMA0NSZH: Transfer Size High Byte ………………………………. 158
SFR Definition 11.13. DMA0NSZL: Memory Transfer Size Low Byte
…………………… 158
SFR Definition 12.1. CRC0CN: CRC0 Control
………………………………………………….. 163
SFR Definition 12.2. CRC0IN: CRC0 Data Input ……………………………………………….. 164
SFR Definition 12.3. CRC0DAT: CRC0 Data Output ………………………………………….. 16
SFR Definition 12.4. CRC0AUTO: CRC0 Automatic Control ……………………………….. 165
SFR Definition 12.5. CRC0CNT: CRC0 Automatic Flash Sector Count ………………… 165
SFR Definition 12.6. CRC0FLIP: CRC0 Bit Flip ………………………………………….
…… 166
SFR Definition 13.1. CRC1CN: CRC1 Control
…………………………………….
…………. 171
SFR Definition 13.2. CRC1IN: CRC1 Data IN
……………………………………
……… 172
SFR Definition 13.3. CRC1POLL: CRC1 Polynomial LSB …………………………………… 172
SFR Definition 13.4. CRC1POLH: CRC1 Polynomial MSB …………………………………. 172
SFR Definition 13.5. CRC1OUTL: CRC1 Output LSB ………………………………………… 173
SFR Definition 13.6. CRC1OUTH: CRC1 Output MSB
………….
………………………… 173
SFR Definition 14.1. AES0BCFG: AES Block Configuration
……………………………….. 201
SFR Definition 14.2. AES0DCFG: AES Data Configuration
………………………………… 202
SFR Definition 14.3. AES0BIN: AES Block Input ……………………………………………….. 203
SFR Definition 14.4. AES0XIN: AES XOR Input …….
………………………………………… 204
SFR Definition 14.5. AES0KIN: AES Key Input
……..
………………………………………. 204
SFR Definition 14.6. AES0YOUT: AES Y Output
………………………………………………. 205
SFR Definition 15.1. ENC0CN: Encoder Dec
er 0 Control
……………………………….. 213
SFR Definition 15.2. ENC0L: ENC0 Data Low Byte
…………………………………………… 214
SFR Definition 15.3. ENC0M: ENC0 Data Middle Byte
………………………………………. 214
SFR Definition 15.4. ENC0H: ENC0
High Byte ………………………………………….. 214
SFR Definition 16.1. SFRPGCN: SFR Page Control ………………………………………….. 217
SFR Definition 16.2. SFRPAGE: SFR Page ……………………………………………………… 218
SFR Definition 16.3. SFRNEX
: SFR Next
………………………………………………………. 219
SFR Definition 16.4. SFRLAST: SFR Last ………………………………………………………… 220
SFR Definition 17.1. IE: Interrupt Enable ………………………………………………………….. 235
SFR Definition 17.2. IP: Interrupt Priority ………………………………………………………….. 236
SFR Definition 17.3. EIE1: Extended Interrupt Enable 1
…………………………………….. 237
SFR Definition
. EIP1: Extended Interrupt Priority 1
…………………………………….. 238
SFR Definition 17.5. EIE2: Extended Interrupt Enable 2
…………………………………….. 239
SFR Definition 17.6. EIP2: Extended Interrupt Priority 2
…………………………………….. 240
SFR
efi
ition 17.7. IT01CF: INT0/INT1 Configuration ………………………………………. 242
SF
Definition 18.1. DEVICEID: Device Identification ………………………………………… 248
SFR Definition 18.2. REVID: Revision Identification …………………………………………… 249
SFR Definition 18.3. PSCTL: Program Store R/W Control
………………………………….. 253
FR Definition 18.4. FLKEY: Flash Lock and Key ……………………………………………… 254
SFR Definition 18.5. FLSCL: Flash Scale …………………………………………………………. 255
SFR Definition 18.6. FLWR: Flash Write Only …………………………………………………… 255
SFR Definition 18.7. FRBCN: Flash Read Buffer Control ……………………………………. 256
SFR Definition 19.1. PCLKACT: Peripheral Active Clock Enable …………………………. 260
SFR Definition 19.2. PCLKEN: Peripheral Clock Enable …………………………………….. 261
20
Rev. 1.0
Si102x/3x
SFR Definition 19.3. CLKMODE: Clock Mode …………………………………………………… 262
1,2,3 ……………….
.
2
65
SFR Definition 19.4. PMU0CF: Power Management Unit Configuration
SFR Definition 19.5. PMU0FL: Power Management Unit Flag
1,2 ………………………………….
.
2
66
SFR Definition 19.6. PMU0MD: Power Management Unit Mode ………………………….. 267
SFR Definition 19.7. PCON: Power Management Control Register
……………………… 268
SFR Definition 20.1. DC0CN: DC-DC Converter Control
……………………………………. 27
SFR Definition 20.2. DC0CF: DC-DC Converter Configuration ……………………………. 274
SFR Definition 20.3. DC0MD: DC-DC Converter Mode ………………………………………. 275
SFR Definition 20.4. DC0RDY: DC-DC Converter Ready Indicator
………………
…… 276
SFR Definition 21.1. REG0CN: Voltage Regulator Control
……………………
…………. 277
SFR Definition 22.1. VDM0CN: VDD Supply Monitor Control
………………
……… 282
SFR Definition 22.2. RSTSRC: Reset Source
…………………………………………………… 285
SFR Definition 23.1. CLKSEL: Clock Select ……………………………………………………… 291
SFR Definition 23.2. OSCICN: Internal Oscillator Control
…………………………………… 292
SFR Definition 23.3. OSCICL: Internal Oscillator Calibration
….
………………………… 293
SFR Definition 23.4. OSCXCN: External Oscillator Control …………………………………. 294
SFR Definition 24.1. RTC0KEY: SmaRTClock Lock and Key
……………………………… 298
SFR Definition 24.2. RTC0ADR: SmaRTClock Address
…………………………………….. 298
SFR Definition 24.3. RTC0DAT: SmaRTClock Data
………………………………………… 299
Internal Register Definition 24.4. RTC0CN: SmaRTC
ck Control
. . . . . . . . . . . . . . . 306
Internal Register Definition 24.5. RTC0XCN: SmaRTClock Oscillator Control . . . . . . 307
Internal Register Definition 24.6. RTC0XCF:
aRTClock Oscillator Configuration
. 308
Internal Register Definition 24.7. RTC0CF: SmaRTClock Configuration
. . . . . . . . . . 309
Internal Register Definition 24.8. CAPTUREn: SmaRTClock Timer Capture
. . . . . . . 310
Internal Register Definition 24.9. ALA
0Bn: SmaRTClock Alarm 0 Match Value
. . 310
Internal Register Definition 24.10. ALARM1Bn: SmaRTClock Alarm 1 Match Value
. 311
Internal Register Definition 24.11. ALARM2Bn: SmaRTClock Alarm 2 Match Value
. 311
SFR Definition 25.1. PC0MD:
C0 Mode Configuration ……………………………………… 321
SFR Definition 25.2. PC0PCF: PC0 Mode Pull-Up Configuration
………………………… 322
SFR Definition 25.3. PC0TH: PC0 Threshold Configuration ………………………………… 323
SFR Definition 25.4. PC0STAT: PC0 Status
…………………………………………………….. 324
SFR Definition 25.5. PC0DCH: PC0 Debounce Configuration High ……………………… 325
SFR Definition
. PC0DCL: PC0 Debounce Configuration Low
………………………. 326
SFR Definition 25.7. PC0CTR0H: PC0 Counter 0 High (MSB)
……………………………. 327
SFR Definition 25.8. PC0CTR0M: PC0 Counter 0 Middle …………………………………… 327
SFR
efi
ition 25.9. PC0CTR0L: PC0 Counter 0 Low (LSB) ………………………………. 327
SF
Definition 25.10. PC0CTR1H: PC0 Counter 1 High (MSB)
………………………….. 328
SFR Definition 25.11. PC0CTR1M: PC0 Counter 1 Middle …………………………………. 328
SFR Definition 25.12. PC0CTR1L: PC0 Counter 1 Low (LSB) …………………………….. 328
FR Definition 25.13. PC0CMP0H: PC0 Comparator 0 High (MSB) …………………….. 329
SFR Definition 25.14. PC0CMP0M: PC0 Comparator 0 Middle
…………………………… 329
SFR Definition 25.15. PC0CMP0L: PC0 Comparator 0 Low (LSB) ………………………. 329
SFR Definition 25.16. PC0CMP1H: PC0 Comparator 1 High (MSB) …………………….. 330
SFR Definition 25.17. PC0CMP1M: PC0 Comparator 1 Middle
…………………………… 330
SFR Definition 25.18. PC0CMP1L: PC0 Comparator 1 Low (LSB) ………………………. 330
Rev. 1.0
21
Si102x/3x
SFR Definition 25.19. PC0HIST: PC0 History
…………………………………………………… 331
SFR Definition 25.20. PC0INT0: PC0 Interrupt 0 ……………………………………………….. 332
SFR Definition 25.21. PC0INT1: PC0 Interrupt 1 ……………………………………………….. 333
SFR Definition 26.1. LCD0Dn: LCD0 Data
……………………………………………………….. 335
SFR Definition 26.2. LCD0CN: LCD0 Control Register
………………………………………. 337
SFR Definition 26.3. LCD0CNTRST: LCD0 Contrast Adjustment
………………………… 34
SFR Definition 26.4. LCD0MSCN: LCD0 Master Control
……………………………………. 342
SFR Definition 26.5. LCD0MSCF: LCD0 Master Configuration ……………………………. 343
SFR Definition 26.6. LCD0PWR: LCD0 Power …………………………………………..
…… 343
SFR Definition 26.7. LCD0VBMCN: LCD0 VBAT Monitor Control
………….
…………. 344
SFR Definition 26.8. LCD0CLKDIVH: LCD0 Refresh Rate Prescaler High
…….. 345
SFR Definition 26.9. LCD0CLKDIVL: LCD Refresh Rate Prescaler Low Byte
……….. 345
SFR Definition 26.10. LCD0BLINK: LCD0 Blink Mask ………………………………………… 346
SFR Definition 26.11. LCD0TOGR: LCD0 Toggle Rate
……………………………………… 347
SFR Definition 26.12. LCD0CF: LCD0 Configuration
…………….
………………………… 348
SFR Definition 26.13. LCD0CHPCN: LCD0 Charge Pump Control ………………………. 348
SFR Definition 26.14. LCD0CHPCF: LCD0 Charge Pump Configuration
……………… 349
SFR Definition 26.15. LCD0CHPMD: LCD0 Charge Pump Mode ………………………… 349
SFR Definition 26.16. LCD0BUFCN: LCD0 Buffer Control ………………………………….. 349
SFR Definition 26.17. LCD0BUFCF: LCD0 Buffer Co
iguration ………………………….
350
SFR Definition 26.18. LCD0BUFMD: LCD0 Buffer Mode ……………………………………. 350
SFR Definition 26.19. LCD0VBMCF: LCD0 V
AT Monitor Configuration ……………… 350
SFR Definition 27.1. XBR0: Port I/O Crossbar Register 0 …………………………………… 358
SFR Definition 27.2. XBR1: Port I/O Cros
bar Register 1 …………………………………… 359
SFR Definition 27.3. XBR2: Port I/O
sbar Register 2 …………………………………… 360
SFR Definition 27.4. P0MASK: Port0 Mask Register ………………………………………….. 361
SFR Definition 27.5. P0MAT: Port0 Match Register …………………………………………… 361
SFR Definition 27.6. P1MASK: Port1 Mask Register ………………………………………….. 362
SFR Definition 27.7. P1MAT: Port1 Match Register …………………………………………… 362
SFR Definition 27.8. P0: Port0 ………………………………………………………………………… 364
SFR Definition 27.9. P0SKIP: Port0 Skip ………………………………………………………….. 364
SFR Definition 27.10. P0MDIN: Port0 Input Mode ……………………………………………… 365
SFR Definition
1. P0MDOUT: Port0 Output Mode ……………………………………….. 365
SFR Definition 27.12. P0DRV: Port0 Drive Strength
………………………………………….. 366
SFR Defin
tion 27.13. P1: Port1 ………………………………………………………………………. 366
SFR
efi
ition 27.14. P1SKIP: Port1 Skip ………………………………………………………… 367
SF
Definition 27.15. P1MDIN: Port1 Input Mode ……………………………………………… 367
SFR Definition 27.16. P1MDOUT: Port1 Output Mode ……………………………………….. 368
SFR Definition 27.17. P1DRV: Port1 Drive Strength
………………………………………….. 368
FR Definition 27.18. P2: Port2 ………………………………………………………………………. 369
SFR Definition 27.19. P2SKIP: Port2 Skip ………………………………………………………… 369
SFR Definition 27.20. P2MDIN: Port2 Input Mode ……………………………………………… 370
SFR Definition 27.21. P2MDOUT: Port2 Output Mode ……………………………………….. 370
SFR Definition 27.22. P2DRV: Port2 Drive Strength
………………………………………….. 371
SFR Definition 27.23. P3: Port3 ………………………………………………………………………. 371
22
Rev. 1.0
Si102x/3x
SFR Definition 27.24. P3MDIN: Port3 Input Mode ……………………………………………… 372
SFR Definition 27.25. P3MDOUT: Port3 Output Mode ……………………………………….. 372
SFR Definition 27.26. P3DRV: Port3 Drive Strength
………………………………………….. 373
SFR Definition 27.27. P4: Port4 ………………………………………………………………………. 373
SFR Definition 27.28. P4MDIN: Port4 Input Mode ……………………………………………… 374
SFR Definition 27.29. P4MDOUT: Port4 Output Mode ……………………………………….. 37
SFR Definition 27.30. P4DRV: Port4 Drive Strength
………………………………………….. 375
SFR Definition 27.31. P5: Port5 ………………………………………………………………………. 375
SFR Definition 27.32. P5MDIN: Port5 Input Mode ……………………………………….
…… 376
SFR Definition 27.33. P5MDOUT: Port5 Output Mode ………………………….
…………. 376
SFR Definition 27.34. P5DRV: Port5 Drive Strength
…………………………..
……… 377
SFR Definition 27.35. P6: Port6 ………………………………………………………………………. 377
SFR Definition 27.36. P6MDIN: Port6 Input Mode ……………………………………………… 378
SFR Definition 27.37. P6MDOUT: Port6 Output Mode ……………………………………….. 378
SFR Definition 27.38. P6DRV: Port6 Drive Strength
……………..
………………………… 379
SFR Definition 27.39. P7: Port7 ………………………………………………………………………. 379
SFR Definition 27.40. P7MDOUT: Port7 Output Mode ……………………………………….. 380
SFR Definition 27.41. P7DRV: Port7 Drive Strength
………………………………………….. 380
SFR Definition 28.1. SMB0CF: SMBus Clock/Config
ration ………………………………..
387
SFR Definition 28.2. SMB0CN: SMBus Control …….
………………………………………. 389
SFR Definition 28.3. SMB0ADR: SMBus Slave Address …………………………………….. 391
SFR Definition 28.4. SMB0ADM: SMBus Sla
Address Mask ……………………………. 392
SFR Definition 28.5. SMB0DAT: SMBus Data …………………………………………………… 393
SFR Definition 29.1. SCON0: Serial Port
Control ……………………………………………. 407
SFR Definition 29.2. SBUF0: Serial (
T0) Port Data Buffer ……………………………. 408
SFR Definition 30.1. SPI0CFG: SPI0 Configuration
…………………………………………… 418
SFR Definition 30.2. SPI0CN: SPI0 Control
……………………………………………………… 419
SFR Definition 30.3. SPI0CKR
SPI0 Clock Rate ………………………………………………. 420
SFR Definition 30.4. SPI0DAT: SPI0 Data
……………………………………………………….. 420
SFR Definition 31.1. SPI1CFG: SPI1 Configuration
…………………………………………… 431
SFR Definition 31.2. SPI1CN: SPI1 Control
……………………………………………………… 432
SFR Definition 31.3. SPI1CKR: SPI1 Clock Rate ………………………………………………. 433
SFR Definition
. SPI1DAT: SPI1 Data
……………………………………………………….. 433
SFR Definition 33.1. CKCON: Clock Control
…………………………………………………….. 484
SFR Definition 33.2. TCON: Timer Control ……………………………………………………….. 489
SFR
efi
ition 33.3. TMOD: Timer Mode …………………………………………………………. 490
SF
Definition 33.4. TL0: Timer 0 Low Byte ……………………………………………………… 491
SFR Definition 33.5. TL1: Timer 1 Low Byte ……………………………………………………… 491
SFR Definition 33.6. TH0: Timer 0 High Byte
……………………………………………………. 492
FR Definition 33.7. TH1: Timer 1 High Byte
……………………………………………………. 492
SFR Definition 33.8. TMR2CN: Timer 2 Control ………………………………………………… 496
SFR Definition 33.9. TMR2RLL: Timer 2 Reload Register Low Byte …………………….. 497
SFR Definition 33.10. TMR2RLH: Timer 2 Reload Register High Byte
…………………. 497
SFR Definition 33.11. TMR2L: Timer 2 Low Byte ………………………………………………. 498
SFR Definition 33.12. TMR2H Timer 2 High Byte ………………………………………………. 498
Rev. 1.0
23
Si102x/3x
SFR Definition 33.13. TMR3CN: Timer 3 Control ………………………………………………. 502
SFR Definition 33.14. TMR3RLL: Timer 3 Reload Register Low Byte …………………… 503
SFR Definition 33.15. TMR3RLH: Timer 3 Reload Register High Byte
…………………. 503
SFR Definition 33.16. TMR3L: Timer 3 Low Byte ………………………………………………. 504
SFR Definition 33.17. TMR3H Timer 3 High Byte ………………………………………………. 504
SFR Definition 34.1. PCA0CN: PCA Control
…………………………………………………….. 51
SFR Definition 34.2. PCA0MD: PCA Mode
………………………………………………………. 520
SFR Definition 34.3. PCA0PWM: PCA PWM Configuration ………………………………… 521
SFR Definition 34.4. PCA0CPMn: PCA Capture/Compare Mode
…………………
…… 522
SFR Definition 34.5. PCA0L: PCA Counter/Timer Low Byte
………………….
………… 523
SFR Definition 34.6. PCA0H: PCA Counter/Timer High Byte ……………….
……… 523
SFR Definition 34.7. PCA0CPLn: PCA Capture Module Low Byte ……………………….. 524
SFR Definition 34.8. PCA0CPHn: PCA Capture Module High Byte
……………………… 524
C2 Register Definition 35.1. C2ADD: C2 Address ……………………………………………… 525
C2 Register Definition 35.2. DEVICEID: C2 Device ID …………..
………………………… 526
C2 Register Definition 35.3. REVID: C2 Revision ID ………………………………………….. 526
C2 Register Definition 35.4. FPCTL: C2 Flash Programming Control …………………… 527
C2 Register Definition 35.5. FPDAT: C2 Flash Programming Data ………………………. 527
24
Rev. 1.0
Si102x/3x
1. System
Overview
Si102x/3x devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features are
listed below. Refer to
T
a
ble 2.1 for specific product feature selection and part ordering numbers.
240-960 MHz EZRadioPRO® transceiver
Power efficient on-chip dc-dc buck converter
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 10-bit 300 ksps, or 12-bit 75 ksps single-ended ADC with 16 external analog inputs and 4 internal
inputs such as various power supply voltages and the temperature sensor
6-bit programmable current reference
Precision programmable 24.5 MHz internal oscillator with spread spectrum technology
128 kB, 64 kB, 32 kB, or 16 kB of on-chip flash memory
8448 or 4352 bytes of on-chip RAM
128 segment LCD driver
2
SMBus/I C,
enhanced UAR
T
,
a
nd two enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable counter/timer array (PCA) with six capture/compare modules and watchdog timer
function
Hardware AES, DMA, and pulse counter
On-chip power-on reset, V
monitor, and temperature sensor
DD
Two on-chip voltage comparators
53-port I/O
With on-chip power-on reset, V
monitor, watch
og timer, and clock oscillator, the Si102x/3x devices are
DD
truly stand-alone system-on-a-chip solutions
flash memory can be reprogrammed even in-circuit, pro-
viding non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has
complete control of all peripherals, and may individually shut down any or all peripherals for power sav-
ings.
The on-chip Silicon Labs 2-w
re (C2) development interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying pack
pins.
Each device is specified for 1.8 to 3.8 V operation over the industrial temperature range (–40 to +85 °C).
The port I/O
nd RST pins are tolerant of input signals up to VIO + 2.0
V
.
T
he Si102x/3x devices are avail-
able i
an 85-pin LGA package that is lead-free and RoHS-compliant. See
T
a
ble 2.1 for ordering informa-
tion
ck diagrams are included in Figure 1.1 and Figure 1.2.
The transceiver’s extremely low receive sensitivity (–121
dBm) coupled with industry leading +13 or
+20 dBm output power ensures extended range and improved link performance. Built-in antenna diversity
nd support for frequency hopping can be used to further extend range and enhance performance. The
advanced radio features including continuous frequency coverage from 240–960 MHz in 156 Hz or 312 Hz
steps allow precise tuning control. Additional system features such as an automatic wake-up timer, low
battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall
current consumption.
Rev. 1.0
25
Si102x/3x
The transceiver’s digital receive architecture features a high-performance ADC and DSP-based modem
which performs demodulation, filtering, and packet handling for increased flexibility and performance. The
direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and
reduced spectral spreading, ensuring compliance with global regulations including FCC, ETSI, ARIB, and
802.15.4d.
26
Rev. 1.0
Si102x/3x
Port I/O Configuration
CIP-51 8051
Controller Core
128/64/32/16 kByte
ISP Flash Program
Memory
Power On
Reset/PMU
16
Port 0-1
Drivers
P0.0…P1.7
Digital Peripherals
Wake
Reset
4
UART
Port 2
Drivers
P2.4…P2.7
Timers
32
Port 3-6
Drivers
Debug /
Programming
Hardware
0/1/2/3
C2CK/RST
256 Byte SRAM
P3.0…P6.7
Priority
Crossbar
PCA/
8192/4096 Byte XRAM
Port 7
Driver
Decoder
WDT
P7.0/C2D
C2D
DMA
SMBus
SPI 0
Analog
CRC
VBAT
VBAT
RF XCVR
(240-960 MHz,
+20/+13 dBm)
VREG
VREG
Power
Engine
VDD
Digital
Power
Crossbar Control
LCD (4×32)
AES
Engine
DCOUT+
PA
VCO
Encoder
EMIF
SFR
Bus
DC/DC
Buck
Converter
AGC
LNA
SYSCLK
RXn
DCEN
DCIN-
Pulse Counter
EZRadioPro SPI 1
Precision
24.5 MHz
Oscillator
Mi
r
PGA
ADC
Low Power
20 MHz
Oscillator
Analog Peripherals
LCD Charge
Pump
CAP
igital
Modem
External
VREF
Internal
VREF
External
Oscillator
Circuit
XTAL1
XTAL2
VDD
VRE
Delta
Sigma
Modulator
A
M
U
X
12-bit
Temp
Sensor
75ksps
ADC
Digital
Logic
Enhanced
smaRTClock
Oscillator
XTAL3
XTAL4
GND
GND
CP0,
30 MHz
XOUT
XIN
System Clock
Configuration
CP
P1A
Comparators
Figure 1.1. Si102
lock Diagram
Port I/O Configuration
CIP-51 8051
Power On
Reset/PMU
16
Port 0-1
Drivers
Controller Core
Digital Peripherals
128/64/32/
6 kByte
P0.0…P1.7
Wake
Reset
4
UART
Port 2
Drivers
ISP Flash Pr
gram
P2.4…P2.7
ory
Timers
32
Port 3-6
Drivers
Debug /
Programming
Hardware
0/1/2/3
C2CK/RST
256 Byte SRAM
P3.0…P6.7
Priority
Crossbar
Decoder
PCA/
WDT
8192/4096 Byte XRAM
DMA
Port 7
Driver
P7.0/C2D
C2D
SMBus
SPI 0
Analog
CRC
VBA
VBAT
RF XCVR
(240-960 MHz,
+20/+13 dBm)
VREG
VREG
Power
Engine
VDD
Digital
Power
Crossbar Control
AES
Engine
DCOUT+
PA
VCO
TX
Encoder
EMIF
SFR
Bus
DC/DC
“Buck”
Converter
AGC
LNA
SYSCLK
RXp
RXn
DCEN
DCI
–
Pulse Counter
EZRadioPro SPI 1
Precision
24.5 MHz
Oscillator
Mixer
PGA
ADC
Low Power
20 MHz
Oscillator
Analog Peripherals
LCD Charge
Pump
CAP
Digital
Modem
External
VREF
Internal
VREF
External
Oscillator
Circuit
XTAL1
XTAL2
VDD
VREF
Delta
Sigma
Modulator
A
M
U
X
12-bit
Temp
Sensor
75ksps
ADC
Digital
Logic
Enhanced
smaRTClock
Oscillator
XTAL3
XTAL4
GND
GND
CP0, CP0A
+
–
30 MHz
XOUT
XIN
System Clock
Configuration
CP1, CP1A
+
–
Comparators
Figure 1.2. Si103x Block Diagram
Rev. 1.0
27
Si102x/3x
1.1. Typical
Connection Diagram
The application shown in Figure 1.7 is designed for a system with a TX/RX direct-tie configuration without
the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie
reference design is available from Silicon Laboratories applications support.
For applications seeking improved performance in the presence of multipath fading, antenna diversity can
be used. Antenna diversity support is integrated into the EZRadioPRO transceiver and can improve t
system link budget by 8–10 dB in the presence of these fading conditions, resulting in substantial rang
increases. A complete Antenna Diversity reference design is available from Silicon Laboratories applica-
tions support.
supply voltage
X1
30MHz
C6
C7
C8
1u
100p
100n
L1
VDD_RF
VDD_MCU
VDD_DIG
L2
TX
Px.x
L4
C3
L3
C2
C1
RFp
Si1020
1/2/3
Si1
/1/2/3
RXn
C4
0.1 uF
0.1 uF
L6
L5
C9
1u
C5
Figure 1.3. Si102x/3x RX/TX Direct-tie Application Example
Supply Voltage
X1
30 MHz
C6
C7
C8
1 u
100 p
100 n
L1
VDD_RF
VDD_MCU
VDD_DIG
TR &
-DIV
Switch
L3
L2
TX
Px.x
C1
C3
C2
RXp
1
6
5
4
Si102x
Si103x
RXn
2
3
C4
0.1 uF
0.1 uF
L4
C9
1u
C5
Figure 1.4. Si102x/3x Antenna Diversity Application Example
28
Rev. 1.0
Si102x/3x
1.2. CIP-51™
Microcontroller Core
1.2.1. Fully 8051 Compatible
The Si102x/3x family utilizes Silicon Labs’ proprietary CIP-51 microcontroller core. The CIP-51 is fully com-
patible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to
develop software. The CIP-51 core offers all the peripherals included with a standard 8052.
1.2.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 sys
em
clock cycles to execute with a maximum system clock of 12–24 MHz. By contrast, the CIP-5
core exe-
cutes 70% of its instructions in one or two system clock cycles, with only four instructions
king more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute
1
2
2/3
5
3
3/4
7
4
3
4/5
1
5
2
8
1
Number of Instructions
26
50
14
With the CIP-51’s maximum system clock at 25 MHz, it has a
k throughput of 25 MIPS.
1.2.3. Additional Features
The Si102x/3x SoC family includes several key enh
ncements to the CIP-51 core and peripherals to
improve performance and ease of use in end applicat
.
The extended interrupt handler provides multiple
terrupt sources into the CIP-51 allowing numerous ana-
log and digital peripherals to interrupt the co
ller. An interrupt driven system requires less intervention
by the MCU, giving it more effective throughp
The extra interrupt sources are very useful when building
multi-tasking, real-time systems.
Eight reset sources are available: p
wer-on reset circuitry (POR), an on-chip V
monitor (forces reset
DD
when power supply voltage drops below safe levels), a watchdog timer, a missing clock detector, SmaRT-
Clock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an exter-
nal reset pin, and an illegal flash access protection circuit. Each reset source except for the POR, Reset
Input Pin, or flash error may be disabled by the user in software. The WDT may be permanently disabled in
software after a power-on reset during MCU initialization.
The internal oscilla
actory calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and
supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz
low power o
illator is also available which facilitates low-power operation. An external oscillator drive cir-
cuit is
nclu
ed, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to
gen
e the system clock. If desired, the system clock source may be switched on-the-fly between both
internal and external oscillator circuits. An external oscillator can also be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to
the fast (up to 25 MHz) internal oscillator as needed.
Rev. 1.0
29
Si102x/3x
1.3. Port
Input/Output
Digital and analog resources are available through 53 I/O pins. Port pins are organized as eight byte-wide
ports. Port pins can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the inter-
nal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal ana-
log resources. P7.0 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See
Section “35. C2 Interface” on page 525 for more details.
The designer has complete control over which digital and analog functions are assigned to individual po
pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See
Section “27. Port Input/Output” on page 351 for more information on the Crossbar.
For Port I/Os configured as push-pull outputs, current is sourced from the VIO, VIOR
F
,
o
r
AT supply pin.
Port I/Os used for analog functions can operate up to the supply voltage. See Section
rt Input/Out-
put” on page 351 for more information on Port I/O operating modes and the electrical spe
cations chap-
ter for detailed electrical specifications.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
PnMDOUT
PnMDIN Registers
External Interrupts
EX0 and EX1
P0.0
P0
I/O
8
Priority
Cells
Decode
P0.7
P1.0
2
UART
Highest
Priority
P1
I/O
Cells
8
8
4
2
SPI0
SPI1
P1.7
P2.0
SMBus
P2
I/O
Cells
Digital
Crossbar
CP0
CP1
Outputs
4
P2.7
P3.0
P3
I/O
Cells
8
8
8
SYSCLK
PCA
P3.7
P4.0
7
2
P4
I/O
Cells
Lowest
Priority
T0, T1
P4.7
P5.0
P5
I/O
8
P0
Cells
P5.7
P6.0
P6
I/O
Cells
8
8
1
(P6.0-P6.7)
P6
P7
P6.7
P7.0
1
P7
(P7.0)
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
To LCD
To EMIF
Figure 1.5. Port I/O Functional Block Diagram
30
Rev. 1.0
Si102x/3x
1.4. Serial
Ports
2
The Si102x/3x Family includes an SMBus/I C interface, a full-duplex UART with enhanced baud rate con-
figuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hardware and
makes extensive use of the CIP-51’s interrupts, thus requiring very little CPU intervention.
1.5. Programmable
Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pu
pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programma-
ble capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the sys
m clock, or
the external oscillator clock source divided by 8.
Each capture/compare module can be configured to operate in a variety of modes: edge-t
ered capture,
software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Addi-
tionally, Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset,
Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External
Clock Input may be routed to Port I/O via the Digital Crossbar.
SYSCL
K
/12
SYSCL
K
/
4
PCA
CLOCK
MUX
Timer0 Overflow
ECI
16 -Bit Counter/Timer
SYSCLK
External Clock 8
/
Capture/ Compare
Modul
e
0
Capture/ Com
e
Modul
e
1
Capture/ Compare
Modul
e
2
Capture/ Compare
Modul
e
3
Capture/ Compare
Modul
e
4
Capture/ Compare
Module5 / WDT
Crossbar
Port
I
/O
Figure 1.6. PCA Block Diagram
Rev. 1.0
31
Si102x/3x
1.6. SAR
ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode
The ADC0 on Si102x/3x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation-register
(SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autono-
mous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples,
then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulato
that can automatically oversample and average the ADC results. See Section “5.4.
12-Bit Mode”
page 83 for more details on using the ADC in 12-bit mode.
The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in
single-ended mode and may be configured to measure various different signals using the a
alog multi-
plexer described in Section “5.7. ADC0 Analog Multiplexer” on page 94. The voltage ref
for the ADC
is selected as described in Section “5.9. Voltage and Ground Reference Options” on pag
.
ADC0CN
VDD
000
001
010
011
100
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
Start
Conversion
ADC0TK
Burst Mode Logic
ADC0PWR
10/12-Bit
SAR
AIN+
From
AMUX0
16-Bit Accumulator
AD0WINT
ADC
Window
Compare
Logic
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
ADC0CF
Figure 1.7. ADC0 Functional Block Diagram
32
Rev. 1.0
Si102x/3x
ADC0MX
P0.0
Programmable
Attenuator
AI
N
+
ADC0
AMUX
P2.6*
VBAT
Temp
Sensor
Gai
n
=
0
. 5 or1
Digital Supply
VD
D
/
D
C
+
*P1.7-P2. 6
only available
s
inputs on 32- pin pa
es
Figure 1.8. ADC0 Multiplexer Block Diagram
1.7. Programmable
Current
eference (IREF0)
Si102x/3x devices include an on-chip programmable current reference (source or sink) with two output cur-
rent settings: low power mode and high current mode. The maximum current output in low power mode is
63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps).
1.8. Comparators
Si102x/3x devices
de two on-chip programmable voltage comparators: Comparator 0 (CPT0) which is
shown in Figure 1.9; Comparator 1 (CPT1) which is shown in Figure 1.10. The two comparators operate
identically but may differ in their ability to be used as reset or wake-up sources. See Section “22. Reset
Sources” o
page 278 and the Section “19. Power Management” on page 257 for details on reset sources
and
power mode wake-up sources, respectively.
The comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
ystem clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
The comparator inputs may be connected to Port I/O pins or to other internal signals.
Rev. 1.0
33
Si102x/3x
CP0EN
CP0OUT
CP0RIF
VDD
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0
Interrupt
CPT0MD
Analog Input Multiplexer
CP0
Rising-edge
CP0
F
g-e
ge
Px.x
CP0 +
Interrupt
Logic
Px.x
Px.x
CP0
+
–
SET
SET
CLR
D
Q
Q
D
Q
Q
CLR
Crossbar
(SYNCHRONI
R
(ASYNCH
ONOUS)
GND
CP0 –
CP0A
Reset
Decision
Tree
Px.x
Figure 1.9. Comparator 0 Functional Block Diagram
CP1EN
CP1OUT
CP1RIF
CP1FIF
VDD
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1
Interrupt
CPT0MD
Analog Input Multiplexer
CP1
Rising-edge
CP1
Falling-edge
Px.x
CP1 +
Interrupt
Logic
Px.
Px.x
CP1
+
–
SET
SET
CLR
D
Q
Q
D
Q
Q
CLR
Crossbar
(SYNCHRONIZER)
(ASYNCHRONOUS)
GND
CP1 –
CP1A
Reset
Decision
Tree
Px.x
Figure 1.10. Comparator 1 Functional Block Diagram
34
Rev. 1.0
Si102x/3x
2. Ordering
Information
Table 2.1. Product Selection Guide
Si1020-B-GM3 25 128 8448 20 128 53
Si1021-B-GM3 25
64 8448
20 128 53
Si1022-B-GM3 25
32 8448
20 128 53
Si1023-B-GM3 25
16 4352
20 128 53
Si1024-B-GM3 25 128 8448 13 128 53
Si1025-B-GM3 25
64 8448
13 128
Si1026-B-GM3 25
32 8448
13 128 53
Si1027-B-GM3 25
16 4352
13 128 53
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
LGA-85 (6×8)
Si1030-B-GM3 25 128 8448 20
Si1031-B-GM3 25
64 8448
20
Si1032-B-GM3 25
32 8448
20
Si1033-B-GM3 25
16 4352
20
Si1034-B-G
3 25 128 8448 13
Si1
B-GM3 25
64 8448
13
Si1036-B-GM3 25
32 8448
13
Si1037-B-GM3 25
16 4352
13
—
—
—
—
—
—
—
—
53
53
53
53
53
53
53
53
All packages are lead-free (RoHS Compliant).
Rev. 1.0
35
Si102x/3x
3. Pinout
and Package Definitions
Table 3.1. Pin Definitions for the Si102x/3x
Pin
Number
Name
Type
Description
VBAT
VBATDC
VDC
A43
A44
A46
P In
P In
P In
Battery Supply Voltage. Must be 1.8 to 3.8
V
.
DC0 Input Voltage. Must be 1.8 to 3.8 V.
Alternate Power Supply Voltage. Must be 1.8 to 3.6
V
.
is supply
voltage must always be
VBAT. Software may s
t this supply
voltage to power the digital logic.
Positive output of the dc-dc converter. A 1 u to 10 uF ceramic
capacitor is required on this pin when using the dc-dc converter.
This pin can supply power to externa
evices when the dc-dc
converter is enabled.
P Out
GNDDC
A45
P In
DC-DC converter return current path. This pin is typically tied to
the ground plane.
GND
GND
GND
GND
GND
GND
IND
D2
D6
G
G
Required Ground.
Required Ground.
Required Ground.
Required Gro
Required Ground.
Requ
Ground.
B16
B17
A32
B28
B27
G
G
G
G
P In
DC-DC Inductor Pin. This pin requires a 560 nH inductor to VDC if
the DC-DC converter is used.
VIO
VIORF
RST/
B26
B29
7
P In
P In
I/O Power Supply for P0.0–P1.4 and P2.4–P7.0 pins. This supply
voltage must always be
VBAT.
I/O Power Supply for P1.5–P2.3 pins. This supply voltage must
always be
VBAT
D I/O
Device Reset. Open-drain output of internal POR or V
monitor.
DD
An external source can initiate a system reset by driving this pin
low for at least 15 µs. A 1 k
to 5 k
pullup to V
is recom-
DD
mended. See Reset Sources Section for a complete description.
Clock signal for the C2 Debug Interface.
C2CK
P7.0/
D I/O
D I/O
A48
Port 7.0. This pin can only be used as GPIO. The Crossbar cannot
route signals to this pin and it cannot be configured as an analog
input. See Port I/O Section for a complete description.
Bi-directional data signal for the C2 Debug Interface.
C2D
D I/O
Rev. 1.0
36
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x
(Continued)
Pin
Name
Type
Description
Number
VLCD
P0.0
A29
A42
P I/O
LCD Power Supply. This pin requires a 10 µF capacitor to stabilize
the charge pump.
D I/O or A
Port 0.0. See Port I/O Section for a complete description.
In
A In
V
External V
Input.
REF
REF
A Out
Internal V
Output. External V
decoupling
citors are
REF
REF
recommended. See ADC0 Section for details.
P0.1
A41
A40
D I/O or A
Port 0.1. See Port I/O Section for a complete description.
In
G
AGND
P0.2
Optional Analog Ground. See ADC0
ec
ion for details.
D I/O or A
Port 0.2. See Port I/O Section for a complete description.
In
A In
XTAL1
P0.3
External Clock Input. T
pin is the external oscillator return for a
crystal or resonator. Se
scillator Section.
A39
D I/O or A
Port 0.3. See Port I/O Section for a complete description.
In
A Out
D In
XTAL2
External Clock Output. This pin is the excitation driver for an
exte
crystal or resonator.
External Clock Input. This pin is the external clock input in exter-
nal CMOS clock mode.
External Clock Input. This pin is the external clock input in capaci-
tor or RC oscillator configurations.
A In
See Oscillator Section for complete details.
P0.4
A38
A37
A36
D I/O or A
Port 0.4. See Port I/O Section for a complete description.
In
D Out
TX
UART TX Pin. See Port I/O Section.
P0.5
D I/O or A
Port 0.5. See Port I/O Section for a complete description.
In
D In
RX
UART RX Pin. See Port I/O Section.
P0.6
D I/O or A
Port 0.6. See Port I/O Section for a complete description.
In
D In
CNVSTR
External Convert Start Input for ADC0. See ADC0 section for a
complete description.
37
Rev. 1.0
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x
(Continued)
Pin
Name
Type
Description
Number
P0.7
A35
D I/O or A
Port 0.7. See Port I/O Section for a complete description.
In
A Out
IREF0
P1.0
IREF0 Output. See IREF Section for complete description.
A34
A33
A31
A30
D I/O or
Port 1.0. See Port I/O Section for a complete description. May
A In
also be used as SCK for SPI0.
Pulse Counter 0.
PC0
P1.1
D I/O
D I/O or
Port 1.1. See Port I/O Section for a complete des
tion.
A In
May also be used as MISO for SPI0.
PC1
P1.2
D I/O
Pulse Counter 1.
D I/O or
Port 1.2. See Port I/O Section for a complete description.
A In
May also be used as MOSI for SPI0.
XTAL3
P1.3
A In
SmaRTClock Oscillator Crystal Input.
D I/O or
Port 1.3. See Port I/O
ion for a complete description.
A In
May also be used as NSS for SPI0.
XTAL4
P1.4
A Out
SmaRTClock
illator Crystal Output.
A28
A27
A26
D7
D I/O or
Port 1.4.
ee Port I/O Section for a complete description.
A In
P1.5
P1.6
P1.7
P2.4
D I/O or
Port 1.5. See Port I/O Section for a complete description.
VIORF supply.
D I/O o
Port 1.6. See Port I/O Section for a complete description.
A In
VIORF supply. INT0/1
D I/O or
Port 1.7. See Port I/O Section for a complete description.
A In
VIORF supply. INT0/1
A In
A12
D I/O or
Port 2.4. See Port I/O Section for a complete description.
A In
COM0
.5
A O
LCD Common Pin 0 (Backplane Driver)
B10
A11
D I/O or
Port 2.5. See Port I/O Section for a complete description.
A In
COM1
P2.6
A O
LCD Common Pin 1 (Backplane Driver)
D I/O or
Port 2.6. See Port I/O Section for a complete description.
A In
COM2
A O
LCD Common Pin 2 (Backplane Driver)
Rev. 1.0
38
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x
(Continued)
Pin
Name
Type
Description
Number
P2.7
A10
A9
A8
A7
A6
A5
A4
3
A2
A1
D I/O or
Port 2.7. See Port I/O Section for a complete description.
A In
COM2
P3.0
A O
LCD Common Pin 3 (Backplane Driver)
D I/O or
Port 3.0. See Port I/O Section for a complete description.
A In
LCD0
P3.1
A O
LCD Segment Pin 0
D I/O or
Port 3.1. See Port I/O Section for a complete description.
A In
LCD1
P3.2
A O
LCD Segment Pin 1
D I/O or
Port 3.2. See Port I/O Section for a complete description.
A In
LCD2
P3.3
A O
LCD Segment Pin 2
D I/O or
Port 3.3. See Port I/O Section for a complete description.
A In
LCD3
P3.4
A O
LCD Seg
nt Pin 3
D I/O or
Port
. See Port I/O Section for a complete description.
A In
LCD4
P3.5
A O
LCD Segment Pin 4
D I/O or
Port 3.5. See Port I/O Section for a complete description.
A In
LCD5
P3.6
A O
LCD Segment Pin 5
D I/O or
Port 3.6. See Port I/O Section for a complete description.
A In
LCD6
.7
A O
LCD Segment Pin 6
D I/O or
Port 3.7. See Port I/O Section for a complete description.
A In
LCD7
P4.0
A O
LCD Segment Pin 7
D I/O or
Port 4.0. See Port I/O Section for a complete description.
A In
LCD8
A O
LCD Segment Pin 8
39
Rev. 1.0
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x
(Continued)
Pin
Name
Type
Description
Number
P4.1
B25
D I/O or
Port 4.1. See Port I/O Section for a complete description.
A In
LCD9
P4.2
A O
LCD Segment Pin 9
B24
B23
D4/D8
B22
B21
B20
19
B18
B15
D I/O or
Port 4.2. See Port I/O Section for a complete description.
A In
LCD10
P4.3
A O
LCD Segment Pin 10
D I/O or
Port 4.3. See Port I/O Section for a complete description.
A In
LCD11
P4.4
A O
LCD Segment Pin 11
D I/O or
Port 4.4. See Port I/O Section for a complete description.
A In
LCD12
P4.5
A O
LCD Segment Pin 12
D I/O or
Port 4.5. See Port I/O Section for a complete description.
A In
LCD13
P4.6
A O
LCD Seg
nt Pin 13
D I/O or
Port
. See Port I/O Section for a complete description.
A In
LCD14
P4.7
A O
LCD Segment Pin 14
D I/O or
Port 4.7. See Port I/O Section for a complete description.
A In
LCD15
P5.0
A O
LCD Segment Pin 15
D I/O or
Port 5.0. See Port I/O Section for a complete description.
A In
LCD1
.1
A O
LCD Segment Pin 16
D I/O or
Port 5.1. See Port I/O Section for a complete description.
A In
LCD17
P5.2
A O
LCD Segment Pin 17
D I/O or
Port 5.2. See Port I/O Section for a complete description.
A In
LCD18
A O
LCD Segment Pin 18
Rev. 1.0
40
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x
(Continued)
Pin
Name
Type
Description
Number
P5.3
B14
B13
B12
B9
D I/O or
Port 5.3. See Port I/O Section for a complete description.
A In
LCD19
P5.4
A O
LCD Segment Pin 19
D I/O or
Port 5.4. See Port I/O Section for a complete description.
A In
LCD20
P5.5
A O
LCD Segment Pin 20
D I/O or
Port 5.5. See Port I/O Section for a complete description.
A In
LCD21
P5.6
A O
LCD Segment Pin 21
D I/O or
Port 5.6. See Port I/O Section for a complete description.
A In
LCD22
P5.7
A O
LCD Segment Pin 22
B8
D I/O or
Port 5.7. See Port I/O Section for a complete description.
A In
LCD23
P6.0
A O
LCD Seg
nt Pin 23
B7
D I/O or
Port
. See Port I/O Section for a complete description.
A In
LCD24
P6.1
A O
LCD Segment Pin 24
B6
D I/O or
Port 6.1. See Port I/O Section for a complete description.
A In
LCD25
P6.2
A O
LCD Segment Pin 25
5
D I/O or
Port 6.2. See Port I/O Section for a complete description.
A In
LCD2
.3
A O
LCD Segment Pin 26
B4
D I/O or
Port 6.3. See Port I/O Section for a complete description.
A In
LCD27
P6.4
A O
LCD Segment Pin 27
B3
D I/O or
Port 6.4. See Port I/O Section for a complete description.
A In
LCD28
A O
LCD Segment Pin 28
41
Rev. 1.0
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x
(Continued)
Pin
Name
Type
Description
Number
P6.5
B2
D I/O or
Port 6.5. See Port I/O Section for a complete description.
A In
LCD29
P6.6
A O
LCD Segment Pin 29
B1
D I/O or
Port 6.6. See Port I/O Section for a complete description.
A In
LCD30
P6.7
A O
LCD Segment Pin 30
D1/D5
D I/O or
Port 6.7. See Port I/O Section for a complete description.
A In
LCD31
A O
P In
LCD Segment Pin 31
VDD_RF
A17
A18
+1.8 to +3.6 V supply voltage input to all analog +1.7 V regulators.
The recommended VDD supply voltage is +3.3 V
TX
A O
Transmit output pin. The PA output is an open-drain connection so
the L-C match must s
VDD (+3.3 VDC nominal) to this pin.
RXp
RXn
A19
A20
A16
A21
A I
A I
Differential RF input pins of the LNA. See application schematic
for example m
tching network.
NC
—
No Conne
Not connected internally to any circuitry.
ANT_A
D O
Extra
ntenna or TR switch control to be used if more GPIO are
requi
Pin is a hardwired version of GPIO setting 11000,
Antenna 2 and can be manually controlled by the antdiv[2:0] bits
in register 08h. See register description of 08h.
GPIO_0
GPIO_1
GPIO_2
A22
A23
A24
D I/O
D I/O
D I/O
General Purpose Digital I/O that may be configured through the
registers to perform various functions including: Microcontroller
Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect, T/R switch, AntDiversity control, etc. See the SPI GPIO
Configuration Registers, Address 0Bh, 0Ch, and 0Dh for more
information.
VR_DIG
VDD_D
nIRQ
3
A25
B11
P Out
Regulated Output Voltage of the Digital 1.7 V regulator. A 1 µF
decoupling capacitor is required.
P In
+1.8 to +3.6 V supply voltage input to the Digital +1.7 V
regulator. The recommended VDD supply voltage is +3.3
V
.
D O
General Microcontroller Interrupt Status output. When the EZRa-
dioPRO transceiver exhibits anyone of the Interrupt Events, the
nIRQ pin will be set low. Please see the Control Logic registers
section for more information on the Interrupt Events. The Micro-
controller can then determine the state of the interrupt by reading
a corresponding SPI Interrupt Status Registers, Address 03h and
04h. No external resistor pull-up is required, but it may be desir-
able if multiple interrupt lines are connected.
Rev. 1.0
42
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x
(Continued)
Pin
Name
Type
Description
Number
XOUT
A13
D I
or
A I/O
Crystal Oscillator Output/External Reference Input. Connect to an
external 30 MHz crystal or to an external source. If using an exter-
nal source with no crystal, then DC coupling with a nominal
0.8 VDC level is recommended with a minimum amplitude of
700 mVpp.
XIN
A14
A15
D O
or
A I/O
Crystal Oscillator Input. Connect to an external 30 MH
rystal or
leave floating when driving with an external sour
n XOU
T
.
SDN
D I
Shutdown input pin. SDN should be low in all modes except Shut-
down mode. When SDN is high, the radio will be completely shut
down, and the contents of the registers will be lost.
43
Rev. 1.0
Si102x/3x
Figure 3.1. LGA-85 Pinout Diagram (Top View)
Rev. 1.0
44
Si102x/3x
3.1. LGA-85
Package Specifications
3.1.1. Package Drawing
Figure 3.2. LGA-85 Package Drawing
Rev. 1.0
45
Si102x/3x
Table 3.2. LGA-85 Package Dimensions
Symbol
Min
—
Nom
Max
0.94
0.40
6.10
8.10
—
A
c
—
0.32
5.90
7.90
—
0.36
6.00
8.00
3.04
5.50
3.00
2.46
5.00
7.5
2.42
3.30
5.52
0.50
0.30
0.30
0.10
0.10
0.10
0.20
D
E
D1
D2
D3
E1
E2
E3
E4
E5
E6
e
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
b
0.25
0.25
—
0.35
0.35
—
L
L1
aaa
bbb
Y
—
—
—
—
—
—
Notes:
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
Dimensioning and
T
o
lerancing per ANSI Y14.5M-1994.
3.
Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
46
Rev. 1.0
Si102x/3x
3.1.2. Land Pattern
Figure 3.3. LGA-85 Land Pattern
Table 3.
LGA-85 Land Pattern Dimensions
Symbol
Max (mm)
C1
C2
C3
C4
C5
C6
e
5.50
7.50
3.00
5.00
2.47
2.51
0.50
0.35
3.09
f
P1
Notes:
General
1.
All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance
of 0.05 mm is assumed.
2.
Dimensioning and
T
o
lerancing is per the ANSI Y14.5M-1994 specification.
3.
This Land Pattern Design is based on the IPC-7351 guidelines.
Rev. 1.0
47
Si102x/3x
4. Electrical
Characteristics
Throughout the MCU Electrical Characteristics chapter:
“VDD” refers to the VBAT or VBATDC Supply Voltage.
“VIO” refers to the VIO or VIORF Supply Voltage.
4.1. Absolute
Maximum Specifications
Table 4.1. Absolute Maximum Ratings
Parameter
Conditions
Min
–55
–65
–0.3
Typ
—
x
Units
°C
Ambient
T
e
mperature under Bias
Storage
T
e
mperature
—
150
°C
Voltage on any Port I/O Pin or
RST with Respect to GND
—
VIO + 2
V
Voltage on VDD with respect to
GND
–0.3
—
—
—
—
—
4.0
500
100
200
V
Maximum
T
o
tal Current through
VDD or GND
mA
mA
mA
Maximum Current through RST
or any Port Pin
—
Maximum
T
o
tal Current through
all Port Pins
—
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings
this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect dev
e reliability.
Rev. 1.0
48
Si102x/3x
4.2. MCU
Electrical Characteristics
Table 4.2. Global Electrical Characteristics
1,2
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Supply Voltage (V
Conditions
Min
Typ
Max
Units
)
1.8
3.8
V
DD
Minimum RAM Data
—
—
1.4
0.3
—
0.5
V
not in sleep mode
in sleep mode
1
Retention Voltage
2
0
—
—
—
—
25
MHz
ns
SYSCLK (System Clock)
T
T
(SYSCLK High Time)
18
SYSH
SYSL
(SYSCLK Low Time)
18
—
ns
Specified Operating
–40
+85
°C
T
e
mperature Range
Notes:
1.
Based on device characterization data; not production tested.
2.
SYSCLK must be at least 32 kHz to enable debugging.
Table 4.3. Digital Supply Current at VBAT pin with DC
C Converter Enabled
–40 to +85 °C, VBAT = 3.6V, VDC = 1.9V, 24.5 MHz system clock unl
otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current—CPU Active (Normal Mod
tching instructions from flash, no external
load)
1,2,3
V
V
= 3.0 V
= 3.3 V
= 3.6 V
—
—
—
4.1
4.0
3.8
—
—
—
mA
mA
mA
T
BAT
BAT
I
BAT
Digital Supply Current—CPU Inac
ive (Sleep Mode, sourcing current to external device)
1
sourcing 9 mA to external device
sourcing 19 mA to external device
—
—
6.5
13
—
—
mA
mA
I
BAT
Notes:
1.
Based on device characterization data; Not production tested.
2.
Digital Suppl
rent depends upon the particular code being executed. The values in this table are obtained
with the CPU
cuting a mix of instructions in two loops: djnz R1, $, followed by a loop that accesses an
SFR, and moves data around using the CPU (between accumulator and b-register). The supply current will
vary
ghtly based on the physical location of this code in flash. As described in the Flash Memory chapter, it
s be
t to align the jump addresses with a flash word address (byte location /4), to minimize flash accesses
nd power consumption.
3.
Includes oscillator and regulator supply current.
49
Rev. 1.0
Si102x/3x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current – Active Mode, No Clock Gating (PCLKACT=0x0F)
(CPU Active, fetching instructions from flash)
1,2
V
= 1.8–3.8 V, F = 24.5 MHz
DD
—
4.9
3.9
5.5
—
mA
mA
I
DD
(includes precision oscillator current)
V
= 1.8–3.8 V, F = 20 MHz
—
DD
(includes low power oscillator current)
V
V
= 1.8
V
, F = 1
M
Hz
= 3.8
V
, F = 1
M
Hz
—
—
175
190
—
µA
µA
DD
DD
(includes external oscillator/GPIO current)
V
= 1.8–3.8
V
, F = 32.768 kHz
—
—
85
—
—
µA
DD
(includes SmaRTClock oscillator current)
I
Frequency
183
µA/MHz
DD
V
= 1.8–3.8 V, T = 25
°
C
DD
1, 4
Sensitivity
Digital Supply Current – Active Mode, All Peripheral Clocks Disabled (PCLKACT=0x00)
(CPU Active, fetching instructions from flash)
1,2
V
= 1.8–3.8 V, F = 24.5 MHz
—
3.9
—
mA
mA
DD
I
DD
(includes precision oscillator current)
V
= 1.8–3.8 V
20 MHz
—
3.1
—
DD
(includes low po
r oscillator current)
V
V
.8
V
, F = 1
M
Hz
=
8 V, F = 1
M
Hz
—
—
165
180
—
—
µA
µA
DD
DD
(includes external oscillator/GPIO current)
I
Frequency
—
140
—
µA/MHz
DD
V
= 1.8–3.8 V, T = 25
°
C
DD
1, 3
Sensitivity
Notes:
:
1.
Active Current measure using typical code loop—Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesse
SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current
ill vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to
min
e flash accesses and power consumption.
2
cludes oscillator and regulator supply current.
Based on device characterization data; Not production tested.
4.
Measured with one-shot enabled.
5.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0
F
.
6.
Using SmaRTClock oscillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
7.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
Rev. 1.0
50
Si102x/3x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current—Idle Mode
(CPU Inactive, not fetching instructions from flash)
2
V
= 1.8–3.8 V, F = 24.5 MHz
—
—
3.5
2.6
—
—
mA
mA
DD
I
DD
(includes precision oscillator current)
V
= 1.8–3.8 V, F = 20 MHz
DD
(includes low power oscillator current)
V
V
= 1.8
V
, F = 1
M
Hz
= 3.8
V
, F = 1
M
Hz
—
—
340
360
—
µA
µA
DD
DD
(includes external oscillator/GPIO current)
5
V
= 1.8–3.8
V
, F = 32.768 kHz
—
—
—
µA
DD
23
(includes SmaRTClock oscillator current)
3
135
µA/MHz
V
= 1.8–3.8 V, T = 25
°
C
I
Frequency Sensitivity
DD
DD
Digital Supply Current— Low Power Idle Mode, All peripheral clocks enabled (PCLKEN = 0x0F)
(CPU Inactive, not fetching instructions from flash)
2, 6
V
= 1.8–3.8 V, F = 24.5 MHz
—
1.5
1.9
mA
DD
I
DD
(includes precision oscillator
rent)
V
= 1.8–3.8 V, F = 20 MHz
—
1.07
—
mA
DD
(includes low power oscillator current)
V
V
= 1.8
V
,
1 MHz
= 3.
, F = 1 MHz
—
—
270
280
—
—
µA
µA
DD
DD
(includes exter
al oscillator/GPIO current)
5
V
= 1.8
V, F = 32.768 kHz
—
—
—
—
µA
DD
232
(includes SmaRTClock oscillator current)
3
5
µA/MHz
= 1.8–3.8 V, T = 25
°
C
I
Frequency Sensitivity
47
DD
DD
Notes:
:
1.
Active Current measure using typical code loop—Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained w
th the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply curren
ll vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chap
t is best to align the jump addresses with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
2.
Inclu
s oscillator and regulator supply current.
3.
ased on device characterization data; Not production tested.
Measured with one-shot enabled.
5.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0
F
.
6.
Using SmaRTClock oscillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
7.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
51
Rev. 1.0
Si102x/3x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter Conditions
Min
Typ
Max
Units
Digital Supply Current— Low Power Idle Mode, All Peripheral Clocks Disabled (PCLKEN = 0x00)
(CPU Inactive, not fetching instructions from flash)
2, 7
V
= 1.8–3.8 V, F = 24.5 MHz
—
—
487
340
—
—
µA
µA
DD
I
DD
(includes precision oscillator current)
V
= 1.8–3.8 V, F = 20 MHz
DD
(includes low power oscillator current)
V
V
= 1.8
V
, F = 1
M
Hz
= 3.8
V
, F = 1
M
Hz
—
—
90
94
—
µA
µA
DD
DD
(includes external oscillator/GPIO current)
3
5
—
—
µA/MHz
µA
V
= 1.8–3.8 V, T = 25
°
C
I
Frequency Sensitivity
11
DD
DD
Digital Supply Current—Suspend Mode
Digital Supply Current
(Suspend Mode)
V
V
= 1.8 V
= 3.8 V
—
—
77
84
—
—
DD
DD
Notes:
:
1.
Active Current measure using typical code loop—Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the partic
code being executed. The values in this
table are obtained with the CPU executing a mix of instruc
ion
two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current will vary slightly based on the physica
location of this code in flash. As described in the Flash
Memory chapter, it is best to align the jump addres
ith a flash word address (byte location /4), to
minimize flash accesses and power consumpti
2.
Includes oscillator and regulator supply cur
ent.
3.
Based on device characterization data; N
duction tested.
4.
Measured with one-shot enabled.
5.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0
F
.
6.
Using SmaRTClock oscillator wi
ex
ernal 32.768 kHz CMOS clock. Does not include crystal bias current.
7.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
Rev. 1.0
52
Si102x/3x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current—Sleep Mode (LCD enabled, RTC enabled)
Digital Supply Current
(Sleep Mode, SmaRTClock
running, internal LFO, LCD
Contrast Mode 1, charge
pump disabled, 60 Hz
1.8
V
, T =
2
5
°
C, static LCD
3.0
V
, T =
2
5
°
C, static LCD
3.6
V
, T =
2
5
°
C, static LCD
—
—
—
0.4
0.6
0.8
—
—
—
µA
1.8
V
, T =
2
5
°
C, 2-Mux LCD
3.0
V
, T =
2
5
°
C, 2-Mux LCD
3.6
V
, T =
2
5
°
C, 2-Mux LCD
—
—
—
0.7
1.0
1.2
—
—
—
µA
µA
µA
µA
µA
µA
refresh rate, driving 32
segment pins w/ no load)
1.8
V
, T =
2
5
°
C, 4-Mux LCD
3.0
V
, T =
2
5
°
C, 4-Mux LCD
3.6
V
, T =
2
5
°
C, 4-Mux LCD
—
—
—
0.7
1.1
1.2
—
—
Digital Supply Current
1.8
V
, T =
2
5
°
C, static LCD
3.0
V
, T =
2
5
°
C, static LCD
3.6
V
, T =
2
5
°
C, static LCD
—
—
0.8
1.1
1.4
—
—
—
(Sleep Mode, SmaRTClock
running, 32.768 kHz Crys-
tal, LCD Contrast Mode 1,
charge pump disabled,
60 Hz refresh rate, driving
32 segment pins w/ no load)
1.8
V
, T =
2
5
°
C, 2-Mux LCD
3.0
V
, T =
2
5
°
C, 2-Mux LCD
3.6
V
, T =
2
5
°
C, 2-Mux LCD
—
—
—
1.1
1.5
1.8
—
—
—
1.8
V
, T =
2
5
°
C, 4-Mux
3.0
V
, T =
2
5
°
C, 4-Mux L
D
3.6
V
, T =
2
5
°
C, 4-Mux LCD
—
—
—
1.2
1.6
1.9
—
—
—
Digital Supply Current
1.8
V
, T =
2
5
°
C
atic LCD
1.8
V
, T =
2
5
C, 2-Mux LCD
1.8
V
, T =
2
°
C
3-Mux LCD
1.8
V
, T
25
°
C, 4-Mux LCD
—
—
—
—
1.2
1.6
1.8
2.0
—
—
—
—
(Sleep Mode, SmaRTClock
running, internal LFO, LCD
Contrast Mode 3 (2.7 V),
charge pump enabled,
60 Hz refresh rate, driving
32 segment pins w/ no load)
Notes:
:
1.
Active Current measure using typical code loop—Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained w
th the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current will vary slightly based on the physical location of this code in flash. As described in the Flash
Memory cha
is best to align the jump addresses with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
2.
Includes oscillator and regulator supply current.
3.
Bas
d on device characterization data; Not production tested.
easured with one-shot enabled.
5.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0
F
.
6.
Using SmaRTClock oscillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
7.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
53
Rev. 1.0
Si102x/3x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current
(Sleep Mode, SmaRTClock
running, 32.768 kHz Crys-
tal, LCD Contrast Mode 3
(2.7 V), charge pump
enabled, 60 Hz refresh rate,
driving 32 segment pins w/
no load)
1.8
V
, T =
2
5
°
C, static LCD
1.8
V
, T =
2
5
°
C, 2-Mux LCD
1.8
V
, T =
2
5
°
C, 3-Mux LCD
1.8
V
, T =
2
5
°
C, 4-Mux LCD
—
—
—
—
1.3
1.8
1.8
2.0
—
—
—
—
µA
Digital Supply Current—Sleep Mode (LCD disabled, RTC enabled)
Digital Supply Current
(Sleep Mode, SmaRTClock
running, 32.768 kHz crystal)
1.8
V
, T =
2
5
°
C
3.0
V
, T =
2
5
°
C
3.6
V
, T =
2
5
°
C
1.8
V
, T =
8
5
°
C
3.0
V
, T =
8
5
°
C
—
—
—
0.35
0.55
0.60
1.56
2.38
2.79
—
—
—
µA
µA
—
—
—
—
—
3.6
V
, T =
8
5
°
C
(includes SmaRTClock oscillator and
V
Supply Monitor)
BAT
Digital Supply Current
(Sleep Mode, SmaRTClock
running, internal LFO)
1.8
V
, T =
2
5 °C
3.0
V
, T =
2
5 °C
3.6
V
, T =
2
5 °C
1.8
V
, T =
°C
3.0
V
, T =
8
5 °C
3.6
V
T = 85 °C
—
—
—
0.20
0.35
0.45
1.30
2.06
2.41
—
—
—
—
—
—
—
—
—
(includes S
RTClock oscillator and
upply Monitor)
V
BAT
Notes:
:
1.
Active Current measure using ty
cal code loop—Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current will vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chapter,
t is best to align the jump addresses with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
2.
Includes osci
and regulator supply current.
3.
Based on device characterization data; Not production tested.
4.
Mea
ed with one-shot enabled.
5
ow-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0
F
.
Using SmaRTClock oscillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
7.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
Rev. 1.0
54
Si102x/3x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current—Sleep Mode (LCD disabled, RTC disabled)
Digital Supply Current
(Sleep Mode)
1.8
V
, T =
2
5 °C
3.0
V
, T =
2
5 °C
3.6
V
, T =
2
5 °C
1.8
V
, T =
8
5 °C
3.0
V
, T =
8
5 °C
—
—
—
0.05
0.08
0.12
1.2
2.2
2.4
—
—
—
µA
—
—
—
—
—
3.6
V
, T =
8
5 °C
(includes POR supply monitor)
Digital Supply Current
(Sleep Mode, POR Supply
Monitor Disabled)
1.8
V
, T =
2
5 °C
3.0
V
, T =
2
5 °C
3.6
V
, T =
2
5 °C
1.8
V
, T =
8
5 °C
3.0
V
, T =
8
5 °C
3.6
V
, T =
8
5 °C
—
—
—
—
—
0.01
0.02
0.03
1.1
2.1
2.3
—
—
—
—
—
µA
Notes:
:
1.
Active Current measure using typical code loop—Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained with the CPU executing a mix of instructio
two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU
between accumulator and b-register). The
supply current will vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chapter, it is best to align the jump address
with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
2.
Includes oscillator and regulator supply curren
3.
Based on device characterization data; No
roduction tested.
4.
Measured with one-shot enabled.
5.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0
F
.
6.
Using SmaRTClock oscillator wi
xternal 32.768 kHz CMOS clock. Does not include crystal bias current.
7.
Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
55
Rev. 1.0
Si102x/3x
7
6
5
4
3
2
1
0
Active
Idle
LP
dle
LKEN=0x0F)
LP Idle (PCLKEN=0x00)
0
5
10
15
20
25
30
Frequency (MHz)
Figure 4.1. Frequency Sensitivity (External CMOS Clock, 25
°
C)
Rev. 1.0
56
Si102x/3x
Table 4.5. Port I/O DC Electrical Characteristics
V
IO
= 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified.
Parameters
Conditions
Min
V –
0.7
Typ
Max
Units
Output High Voltage
High Drive Strength, PnDRV.n = 1
IOH = –3 mA, Port I/O push-pull
IO
—
—
—
—
IOH = –10 µA, Port I/O push-pull
V
– 0.1
IO
IOH = –10 mA, Port I/O push-pull
See Chart
V
Low Drive Strength, PnDRV.n = 0
—
—
V
V
– 0.7
– 0.1
IOH = –1 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –3 mA, Port I/O push-pull
—
—
—
IO
IO
S
Chart
—
Output Low Voltage
High Drive Strength, PnDRV.n = 1
I
I
I
= 8.5 mA
= 10 µA
= 25 mA
OL
OL
OL
—
—
—
—
—
0.6
0.1
—
See Chart
V
Low Drive Strength, PnDRV.n =
I
I
I
= 1.4 mA
= 10 µA
—
—
—
—
—
0.6
0.1
—
OL
OL
OL
See Chart
= 4 mA
Input High Voltage
Input Low Voltage
V
V
V
V
= 2.0 to 3.8 V
V
– 0.6
—
—
—
—
—
—
V
V
V
V
DD
IO
= 1.8 to 2
V
= 2.0 to 3.8 V
= 1.8 to 2.0 V
0.7 x V
—
DD
DD
DD
IO
0.6
0.3 x V
—
IO
Weak Pullup Off
—
—
—
—
4
±1
—
35
Input Leakage
Current
eak Pullup On, V
= 0
V
, V
=
1
.8 V
µA
IN
DD
Weak Pullup On, Vin = 0 V, V
= 3.8 V
20
DD
57
Rev. 1.0
Si102x/3x
Typical VOH (High Drive Mode)
3.6
3.3
3
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0
5
10
15
20
25
30
35
40
45
50
Load Current (mA)
Typical VOH (Low Drive M
3.6
3.3
3
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Load Current (mA)
Figure 4.2. Typical VOH Curves, 1.8–3.6 V
Rev. 1.0
58
Si102x/3x
Typical VOL (High Drive Mode)
1.8
1.5
1.2
0.9
0.6
0.3
0
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
-80
-70
-60
-50
-40
-30
-20
-10
0
Load Current (mA)
Typical VOL (Low Drive Mo
1.8
1.5
1.2
0.9
0.6
0.3
0
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Load Current (mA)
Figure 4.3. Typical VOL Curves, 1.8–3.6 V
59
Rev. 1.0
Si102x/3x
Table 4.6. Reset Electrical Characteristics
V
DD
= 1.8 to 3.8
V
, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
= 1.4 mA,
Min
Typ
Max
Units
RST Output Low Voltage
RST Input High Voltage
I
—
—
0.6
V
OL
V
– 0.6
V
V
V
V
= 2.0 to 3.8 V
= 1.8 to 2.0 V
= 2.0 to 3.8 V
= 1.8 to 2.0 V
—
—
—
—
—
V
V
V
V
DD
DD
DD
DD
DD
0.7 x V
—
—
0.6
DD
RST Input Low Voltage
x V
—
DD
—
—
4
—
35
RST = 0.0
V
,
V
DD = 1.8 V
RST = 0.0
V
,
V
DD = 3.8 V
RST Input Pullup Current
VDD Monitor Threshold
µA
V
20
Early Warning
Reset Trigger
(all power modes except Sleep)
1.8
1.
1.85
1.75
1.9
1.8
(V
)
RST
VBAT Ramp Time for
Power On
VBAT Ramp from 0–1.8 V
—
—
3
ms
V
Brownout Condition (VDD Falling)
0.45
—
0.7
1.0
—
POR Monitor Threshold
(V
)
POR
Recovery from Brownout (VDD
g)
1.75
Missing Clock Detector
Timeout
Time from last system clock rising edge
to reset initi
n
100
650
1000
µs
Minimum System Clock w/
Missing Clock Detector
Enabled
System clock frequ
ncy which triggers
a missing cl
k detector timeout
—
7
10
kHz
µs
Delay between release of any reset
source and code
Reset Time Delay
—
10
—
e
ecution at location 0x0000
Minimum RST Low Time to
Generate a System Reset
15
—
—
—
—
300
14
—
—
—
—
µs
ns
Digital/Analog Monitor
Turn-on Time
Digital Monitor Sup
Current
µA
µA
Analog Mo
or Supply
Curre
14
Note
The VBAT monitor electrical specifications apply to both the analog and digital VBAT monitors (Register 22.1,
“VDM0CN: VDD Supply Monitor Control,” on page 282).
Rev. 1.0
60
Si102x/3x
Table 4.7. Power Management Electrical Specifications
V
DD
= 1.8 to 3.8
V
, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
2
Typ
—
Max
3
Units
SYSCLKs
ns
Idle Mode Wake-up Time
Suspend Mode Wake-up Time
CLKDIV = 0x00
—
400
—
Low Power or Precision Osc.
—
2
—
µs
Sleep Mode Wake-up Time
Table 4.8. Flash Electrical Characteristics
V
DD
= 1.8 to 3.8
V
, –40 to +85 °C unless otherwise specified.,
Parameter
Flash Size
Conditions
Min
Typ
Max
Units
bytes
bytes
bytes
bytes
Si1020/24/30/34
Si1021/25/31/35
Si1022/26/32/36
Si1023/27/33/37
131072
65536
32768
16384
—
—
—
—
—
—
—
—
Erase/Write
Cycles
Endurance
k
100k
—
Erase Cycle Time
Write Cycle Time
28
57
32
64
36
71
ms
µs
Table 4.9. Internal Precision Oscillator
lectrical Characteristics
V
DD
= 1.8 to 3.8 V; T
A
= –40 to +85 °C unless oth
e specified; Using factory-calibrated settings.
Parameter
Oscillator Frequency
Oscillator Supply Current
Conditions
–40 to +85 °C,
Min
Typ
Max
Units
24
24.5
25
MHz
V
= 1.8–3.8 V
DD
25 °C; includes bias current
of 50 µA typical
—
300*
—
µA
(from V
)
DD
*Note:
Does not include clock divider or clock tree supply current.
Table 4.10. Intern
Low-Power Oscillator Electrical Characteristics
V
DD
= 1.8 to 3.8 V; T
A
= –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
rameter
Conditions
Min
Typ
Max
Units
–40 to +85 °C,
Os
or Frequency
18
20
22
MHz
V
= 1.8–3.8 V
DD
25 °C
Oscillator Supply Current
—
100*
—
µA
No separate bias current
required
(from V
)
DD
*Note:
Does not include clock divider or clock tree supply current.
61
Rev. 1.0
Si102x/3x
Table 4.11. SmaRTClock Characteristics
V
DD
= 1.8 to 3.8 V; T
A
= –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Conditions
Min
Typ
Max
Units
Oscillator Frequency (LFO)
13.1
16.4
19.7
kHz
Table 4.12. ADC0 Electrical Characteristics
V
= 1.8 to 3.8 V, VREF = 1.65 V (REFSL[1:0] = 11),
–
40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
DC Accuracy
12-bit mode
10-bit mode
12-bit mode
1
10-bit mode
12-bit mode
1
10-bit mode
12
10
Resolution
bits
LSB
LSB
LSB
LSB
—
—
±1
±0.5
±3
±1
Integral Nonlinearity
—
—
±0.8
±0.5
±2
±1
Differential Nonlinearity
(Guaranteed Monotonic)
12-bit mode
10-bit mode
12-bit mode
2
10-bit mode
—
—
—
—
±<1
±<1
±1
±3
±3
Offset Error
±4
±2.5
Full Scale Error
±1
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, maximum
sampling rate)
12-b
mode
10-bit mode
it mode
10-bit mode
12-bit mode
10-bit mode
62
54
—
—
—
—
65
58
76
73
82
75
—
—
—
—
—
—
Signal-to-Noise Plus Distortion
3
Signal-to-Distortion
3
dB
dB
dB
Spurious-Free Dynamic Range
3
Conversion Rate
Normal Power Mode
Low Power Mode
10-bit Mode
—
—
13
11
—
—
—
—
8.33
4.4
—
SAR Conversion Clock
MHz
Conversion Time i
R Clocks
Track/Hold
cquisition Time
Thro
ghput Rate
clocks
8-bit Mode
—
Initial Acquisition
Subsequent Acquisitions
(dc input, burst mode)
1.5
1.1
—
—
—
—
us
12-bit mode
10-bit mode
—
—
75
300
—
—
ksps
1.
INL and DNL specifications for 12-bit mode do not include the first or last four ADC codes.
2.
The maximum code in 12-bit mode is 0xFFFC. The Full Scale Error is referenced from the maximum code.
3.
Performance in 8-bit mode is similar to 10-bit mode.
Rev. 1.0
62
Si102x/3x
Table 4.12. ADC0 Electrical Characteristics (Continued)
V
= 1.8 to 3.8 V, VREF = 1.65 V (REFSL[1:0] = 11),
–
40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
Analog Inputs
ADC Input Voltage Range
Single Ended (AIN+ – GND)
Single Ended
0
0
—
—
VREF
VDD
V
V
Absolute Pin Voltage with respect
to GND
1x Gain
0.5x Gain
16
13
Sampling Capacitance
—
—
—
pF
Input Multiplexer Impedance
5
k
Power Specifications
Normal Power Mode:
Conversion Mode (300 ksps)
Tracking Mode (0 ksps)
Low Power Mode:
Conversion Mode (150 ksps)
Tracking Mode (0 ksps)
Internal High Speed VR
External VREF
—
—
650
740
—
—
Power Supply Current
(V supplied
to ADC0)
µA
dB
DD
—
—
—
—
370
400
67
—
—
—
—
Power Supply Rejection
74
1.
INL and DNL specifications for 12-bit mode do not in
lude the first or last four ADC codes.
2.
The maximum code in 12-bit mode is 0xFFFC. The
Scale Error is referenced from the maximum code.
3.
Performance in 8-bit mode is similar to 10-bit m
e.
Table 4.13. Temperature Sensor Electri
Characteristics
V
= 1.8 to 3.8 V,
–
40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
—
Typ
±1
Max
—
Units
°C
Linearity
Slope
—
3.40
40
—
mV/°C
µV/°C
mV
Slope Error*
Offset
—
—
T
e
mp = 25 °C
T
e
mp = 25 °C
—
1025
18
—
Offset Error*
—
—
mV
T
e
mperatu
Sensor Turn-On
Tim
—
—
1.7
35
—
—
µs
Supply Current
µA
*Note:
Represents one standard deviation from the mean.
63
Rev. 1.0
Si102x/3x
Table 4.14. Voltage Reference Electrical Characteristics
V
= 1.8 to 3.8 V,
–
40 to +85 °C unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
Internal High-Speed Reference (REFSL[1:0] = 11)
–40 to +85 °C,
= 1.8–3.8 V
Output Voltage
1.62
—
1.65
—
1.68
1.5
V
V
DD
VREF Turn-on Time
Supply Current
µs
µA
Normal Power Mode
Low Power Mode
—
—
260
140
—
External Reference (REFSL[1:0] = 00, REFOE = 0)
Input Voltage Range
0
—
V
V
DD
Sample Rate = 300 ksps;
Input Current
—
5.25
—
µA
VREF = 3.0 V
Rev. 1.0
64
Si102x/3x
Table 4.15. IREF0 Electrical Characteristics
V
= 1.8 to 3.8 V,
–
40 to +85 °C, unless otherwise specified.
DD
Parameter
Conditions
Min
Typ
Max
Units
bits
V
Static Performance
Resolution
6
Low Power Mode, Source
High Current Mode, Source
Low Power Mode, Sink
0
0
0.3
0.8
—
—
—
—
V
V
– 0.4
DD
– 0.8
DD
Output Compliance Range
V
DD
High Current Mode, Sink
Integral Nonlinearity
Differential Nonlinearity
Offset Error
—
—
<±0.2
<±0.2
±
LSB
LSB
±1.0
—
—
—
—
—
<±0.1
—
±0.5
±5
LSB
%
Low Power Mode, Source
High Current Mode, Source
Low Power Mode, Sink
—
±6
%
Full Scale Error
—
±8
%
High Current Mode, Sink
—
±8
%
Low Power Mode
Sourcing 20 µA
Absolute Current Error
—
<±1
±3
%
Dynamic Performance
Output Settling Time to 1/2 LSB
Startup Time
—
—
300
1
—
—
ns
µs
Power Consumption
Low Power Mode, Source
REF0DAT = 000001
IREF0DAT = 111111
Net Power Supply Current
(V supplied
to IREF0 minus
—
—
10
10
—
—
µA
µA
DD
any output source current)
High Current Mode, Source
IREF0DAT = 000001
IREF0DAT = 111111
—
—
10
10
—
—
µA
µA
Low Power Mode, Sink
IREF0DAT = 000001
IREF0DAT = 111111
—
—
1
—
—
µA
µA
11
High Current Mode, Sink
IREF0DAT = 000001
IREF0DAT = 111111
—
—
12
81
—
—
µA
µA
Note:
Refer to “6.1. PWM Enhanced Mode” on page 102 for information on how to improve IREF0 resolution.
65
Rev. 1.0
Si102x/3x
Table 4.16. Comparator Electrical Characteristics
V
DD
= 1.8 to 3.8
V
, –40 to +85 °C unless otherwise noted.
Parameter
Response Time:
Conditions
Min
—
—
—
—
—
—
—
—
Typ
120
110
Max
—
Units
ns
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
CP0+ – CP0– = 100 mV
CP0+ – CP0– = –100 mV
*
*
*
*
Mode 0, V
= 2.4
V
, V
= 1.2 V
= 1.2 V
= 1.2 V
= 1.2 V
—
ns
DD
CM
CM
CM
CM
180
220
350
600
1240
3200
—
ns
Response Time:
Mode 1, V
= 2.4
V
, V
—
ns
DD
ns
Response Time:
Mode 2, V
= 2.4
V
, V
ns
DD
—
ns
Response Time:
Mode 3, V
= 2.4
V
, V
—
ns
DD
Common-Mode Rejection Ratio
—
1.5
—
—
mV/V
V
Inverting or Non-Inverting Input
Voltage Range
–0.25
V
+ 0.25
DD
Input Capacitance
Input Bias Current
Input Offset Voltage
Power Supply
—
—
12
1
—
—
pF
nA
–10
—
+10
mV
Power Supply Rejection
—
0.1
—
mV/V
VDD = 3.8 V
VDD = 3.0 V
VDD = 2.4 V
VDD = 1.8 V
Mode 0
—
—
—
—
—
—
—
—
0.6
1.0
1.8
10
—
—
—
—
—
—
—
—
µs
µs
µs
µs
µA
µA
µA
µA
Power-up Time
23
Mode 1
8.8
2.6
0.4
Supply Current at DC
Mode 2
Mode 3
*Note:
Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 1.0
66
Si102x/3x
Table 4.16. Comparator Electrical Characteristics (Continued)
V
DD
= 1.8 to 3.8
V
, –40 to +85 °C unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
Hysteresis
Mode 0
Hysteresis 1
Hysteresis 2
Hysteresis 3
Hysteresis 4
Mode 1
(CPnHYP/N1–0 = 00)
(CPnHYP/N1–0 = 01)
(CPnHYP/N1–0 = 10)
(CPnHYP/N1–0 = 11)
—
—
—
—
0
—
—
mV
mV
mV
mV
8.5
17
34
Hysteresis 1
Hysteresis 2
Hysteresis 3
Hysteresis 4
Mode 2
(CPnHYP/N1–0 = 00)
(CPnHYP/N1–0 = 01)
(CPnHYP/N1–0 = 10)
(CPnHYP/N1–0 = 11)
—
—
—
—
0
—
—
—
—
mV
mV
mV
mV
6.5
13
26
Hysteresis 1
Hysteresis 2
Hysteresis 3
Hysteresis 4
Mode 3
(CPnHYP/N1–0 = 00)
(CPnHYP/N1
01)
(CPnHY
N1–0 = 10)
(CPn
P/N1–0 = 11)
—
2
0
5
1
mV
mV
mV
mV
10
20
30
5
10
20
12
Hysteresis 1
Hysteresis 2
Hysteresis 3
Hysteresis 4
(CPnHYP/N1–0 = 00)
(CPnHYP/N1–0 = 01)
(CPnHYP/N1–0 = 10)
(CPnHYP/N1–0 = 11)
—
—
—
—
0
4.5
9
—
—
—
—
mV
mV
mV
mV
17
*Note:
Vcm is the co
n-mode voltage on CP0+ and CP0–.
Table 4.17
VREG0 Electrical Characteristics
V
DD
=
8 to
.8
V
,
–40 to +85 °C unless otherwise specified.
Parameter
nput Voltage Range
Bias Current
Conditions
Min
1.8
—
Typ
—
Max
Units
V
3.8
—
Normal, idle, suspend, or stop mode
20
µA
67
Rev. 1.0
Si102x/3x
Table 4.18. LCD0 Electrical Characteristics
V
DD
= 1.8 to 3.8 V; T
A
= –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Conditions
Min
Typ
±30
—
Max
Units
mV
Charge Pump Output Voltage
Error
—
—
LCD Clock Frequency
16
33
kHz
Table 4.19. PC0 Electrical Characteristics
V
DD
= 1.8 to 3.8 V; T
A
= –40 to +85 °C unless otherwise specified; Using factory-calibrated settings
Parameter
Conditions
1.8 V
Min
—
Typ
145
175
2
285
M
—
Units
2.2 V
—
—
Supply Current
(25 °C, 2 ms sample rate)
nA
3.0 V
—
—
3.8 V
—
—
Rev. 1.0
68
Si102x/3x
Table 4.20. DC0 (Buck Converter) Electrical Characteristics
V
DD
= 1.8 to 3.8 V; T
A
= –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Condition
Min
Typ
Max
Units
Input Voltage
Range
1.8
—
3.8
V
Input Supply to Output
Voltage Differential
(for regulation)
0.45
—
—
V
Output Voltage Range
Programmable from 1.8 to 3.5 V
1.8
—
1.9
—
3.5
V
V
= 1.8 to 3.0
V
.
DC
Output Power
mW
V
BAT
V +
0.5.
DC
Output Load Current
—
—
85
mA
µH
1
Inductor Value
0.47
0.56
0.68
For load currents less than 50 mA
For load currents greater than
50 mA
450
550
—
—
—
—
Inductor Current Rating
mA
2
Output Capacitor Value
1
2.2
4.7
10
—
µF
µF
2
Input Capacitor
—
—
—
—
—
—
—
—
—
—
—
3
T
a
rget output = 1.8 to 3
0 V
85
70
50
10
Output Load Current
(based on output power
specification)
3
3
T
a
rget output = 3.1 V
T
a
rget output = 3
3 V
mA
3
3
4
4
T
a
rget output =
V
Output = 1.9 V;
Load Regulation
Load cur
up to 85 mA;
Supply range = 2.4–3.8 V
—
0.03
—
mV/mA
Maximum DC Load Current
During Startup
—
—
5
mA
Switching Clock Frequency
1.9
2.9
3.8
MHz
Notes:
1.
Recommended: Inductor similar to NLV32T-R56J-PF (0.56 µH)
2.
Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with
ESR < 10 m
(@ frequency > 1 MHz)
3.
V
BAT
V
5. Auto-Bypass enabled (DC0MD.2 = 1).
DC
4.
V
= 3.8V. Auto-Bypass disabled (DC0MD.2 = 0).
BAT
69
Rev. 1.0
Si102x/3x
®
4.3. EZRadioPRO
Peripheral Electrical Characteristics
Table 4.21. DC Characteristics
Parameter
Symbol
Conditions
Min Typ Max
Units
Supply Voltage
Range
V
1.8 3.0
3.6
V
DD_RF
Power Saving Modes
I
RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF
—
—
15
50
nA
nA
Shutdown
I
Low Power Digital Regulator ON (Register
values retained) and Main Digital
45
8
0
Standby
Regulator, and RC Oscillator OFF
I
RC Oscillator and Low Power Digital
Regulator ON
—
1
—
µA
Sleep
(Register values retained) and Main Digital
Regulator OFF
I
Main Digital Regulator and Low Battery
Detector ON,
Crystal Oscillator and all other blocks OFF
—
—
—
1
1
—
—
—
µA
µA
µA
Sensor-
LBD
I
Main Digital Regulator and
mperature
Sensor ON,
Crystal Oscillator and all other blocks OFF
Sensor-TS
I
Crystal Oscilla
and Main Digital
Regu
or ON,
800
Ready
all other blo
s OF
F
.
C
rystal Oscillator
buffer disabled
TUNE Mode Current
RX Mode Current
I
Synthe
er and regulators enabled
—
—
—
8.5
18.5
85
—
—
—
mA
mA
mA
Tune
I
RX
TX Mode Current
Si1020/21/22/23/30/
31/32/33
I
I
txpow[2:0] = 111 (+20 dBm)
Using Silicon Labs’ Reference Design.
TX current consumption is dependent on
match and board layout.
TX_+20
TX Mode Current
Si1024/25/26/27/34/
35/36/37
txpow[2:0] = 110 (+13 dBm)
Using Silicon Labs’ Reference Design.
TX current consumption is dependent on
match and board layout.
—
—
30
17
—
—
mA
mA
TX_+13
I
txpow[2:0] = 010 (+1 dBm)
Using Silicon Labs’ Reference Design.
TX current consumption is dependent on
match and board layout.
TX_+1
Rev. 1.0
70
Si102x/3x
Table 4.22. Synthesizer AC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max Units
Synthesizer Frequency
F
240
—
960
MHz
SYN
Range
Synthesizer Frequency
Resolution
F
Low Band, 240–480 MHz
High Band, 480–960 MHz
—
—
156.25
312.5
—
—
—
Hz
Hz
V
RES-LB
F
RES-HB
REF_LV
Reference Frequency
f
When using external reference
signal driving XOUT pin, instead
of using crystal. Measured peak-
0.7
1.6
1
Input Level
to-peak (V
)
PP
Synthesizer Settling Time
t
Measured from exiting Ready
mode with XOSC running to any
frequency.
—
—
200
2
—
4
µs
LOCK
Including VCO Calibration.
1
Residual FM
F
Integrated over
250 kHz band-
width (500 Hz lower bound of
integration)
kHz
RMS
RMS
Phase Noise
L
(f )
F = 10 kH
F = 100 kH
F = 1 MHz
F
0 MHz
—
—
—
—
–80
–90
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
M
–115
–130
Notes:
1.
Guaranteed by characterization; not produ
n tested.
71
Rev. 1.0
Si102x/3x
Table 4.23. Receiver AC Electrical Characteristics
Parameter
Symbol
Conditions
Min
240
—
Typ
Max Units
RX Frequency Range
—
960
—
MHz
dBm
F
RX
1
(BER < 0.1%)
(2 kbps, GFSK, BT = 0.5,
f =
5 kHz)
3
RX Sensitivity
–121
P
RX_2
(BER < 0.1%)
(40 kbps, GFSK, BT = 0.5,
f =
20 kHz)
(BER < 0.1%)
(100 kbps, GFSK, BT = 0.5,
f =
50 kHz)
(BER < 0.1%)
(125 kbps, GFSK, BT = 0.5,
f =
62.5 kHz)
—
—
—
–108
–104
–101
—
—
—
dBm
dBm
dBm
P
RX_40
P
P
RX_100
RX_125
(BER < 0.1%)
(4.8 kbps, 350 kHz BW, OOK)
—
—
–110
–102
—
—
dBm
dBm
P
RX_OOK
(BER < 0.1%)
(40 kbps, 400 kHz BW, OOK)
2
RX Channel Bandwidth
2.6
—
—
0
620
0.1
kHz
BW
Up to +5 dBm Inpu
l
BER Variation vs Power
ppm
P
RX_RES
2
Level
915 MHz
8
Hz
433 MHz
315 MHz
LNA Input Impedance
(Unmatched—measured
differentially across RX
input pins)
—
—
—
—
—
—
—
—
51–60j
54–63j
89–110j
107–137j
±0.5
—
—
—
—
—
—
—
—
R
IN-RX
RSSI Resolution
dB
dB
dB
dB
RES
RSSI
1-CH
2-C
3-CH
Desired Ref Signal 3 dB above
sensitivity, BER < 0.1%. Interferer
and desired modulated with
40 kbps
F = 20 kHz GFSK with BT
= 0.5, channel spacing = 150 kHz
1-Ch Offset Selectivity
2-Ch Offset Selectivity
3-Ch Offset Selectivity
–31
C/I
C/I
C/I
–35
–40
Desired Ref Signal 3 dB above
sensitivity. Interferer and desired
modulated with 40 kbps
F =
20 kHz GFSK with BT = 0.5
Blocking at 1 MHz Offset
Blocking at 4 MHz Offset
Blocking at 8 MHz
set
Image Rejection
—
—
—
—
–52
–56
–63
–30
—
—
—
—
dB
dB
dB
dB
1M
4M
8M
BLOCK
BLOCK
BLOCK
Rejection at the image frequency.
IF=937 kHz
Im
REJ
1
Measured at RX pins
Spurious E
issions
—
—
–54
dBm
P
OB_RX1
Not
1.
Receive sensitivity at multiples of 30 MHz may be degraded. If channels with a multiple of 30 MHz are required
it is recommended to shift the crystal frequency. Contact Silicon Labs Applications Support for
recommendations.
2.
Guaranteed by characterization; not production tested.
Rev. 1.0
72
Si102x/3x
Table 4.24. Transmitter AC Electrical Characteristics
Parameter
Symbol
Conditions
Min
240
Typ
—
Max Units
TX Frequency Range
F
960
256
40
MHz
kbps
kbp
kHz
TX
1
FSK Data Rate
DR
0.123
0.123
±0.625
±0.625
—
—
FSK
1
OOK Data Rate
DR
—
OOK
Modulation Deviation
∆
f1
∆
f2
∆
f
860–960 MHz
240–860 MHz
±320
±160
—
kHz
Modulation Deviation
Resolution
0.625
—
kHz
RES
Output Power Range—
Si1020/21/22/23/30/31/32/33
P
P
+1
–4
20
+13
dBm
dBm
TX
TX
2
2
Output Power Range—
Si1024/25/26/27/34/35/36/37
—
TX RF Output Steps
P
P
controlled by txpow[2:0]
—
—
3
2
—
—
dB
dB
RF_OUT
TX RF Output Level
–40 to +85
C
RF_TEMP
Variation vs.
T
e
mperature
TX RF Output Level
Variation vs. Frequency
P
Measured across any one
frequency
d
—
—
—
—
1
—
—
dB
RF_FREQ
Transmit Modulation
B*T
Gaussian Filterin
Band-
width Time Product
0.5
—
—
Filtering
1
Spurious Emissions
P
P
P
+13 dBm,
O
–54
–54
dBm
dBm
OB-TX1
OB-TX2
Frequencies <1 GHz
1–
2.75 GHz, excluding
harmonics
1
Harmonics
P
P
Using reference design TX
matching network and filter
with max output power. Har-
monics reduce linearly with
output power.
—
—
—
—
–42
–42
dBm
dBm
2HARM
3
RM
Notes:
1.
Guaranteed by characterization; not production tested.
2.
Output power is dependent on matching components, board layout, and is measured at the pin.
73
Rev. 1.0
Si102x/3x
Table 4.25. Auxiliary Block Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Units
T
e
mperature Sensor
Accuracy
TS
After calibrated via sen-
sor offset register
tvoffs[7:0]
—
0.5
—
°C
A
T
e
mperature Sensor
Sensitivity
TS
—
—
5
50
250
—
—
—
mV/°C
mV
S
Low Battery Detector
Resolution
LBD
RES
Low Battery Detector
Conversion Time
LBD
—
µs
CT
Microcontroller Clock
Output Frequency
F
Configurable to
30 MHz, 15 MHz,
10 MHz, 4 MHz, 3 MHz,
2 MHz, 1 MHz, or
32.768 kHz
32.768k
30M
Hz
MC
General Purpose ADC Res-
ADC
olution
—
—
—
8
4
—
—
—
bit
mV/bit
µs
ENB
RES
General Purpose ADC Bit
ADC
Resolution
T
e
mp Sensor & General
Purpose ADC Conversion
Time
ADC
305
CT
30 MHz XTAL Start-Up time
t
Us
g XTAL and board
ut in reference
design. Start-up time
will vary with XTAL type
and board layout.
—
—
600
97
—
—
µs
fF
30M
30 MHz XTAL Cap
Resolution
30M
See “32.5.5. Crystal
Oscillator” on page 457
for the total load capaci-
tance calculation
RES
32 kHz XTAL Start
Time
t
—
—
6
—
—
sec
32k
32 kHz Accuracy using
Internal RC Oscillator
32KRC
1000
ppm
RES
32 kHz RC Oscillator
Sta
t
—
—
500
9.5
—
—
µs
32kRC
POR Reset Time
t
Current consumption
during POR time is
200 µA typical
ms
POR
Software Reset Time
t
—
250
—
µs
soft
Rev. 1.0
74
Si102x/3x
Table 4.26. Digital IO Specifications (nIRQ)
Parameter
Symbol
Conditions
to 0.9 x V
,
DD_RF
Min
Typ
Max Units
1
Rise Time
T
0.1 x V
0.9 x V
—
—
8
ns
ns
pF
V
RISE
DD_RF
C =
5 pF
L
1
Fall Time
T
to 0.1 x V
—
—
—
—
—
—
8
FALL
DD_RF
DD_R
F
,
C =
5 pF
L
Input Capaci-
C
V
1
IN
1
tance
Logic High Level
Input Voltage
V
V
– 0.6
—
0.6
IH
DD_RF
Logic Low Level
Input Voltage
V
V
IL
Input Current
I
0<V <
V
DD_RF
–100
–
6
DD_RF
—
—
100
—
nA
V
IN
IN
Logic High Level
Output Voltage
V
I
<1 mA source, V
<1 mA sink, V
=1.8 V
DD_RF
=1.8 V
OH
OH
DD_RF
Logic Low Level
V
I
—
—
0.6
V
OL
OL
Output Voltage
Notes:
1.
Guaranteed by characterization; not production tested.
Table 4.27. GPIO Specifications (GPIO_0, GPI
1, and GPIO_2)
Parameter
Symbol
Con
ions
to 0.9 x V
,
DD_RF
Min
Typ
Max
Units
1
Rise Time
T
0.1 x V
—
—
8
ns
RISE
DD
C =
10 p
DRV<1:0> = HH
L
1
Fall Time
T
0.9 x V
to 0.1 x V
—
—
8
1
ns
FALL
DD_RF
DD_R
F
,
= 10 p
F
,
D
RV<1:0> = HH
1
Input Capacitance
C
V
—
—
—
pF
V
IN
Logic High Level Input
Voltage
V
– 0.6
DD_RF
IH
Logic Low Level Input
Voltage
V
—
—
0.6
V
IL
Input Current
I
0<V <
V
DD_RF
–100
5
—
—
100
25
nA
µA
IN
IN
Input Current If Pul-
lup is Activ
d
I
V =
0 V
IL
INP
Max
m Output
Cur
nt
I
DRV<1:0> = LL
DRV<1:0> = LH
DRV<1:0> = HL
DRV<1:0> = HH
0.1
0.9
1.5
1.8
0.5
2.3
3.1
3.6
—
0.8
3.5
4.8
5.4
—
mA
mA
mA
mA
V
OmaxLL
I
I
OmaxLH
OmaxHL
OmaxHH
I
Logic High Level
V
I
< I
source,
V
– 0.6
DD_RF
OH
OH Omax
Output Voltage
V
= 1.8 V
DD_RF
Notes:
1.
Guaranteed by characterization; not production tested.
75
Rev. 1.0
Si102x/3x
Table 4.27. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)
(Continued)
Logic Low Level
V
I
< I
sink,
OL Omax
—
—
0.6
V
OL
Output Voltage
V
= 1.8 V
DD_RF
Notes:
1.
Guaranteed by characterization; not production tested.
Table 4.28. Absolute Maximum Ratings
Parameter
Value
Unit
V
to GND
–0.3, +3.6
–0.3, +8.0
–0.3, +6.5
V
V
DD_RF
Instantaneous V
to GND on TX Output Pin
RF-peak
Sustained V
to GND on TX Output Pin
V
RF-peak
Voltage on Digital Control Inputs
Voltage on Analog Inputs
–0.3, V
–0.3
V
+ 0.3
+ 0.3
V
DD_RF
V
DD_RF
RX Input Power
+10
dBm
C
C/W
C
C
Operating Ambient
T
e
mperature Range T
–40 to +85
30
A
Thermal Impedance
JA
Junction
T
e
mperature T
+125
J
Storage
T
e
mperature Range T
–55 to +125
STG
Note:
Stresses beyond those listed under “Absolute Maxi
Ratings” may cause permanent damage to the
device. These are stress ratings only and functional o
eration of the device at or beyond these ratings in the
operational sections of the specifications is no
mpl
ed. Exposure to absolute maximum rating conditions for
extended periods may affect device reliabi
Power Amplifier may be damaged if switched on without proper
load or termination connected. TX matchin
twork design will influence TX VRF-peak on TX output pin.
Caution: ESD sensitive device.
Table 4.29. Thermal Properties
Parameter
Value
–40 to +85
30
Unit
C
Operating Ambient
T
e
mperature Range T
A
Thermal Impedan
C
/
W
C
A
Maximum Junction
T
e
mperature T
+125
J
Storage
T
perature Range T
–55 to +125
C
STG
No
tresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.
Rev. 1.0
76
Si102x/3x
5. SAR
ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode
The ADC0 on Si102x/3x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation-register
(SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autono-
mous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples
then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumula
that can automatically oversample and average the ADC results. See Section 5.4 for more details on using
the ADC in 12-bit mode.
The ADC is fully configurable under software control via Special Function Registers. The ADC
perates in
Single-ended mode and may be configured to measure various different signals usin
analog multi-
plexer described in “5.7.
ADC0 Analog Multiplexer” on page 94. The voltage referen
the ADC is
selected as described in “5.9. Voltage and Ground Reference Options” on page 99.
ADC0CN
VDD
000
001
010
011
100
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
art
C
version
ADC0TK
Burst Mode Logic
ADC0PWR
10/
2-Bit
SAR
AIN+
From
AMUX0
16-Bit Accumulator
AD0WINT
ADC
Window
Compare
Logic
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
ADC0CF
Figure 5.1. ADC0 Functional Block Diagram
5.1. Output
Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the
ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the
etting of the AD0SJST[2:0]. When the repeat count is set to 1, conversion codes are represented as 10-
bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example codes are shown below
for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to 0.
Rev. 1.0
77
Si102x/3x
Input Voltage
Right-Justified ADC0H:ADC0L
(AD0SJST = 000)
Left-Justified ADC0H:ADC0L
(AD0SJST = 100)
VREF x 1023/1024
VREF x 512/1024
VREF x 256/1024
0
0x03FF
0x0200
0x0100
0x0000
0xFFC0
0x8000
0x4000
0x0000
When the repeat count is greater than 1, the output conversion code represents the accumula
d result of
the conversions performed and is updated after the last conversion in the series is fini
. Sets of 4, 8,
16, 32, or 64 consecutive samples can be accumulated and represented in unsigned i
format. The
repeat count can be selected using the AD0RPT bits in the ADC0AC register. When a rep
t count higher
than 1, the ADC output must be right-justified (AD0SJST = 0xx); unused bits in the ADC0H and ADC0L
registers are set to 0. The example below shows the right-justified result for various input voltages and
n
repeat counts. Notice that accumulating 2
samples is equivalent to left-shift
by
n
bit positions when all
samples returned from the ADC have the same value.
Input Voltage
Repeat Count = 4
Repeat Count = 16
Repeat Count = 64
V
x 1023/1024
x 512/1024
x 511/1024
0
0x0FFC
0x3FF0
0xFFC0
REF
V
0x0800
0x07FC
0x0000
0x200
0x1FF0
x0000
0x8000
0x7FC0
0x0000
REF
V
REF
The AD0SJST bits can be used to format th
ontents of the 16-bit accumulator. The accumulated result
can be shifted right by 1, 2, or 3 bit positions.
sed on the principles of oversampling and averaging, the
effective ADC resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4.
The example below shows how to in
ease the effective ADC resolution by 1, 2, and 3 bits to obtain an
effective ADC resolution of 11-bit, 12
bit, or 13-bit respectively without CPU intervention.
Input Voltage
Repeat Count = 4
Shift Right = 1
11-Bit Result
Repeat Count = 16
Shift Right = 2
12-Bit Result
Repeat Count = 64
Shift Right = 3
13-Bit Result
V
x 1023/1024
x 512/1024
x 5
/1024
0
0x07F7
0x0400
0x03FE
0x0000
0x0FFC
0x0800
0x04FC
0x0000
0x1FF8
0x1000
0x0FF8
0x0000
REF
V
REF
V
RE
78
Rev. 1.0
Si102x/3x
5.2. Modes
of Operation
ADC0 has a maximum conversion speed of 300 ksps in 10-bit mode. The ADC0 conversion clock (SAR-
CLK) is a divided version of the system clock when burst mode is disabled (BURSTEN = 0), or a divided
version of the low power oscillator when burst mode is enabled (BURSEN = 1). The clock divide value is
determined by the AD0SC bits in the ADC0CF register.
5.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2
–
0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 3 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed “on-
demand”. During conversion, the AD0BUSY bit is set to logic 1 and re
et to
ogic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be
used. Converted data is available in the ADC0 data registers, A
C0H:ADC0L, when bit AD0INT is logic 1.
When Timer 2 or Timer 3 overflows are used as the convers
source, Low Byte overflows are used if
Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See “33. Timers” on
page 483 for timer configuration.
Important Note About Using CNVSTR:
The CNVSTR
put pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar.
T
o
c
onfigure the Crossbar to skip P
, set to 1 Bit 6 in register P0SKI
P
.
S
ee “27. Port Input/Out-
put” on page 351 for details on Port I/O config
tion.
5.2.2. Tracking Modes
Each ADC0 conversion must be pre
eded by a minimum tracking time in order for the converted result to
be accurate. The minimum tracking time is given in
T
a
ble 4.12. The AD0TM bit in register ADC0CN con-
trols the ADC0 track-and-hold mode. In its default state when Burst Mode is disabled, the ADC0 input is
continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0
operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking
period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate
conversions in low
er tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on
the rising edge of CNVSTR (see Figure 5.2). Tracking can also be disabled (shutdown) when the device is
in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings
are freque
y changed, due to the settling time requirements described in “5.2.4. Settling Time Require-
men
n page 82.
Rev. 1.0
79
Si102x/3x
A. ADC0 Timing for External Trigger Source
CNVSTR
(AD0CM[2:0]=100)
1
2 3 4 5 6 7 8 9
10 11 12 13 14
SAR Clocks
AD0TM=1
Low Power
or Convert
Low Power
Mod
Track
Convert
Convert
AD0TM=0
Track or Convert
ck
B. ADC0 Timing for Internal Trigger Source
Write ‘1’ to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3
Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
1
1
2
3
4
5
5
6
6
7
7
8
8
9 10
11 12 13 14 15 16 17
SAR
Clocks
Low Power
or Convert
Track
Convert
Low Power Mode
AD0TM=1
2
3
9 10
11 12 13 14
SAR
Clocks
Track or
Convert
Convert
Track
AD0TM=0
Figure 5.2. 10-Bit ADC T
ck and Conversion Example Timing (BURSTEN = 0)
80
Rev. 1.0
Si102x/3x
5.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver-
sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or
64 using an internal Burst Mode clock (approximately 20 MHz), then re-enters a low power state. Since the
Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a
low power state within a single system clock cycle, even if the system clock is slow (e.g. 32.768 kHz), or
suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains e
abled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. I
C0 is powered
down, it will automatically power up and wait the programmable Power-Up Time
olled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.3
ows an exam-
ple of Burst Mode Operation with a slow system clock and a repeat count of 4.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate ea
conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
In Burst Mode, tracking is determined by the settings in AD0PWR and AD0TK. The default settings for
these registers will work in most applications without modif
cat
however, settling time requirements may
need adjustment in some applications. Refer to “5.2.4. Settling Time Requirements” on page 82 for more
details.
Notes:
Setting AD0TM to 1 will insert an additional 3
R clocks of tracking before each conversion,
regardless of the settings of AD0PWR and AD0TK.
When using Burst Mode, care must be tak
o issue a convert start signal no faster than once every
four SYSCLK periods. This includes external convert start signals.
System Clock
Convert Start
AD0
1
AD0EN = 0
Powered
Down
Power-Up
and Track
T
3
T
3
T
3
T
3
Powered
Down
Power-Up
and Track
C
T
C
T
C
T
C
T
T
C..
C..
AD0TM = 0
AD0EN = 0
Powered
Down
Power-Up
and Track
Powered
Down
Power-Up
and Track
C
T C T C T C
AD0PWR
AD0TK
T = Tracking set by AD0TK
T3 = Tracking set by AD0TM (3 SAR clocks)
C = Converting
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4
Rev. 1.0
81
Si102x/3x
5.2.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion.
For many applications, these three SAR clocks will meet the minimum tracking time requirements, and
higher values for the external source impedance will increase the required tracking time.
Figure 5.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation . When measuring the
T
e
mperature Sensor output or
V
with respect to GND,
R
reduces to
R
. See
T
a
ble
4.12 for ADC0 minimum
ttling time
DD
TOTAL
MUX
requirements as well as the mux impedance and sampling capacitor values.
2
n
SA
——
t
= ln
R
TOTAL
C
SAMPLE
ADC0 Settling Time Requirements
Where:
SA
is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t
is the required settling time in seconds
R
is the sum of the AMUX0 resistance and any external source resistance.
TOTAL
n
is the ADC resolution in bits (10).
MUX Select
P0.x
R
MUX
C
SAMPLE
RC
I
put
= R
MUX
* C
SAMPLE
Note:
The value of CSAMPLE depends on the PGA Gain. See
T
a
ble 4.12 for details.
Figure 5.4. ADC0 Equivalent Input Circuits
5.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by
. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is V
x 2.
EF
REF
The
gain setting can be useful to obtain a higher input Voltage range when using a small V
volt-
REF
age,
r to measure input voltages that are between V
trolled by the AMP0GN bit in register ADC0C
F
.
and V
. Gain settings for the ADC are con-
DD
REF
82
Rev. 1.0
Si102x/3x
5.3. 8-Bit
Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles
than a 10-bit conversion. This can result in an overall lower power consumption since the system can
spend more time in a low power mode. The two LSBs of a conversion are always 00 in this mode, and the
ADC0L register will always read back 0x00.
5.4. 12-Bit
Mode
Si102x/3x devices have an enhanced SAR converter that provides 12-bit resolution while retaining the 10-
and 8-bit operating modes of the other devices in the family. When configured for 12-bit conv
sions, the
ADC performs four 10-bit conversions using four different reference voltages and combin
the results into
a single 12-bit value. Unlike simple averaging techniques, this method provides true 12
olution of ac
or dc input signals without depending on noise to provide dithering. The converter also
ploys a hard-
ware Dynamic Element Matching algorithm that reconfigures the largest elements of the internal DAC for
each of the four 10-bit conversions to cancel the any matching errors, enabling the
onverter to achieve
12-bit linearity performance to go along with its 12-bit resolution. For best performance, the Low Power
Oscillator should be selected as the system clock source while taking 12-bit
DC measurements.
The 12-bit mode is enabled by setting the AD012BE bit (ADC0AC.7) t
logic 1 and configuring Burst Mode
for four conversions as described in Section 5.2.3. The conversion can be initiated using any of the meth-
ods described in Section 5.2.1, and the 12-bit result will appear in
he ADC0H and ADC0L registers. Since
the 12-bit result is formed from a combination of four 10-bit resu
s, the maximum output value is 4 x (1023)
= 4092, rather than the max value of (2^12 – 1) = 4095 that is
uced by a traditional 12-bit converter.
T
o
further increase resolution, the burst mode repeat value may be configured to any multiple of four conver-
sions. For example, if a repeat value of 16 is selected
the ADC0 output will be a 14-bit number (sum of
four 12-bit numbers) with 13 effective bits of resolutio
Rev. 1.0
83
Si102x/3x
5.5. Low
Power Mode
The SAR converter provides a low power mode that allows a significant reduction in operating current
when operating at low SAR clock frequencies. Low power mode is enabled by setting the AD0LPM bit
(ADC0PWR.7) to 1. In general, low power mode is recommended when operating with SAR conversion
clock frequency at 4 MHz or less. See the Electrical Characteristics chapter for details on power consump-
tion and the maximum clock frequencies allowed in each mode. Setting the Low Power Mode bit reduce
the bias currents in both the SAR converter and in the High-Speed Voltage Reference.
Table 5.1. Representative Conversion Times and Energy Consumption for the
R ADC
with 1.65 V High-Speed VREF
Normal Power Mode
10 bit
Low Power
ode
10 bit
12 bit
8 bit
12 bit
8 bit
Highest nominal
SAR clock
8.17 MHz
(24.5/3)
8.17 MHz
(24.5/3)
6.67 MHz
(20.0/3)
4.08
MHz
4.08
MHz
4.00 MHz
(20.0/5)
frequency
(24.5/6)
(24.5/6)
Total number of
conversion clocks
required
11
13
52 (13 x 4)
11
13
52 (13*4)
Total tracking time
(min)
1.5 µs
1.5 µs
8 µs
(1.5+3 x 1.1)
1.5 µs
1.5 µs
4.8 µs
(1.5+3 x 1.1)
Total time for one
conversion
2.85 µs
3.09
12.6 µs
4.19 µs
4.68 µs
17.8 µs
ADC Throughput
351 ksps
8.2 nJ
323 ksps
8.9 nJ
79 ksps
36.5 nJ
238 ksps
214 ksps
6.5 nJ
7.3 nJ
56 ksps
27.7 nJ
Energy per
conversion
Note:
This table assumes that the 24.5 MHz precision oscillator is used for 8- and 10-bit modes, and the 20 MHz
low power oscillator is used for 12-bit mode. The values in the table assume that the oscillators run at their
nominal freq
es. The maximum SAR clock values given in
T
a
ble 4.12 allow for maximum oscillation
frequencies of 25.0 MHz and 22 MHz for the precision and low-power oscillators, respectively, when using
the given SAR clock divider values. Energy calculations are for the ADC subsystem only and do not include
CP
urrent.
84
Rev. 1.0
Si102x/3x
SFR Definition 5.1. ADC0CN: ADC0 Control
Bit
7
6
5
4
3
2
1
0
Name
AD0EN BURSTEN AD0INT AD0BUSY
AD0WINT
ADC0CM[2:0]
Type
R/W
0
R/W
0
R/W
0
W
0
R/W
0
R/W
0
Reset
0
0
SFR Page = 0x0; SFR Address = 0xE8; bit-addressable;
Bit
Name
Function
7
AD0EN
ADC0 Enable.
0: ADC0 Disabled (low-power shutdown).
1: ADC0 Enabled (active and ready for data conversi
).
6
5
BURSTEN
ADC0 Burst Mode Enable.
0: ADC0 Burst Mode Disabled.
1: ADC0 Burst Mode Enabled.
AD0INT
ADC0 Conversion Complete Interrup
ag.
Set by hardware upon completion of a data conversion (BURSTEN=0), or a burst
of conversions (BURSTEN=1). Can trigger an interrupt. Must be cleared by soft-
ware.
4
3
AD0BUSY
AD0WINT
ADC0 Busy.
Writing 1 to this bit init
es an ADC conversion when ADC0CM[2:0] = 000.
ADC0 Window Compare Interrupt Flag.
Set by hardware when the contents of ADC0H:ADC0L fall within the window speci-
fied by ADC0
TH:ADC0GTL and ADC0LTH:ADC0LTL. Can trigger an interrupt.
Must be cleared by software.
2:0 ADC0CM[2:0]
ADC0 Start of Conversion Mode Select.
Specifies the ADC0 start of conversion source.
000: ADC0 conversion initiated on write of 1 to AD0BUS
Y
.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 3.
1xx: ADC0 conversion initiated on rising edge of CNVSTR.
Rev. 1.0
85
Si102x/3x
SFR Definition 5.2. ADC0CF: ADC0 Configuration
Bit
7
6
5
AD0SC[4:0]
R/W
4
3
2
AD08BE
R/W
0
1
AD0TM
R/W
0
0
AMP0G
R/W
Name
Type
Reset
1
1
1
1
1
0
SFR Page = 0x0; SFR Address = 0xBC
Bit
Name
Function
7:3 AD0SC[4:0]
ADC0 SAR Conversion Clock Divider.
SAR Conversion clock is derived from FCLK by the following equation, where
AD0SC
refers to the 5-bit value held in bits AD0SC[4:0]
AR Conversion clock
requirements are given in
T
a
ble 4.12.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the 20 MHz low power oscillator, independent of the system
clock.
FCLK
CLK
SAR
—————–
–
–
AD0SC
=
– 1
*
*Round the result up.
or
FCLK
–
–
———————–
=
CLK
SAR
AD
0
SC
+ 1
2
1
AD08BE
AD0TM
ADC0 8-Bit Mode Enable.
0: ADC0 operates in 10-bit mode (normal operation).
ADC0 operates in 8-bit mode.
ADC0 Track Mode.
Selects between Normal or Delayed Tracking Modes.
0: Normal Track Mode: When ADC0 is enabled, conversion begins immediately fol-
lowing the start-of-conversion signal.
1: Delayed Track Mode: When ADC0 is enabled, conversion begins 3 SAR clock
cycles following the start-of-conversion signal. The ADC is allowed to track during
this time.
0
AMP0GN
ADC0 Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
86
Rev. 1.0
Si102x/3x
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration
Bit
7
6
AD0AE
W
5
4
3
2
1
0
Name
AD012BE
AD0SJST[2:0]
AD0RPT[2:0]
Type
R/W
0
R/W
0
R/W
0
Reset
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBA
Bit
Name
Function
7
AD012BE
ADC0 12-Bit Mode Enable.
Enables 12-bit Mode.
0: 12-bit Mode Disabled.
1: 12-bit Mode Enabled.
6
AD0AE
ADC0 Accumulate Enable.
Enables multiple conversions to be accumulated when burst mode is disabled.
0: ADC0H:ADC0L contain the result o
he latest conversion when Burst Mode is
disabled.
1: ADC0H:ADC0L contain the accumulated conversion results when Burst Mode
is disabled. Software must wr
e 0x0000 to ADC0H:ADC0L to clear the accumu-
lated result.
This bit is write-only. Al
ys reads 0b.
5:3
AD0SJST[2:0]
ADC0 Accumulato
hift and Justify.
Specifies the format of data read from ADC0H:ADC0L.
000: Right justified. No shifting applied.
001: Right
stified. Shifted right by 1 bit.
010: Right justified. Shifted right by 2 bits.
011: Right justified. Shifted right by 3 bits.
100: Left justified. No shifting applied.
All remaining bit combinations are reserved.
2:0
AD0RPT[
ADC0 Repeat Count.
Selects the number of conversions to perform and accumulate in Burst Mode.
This bit field must be set to 000 if Burst Mode is disabled.
000: Perform and Accumulate 1 conversion.
001: Perform and Accumulate 4 conversions.
010: Perform and Accumulate 8 conversions.
011: Perform and Accumulate 16 conversions.
100: Perform and Accumulate 32 conversions.
101: Perform and Accumulate 64 conversions.
All remaining bit combinations are reserved.
Rev. 1.0
87
Si102x/3x
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time
Bit
7
6
5
4
3
2
1
0
Name
AD0LPM
AD0PWR[3:0]
R/W
Type
R/W
0
R
0
R
0
R
0
Reset
1
1
1
1
SFR Page = 0xF; SFR Address = 0xBA
Bit
Name
Function
7
AD0LPM
ADC0 Low Power Mode Enable.
Enables Low Power Mode Operation.
0: Low Power Mode disabled.
1: Low Power Mode enabled.
6:4
Unused
Read = 0000b; Write = Don’t Care.
3:0 AD0PWR[3:0]
ADC0 Burst Mode Power-Up Time.
Sets the time delay required for ADC0
ower up from a low power state.
For BURSTEN = 0:
ADC0 power state controlled by AD0EN.
For BURSTEN = 1 and AD0E
1:
ADC0 rem
ns enabled and does not enter a low power state after
all conversions are comple
e.
Conversions can beg
mediately following the start-of-conversion signal.
For BURSTEN = 1 and AD0EN = 0:
ADC0 enters a low power state after all conversions are complete.
Conversions
n begin a programmed delay after the start-of-conversion signal.
The ADC0 Burst Mode Power-Up time is programmed according to the following
equation:
Tstartup
400
ns
———————-
AD0PWR
=
– 1
or
Tstartup
=
AD0PWR
+ 1
400
ns
Note:
Setting AD0PWR to 0x04 provides a typical tracking time of 2 us for the first sample
taken after the start of conversion.
88
Rev. 1.0
Si102x/3x
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
AD0TK[5:0]
R/W
R
0
R
0
0
1
1
1
1
0
SFR Page = 0xF; SFR Address = 0xBD
Bit
7
Name
Function
Reserved Read
= 0b; Write = Must Write 0b.
Unused Read
= 0b; Write = Don’t Care.
6
5:0 AD0TK[5:0]
ADC0 Burst Mode Track Time.
Sets the time delay between consecutive conversions performed in Burst Mode.
The ADC0 Burst Mode Track time is programmed according to the following equa-
tion:
Ttrack
50
ns
–
—————-
AD0TK
= 63
–
or
Ttrack
=
64 –
AD0TK
50
ns
Notes:
1.
If AD0TM is set to 1, an additional 3 SAR clock cycles of Track time will be inserted prior to starting the
conversion.
2.
The Burst Mode Track delay is not inserted prior to the first conversion. The required tracking time for the first
conversion should be met by the Burst Mode Power-Up Time.
Rev. 1.0
89
Si102x/3x
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
ADC0[15:8]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBE
Bit Name
Description
Read
7:0 ADC0[15:8]
ADC0 Data Word High
Most Significant Byte of the
Set the most significant
16-bit ADC0 Accumulator
byte of the 16-bit ADC0
formatted according to the
ccumulator to the value
settings in AD0SJST[2:0].
written.
Byte.
Note:
If Accumulator shifting is enabled, the most significant bits of the value read will be zeros. This register
should not be written when the SYNC bit is set to 1.
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
ADC0[7:0]
R/W
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBD;
Bit
Name
Description
Read
Write
7:0
ADC0[7:0]
ADC0 Data Word Low
Least Significant Byte of the
Set the least significant
Byte.
16-bit ADC0 Accumulator
formatted according to the
settings in AD0SJST[2:0].
byte of the 16-bit ADC0
Accumulator to the value
written.
Note:
If Accumulator shifting is enabled, the most significant bits of the value read will be the least significant bits of
the
cumulator high byte. This register should not be written when the SYNC bit is set to 1.
5.6. Programmable
Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limits, and notifies the system when a desired condition is detected. This is especially effective in
n interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
90
Rev. 1.0
Si102x/3x
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
AD0GT[15:8]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xC4
Bit Name
7:0 AD0GT[15:8]
ADC0 Greater-Than High Byte.
Most Significant Byte of the 16-bit Greater-Than window compare register.
Function
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte
Bit
7
6
5
4
2
1
0
Name
Type
Reset
AD0GT[7:0]
W
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xC3
Bit Name
7:0 AD0GT[7:0]
ADC0 Greater
han Low Byte.
Least Significant Byte of the 16-bit Greater-Than window compare register.
Note:
In 8-bit mode, this register should be set to 0x00.
Function
Rev. 1.0
91
Si102x/3x
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
AD0LT[15:8]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC6
Bit
Name
Function
7:0 AD0LT[15:8]
ADC0 Less-Than High Byte.
Most Significant Byte of the 16-bit Less-Than window compare register.
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte
Bit
7
6
5
4
2
1
0
Name
Type
Reset
AD0LT[7:0]
W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC5
Bit
Name
Function
7:0
AD0LT[7:0]
ADC0 Less-
an Low Byte.
Least Significant Byte of the 16-bit Less-Than window compare register.
Note:
In 8-bit mode, this register should be set to 0x00.
5.6.1. Window Detector In Single-Ended Mode
Figure 5.5
show
two
example
window
comparisons
for
right-justified
data,
with
ADC0LTH:ADC0LTL
0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In
left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC
:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x
040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.6 shows an example using left-justi-
ied data with the same comparison values.
92
Rev. 1.0
Si102x/3x
ADC0H:ADC0L
0x03FF
ADC0H:ADC0L
0x03FF
Input Voltage
(Px.x – GND)
Input Voltage
(Px.x – GND)
VREF x (1023/1024)
VREF x (1023/1024)
AD0WINT
not affected
AD0WINT=1
0x0081
0x0081
VREF x (128/1024)
VREF x (64/1024)
0x0080
0x007F
ADC0LTH:ADC0LTL
VREF x (128/1024)
VREF x (64/1024)
0x0080
0x007F
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
0x0041
0x0040
0x0041
0x0040
ADC0GTH:ADC0GTL
ADC0LT
LTL
0x003F
0x003F
AD0WINT=1
AD0WINT
not affected
0x0000
0x0000
0
0
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data
ADC0H:ADC0L
0xFFC0
ADC0H:ADC0L
0xFFC0
Input Voltage
(Px.x – GND)
Input Volt
(P
x – G
VREF x (1023/1024)
VREF x (1023/1024)
AD0WINT
not affected
AD0WINT=1
0x2040
0x2040
VREF x (128/1024)
VREF x (64/1024)
0x2000
0x1FC0
ADC0LTH:ADC0LTL
VREF x (128/1024)
VREF x (64/1024)
0x2000
0x1FC0
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0
T=1
0x1040
0x1000
0x1040
0x1000
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x0FC0
0x0FC0
AD0WINT=1
AD0WINT
not affected
0x0000
0x0000
0
0
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data
5.6.2. ADC0 Specifications
See “4. Elec
ical Characteristics” on page 48 for a detailed listing of ADC0 specifications.
Rev. 1.0
93
Si102x/3x
5.7. ADC0
Analog Multiplexer
ADC0 on Si102x/3x has an analog multiplexer, referred to as AMUX0.
AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the
positive input: Port I/O pins, the on-chip temperature sensor, the VBAT Power Supply, Regulated Digital
Supply Voltage (Output of VREG0), VDC Supply, or the positive input may be connected to GND. The
ADC0 input channels are selected in the ADC0MX register described in SFR Definition 5.12.
ADC0MX
P0.0
Programmable
Attenu
tor
AIN+
ADC0
AMUX
P2.3*
VBAT
Temp
Sensor
Gain = 0.5 or 1
Digital Supply
VDC
*P1.0 – P1.3 are not available as analog inputs
Figure 5.7. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration:
Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar.
T
o
c
onfigure a Port pin for analog
input, set t
0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT = 0 and
Por
h = 1).
T
o
f
orce the Crossbar to skip a Port pin, set to 1 the corresponding bit in register PnSKI
P
.
See Section “27. Port Input/Output” on page 351 for more Port I/O configuration details.
Rev. 1.0
94
Si102x/3x
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select
Bit
7
6
5
4
3
2
1
0
AD0MX
Name
Type
Reset
R
0
R
0
R
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
SFR Page = 0x0; SFR Address = 0xBB
Bit
Name
Unused Read
= 000b; Write = Don’t Care.
AD0MX
Function
7:5
4:0
AMUX0 Positive Input Selection.
Selects the positive input channel for ADC0.
00000:
00001:
00010:
00011:
00100:
00101:
00110:
00111:
01000:
01001:
01010:
01011:
01100:
01101:
01110:
01111:
P0.0
10000:
10001:
10010:
10011:
00:
10101:
10110:
10111:
11000:
11001:
11010:
11011:
11100:
P2.0
P2.1
P2.2
P2.3
P0.1
P0.2
P0.3
P0.4
Reserved.
P0.5
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
P0.6
P0.7
Reserved
Reserved
Reserved
Reserved
P
4
T
e
mperature Sensor
VBAT Supply Voltage
(1.8–3.6 V)
P1.5
P1.6
11101:
11110:
11111:
Digital Supply Voltage
(VREG0 Output, 1.7 V Typical)
P1.7
VBAT Supply Voltage
(1.8–3.6 V)
Ground
95
Rev. 1.0
Si102x/3x
5.8. Temperature
Sensor
An on-chip temperature sensor is included on the Si102x/3x which can be directly accessed via the ADC
multiplexer in single-ended configuration.
T
o
u
se the ADC to measure the temperature sensor, the ADC
mux channel should select the temperature sensor. The temperature sensor transfer function is shown in
Figure 5.8. The output voltage (V
) is the positive ADC input when the ADC multiplexer is set correctly.
TEMP
The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in SF
Definition 5.15. REF0CN: Voltage Reference Control. While disabled, the temperature sensor defaults to
high impedance state and any ADC measurements performed on the sensor will result in meaningless
data. Refer to
T
a
ble 4.12 for the slope and offset parameters of the temperature sensor.
V
TEMP
=
Slope
x (Temp
C
– 25) +
Offset
Temp
C
= 25 + (V
TEMP
–
Offset
) /
Slope
Slop
e
( V / deg
C
)
Offse
t
( V at 25 Celsius)
Temperature
Figure 5.8. Temperature Sensor Transfer Function
5.8.1. Calibrat
on
The uncalib
ted temperature sensor output is extremely linear and suitable for relative temperature mea-
surem
nts
see
T
a
ble 4.13 for linearity specifications). For absolute temperature measurements, offset
and
ain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps:
1. Control/measure the ambient temperature (this temperature must be known).
2. Power the device, and delay for a few seconds to allow for self-heating.
3. Perform an ADC conversion with the temperature sensor selected as the positive input and GND
selected as the negative input.
4. Calculate the offset characteristics, and store this value in non-volatile memory for use with
subsequent temperature sensor measurements.
Rev. 1.0
96
Si102x/3x
Figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C.
Parame-
ters that affect ADC measurement, in particular the voltage reference value, will also affect tem-
perature measurement.
A single-point offset measurement of the temperature sensor is performed on each device during produc-
tion test. The measurement is performed at 25 °C ±5 °C, using the ADC with the internal high speed refer-
ence buffer selected as the Voltage Reference. The direct ADC result of the measurement is stored in t
SFR registers TOFFH and TOFFL, shown in SFR Definition 5.13 and SFR Definition 5.14.
5.00
4.00
3.00
2.00
1.00
0.00
00
4.00
3.00
2.00
1.00
0.00
-1.00
-2.00
-3.00
-4.00
-5.00
0
-40.00
-20.00
0.00
60.00
80.00
20.00
-1.00
-2.00
-3.00
-4.00
-5.00
Temperature (degrees C)
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (V
REF
= 1.68 V)
97
Rev. 1.0
Si102x/3x
SFR Definition 5.13. TOFFH: Temperature Sensor Offset High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TOFF[9:2]
R
R
R
R
R
R
R
R
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Page = 0xF; SFR Address = 0x86
Bit
Name
Function
7:0
TOFF[9:2]
Temperature Sensor Offset High Bits.
Most Significant Bits of the 10-bit temperature sensor offset measurement.
SFR Definition 5.14. TOFFL: Temperature Sensor Offset Low Byte
Bit
7
6
5
4
2
1
0
Name
Type
Reset
TOFF[1:0]
R
R
Varies
Varies
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x85
Bit
Name
Function
7:6
TOFF[1:0]
Temperature S
sor Offset Low Bits.
Least Significan
Bits of the 10-bit temperature sensor offset measurement.
5:0
Unused
Read = 0; Write = Don’t Care.
Rev. 1.0
98
Si102x/3x
5.9. Voltage
and Ground Reference Options
The voltage reference MUX is configurable to use an externally connected voltage reference, the internal
voltage reference, or one of two power supply voltages (see Figure 5.10). The ground reference MUX
allows the ground reference for ADC0 to be selected between the ground pin (GND) or a port pin dedi-
cated to analog ground (P0.1/AGND).
The voltage and ground reference options are configured using the REF0CN SFR described on S
Definition 5.15. REF0CN:
Voltage Reference Control. Electrical specifications are can be found in th
Electrical Specifications Chapter.
Important Note About the V
and AGND Inputs:
Port pins are used as the external V
nd AGND
REF
RE
inputs. When using an external voltage reference or the internal precision reference, P0.
REF should be
configured as an analog input and skipped by the Digital Crossbar. When using AGND a
round refer-
ence to ADC0, P0.1/AGND should be configured as an analog input and skipped by the
gital Crossbar.
Refer to Section “27. Port Input/Output” on page 351 for complete Port I/O configuration details. The exter-
nal reference voltage must be within the range 0
V
VDD and the external ground reference must be
REF
at the same DC voltage potential as GND.
REF0CN
ADC
Input
Mux
Temp Sensor
EN
VDD
External
Voltage
Reference
Circuit
R1
P0.0/VREF
VBAT
00
01
10
11
VREF
(to ADC)
Internal 1.8V
Regulated Digital Supply
GND
Internal 1.65V
High Speed Reference
+
4.7
F
0.
GND
0
1
Ground
(to ADC)
Reco
n
ded
Bypass
a
p
citors
P0.1/AGND
REFGND
Figure 5.10. Voltage Reference Functional Block Diagram
Rev. 1.0
99
Si102x/3x
5.10. External
Voltage Reference
To
u
se an external voltage reference, REFSL[1:0] should be set to 00. Bypass capacitors should be added
as recommended by the manufacturer of the external voltage reference. If the manufacturer does not pro-
vide recommendations, a 4.7uF in parallel with a 0.1uF capacitor is recommended.
5.11. Internal
Voltage Reference
For applications requiring the maximum number of port I/O pins, or very short VREF turn-on time, t
1.65 V high-speed reference will be the best internal reference option to choose. The high speed internal
reference is selected by setting REFSL[1:0] to 11. When selected, the high speed internal reference will be
automatically enabled/disabled on an as-needed basis by ADC0.
For applications with a non-varying power supply voltage, using the power supply as th
ge reference
can provide ADC0 with added dynamic range at the cost of reduced power supply noise
ction.
T
o
u
se
the 1.8 to 3.6 V power supply voltage (V
) or the 1.8 V regulated digital supply voltage as the reference
DD
source, REFSL[1:0] should be set to 01 or 10, respectively.
5.12. Analog
Ground Reference
To
p
revent ground noise generated by switching digital logic from affecting sensitive analog measure-
ments, a separate analog ground reference option is available. When enabled, the ground reference for
ADC0 during both the tracking/sampling and the conversion periods is taken from the P0.1/AGND pin. Any
external sensors sampled by ADC0 should be referenced to the P0.1/AGND pin. This pin should be con-
nected to the ground terminal of any external sensors sampled
ADC0. If an external voltage reference is
used, the P0.1/AGND pin should be connected to the ground
he external reference and its associated
decoupling capacitor. The separate analog ground reference option is enabled by setting REFGND to 1.
Note that when sampling the internal temperature sen
or, the internal chip ground is always used for the
sampling operation, regardless of the setting of the
GND bit. Similarly, whenever the internal 1.65 V
high-speed reference is selected, the internal c
ground is always used during the conversion period,
regardless of the setting of the REFGND bit.
5.13. Temperature
Sensor Enable
The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the tem-
perature sensor defaults to a high i
edance state and any ADC0 measurements performed on the sen-
sor result in meaningless data. See Section “5.8.
T
e
mperature Sensor” on page
96 for details on
temperature sensor character
stics when it is enabled.
100
Rev. 1.0
Si102x/3x
SFR Definition 5.15. REF0CN: Voltage Reference Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
REFGND
R/W
REFSL
TEMPE
R/W
R
0
R
0
R/W
1
R/W
1
R
0
R
0
0
0
SFR Page = 0x0; SFR Address = 0xD1
Bit
Name
Unused Read
= 00b; Write = Don’t Care.
Function
7:6
5
REFGND
Analog Ground Reference.
Selects the ADC0 ground reference.
0: The ADC0 ground reference is the GND pin.
1: The ADC0 ground reference is the P0.1/AGND pin.
4:3
REFSL
Voltage Reference Select.
Selects the ADC0 voltage reference.
00: The ADC0 voltage reference is the P0
VREF pin.
01: The ADC0 voltage reference is the VDD pin.
10: The ADC0 voltage reference
the internal 1.8 V digital supply voltage.
11: The ADC0 voltage reference
he internal 1.65 V high speed voltage reference.
2
TEMPE
Temperature Sensor Enabl
.
Enables/Disables the in
l temperature sensor.
0:
T
e
mperature Sensor Disabled.
1:
T
e
mperature Sensor Enabled.
1:0
Unused Read
= 00b; Wr
te = Don’t Care.
5.14. Voltage
Reference Electrical Specifications
See
T
a
ble 4.14 on page 64 for detailed Voltage Reference Electrical Specifications.
Rev. 1.0
101
Si102x/3x
6. Programmable
Current Reference (IREF0)
Si102x/3x devices include an on-chip programmable current reference (source or sink) with two output cur-
rent settings: Low Power Mode and High Current Mode. The maximum current output in Low Power Mode
is 63 µA (1 µA steps) and the maximum current output in High Current Mode is 504 µA (8 µA steps).
The current source/sink is controlled though the IREF0CN special function register. It is enabled by settin
the desired output current to a non-zero value. It is disabled by writing 0x00 to IREF0CN. The port I/O
associated with ISRC0 should be configured as an analog input and skipped in the Crossbar. See “Port
Input/Output” on page 351 for more details.
SFR Definition 6.1. IREF0CN: Current Reference Control
Bit
7
SINK
R/W
0
6
MODE
R/W
0
5
4
3
2
1
0
Name
Type
Reset
IREF0DAT
R/W
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB9
Bit
Name
Fu
tion
7
SINK
IREF0 Current Sink Enable.
Selects if IREF0 is a current
rce or a current sink.
0: IREF0 is a current so
e.
1: IREF0 is a current sink.
6
MDSEL
IREF0 Output Mode
elect.
Selects Low Power or High Current Mode.
0: Low Pow
r Mode is selected (step size = 1 µA).
1: High Current Mode is selected (step size = 8 µA).
5:0 IREF0DAT[5:0]
IREF0 Data Word.
Specifies the number of steps required to achieve the desired output current.
Output current = direction x step size x IREF0DA
T
.
IREF0 is in a low power state when IREF0DAT is set to 0x00.
6.1. PWM
Enhanced Mode
The precisi
n of the current reference can be increased by fine tuning the IREF0 output using a PWM sig-
nal
rated by the PCA. This mode allows the IREF0DAT bits to perform a course adjustment on the
IREF
output. Any available PCA channel can perform a fine adjustment on the IREF0 output. When
enabled (PWMEN = 1), the CEX signal selected using the PWMSS bit field is internally routed to IREF0 to
control the on time of a current source having the weight of 2 LSBs. With the two least significant bits of
REF0DAT set to 00b, applying a 100% duty cycle on the CEX signal will be equivalent to setting the two
LSBs of IREF0DAT to 10b. PWM enhanced mode is enabled and setup using the IREF0CF register.
Rev. 1.0
102
Si102x/3x
SFR Definition 6.2. IREF0CF: Current Reference Configuration
Bit
7
6
5
4
3
2
1
0
Name
PWMEN
PWMSS[2:0]
Type
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0
0
SFR Page = 0xF; SFR Address = 0xB9
Bit
Name
Function
7
PWMEN
PWM Enhanced Mode Enable.
Enables the PWM Enhanced Mode.
0: PWM Enhanced Mode disabled.
1: PWM Enhanced Mode enabled.
6:3
2:0
Unused
Read = 0000b, Write = don’t care.
PWMSS[2:0]
PWM Source Select.
Selects the PCA channel to use for t
ne-tuning control signal.
000: CEX0 selected as fine-tuning con
ol signal.
001: CEX1 selected as fine-tuning control signal.
010: CEX2 selected as fine-
ng control signal.
011: CEX3 selected as fi
-tuning control signal.
100: CEX4 selected as f
ne-tuning control signal.
101: CEX5 selecte
fine tuning control signal.
All Other Values: Reserved.
6.2. IREF0
Specifications
See
T
a
ble 4.15 on page 65 for a detailed listing of IREF0 specifications.
103
Rev. 1.0
Si102x/3x
7. Comparators
Si102x/3x devices include two on-chip programmable voltage comparators: Comparator
0 (CPT0) is
shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate identi-
cally, but may differ in their ability to be used as reset or wake-up sources. See the Reset Sources chapter
and the Power Management chapter for details on reset sources and low power mode wake-up sources,
respectively.
The comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the port pins: a synchronous latched output (CP0, CP1), or an asyn-
chronous raw output (CP0A, CP1A). The asynchronous CP0A signal is available even when
e system
clock is not active. This allows the comparator to operate and generate an output whe
he device is in
some low power modes.
7.1. Comparator
Inputs
Each comparator performs an analog comparison of the voltage levels at its positive
CP0+ or CP1+) and
negative (CP0- or CP1-) input. Both comparators support multiple port pin inputs multiplexed to their posi-
tive and negative comparator inputs using analog input multiplexers. The
nalog input multiplexers are
completely under software control and configured using SFR registers. See “7.6. Comparator0 and Com-
parator1 Analog Multiplexers” on page 111 for details on how to select and configure comparator inputs.
Important Note About Comparator Inputs:
The port pins selected as comparator inputs should be con-
figured as analog inputs and skipped by the crossbar. See “27
Port Input/Output” on page 351 for more
details on how to configure port I/O pins as analog inputs
Th
mparator may also be used to compare
the logic level of digital signals, however, port I/O pins configured as digital inputs must be driven to a valid
logic state (HIGH or LOW) to avoid increased power c
nsumption.
CP0EN
CP0OUT
CP0RIF
CP0FIF
VDD
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0
Interrupt
CPT0MD
Analog Input Multiplexer
CP0
Rising-edge
CP0
Falling-edge
Px.x
CP0 +
Interrupt
Logic
Px.x
Px.x
CP0
+
–
SET
SET
CLR
D
Q
Q
D
Q
Q
CLR
Crossbar
(SYNCHRONIZER)
(ASYNCHRONOUS)
GND
CP0 –
CP0A
Reset
Decision
Tree
Px.x
Figure 7.1. Comparator 0 Functional Block Diagram
Rev. 1.0
104
Si102x/3x
7.2. Comparator
Outputs
When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the
voltage at the negative input. When disabled, the comparator output is a logic 0. The comparator output is
synchronized with the system clock as shown in Figure 7.2. The synchronous latched output (CP0, CP1)
can be polled in software (CPnOUT bit), used as an interrupt source, or routed to a port pin through the
crossbar.
The asynchronous raw comparator output (CP0A, CP1A) is used by the low power mode wakeup logic an
reset decision logic. See “19. Power Management” on page 257 and “22. Reset Sources” on page 278 for
more details on how the asynchronous comparator outputs are used to make wake-up and reset decisions.
The asynchronous comparator output can also be routed directly to a port pin through the cro
ba
, and is
available for use outside the device even if the system clock is stopped.
When using a comparator as an interrupt source, comparator interrupts can be generate
n rising-edge
and/or falling-edge comparator output transitions. Two independent interrupt flags (CPnRIF and CPnFIF)
allow software to determine which edge caused the comparator interrupt. The compa
ator rising-edge and
falling-edge interrupt flags are set by hardware when a corresponding edge is detected regardless of the
interrupt enable state. Once set, these bits remain set until cleared by softwa
e.
The rising-edge and falling-edge interrupts can be individually enab
ed using the CPnRIE and CPnFIE
interrupt enable bits in the CPTnMD register. In order for the CPnRIF and/or CPnFIF interrupt flags to gen-
erate an interrupt request to the CPU, the comparator must be enabled as an interrupt source and global
interrupts must be enabled. See “17. Interrupt Handler” on pag
231 for additional information.
CP1EN
CP1OUT
CP1RIF
CP1FIF
VDD
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1
Interrupt
CPT1MD
Analog Input Multiplexer
CP1
Rising-edge
CP1
Falling-edge
Px.x
CP1 +
Interrupt
Logic
Px.x
Px.x
CP1
+
–
SET
SET
CLR
D
Q
Q
D
Q
Q
CLR
Crossbar
(SYNCHRONIZER)
(ASYNCHRONOUS)
GND
CP1 –
CP1A
Reset
Decision
Tree
Px.x
Figure 7.2. Comparator 1 Functional Block Diagram
105
Rev. 1.0
Si102x/3x
7.3. Comparator
Response Time
Comparator response time may be configured in software via the CPTnMD registers described on “SFR
Definition 7.2.
CPT0MD: Comparator 0 Mode Selection” on page 108 and “SFR Definition 7.4.
CPT1MD:
Comparator 1 Mode Selection” on page 110. Four response time settings are available: Mode 0 (Fastest
Response Time), Mode 1, Mode 2, and Mode 3 (Lowest Power). Selecting a longer response time reduces
the comparator active supply current. The comparators also have low power shutdown state, which i
entered any time the comparator is disabled. Comparator rising edge and falling edge response times a
typically not equal. See
T
a
ble 4.16 on page 66 for complete comparator timing and supply current specifi-
cations.
7.4. Comparator
Hysterisis
The comparators feature software-programmable hysterisis that can be used to stabil
comparator
output while a transition is occurring on the input. Using the CPTnCN registers, the user c
program both
the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going sym-
metry of this hysteresis around the threshold voltage (i.e., the comparator negative input).
Figure 7.3 shows that when positive hysterisis is enabled, the comparator o
ut does not transition from
logic 0 to logic 1 until the comparator positive input voltage has exceeded the threshold voltage by an
amount equal to the programmed hysterisis. It also shows that whe
negative hysterisis is enabled, the
comparator output does not transition from logic 1 to logic 0 until the comparator positive input voltage has
fallen below the threshold voltage by an amount equal to the prog
ammed hysterisis.
The amount of positive hysterisis is determined by the settings
he CPnHYP bits in the CPTnCN register
and the amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits in the
same register. Settings of 20 mV, 10 mV, 5 mV, or 0 mV can be programmed for both positive and negative
hysterisis. See “
T
a
ble 4.16.
Comparator Electrical C
acteristics” on page 66 for complete comparator
hysterisis specifications.
CPn+
VIN+
VIN-
+
CPn
_
OUT
CPn-
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed
P0HYP Bits)
IN-
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
INPUTS
VIN+
V
OH
OUTPUT
V
OL
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
Figure 7.3. Comparator Hysteresis Plot
Rev. 1.0
106
Si102x/3x
7.5. Comparator
Register Descriptions
The SFRs used to enable and configure the comparators are described in the following register descrip-
tions. A comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used. From an
enabled state, a comparator can be disabled and placed in a low power state by clearing the CPnEN bit to
logic 0.
Important Note About Comparator Settings:
False rising and falling edges can be detected by the co
parator while powering on or if changes are made to the hysteresis or response time control bits. There
fore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short
time after the comparator is enabled or its mode bits have been changed. The comparator power up time is
specified in
T
a
ble 4.16, “Comparator Electrical Characteristics,” on page 66.
SFR Definition 7.1. CPT0CN: Comparator 0 Control
Bit
7
6
5
4
3
2
1
0
Name
CP0EN
CP0OUT
R
CP0RIF
R/W
CP0FIF
R/W
CP0HYP[1:0]
R/W
CP0HYN[1:0]
R/W
R/W
0
Type
0
0
0
0
0
0
0
Reset
SFR Page= 0x0; SFR Address = 0x9B
Bit
Name
Function
7
CP0EN
Comparator0 Enable Bit.
0: Comparator0 Disable
1: Comparator0 En
d.
6
5
CP0OUT
CP0RIF
Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0
–
.
1: Voltage
n CP0+ > CP0
–
.
Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4
CP0FIF
Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3-2
C
0HYP[1:0]
Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 m
V
.
1-0
CP0HYN[1:0]
Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 m
V
.
107
Rev. 1.0
Si102x/3x
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CP0RIE
R/W
CP0FIE
R/W
CP0MD[1:0]
R/W
R/W
1
R
0
R
0
R
0
0
0
1
0
SFR Page = 0x0; SFR Address = 0x9D
Bit
Name
Reserved Read
= 1b, Must Write 1b.
Function
7
6
5
Unused
CP0RIE
Read = 0b, Write = don’t care.
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4
CP0FIE
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt di
abled.
1: Comparator0 Falling-edge interrupt
led.
3:2
1:0
Unused
Read = 00b, Write = don’t care.
CP0MD[1:0]
Comparator0 Mode Select
These bits affect the respo
e time and power consumption for Comparator0.
00: Mode 0 (Fastest R
sponse Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.0
108
Si102x/3x
SFR Definition 7.3. CPT1CN: Comparator 1 Control
Bit
7
6
5
4
3
2
1
0
Name
CP1EN
CP1OUT
R
CP1RIF
R/W
CP1FIF
R/W
CP1HYP[1:0]
R/W
CP1HYN[1:0]
R/W
R/W
0
Type
0
0
0
0
0
0
0
Reset
SFR Page= 0x0; SFR Address = 0x9A
Bit
Name
Function
7
CP1EN
Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
6
5
CP1OUT
CP1RIF
Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1
–
.
1: Voltage on CP1+ > CP1
–
.
Comparator1 Rising-Edge Flag. M
be cleared by software.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
4
CP1FIF
Comparator1 Falling-Edge
g. Must be cleared by software.
0: No Comparator1 Fall
g-Edge has occurred since this flag was last cleared.
1: Comparator1 Fal
-Edge has occurred.
3:2
CP1HYP[1:0]
Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positiv
Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 m
V
.
1:0
CP1HYN[1:0]
Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 m
V
.
109
Rev. 1.0
Si102x/3x
SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CP1RIE
R/W
CP1FIE
R/W
CP1MD[1:0]
R/W
R/W
1
R
0
R
0
R
0
0
0
1
0
SFR Page = 0x0; SFR Address = 0x9C
Bit
Name
Reserved Read
= 1b, Must Write 1b.
Function
7
6
Unused
Unused.
Read = 00b, Write = don’t care.
5
4
CP1RIE
Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enab
ed.
CP1FIE
Comparator1 Falling-Edge Interrupt
ble.
0: Comparator1 Falling-edge interrupt di
abled.
1: Comparator1 Falling-edge interrupt enabled.
3:2
1:0
Unused
Read = 00b, Write = don’t car
CP1MD[1:0]
Comparator1 Mode Sele
These bits affect the re
ponse time and power consumption for Comparator1.
00: Mode 0 (Fastest R
onse Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (S
owest Response Time, Lowest Power Consumption)
Rev. 1.0
110
Si102x/3x
7.6. Comparator0
and Comparator1 Analog Multiplexers
Comparator0 and Comparator1 on Si102x/3x devices have analog input multiplexers to connect port I/O
pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative input multiplex-
ers for Comparator0 and CP1+/CP1- are the positive and negative input multiplexers for Comparator1.
The comparator input multiplexers directly support capacitive sensors. When the Compare input is
selected on the positive or negative multiplexer, any Port I/O pin connected to the other multiplexer can
directly connected to a capacitive sensor with no additional external components. The Compare signal pro
vides the appropriate reference level for detecting when the capacitive sensor has charged or discharged
through the on-chip Rsense resistor. The Comparator0 output can be routed to Timer2 for capturing the
capacitor’s charge and discharge time. See Section “33. Timers” on page 483 for details.
Any of the following may be selected as comparator inputs: port I/O pins, capacitive tou
se compare,
VDD/DC+ supply voltage, regulated digital supply voltage (output of VREG0), the VBAT s
ply voltage or
ground. The comparator’s supply voltage divided by 2 is also available as an input; the resistors used to
divide the voltage only draw current when this setting is selected. The comparator input multiplexers are
configured using the CPT0MX and CPT1MX registers described in SFR Definition 7.5 and SFR Definition
7.6.
CPTnMX
P0.1
P0.3
P0.5
P1.5
P1.7
P2.1
P2.3
P0.0
P0.2
P0.4
P0.6
P1.4
P1.6
P2.0
P2.2
CPnOUT
Rse
CPnOUT
Rsense
Only enabled
Only
led when
Compare is selected
on CPn+ Input MUX.
when Compare is
selected on CPn-
Input MUX.
CPn-
nput
MUX
CPn+
Input
MUX
VBAT
VBAT CPnOUT
VBAT CPnOUT
R
R
R
R
Compare
(1/3 or 2/3) x VBAT
Compare
+
–
(1/3 or 2/3) x VBAT
R
R
VBAT
R
VBAT
R
GND
½ x VBAT
½ x VBAT
R
VBAT
VDC
R
Digital Supply
GND
Figure 7.4. CPn Multiplexer Block Diagram
mportant Note About Comparator Input Configuration:
Port pins selected as comparator inputs should
e configured as analog inputs, and should be skipped by the digital crossbar.
T
o
c
onfigure a port pin for
analog input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver
(PnMDOUT = 0 and Port Latch = 1).
T
o
f
orce the crossbar to skip a port pin, set to 1 the corresponding bit
in register PnSKI
P
.
S
ee Section “27. Port Input/Output” on page 351 for more port I/O configuration details.
Rev. 1.0
111
Si102x/3x
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select
Bit
7
6
5
4
3
2
1
0
CMX0N[3:0]
CMX0P[3:0]
Name
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
SFR Page = 0x0; SFR Address = 0x9F
Bit
Name
Function
7:4
CMX0N
Comparator0 Negative Input Selection.
Selects the negative input channel for Comparator0.
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
P0.1
1000:
1001:
1010:
1011:
1
0:
1101:
1110:
1111:
P
1
P0.3
P2.3
P0.5
Reserved
Reserved
Compare
Reserved
Reserved
Reserved
P1.5
VBAT divided by 2
Digital Supply Voltage
Ground
P1.7
3:0
CMX0P
Comparator0 Positive In
Selection.
Selects the positive input channel for Comparator0.
0000:
0001:
0010:
0011:
0:
0101:
0110:
0111:
P
0
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
P2.0
P0.2
P2.2
P0.4
Reserved
P0.6
Reserved
Reserved
Reserved
P1.4
Compare
VBAT divided by 2
VBAT Supply Voltage
VBAT Supply Voltage
P1.6
112
Rev. 1.0
Si102x/3x
SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select
Bit
7
6
5
4
3
2
1
0
CMX1N[3:0]
CMX1P[3:0]
Name
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
SFR Page = 0x0; SFR Address = 0x9E
Bit
Name
Function
7:4
CMX1N
Comparator1 Negative Input Selection.
Selects the negative input channel for Comparator1.
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
P0.1
1000:
1001:
1010:
1011:
1
0:
1101:
1110:
1111:
P
1
P0.3
P2.3
P0.5
Reserved
Reserved
Compare
Reserved
Reserved
Reserved
P1.5
VBAT divided by 2
Digital Supply Voltage
Ground
P1.7
3:0
CMX1P
Comparator1 Positive In
Selection.
Selects the positive input channel for Comparator1.
0000:
0001:
0010:
0011:
0:
0101:
0110:
0111:
P
0
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
P2.0
P0.2
P2.2
P0.4
Reserved
P0.6
Reserved
Reserved
Reserved
P1.4
Compare
VBAT divided by 2
VBAT Supply Voltage
VDC Supply Voltage
P1.6
Rev. 1.0
113
Si102x/3x
8. CIP-51
Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 35), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single in
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as wel
as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a bloc
diagram).
The CIP-51 includes the following features:
– Fully
Compatible with MCS-51 Instruction
Set
– Extended
Interrupt Handler
– Reset
Input
– 25
MIPS Peak Throughput with 25 MHz
Clock
– Power
Management Modes
– On-chip
Debug Logic
– 0
to 25 MHz Clock Frequency
– Program
and D
Memory Security
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum syste
ock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
ATA BUS
ACCUMULATOR
B
REGISTER
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
W
SRAM
ALU
DATA BUS
SFR_ADDRESS
SFR_CONTROL
D8
BUFFER
SFR
BUS
INTERFACE
D8
SFR_WRITE_DATA
SFR_READ_DATA
D8
DATA POINTER
PC INCREMENTER
D8
MEM_ADDRESS
MEM_CONTROL
PROGRAM COUNTER
(PC)
PRGM. ADDRESS REG.
PIPELINE
MEMORY
INTERFACE
A16
D8
MEM_WRITE_DATA
MEM_READ_DATA
CONTROL
LOGIC
RESET
CLOCK
SYSTEM_IRQs
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
STOP
IDLE
POWER CONTROL
REGISTER
D8
Figure 8.1. CIP-51 Block Diagram
Rev. 1.0
114
Si102x/3x
With the CIP-51’s maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Clocks to Execute
1
2
2/3
5
3
3/4
7
4
3
4/5
1
5
2
8
1
Number of Instructions
26
50
14
Programming and Debugging Support
In-system programming of the flash program memory and communication with on-chip de
ug s
pport logic
is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the sett
ng of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program’s call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requirin
no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “35. C2 Interface
on page 525.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE’s
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys-
tem device programming and debugging. Third party macro
mblers and C compilers are also avail-
able.
8.1. Instruction
Set
The instruction set of the CIP-51 System Controller is f
compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can
e used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional eq
alent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags.
wever, instruction timing is different than that of the stan-
dard 8051.
8.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined a
chitecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are
rogram bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete
the branch is not taken as opposed to when the branch is taken.
T
a
ble 8.1 is the
CIP-51 Instruc
ion Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
115
Rev. 1.0
Si102x/3x
Table 8.1. CIP-51 Instruction Set Summary
Description
Mnemonic
Bytes
Clock
Cycles
Arithmetic Operations
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
ADD A, Rn
1
2
1
2
1
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect
AM
Increment Data
inter
Multiply A and B
Divide A by B
Decim
djust A
DA A
Logical Operations
ANL A, Rn
ANL A, direct
ANL A, @Ri
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, di
ct
OR
@Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Rev. 1.0
116
Si102x/3x
Table 8.1. CIP-51 Instruction Set Summary
(Continued)
Mnemonic
Description
Bytes
Clock
Cycles
CLR A
CPL A
RL A
RLC A
RR A
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
Rotate A right through Carry
Swap nibbles of A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RRC A
SWAP A
Data Transfer
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
Move direct byte to Register
Move immediate to Register
Move A to direct byte
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to dire
te
Move A to indirect R
M
Move direct byte to
direct RAM
Move immedia
indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move
de byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
Boolean Manipulation
POP direct
XCH A, Rn
XCH A, dir
t
XCH
@
i
XC
A, @Ri
CLR C
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
1
2
1
2
1
2
2
1
2
1
2
1
2
2
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
117
Rev. 1.0
Si102x/3x
Table 8.1. CIP-51 Instruction Set Summary
(Continued)
Mnemonic
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
Description
Bytes
Clock
Cycles
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
2
2
2
2
2
2
2
3
3
2
2
2
2
2
2/3
2/3
3/4
3/4
3/4
Move Carry to direct bit
Jump if Carry is set
JNC rel
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Program Branching
JB bit, rel
JNB bit, rel
JBC bit, rel
ACALL addr11
LCALL addr16
RET
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not e
ual zero
Compare direct byte to A and jump if not equal
Compare imme
e to A and jump if not equal
Compare immediate to Register and jump if not
equal
2
3
1
1
2
3
2
1
2
2
3
3
3
4
5
5
3
4
3
3
2/3
2/3
3/4
3/4
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
3
3
3/4
4/5
Compa
immediate to indirect and jump if not
equal
DJNZ Rn, rel
DJNZ direct, rel
NOP
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
2
3
1
2/3
3/4
1
Rev. 1.0
118
Si102x/3x
Notes on Registers, Operands and Addressing Modes:
Rn
—Register R0–R7 of the currently selected register bank.
@Ri
—Data RAM location addressed indirectly through R0 or R1.
rel
—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct
—8-bit internal data location’s address. This could be a direct-access Data RAM
on (0x00–
0x7F) or an SFR (0x80–0xFF).
#data
—8-bit constant
#data16
—16-bit constant
bit
—Direct-accessed bit in Data RAM or SFR
addr11
—11-bit destination address used by ACALL and AJM
P
.
T
he destination must be within the
same 2 kB page of program memory as the first byte of the f
wing instruction.
addr16
—16-bit destination address used by LCALL and LJM
P
.
T
he destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that perfor
the same function as NO
P
.
All mnemonics copyrighted © Intel Corporati
n 1980.
119
Rev. 1.0
Si102x/3x
8.2. CIP-51
Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature’s default state. Detailed descriptions of
the remaining SFRs are included in the sections of the data sheet associated with their corresponding sys-
tem function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
Bit
7
6
5
4
3
2
0
DPL[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0x82
Bit
Name
Function
7:0
DPL[7:0]
Data Pointer Low.
The DPL register is the low byte of the 16
DPTR. DPTR is used to access indi-
rectly addressed flash memory or XRAM.
SFR Definition 8.2. DPH: Data Pointer High Byte
Bit
7
6
5
4
3
2
1
0
DPH[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0x83
Bit
Name
Function
7:0
DPH[7
0]
Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed flash memory or XRAM.
Rev. 1.0
120
Si102x/3x
SFR Definition 8.3. SP: Stack Pointer
Bit
7
6
5
4
3
2
1
0
SP[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
1
1
1
SFR Page = All Pages; SFR Address = 0x81
Bit
Name
Function
7:0
SP[7:0]
Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incre-
mented before every PUSH operation. The SP register d
aults to 0x07 after reset.
SFR Definition 8.4. ACC: Accumulator
Bit
7
6
5
4
3
2
1
0
A
C[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xE0; Bit-Addressable
Bit
Name
Function
7:0
ACC[7:0]
Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition
. B: B Register
Bit
7
6
5
4
3
2
1
0
B[7:0]
R/W
Na
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xF0; Bit-Addressable
Bit
Name
Function
7:0
B[7:0]
B Register.
This register serves as a second accumulator for certain arithmetic operations.
121
Rev. 1.0
Si102x/3x
SFR Definition 8.6. PSW: Program Status Word
Bit
7
6
5
4
3
2
1
0
CY
AC
F0
RS[1:0]
R/W
OV
F1
PARITY
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
0
0
SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable
Bit
Name
Function
7
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithm
c operations.
6
AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-
metic operations.
5
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3
RS[1:0]
Register Bank Select.
These bits select which registe
ank is used during register accesses.
00: Bank 0, Addresses 0x0
0x07
01: Bank 1, Addresses 0x0
x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addre
es 0x18-0x1F
2
OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
T
OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1
0
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY
Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
Rev. 1.0
122
Si102x/3x
9. Memory
Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
Si102x/3x device family is shown in Figure 9.1
PROGRAM/DATA MEMORY
(FLASH)
DATA MEMORY
(RAM)
INTERNAL DATA
ADDRESS SPAC
S1020/24/30/34
Upper 128 RAM
Special Function
Registers
0x1FFFF
128 kB FLASH
(Indirect Addressing Only)
(Direct Addressing Only)
0
(In-System
Programmable in 1024
Byte Sectors)
2
F
(Direct and Indirect
Addressing)
0x00000
0x0FFFF
Si1021/25/31/35
64 kB FLASH
Lower 128 RAM
(Direct and Indirect
Addressing)
General Purpose
Bit Addressable
(In-System
Programmable in 1024
Byte Sectors)
Registers
0x00000
0x07FFF
TERNAL DATA ADDRESS SPACE
Si1022/26/32/36
32 kB FLASH
020/1/2/4/5/6
Si1030/1/2/4/5/6
Si1023/27/33/37
(In-System
Programmable in 1024
Byte Sectors)
0xFFFF
0xFFFF
0x00000
0x03FFF
Off-chip XRAM space
(only on 76-pin package)
Off-chip XRAM space
(only on 76-pin package)
Si1023/27/33/37
16 kB FLASH
0x2000
0x1FFF
0x1000
0x0FFF
(In-System
Programmable in 1024
Byt
ctors)
XRAM – 8192 Bytes
(accessable using MOVX
instruction)
XRAM – 4096 Bytes
(accessable using MOVX
instruction)
0x00000
0x0000
0x0000
Figure 9.1. Si102x/3x Memory Map
9.1. Program
Memory
The Si1020/24/30/34 devices have a 128 kB program memory space, Si1021/25/31/35 devices have a
4 kB
program memory space, Si1022/26/32/36 devices have a 32
kB program memory space, and
Si1023/27/33/37 devices have a 16 kB program memory space. The devices with 128 kB program memory
space implement this flash as in-system re-programmable flash memory in four 32 kB code banks. A com-
mon code bank (Bank 0) of 32 kB is always accessible from addresses 0x0000 to 0x7FF
F
.
T
he upper code
banks (Bank 1, Bank 2, and Bank 3) are each mapped to addresses 0x8000 to 0xFFF
F
,
d
epending on the
selection of bits in the PSBANK register, as described in SFR Definition 9.1. All other devices with 64 kB or
Rev. 1.0
123
Si102x/3x
less of program memory can be used as non-banked devices.
The IFBANK bits select which of the upper banks are used for code execution, while the COBANK bits
select the bank to be used for direct writes and reads of the flash memory.
A note about code banking and the “MOVC A, @A+PC” opcode
: The MOVC A, @A+PC opcode uses
the COBANK bits to generate the effective address. Most compilers expect the reference from this instruc-
tion to be relative to the Program Counter, which uses the IFBANK bits to generate the effective addre
To
a
void incorrect device behavior, we recommend that IFBANK and COBANK be set to the same value i
systems that use (or may use) the “MOVC A, @A+PC” opcode.
The address 0x1FFFF (Si1020/24/30/34), 0xFFFF (Si1021/25/31/35), 0x07FFF (Si1022/2
2/36), or
0x3FFF (Si1023/27/33/37) serves as the security lock byte for the device. Any address
above the lock
byte are reserved.
Si1020/24/30/34
Si1022/26/32/36
Si1023/27/33/37
Si1021/25/31/35
0x1FFFF
Lock Byte
0x1FFFE
Lock Byte
Page
0x1FC00
0x1FBFF
0x0FFFF
Lock Byte
0x0FFFE
Lock Byte
Page
0x0FC00
0x0FBFF
0x
FFF
Lock Byte
Flash
Memory
Space
0x7FFE
Lock Byte
0x03FFF
Lock Byte
Flash
Memory
Space
0x07C00
0x07BFF
0x3FFE
Lock Byte
Page
Flash
Memory
Space
0x03C00
0x03BFF
Flash
Memory
Space
0x0000
0x
000
0x00000
0x00000
Figur
9.2. Flash Program Memory Map
124
Rev. 1.0
Si102x/3x
Internal
Address
IFBANK
=
0
Bank0
IFBANK
=
1
Bank1
IFBANK
=
2
Bank2
IFBANK
=
3
0 xFFFF
Bank3
0
x
8
000
0x
7
F
FF
Bank0
Bank0
Bank0
Bank0
0
x
0
000
Figure 9.3. Address Mem
y Map for Instruction Fetches
Rev. 1.0
125
Si102x/3x
SFR Definition 9.1. PSBANK: Program Space Bank Select
Bit
7
6
5
4
3
2
1
0
COBANK[1:0]
R/W R/W
IFBANK[1:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
0
1
SFR Page = All Pages; SFR Address = 0x84
Bit
Name
Function
7:6
Reserved
Read = 00b, Must Write = 00b.
5:4 COBANK[1:0]
Constant Operations Bank Select.
These bits select which flash bank is targeted during c
tant operations (MOVC
and flash MOVX) involving address 0x8000 to 0xFFF
F
.
00: Constant Operations
T
a
rget Bank 0 (note th
t Bank 0 is also mapped between
0x0000 to 0x7FFF).
01: Constant operations target Bank 1.
10: Constant operations target Bank 2.
11: Constant operations target Bank 3.
3:2
Reserved
Read = 00b, Must Write = 00b.
1:0 IFBANK[1:0]
Instruction Fetch Operations
k Select.
These bits select which fla
bank is used for instruction fetches involving address
0x8000 to 0xFFF
F
.
T
he
e b
ts can only be changed from code in Bank 0.
00: Instructions fetch f
Bank 0 (note that Bank 0 is also mapped between
0x0000 to 0x7FFF).
01: Instructions fetch from Bank 1.
10: Instruction
fetch from Bank 2.
11: Instructions fetch from Bank 3.
Note:
1.
COBANK[1:0] and IFBANK[1:0] should not be set to select any bank other than Bank 0 (00b) on the
Si1022/23/26/27/32/33/36/37 devices.
2.
COBANK[1:0] and IFBANK[1:0] should not be set to select Bank 2 (10b) or Bank 3 (11b) on the
Si1021/25/31
evices.
9.1.1. MOVX Instruction and Program Memory
The MOV
instruction in an 8051 device is typically used to access external data memory. On the
Si10
x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can be re-
confi
ured to write and erase on-chip flash memory space. MOVC instructions are always used to read
flash memory, while MOVX write instructions are used to erase and write flash. This flash access feature
provides a mechanism for the Si102x/3x to update program code and use the program memory space for
on-volatile data storage. Refer to Section “18. Flash Memory” on page 243 for further details.
9.2. Data
Memory
The Si102x/3x device family includes 8448 bytes (Si1020/21/22/25/26/27/30/31/35/36/37) or 4352 bytes
(Si1023/27/33/37) of RAM data memory. 256 bytes of this memory is mapped into the internal RAM space
of the 8051. 8192 or 4096 bytes of this memory is on-chip “external” memory. The data memory map is
shown in Figure 9.1 for reference.
126
Rev. 1.0
Si102x/3x
9.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xF
F
.
T
he
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2
F
,
m
ay either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F
etermines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. In
tions that use
direct addressing will access the SFR space. Instructions using indirect addressing abov
F access the
upper 128 bytes of data memory. Figure 9.1 illustrates the data memory organization of th
Si102x/3x.
9.2.1.1. General
Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1
F
,
m
ay be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers des
nated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
9.2.1.2. Bit
Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually
ddressable bits. Each bit has a bit address from
0x00 to 0x7
F
.
B
it 0 of the byte at 0x20 has bit addres
00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x
A bit access is distinguished from a full byte access by
the type of instruction used (bit source or de
ination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the
position within the byte. For example, the instruction:
MOV
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
9.2.1.3. Stack
A programmer’s stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Sta
Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is plac
t SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis-
ter (R0) of
ister bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a l
atio
in the data memory not being used for data storage. The stack depth can extend up to
256
es.
9.2.2. External RAM
There are 8192 bytes or 4096 bytes of on-chip RAM mapped into the external data memory space. All of
ese address locations may be accessed using the external move instruction (MOVX) and the data
pointer (DPTR), or using MOVX indirect addressing mode (such as @R1) in combination with the EMI0CN
register. Additional off-chip memory or memory-mapped devices may be mapped to the external memory
address space and accessed using the external memory interface. See Section “10. External Data Mem-
ory Interface and On-Chip XRAM” on page 128 for further details.
Rev. 1.0
127
Si102x/3x
10. External
Data Memory Interface and On-Chip XRAM
For Si102x/3x devices, 8 kB of RAM are included on-chip and mapped into the external data memory
space (XRAM). Additionally, an external memory interface (EMIF) is available on the Si102x/3x devices,
which can be used to access off-chip data memories and memory-mapped devices connected to the GPIO
ports. The external memory space may be accessed using the external move instruction (MOVX) and the
data pointer (DPTR), or using the MOVX indirect addressing mode using R0 or R1. If the MOVX instructi
is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provide
by the External Memory Interface Control Register (EMI0CN, shown in SFR Definition 10.1).
Note:
The MOVX instruction can also be used for writing to the flash memory. See Section “
18. Flash
mory
” on
page
243
for details. The MOVX instruction accesses XRAM by default.
10.1. Accessing
XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Po
nter, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The sec-
ond method uses R0 or R1 in combination with the EMI0CN register to
nerate the effective XRAM
address. Examples of both of these methods are given below.
10.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the v
ue of the byte at address 0x1234 into the
accumulator A:
MOV
MOVX
DPTR, #1234h
A, @DPTR
; load DPTR with 16-bit address to read (0x1234)
; load con
ts of 0x1234 into accumulator A
The above example uses the 16-bit immediate M
V instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR
gisters DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR
10.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instructi
uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV
MOV
MOVX
EMI0CN, #12h
R0, #34h
a,
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Rev. 1.0
128
Si102x/3x
10.2. Configuring
the External Memory Interface (EMIF)
Configuring the EMIF consists of five steps:
1. Configure the output modes of the associated port pins as either push-pull or open-drain (push-pull is
most common). The input mode of the associated port pins should be set to digital (reset value).
2. Configure port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic 1).
3. Select Multiplexed mode or Non-Multiplexed mode.
4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select,
or off-chip only).
5. Set up timing to interface with off-chip memory or peripherals.
Each of these five steps is explained in detail in the following sections. The port se
Multiplexed
mode selection, and mode bits are located in the EMI0CF register shown in SFR Definitio
10.3. Port
Configuration
The EMIF appears on Ports 3, 4, 5, and 6 when it is used for off-chip memory access. The EMIF and the
LCD cannot be used simultaneously. When using EMI
F
,
a
ll pins on Ports 3
may only be used for EMIF
purposes or as general purpose I/O. The EMIF pinout is shown in
T
a
ble 10.1 on page 130.
The EMIF claims the associated port pins for memory operations ONLY during the execution of an off-chip
MOVX instruction. Once the MOVX instruction has completed, control of the port pins reverts to the port
latches or to the crossbar settings for those pins. See Section “27. Port Input/Output” on page 351 for more
information about the crossbar and port operation and config
n.
The port latches should be explic-
itly configured to “park” the EMIF pins in a dormant state, most commonly by setting them to a
logic 1
.
During the execution of the MOVX instruction, the E
will explicitly disable the drivers on all port pins
that are acting as inputs (Data[7:0] during a RE
operation, for example). The output mode of the port
pins (whether the pin is configured as open-d
ain or push-pull) is unaffected by the EMIF operation, and
remains controlled by the PnMDOUT register
most cases, the output modes of all EMIF pins should be
configured for push-pull mode.
The Si102x/3x devices support both
e Multiplexed and Non-Multiplexed modes.
129
Rev. 1.0
Si102x/3x
Table 10.1. EMIF Pinout
Multiplexed Mode
Non Multiplexed Mode
Signal Name
Port Pin
8-Bit Mode
1
Signal Name
Port Pin
8-Bit Mode
1
P3.6
P3.7
P3.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
—
16-Bit Mode
2
P3.6
P3.7
P3.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P5.0
P5.1
P5.2
P5.
P5.4
P5.5
P5.6
P5.7
—
16-Bit Mode
2
P3.6
P3.7
P
.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
26
RD
WR
ALE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
RD
WR
D0
P3.6
P3.7
P6.0
P6.1
P6.2
P6.3
6.4
P6.5
P6.6
P6.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
—
D1
D2
D3
D4
D5
D6
D7
A1
A9
—
A2
A10
A11
A12
A13
A14
A15
—
—
A3
—
A4
—
A5
—
A6
—
A7
—
A8
—
A9
—
—
—
—
A10
A11
A12
A13
A14
A15
Required I/O:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Required I/O:
11
19
18
Notes:
1.
Using 8-bit movx instruction without bank select.
2.
Using 16-bit movx instruction.
Rev. 1.0
130
Si102x/3x
SFR Definition 10.1. EMI0CN: External Memory Interface Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PGSEL[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAA
Bit Name
7:0 PGSEL[7:0]
XRAM Page Select Bits.
Function
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page of
RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
…
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
131
Rev. 1.0
Si102x/3x
SFR Definition 10.2. EMI0CF: External Memory Configuration
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
EMD2
EMD[1:0]
EALE[1:0]
R/W
0
0
0
0
0
0
1
1
SFR Page = 0x0; SFR Address = 0xAB
Bit
7:5
4
Name
Unused
EMD2
Function
Read = 000b; Write = Don’t Care.
EMIF Multiplex Mode Select Bit.
0: EMIF operates in Multiplexed Address/Data mode
1: EMIF operates in Non-Multiplexed mode (separate ad
ess and data pins)
3:2 EMD[1:0]
EMIF Operating Mode Select Bits.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to
on-chip memory space
01: Split Mode without Bank Select: Access
s below the 8 kB boundary are directed
on-chip. Accesses above the 8 kB bounda
e directed off-chip. 8-bit off-chip MOVX
operations use current contents of the Address high port latches to resolve the upper
address byte.
T
o
a
ccess off chip space, EMI0CN must be set to a page that is not con-
tained in the on-chip address spa
10: Split Mode with Bank Sel
: Accesses below the 8 kB boundary are directed on-
chip. Accesses above the 8 kB boundary are directed off-chip. 8-bit off-chip MOVX
operations uses the cont
of EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to
the CPU.
1:0 EALE[1:0]
ALE Pulse-Widt
Select Bits.
These bits only have an effect when EMD2 = 0.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
ALE high and ALE low pulse width = 4 SYSCLK cycles.
Rev. 1.0
132
Si102x/3x
10.4. Multiplexed
and Non-Multiplexed Selection
The External Memory Interface is capable of acting in a Multiplexed mode or Non-Multiplexed mode,
depending on the state of the EMD2 (EMI0C
F
.
4) bit.
10.4.1. Multiplexed Configuration
In Multiplexed mode, the data bus and the lower 8 bits of the address bus share the same port pins:
AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8 b
of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is
driven by the EMIF logic. An example of a Multiplexed configuration is shown in Figure 10.1.
In Multiplexed mode, the external MOVX operation can be broken into two phases delineated
y the state
of the ALE signal. During the first phase, ALE is high and the lower 8 bits of the address
are presented
to AD[7:0]. During this phase, the address latch is configured such that the Q outputs r
the states of
the D inputs. When ALE falls, signaling the beginning of the second phase, the addre
latch outputs
remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the data bus con-
trols the state of the AD[7:0] port at the time RD or WR is asserted.
See Section “10.6.2. Multiplexed Mode” on page 141 for more information.
A[15:8]
ADDRESS BUS
74HC373
A[15:8]
A[7:0]
ALE
G
E
M
I
AD[7:0]
ADDRESS/DATA BUS
V
DD
D
Q
64 K X 8
SRAM
(Optional)
8
I/O[7:0]
F
CE
WE
OE
RD
Figure 10.1. Multiplexed Configuration Example
10.4.2. Non-Multiplexed Configuration
n Non-Multiplexed mode, the data bus and the address bus pins are not shared. An example of a non-
multiplexed configuration is shown in Figure
10.2. See Section “10.6.1.
Non-Multiplexed Mode” on
page 138 for more information about non-multiplexed operation.
133
Rev. 1.0
Si102x/3x
A[15:0]
D[7:0]
ADDRESS BUS
A[15:0]
E
M
I
V
DD
(Optional)
64 K X 8
SRA
I/O[7:
8
DATA BUS
CE
WE
OE
F
WR
RD
Figure 10.2. Non-Multiplexed Configuration Example
10.5. Memory
Mode Selection
The external data memory space can be configured in one of f
modes, shown in Figure 10.3, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 10.2). These modes are summarized below.
More information about the different modes can be fou
d in Section “10.6. Timing” on page 136.
EMI0CF[3:2] = 00
EMI0CF[3:2] = 01
EMI0CF[3:2] = 10
EMI0CF[3:2] = 11
0xFFFF
FFF
0xFFFF
0xFFFF
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On
XRAM
Off-C
Memory
(No Bank Select)
Off-Chip
Memory
(Bank Select)
Off-Chip
Memory
On-Chip XRAM
On-Chip XRAM
0x0000
0x0000
0x0000
0x0000
Figure 10.3. EMIF Operating Modes
Rev. 1.0
134
Si102x/3x
10.5.1. Internal XRAM Only
When bits EMI0CF[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the
device. Memory accesses to addresses beyond the populated space will wrap on 8 kB boundaries. As an
example, the addresses 0x2000 and 0x4000 both evaluate to address 0x0000 in on-chip XRAM space.
8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
10.5.2. Split Mode without Bank Select
When bit EMI0C
F
.
[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
Effective addresses below the internal XRAM size boundary will access on-chip XR
ce.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This al
s the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “Split Mode with Bank Select” described below. The lower 8
bits of the Address Bus A[7:0]
are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and unlike 8-bit MOVX operations, the full 16-bit
f the Address Bus A[15:0] are driven
during the off-chip transaction.
10.5.3. Split Mode with Bank Select
When EMI0CF[3:2] are set to 10, the XRAM memor
ap is split into two areas, on-chip space and off-
chip space.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XR
size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or off-chip. The upper 8-bits o
the Address Bus A[15:8] are determined by EMI0CN, and the lower
8-bits of the Address Bus A[7:0] a
e determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are
driven in “Bank Select” mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
10.5.4. External Only
When EMI0CF[3:2
set to 11, all MOVX operations are directed to off-chip space. On-chip XRAM is not
visible to the CPU.
is mode is useful for accessing off-chip memory located between 0x0000 and the
internal XRAM size boundary.
8-bit M
VX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven
(
ical behavior to an off-chip access in “Split Mode without Bank Select” described above). This
all
ws the user to manipulate the upper address bits at will by setting the Port state directly. The lower
8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full
16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
135
Rev. 1.0
Si102x/3x
10.6. Timing
The timing parameters of the EMIF can be configured to enable connection to devices having different
setup and hold time requirements. The address setup time, address hold time, RD and WR strobe widths,
and in Multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods
through EMI0TC, shown in SFR Definition 10.3, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timi
parameters defined by the EMI0TC register. Assuming Non-Multiplexed operation, the minimum executio
time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD or WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional
SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in Mul
iplexed
mode is 7 SYSCLK cycles (2 for /ALE + 1 for RD or WR + 4). The programmable se
d hold times
default to the maximum delay settings after a reset.
T
a
ble 10.2 lists the ac parameters
e EMI
F
,
a
nd
Figure 10.4 through Figure 10.9 show the timing diagrams for the different EMIF modes and MOVX opera-
tions.
Rev. 1.0
136
Si102x/3x
SFR Definition 10.3. EMI0TC: External Memory Timing Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
EAS[1:0]
R/W
EWR[3:0]
R/W
EAH[1:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xAF
Bit
Name
Function
7:6
EAS[1:0]
EMIF Address Setup Time Bits.
00: Address setup time = 0 SYSCLK cycles.
01: Address setup time = 1 SYSCLK cycle.
10: Address setup time = 2 SYSCLK cycles.
11: Address setup time = 3 SYSCLK cycles.
5:2 EWR[3:0]
EMIF WR and RD Pulse-Width Control Bits.
0000: WR and RD pulse width = 1 SYSCLK cycle.
0001: WR and RD pulse width = 2 SYSCL
ycles.
0010: WR and RD pulse width = 3 SYSCLK
ycles.
0011: WR and RD pulse width = 4 SYSCLK cycles.
0100: WR and RD pulse width =
YSCLK cycles.
0101: WR and RD pulse width = 6
YSCLK cycles.
0110: WR and RD pulse widt
= 7 SYSCLK cycles.
0111: WR and RD pulse
h = 8 SYSCLK cycles.
1000: WR and RD pulse width = 9 SYSCLK cycles.
1001: WR and RD pulse width = 10 SYSCLK cycles.
1010: WR and R
pulse width = 11 SYSCLK cycles.
1011: WR and RD pulse width = 12 SYSCLK cycles.
1100: WR and RD pulse width = 13 SYSCLK cycles.
1101: WR and RD pulse width = 14 SYSCLK cycles.
1110: WR and RD pulse width = 15 SYSCLK cycles.
1111: WR and RD pulse width = 16 SYSCLK cycles.
1:0
EAH[1:0]
IF Address Hold Time Bits.
00: Address hold time = 0 SYSCLK cycles.
01: Address hold time = 1 SYSCLK cycle.
10: Address hold time = 2 SYSCLK cycles.
11: Address hold time = 3 SYSCLK cycles.
137
Rev. 1.0
Si102x/3x
10.6.1. Non-Multiplexed Mode
10.6.1.1. 16-bit
MOVX: EMI0CF[4:2] = 101, 110, or 111
Nonmuxed 16-bit WRITE
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from DPL
EMIF WRITE DATA
T
T
WDS
WDH
T
T
T
ACS
ACW
A
WR
RD
Nonmu
ed 16-bit READ
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
P2
EMIF A
DRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from DPL
EMIF READ DATA
T
T
RDS
RDH
T
T
T
ACS
ACW
ACH
RD
WR
Figure 10.4. Non-Multiplexed 16-bit MOVX Timing
Rev. 1.0
138
Si102x/3x
10.6.1.2. 8-bit
MOVX without Bank Select: EMI0CF[4:2] = 101 or 111
Nonmuxed 8-bit WRITE without Bank Select
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
EMIF ADDRESS (8 LSBs) from R0 or R1
EMIF WRITE DATA
T
T
WDS
WDH
T
T
T
ACS
ACW
ACH
WR
RD
Nonmuxed 8-bit READ without Bank Select
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
EMIF
RESS (8 LSBs) from R0 or R1
EMIF READ DATA
T
T
RDS
RDH
T
T
T
ACS
ACW
ACH
RD
Figure 10.5. Non-Multiplexed 8-bit MOVX without Bank Select Timing
139
Rev. 1.0
Si102x/3x
10.6.1.3. 8-bit
MOVX with Bank Select: EMI0CF[4:2] = 110
Nonmuxed 8-bit WRITE with Bank Select
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from R0 or R1
EMIF WRITE DATA
T
T
WDS
WDH
T
T
T
ACS
ACW
ACH
WR
RD
Nonmuxed 8-bit READ w
h Bank Select
EMIF ADDRESS (8 MSBs) from EMI0CN
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
EMIF AD
ESS (8 LSBs) from R0 or R1
EMIF READ DATA
T
T
RDS
RDH
T
T
T
ACS
ACW
ACH
RD
WR
Figure 10.6. Non-Multiplexed 8-bit MOVX with Bank Select Timing
Rev. 1.0
140
Si102x/3x
10.6.2. Multiplexed Mode
10.6.2.1. 16-bit
MOVX: EMI0CF[4:2] = 001, 010, or 011
Muxed 16-bit WRITE
ADDR[15:8]
AD[7:0]
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from
DPL
EMIF WRITE DATA
T
T
ALEL
ALEH
ALE
T
T
WDH
WDS
T
T
T
ACH
ACS
ACW
WR
RD
Muxed 16-bit R
ADDR[15:8]
AD[7:0]
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from
DPL
EMIF READ DATA
T
T
AL
ALEH
T
T
RDH
RDS
ALE
T
T
T
ACH
ACS
ACW
RD
WR
Figure 10.7. Multiplexed 16-bit MOVX Timing
141
Rev. 1.0
Si102x/3x
10.6.2.2. 8-bit
MOVX without Bank Select: EMI0CF[4:2] = 001 or 011
Muxed 8-bit WRITE Without Bank Select
ADDR[15:8]
EMIF ADDRESS (8 LSBs) from
AD[7:0]
EMIF WRITE DATA
R0 or R1
T
T
ALEL
ALEH
ALE
T
T
WDH
WDS
T
T
T
ACH
ACS
ACW
WR
RD
Muxed 8-bit READ Without Bank Select
ADDR[15:8]
AD[7:0]
EMIF ADDRESS (8 LSBs) from
R0 or R1
EMIF READ DATA
T
T
ALEL
ALEH
T
T
RDH
RDS
ALE
T
T
T
ACH
ACS
ACW
RD
WR
Figu
e 10.8. Multiplexed 8-bit MOVX without Bank Select Timing
Rev. 1.0
142
Si102x/3x
10.6.2.3. 8-bit
MOVX with Bank Select: EMI0CF[4:2] = 010
Muxed 8-bit WRITE with Bank Select
ADDR[15:8]
AD[7:0]
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
EMIF WRITE DATA
T
T
ALEL
ALEH
ALE
T
T
WDH
WDS
T
T
T
ACH
ACS
ACW
WR
RD
Muxed 8-bit READ with Bank Select
EMIF ADDRESS (8 MSBs
EMI0CN
ADDR[15:8]
AD[7:0]
EMIF ADDRESS (8 LSBs) from
R0 or R1
EMIF READ DATA
T
T
ALEL
ALEH
T
T
RDH
RDS
ALE
T
T
T
ACH
ACS
ACW
RD
WR
Fi
re 10.9. Multiplexed 8-bit MOVX with Bank Select Timing
143
Rev. 1.0
Si102x/3x
Table 10.2. AC Parameters for External Memory Interface
Parameter
Description
Min*
Max*
3 x T
Units
T
Address/Control Setup Time
0
ns
ACS
SYSCLK
T
Address/Control Pulse Width
Address/Control Hold Time
Address Latch Enable High Time
Address Latch Enable Low Time
Write Data Setup Time
1 x T
16 x T
ns
ns
ns
ns
ns
ns
ns
ns
ACW
SYSCLK
SYSCLK
SYSCLK
SYSCL
LK
T
0
3 x T
4 x T
4 x
ACH
T
1 x T
1 x T
1 x T
ALEH
SYSCLK
SYSCLK
T
ALEL
T
19 x T
WDS
SYSCLK
S
CLK
3 x T
SYSCLK
T
Write Data Hold Time
0
WDH
T
T
Read Data Setup Time
20
0
RDS
Read Data Hold Time
RDH
*Note:
T
is equal to one period of the device system clock (SYSCLK).
SYSCLK
Rev. 1.0
144
Si102x/3x
11. Direct
Memory Access (DMA0)
An on-chip direct memory access (DMA0) is included on the Si102x/3x devices. The DMA0 subsystem
allows autonomous variable-length data transfers between XRAM and peripheral SFR registers without
CPU intervention. During DMA0 operation, the CPU is free to perform some other tasks. In order to save
total system power consumption, the CPU and flash can be powered down. DMA0 improves the system
performance and efficiency with high data throughput peripherals.
DMA0 contains seven independent channels, common control registers, and a DMA0 Engine (see
Figure 11.1). Each channel includes a register that assigns a peripheral to the channel, a channel control
register, and a set of SFRs that include XRAM address information and SFR address informa
n used by
the channel during a data transfer. The DMA0 architecture is described in detail in Sectio
1.1
The DMA0 in Si102x/3x devices supports four peripherals: AES0, ENC0, CRC1, and
Peripherals
with DMA0 capability should be configured to work with the DMA0 through their own registers. The DMA0
provides up to seven channels, and each channel can be configured for one of nine possible data transfer
functions:
XRAM to ENC0L/M/H
ENC0L/M/H SFRs to XRAM
XRAM to CRC1IN SFR
XRAM to SPI1DAT SFR
SPI1DAT SFR to XRAM
XRAM to AES0KIN SFR
XRAM to AES0BIN SFR
XRAM to AES0XIN SFR
AES0YOUT SFR to XRAM
The DMA0 subsystem signals the MCU through a set of interrupt service routine flags. Interrupts can be
generated when the DMA0 transfers half of t
ata length or full data length on any channel.
Rev. 1.0
145
Si102x/3x
Channel 6
Channel 1
Channel 0
Channel memory
interface config
Peripheral assignment –
DMA0nCF[2:0]
Channel
Control
DMA0nBAH
DMA0nBAL
DMA0nAOL
DMA0nSZL
XRAM to ENC0 request
ENC0 to XRAM request
XRAM to CRC1 request
XRAM to SPI1 request
DMA0nCF
DMA0nAOH
DMA0nSZH
SPI1 to XRAM request
MA
ENGINE
XRAM to AES0KIN request
XRAM to AES0BIN request
XRAM to
AES0XIN request
AES0YOUT
to XRAM request
DMA0nMD
Internal
DMA
bus
DMA0SEL
DMA0BUSY
DMA0MINT
DMA0INT
DMA0EN
Common
Control/
Status
control
Figure 11.1. DMA
ock Diagram
11.1. DMA0
Architecture
The first step in configuring a DMA0 channel is to select the desired channel for data transfer using DMA0-
SEL[2:0] bits (DMA0SEL). After setting the DMA0 channel, firmware can address channel-specific regis-
ters such as DMA0NC
F
,
D
MA0NB
/L, DMA0NAOH/L, and DMA0NSZH/L. Once firmware selects a
channel, the subsequent SFR configuration applies to the DMA0 transfer of that selected channel.
Each DMA0 channel consists of an SFR assigning the channel to a peripheral, a channel control register
and a set of SFRs that describe XRAM and SFR addresses to be used during data transfer (See
Figure 11.1). The peripheral assignment bits of DMA0nCF select one of the eight data transfer functions.
The selected channel can choose the desired function by writing to the PERIPH[2:0] bits (DMA0NCF[2:0]).
The control registe
MA0NCF of each channel configures the endian-ness of the data in XRAM, stall
enable, full-length interrupt enable and mid-point interrupt enable. When a channel is stalled by setting the
STALL bit (
MA0NC
F
.
5), DMA0 transfers in progress will not be aborted, but new DMA0 transfers will be
block
unt
the stall status of the channel is reset. After the stall bit is set, software should poll the corre-
spo
g DMA0BUSY to verify that there are no more DMA transfers for that channel.
The memory interface configuration SFRs of a channel define the linear region of XRAM involved in the
transfer through a 12-bit base address register DMA0NBAH:L, a 10-bit address offset register
MA0NAOH:L and a 10-bit data transfer size DMA0NSZH:L. The effective memory address is the address
involved in the current DMA0 transaction.
Effective Memory Address = Base Address + Address Offset
The address offset serves as byte counter. The address offset should be always less than data transfer
length. The address offset increments by one after each byte transferred. For DMA0 configuration of any
channel, address offsets of active channels should be reset to 0 before DMA0 transfers occur.
146
Rev. 1.0
Si102x/3x
Data transfer size DMA0NSZH:L defines the maximum number of bytes for the DMA0 transfer of the
selected channel. If the address offset reaches data transfer size, the full-length interrupt flag bit CHn_INT
(DMA0INT) of the selected channel will be asserted. Similarly, the mid-point interrupt flag bit CHn_MINT is
set when the address offset is equal to half of data transfer size if the transfer size is an even number or
when the address offset is equal to half of the transfer size plus one if the transfer size is an odd number.
Interrupt flags must be cleared by software so that the next DMA0 data transfer can proceed.
The DMA0 subsystem permits data transfer between SFR registers and XRAM. The DMA0 subsyste
executes its task based on settings of a channel’s control and memory interface configuration SFRs. When
data is copied from XRAM to SFR registers, it takes two cycles for DMA0 to read from XRAM and the SFR
write occurs in the second cycle. If more than one byte is involved, a pipeline is used. When d
is copied
from SFR registers to XRAM, the DMA0 only requires one cycle for one byte transaction.
The selected DMA0 channel for a peripheral should be enabled through the ena
its CHn_EN
(DMA0EN.n) to allow the DMA0 to transfer the data. When the DMA0 is transferring data on a channel, the
busy status bit of the channel CHn_BUSY (DMA0BUS
Y
.
n) is set. During the transaction, writes to
DMA0NSZH:L, DMA0NBAH:L, and DMA0NAOH:L are disabled.
Each peripheral is responsible for asserting the peripheral transfer requests
ecessary to service the par-
ticular peripheral. Some peripherals may have a complex state machine to manage the peripheral
requests. Please refer to the DMA enabled peripheral chapters for additional information (AES0, CRC1,
ENC0 and SPI1).
Besides reporting transaction status of a channel, DMA0BUSY can be used to force a DMA0 transfer on
an already configured channel by setting the CHn_BUSY bit (
0BUS
Y
.
n).
The DMA0NMD SFR has a wrap bit that supports address offset wrapping. The size register DMA0NSZ
sets the transfer size. Normally the address offset st
at zero and increases until it reaches size minus
one. At this point the transfer is complete and the int
upt bit will be set. When the wrap bit is set, the
address offset will automatically be reset to zero
d transfers will continue as long as the peripheral keeps
requesting data.
The wrap feature can be used to support key wrapping for the AES0 module. Normally the same key is
used over and over with additional data blocks. So the wrap bit should be set when using the XRAM to
AES0KIN request. This feature supp
ts multiple-block encryption operations.
11.2. DMA0
Arbitration
11.2.1. DMA0 Memory Access Arbitration
If both DMA0 and CPU attempt to access SFR register or XRAM at the same time, the CPU pre-empts the
DMA0 module. DMA0 will be stalled until CPU completes its bus activity.
11.2.2. DMA0 Cha
Arbitration
Multiple DMA0 channels can request transfer simultaneously, but only one DMA0 channel will be granted
the bus to t
sfer the data. Channel 0 has the highest priority. DMA0 channels are serviced based on their
priori
A higher priority channel is serviced first. Channel arbitration occurs at the end of the data transfer
gra
rity (transaction boundary) of the DMA. When there is a DMA0 request at the transaction boundary
from higher priority channel, lower priority ones will be stalled until the highest priority one completes its
transaction. So, for 16-bit transfers, the transaction boundary is at every 2 bytes.
1.3. DMA0
Operation in Low Power Modes
DMA0 remains functional in normal active, low power active, idle, low power idle modes but not in sleep or
suspend mode. CPU will wait for DMA0 to complete all pending requests before it enters sleep mode.
When the system wakes up from suspend or sleep mode to normal active mode, pending DMA0 interrupts
will be serviced according to priority of channels. DMA0 stalls when CPU is in debug mode.
Rev. 1.0
147
Si102x/3x
11.4. Transfer
Configuration
The following steps are required to configure one of the DMA0 channels for operation:
1. Select the channel to be configured by writing DMA0SEL.
2. Specify the data transfer function by writing DMA0NC
F
.
T
his register also specifies the endian-ness
of the data in XRAM and enables full or mid-point interrupts.
3. Configure the wrapping mode by writing to DMA0NMD. Setting this bit will automatically reset the
address offset after each completed transfer.
4. Specify the base address in XRAM for the transfer by writing DMA0NBAH:L.
5. Specify the size of the transfer in bytes by writing DMA0NSZH:L.
6. Reset the address offset counter by writing 0 to DMA0NAOH:L.
7. Enable the DMA0 channel by writing 1 to the appropriate bit in DMA0EN.
148
Rev. 1.0
Si102x/3x
SFR Definition 11.1. DMA0EN: DMA0 Channel Enable
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CH6_EN CH5_EN CH4_EN CH3_EN CH2_EN CH1_EN CH0_EN
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xD2
Bit
7
Name
Unused
CH6_EN
Function
Read = 0b, Write = Don’t Care
6
Channel 6 Enable.
0: Disable DMA0 channel 6.
1: Enable DMA0 channel 6.
5
4
3
2
1
0
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
Channel 5 Enable.
0: Disable DMA0 channel 5.
1: Enable DMA0 channel 5.
Channel 4 Enable.
0: Disable DMA0 chann
1: Enable DMA0 cha
nel 4.
Channel 3 Enab
e.
0: Disable DMA
annel 3.
1: Enable DMA0 channel 3.
Chann
2 Enable.
0: Disable DMA0 channel 2.
1: Enable DMA0 channel 2.
Channel 1 Enable.
0: Disable DMA0 channel 1.
1: Enable DMA0 channel 1.
Channel 0 Enable.
0: Disable DMA0 channel 0.
1: Enable DMA0 channel 0.
Rev. 1.0
149
Si102x/3x
SFR Definition 11.2. DMA0IN
T
:
D
MA0 Full-Length Interrupt
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CH6_INT CH5_INT CH4_INT CH3_INT CH2_INT CH1_INT CH0_INT
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xD3
Bit
7
Name
Unused
CH6_INT
Function
Read = 0b, Write = Don’t Care
1
6
Channel 6 Full-Length Interrupt Flag.
0: Full-length interrupt has not occurred on channel 6.
1: Full-length interrupt has not occurred on channel 6.
5
4
CH5_INT
CH4_INT
0: Full-length interrupt has not occurred on channel 5.
1: Full-length interrupt has not occurred on channel 5.
1
Channel 4 Full-Length Interrupt
lag.
0: Full-length interrupt has not occurred on channel 4.
1: Full-length interrupt h
ot occurred on channel 4.
1
3
2
1
0
CH3_INT
CH2_INT
CH1_INT
CH0_INT
Channel 3 Full-Len
th Interrupt Flag.
0: Full-length in
upt has not occurred on channel 3.
1: Full-length interrupt has not occurred on channel 3.
1
Chann
2 Full-Length Interrupt Flag.
0: Full-length interrupt has not occurred on channel 2.
1: Full-length interrupt has not occurred on channel 2.
1
Channel 1 Full-Length Interrupt Flag.
0: Full-length interrupt has not occurred on channel 1.
1: Full-length interrupt has not occurred on channel 1.
1
Channel 0 Full-Length Interrupt Flag.
0: Full-length interrupt has not occurred on channel 0.
1: Full-length interrupt has not occurred on channel 0.
Note
1.Full-length interrupt flag is set when the offset address DMA0NAOH/L is equal to the data transfer size
DMA0NSZH/L minus 1. This flag must be cleared by software or system reset. The full-length interrupt is
enabled by setting bit 7 of DMA0NCF with DMA0SEL configured for the corresponding channel.
150
Rev. 1.0
Si102x/3x
SFR Definition 11.3. DMA0MIN
T
:
D
MA0 Mid-Point Interrupt
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CH6_MINT CH5_MINT CH4_MINT CH3_MINT CH2_MINT CH1_MINT CH0_MIN
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xD4
Bit
7
Name
Unused
Function
Read = 0b, Write = Don’t Care
6
CH6_MINT
Channel 6 Mid-Point Interrupt Flag.
0: Mid-Point interrupt has not occurred on channel 6.
1: Mid-Point interrupt has not occurred on channel 6.
5
4
3
2
1
0
CH5_MINT
CH4_MINT
CH3_MINT
CH2_MINT
CH1_MINT
H0_MINT
Channel 5 Mid-Point Interrupt Flag.
0: Mid-Point interrupt has not occ
ed on channel 5.
1: Mid-Point interrupt has not occ
ed on channel 5.
Channel 4 Mid-Point Int
rrupt Flag.
0: Mid-Point interrupt ha
t occurred on channel 4.
1: Mid-Point interru
has not occurred on channel 4
.
Channel 3 Mid
nt Interrupt Flag.
0: Mid-Point interrupt has not occurred on channel 3.
1: Mid-P
int interrupt has not occurred on channel 3.
Channel 2 Mid-Point Interrupt Flag.
0: Mid-Point interrupt has not occurred on channel 2.
1: Mid-Point interrupt has not occurred on channel 2.
Channel 1 Mid-Point Interrupt Flag.
0: Mid-Point interrupt has not occurred on channel 1.
1: Mid-Point interrupt has not occurred on channel 1.
Channel 0 Mid-Point Interrupt Flag.
0: Mid-Point interrupt has not occurred on channel 0.
1: Mid-Point interrupt has not occurred on channel 0.
Note:
Mid-point Interrupt flag is set when the offset address DMA0NAOH/L equals half of the data transfer size
DMA0NSZH/L if the transfer size is an even number or half of data transfer size DMA0NSZH/L plus one if the
transfer size is an odd number. This flag must be cleared by software or system reset.The mid-point interrupt
is enabled by setting bit 6 of DMA0NCF with DMA0SEL configured for the corresponding channel.
Rev. 1.0
151
Si102x/3x
SFR Definition 11.4. DMA0BUSY: DMA0 Busy
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CH6_BUSY CH5_BUSY CH4_BUSY CH3_BUSY CH2_BUSY CH1_BUSY CH0_BUS
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xD5
Bit
7
Name
Description
Write
R
ad
Always Reads 0.
: DMA0 channel 6 Idle.
1: Force DMA0 transfer to
1: DMA0 transfer in prog-
Unused
No effect.
0: No effect.
6
CH6_BUSY
Channel 6 Busy.
CH5_BUSY
Channel 5 Busy.
CH4_BUSY
Channel 4 Busy.
CH3_BUSY
Channel 3 Busy.
CH2_BUSY
Channel 2 Busy.
CH1_BUSY
Channel 1 Busy.
CH0_BUSY
annel 0 Busy.
start on channel 6.
ress on channel 6.
5
4
3
2
1
0
0: No effect.
0: DMA0 channel 5 Idle.
1: Force DMA0 transfer to
1: DMA0 transfer in prog-
start on cha
l 5.
ress on channel 5.
0: No effect.
0: DMA0 channel 4 Idle.
1: F
rce DMA0 transfer to
1: DMA0 transfer in prog-
sta
channel 4.
ress on channel 4.
0: No effect.
0: DMA0 channel 3 Idle.
1: Force DMA0 transfer to
1: DMA0 transfer in prog-
start on channel 3.
ress on channel 3.
0: No effect.
0: DMA0 channel 2 Idle.
1: Force DMA0 transfer to
1: DMA0 transfer in prog-
start on channel 2.
ress on channel 2.
0: No effect.
0: DMA0 channel 1 Idle.
1: Force DMA0 transfer to
1: DMA0 transfer in prog-
start on channel 1.
ress on channel 1.
0: No effect.
0: DMA0 channel 0 Idle.
1: Force DMA0 transfer to
1: DMA0 transfer in prog-
start on channel 0.
ress on channel 0.
152
Rev. 1.0
Si102x/3x
SFR Definition 11.5. DMA0SEL: DMA0 Channel Select for Configuration
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
DMA0SEL[2:0]
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Page = 0x2; SFR Address = 0xD1
Bit
7:3
2:0
Name
Unused
Function
Read = 0b, Write = Don’t Care
DMA0SEL[2:0]
Channel Select for Configuration.
These bits select the channel for configuration o
the DMA0 transfer. The
first step to configure a channel for DMA0 tran
fer is to select the desired
channel, and then write to channel specific registers DMA0NC
F
,
DMA0NBAL/H, DMA0NAOL/H, DMA0NSZL/H.
000: Select channel 0
001: Select channel 1
010: Select channel 2
011: Select channel 3
100: Select channel 4
101: Select channe
110: Select chan
el 6
111: Invalid
SFR Definition 11.6. DMA0NMD: DMA Channel Mode
Bit
7
6
5
4
3
2
1
0
WRAP
R/W
0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR
ge = 0x2; SFR Address = 0xD6
Rev. 1.0
153
Si102x/3x
Bit
7:1
0
Name
reserved
WRAP
Function
Read = 0, Write = 0
Wrap Enable.
Setting this bit will enable wrapping.
The DMA0NSZ register sets the transfer size. Normally the DMA0AO valu
starts at zero in increases to the DMANSZ minus one. At this point the trans-
fer is complete and the interrupt bit will be set. If the WRAP bit is set, the
DMA0NAO will be reset to zero.
Note:
This Sfr is a DMA channel indirect register. Select the desired first using the DMA0SEL S
154
Rev. 1.0
Si102x/3x
SFR Definition 11.7. DMA0NCF: DMA Channel Configuration
Bit
7
INTEN
R/W
0
6
MINTEN
R/W
0
5
STALL
R/W
0
4
ENDIAN
R/W
0
3
2
1
0
Name
Type
Reset
PERIPH[3:0]
R/W
R
0
0
0
0
SFR Page = 0x2; SFR Address = 0xC9
Bit
Name
Function
7
INTEN
Full-Length Interrupt Enable.
0: Disable the full-length interrupt of the selected channel.
1: Enable the full-length interrupt of the selecte
channel.
6
5
MINTEN
STALL
Mid-Point Interrupt Enable.
0: Disable the mid-point interrupt of the selected channel.
1: Enable the mid-point interrupt of the selected channel.
DMA0 Stall.
Setting this bit stalls the DMA0 transfer on the selected channel. After a
Stall, this bit must be clea
ed by software to resume normal operation.
0: The DMA0 transfer of
selected channel is not being stalled.
1: The DMA0 transf
of the selected channel is stalled.
4
ENDIAN
Data Transfer
ianness.
This bit sets the byte order for multi-byte transfers. This is only relevant for
two or three byte transfers. The value of this bit does not matter for single
byte tr
fers.
0: Little Endian
1: Big Endian
3:0
PERIPH[2:0]
Peripheral Selection of The Selected Channel.
These bits choose one of the nine DMA0 transfer functions for the selected
channel.
0000: XRAM to ENC0L/M/H
0001: ENC0L/M/H SFRs to XRAM
0010: XRAM to CRC1IN SFR
0011: XRAM to SPI1DAT SFR
0100: SPI1DAT SFR to XRAM
0101: XRAM to AES0KIN SFR
0110: XRAM to AES0BIN SFR
0111: XRAM to AES0XIN SFR
1000: AES0YOUT SFR to XRAM
Note:
This sfr is a DMA channel indirect register. Select the desired first using the DMA0SEL SFR.
Rev. 1.0
155
Si102x/3x
SFR Definition 11.8. DMA0NBAH: Memory Base Address High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
NBAH[3:0]
R/W
R
0
R
0
R
0
R
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xCB
Bit
7:4
3:0
Name
Unused
Function
Read = 0b, Write = Don’t Care
Memory Base Address High Byte.
NBAH[3:0]
Sets high byte of the memory base address whi
h is the DMA0 XRAM start-
ing address of the selected channel if the channel’s address offset
DMA0NAO is reset to 0.
Note:
This sfr is a DMA channel indirect register. Select the desired first using the DMA0SEL SFR.
SFR Definition 11.9. DMA0NBAL: Memory Base Address Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
NBAH[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xCA
Bit
Name
Function
7:0
NBAL[7:0]
Memory Base Address Low Byte.
Sets low byte of the memory base address which is the DMA0 XRAM start-
ing address of the selected channel if the channel’s address offset
DMA0NAO is reset to 0.
Note
his sfr is a DMA channel indirect register. Select the desired first using the DMA0SEL SFR.
156
Rev. 1.0
Si102x/3x
SFR Definition 11.10. DMA0NAOH: Memory Address Offset High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
NAOH[1:0]
R/W
R
0
R
0
R
0
R
0
R
0
R
0
0
0
SFR Page = 0x2; SFR Address = 0xCD
Bit
7:2
1:0
Name
Unused
Function
Read = 0b, Write = Don’t Care
Memory Address Offset High Byte.
NAOH[1:0]
Sets the high byte of the address offset of the se
ected channel which acts a
counter during DMA0 transfer. The address of
set auto-increments by one
after one byte is transferred. When configuring a channel for DMA0 transfer,
the address offset should be reset to 0.
Note:
This sfr is a DMA channel indirect register. Select the desired
using the DMA0SEL SFR.
SFR Definition 11.11. DMA0NAOL: Memor
ddress Offset Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
NACL[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xCC
Bit
Name
Function
Memory Address Offset Low Byte.
7:0
NACL
Sets the low byte of the address offset of the selected channel which acts a
counter during DMA0 transfer. The address offset auto-increments by one
after one byte is transferred. When configuring a channel for DMA0 transfer,
the address offset should be reset to 0.
Note:
This sfr is a DMA channel indirect register. Select the desired first using the DMA0SEL SFR.
Rev. 1.0
157
Si102x/3x
SFR Definition 11.12. DMA0NSZH: Transfer Size High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
NSZH[1:0]
R/W
R
0
R
0
R
0
R
0
R
0
R
0
0
0
SFR Page = 0x2; SFR Address = 0xCF
Bit
7:2
1:0
Name
Unused
Function
Read = 0b, Write = Don’t Care
NSZH[1:0]
Transfer Size High Byte.
Sets high byte of DMA0 transfer size of the sele
ted channel. Transfer size
sets the maximum number of bytes for the DMA0 transfer. When the
address offset is equal to the transfer size, a full-length interrupt is gener-
ated on the channel.
Note:
This sfr is a DMA channel indirect register. Select the desired
using the DMA0SEL SFR.
SFR Definition 11.13. DMA0NSZL: Memor
ransfer Size Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
NSZL[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xCE
Bit
Name
Function
Memory Transfer Size Low Byte.
7:0
NSZL
Sets low byte of DMA0 transfer size of the selected channel. Transfer size
sets the maximum number of bytes for the DMA0 transfer. When the
address offset is equal to the transfer size, a full-length interrupt is gener-
ated on the channel.
Note:
This sfr is a DMA channel indirect register. Select the desired first using the DMA0SEL SFR.
158
Rev. 1.0
Si102x/3x
12. Cyclic
Redundancy Check Unit (CRC0)
Si102x/3x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or
32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts the 16-
bit or 32-bit result to an internal register. The internal result register may be accessed indirectly using the
CRC0PNT bits and CRC0DAT register, as shown in Figure 12.1. CRC0 also has a bit reverse register for
quick data manipulation.
8
8
Automatic CRC
Controller
Flash
Memo
y
CRC0IN
CRC0AUTO
C
C0CNT
CRC0SEL
CRC0INIT
CRC0VAL
CRC0PNT1
CRC0PNT0
CRC Engine
32
RESULT
CRC0FLIP
Write
8
8
8
8
4 to 1 MUX
8
CRC0DAT
CRC0FLIP
Read
Figure 12.1. CRC0 Block Diagram
12.1. 16-bit
CRC Algorithm
The CRC0 unit calculates the 16-bit CRC MSB-first, using a poly of 0x1021. The following describes the
16-bit CRC algorithm performed by the hardware:
1. XOR the most-significant byte of the current CRC result with the input byte. If this is the first iteration
of the CRC unit, the current CRC result will be the set initial value (0x0000 or 0xFFFF).
a. If
the MS
the CRC result is set, left-shift the CRC result, and then XOR the CRC result with
the polynomial (0x1021).
b. I
e MSB of the CRC result is not set, left-shift the CRC result.
2
peat at Step 2a for the number of input bits (8).
Rev. 1.0
159
Si102x/3x
The 16-bit Si102x/3x CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input)
{
unsigned char i;
// loop counter
#define POLY 0x1021
// Create the CRC “dividend” for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ (CRC_input << 8);
// “Divide” the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the “remainder” of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY c
“divide”
// into the “dividend”)
if ((CRC_acc & 0x8000) == 0x8000)
{
// if so, shift the CRC value, and XOR “subtract” the poly
CRC_acc = CRC_acc << 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc << 1;
}
}
// Return the final remainder (CRC value)
return CRC_acc;
}
The following table lists several input values and the associated outputs using the 16-bit CRC algorithm:
Table 12.1. Example 16-bit CRC Outputs
Input
Output
0x63
0x8C
0x7D
0xBD35
0xB1F4
0x4ECA
0x6CF6
0xB166
0xAA, 0xBB, 0xCC
0x00, 0x00, 0xAA, 0xBB, 0xCC
160
Rev. 1.0
Si102x/3x
12.2. 32-bit
CRC Algorithm
The CRC0 unit calculates the 32-bit CRC using a poly of 0x04C11DB7. The CRC-32 algorithm is reflected,
meaning that all of the input bytes and the final 32-bit output are bit-reversed in the processing engine. The
following is a description of a simplified CRC algorithm that produces results identical to the hardware:
Step 1.
XOR the least-significant byte of the current CRC result with the input byte. If this is the
first iteration of the CRC unit, the current CRC result will be the set initial value
(0x00000000 or 0xFFFFFFFF).
Step 2.
Right-shift the CRC result.
Step 3.
If the LSB of the CRC result is set, XOR the CRC result with the reflected pol
omial
(0xEDB88320).
Step 4.
Repeat at Step 2 for the number of input bits (8).
For example, the 32-bit CRC algorithm can be described by the following code:
unsigned long UpdateCRC (unsigned long CRC_acc, unsigned char C
_input)
{
unsigned char i; // loop counter
#define POLY 0xEDB88320 // bit-reversed version of the poly 0x04C11DB7
// Create the CRC “dividend” for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ CRC_input;
// “Divide” the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the “remainder” of each
ide
//
// Only complete this division for 8
its since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can “divide”
// into the “dividend”)
if ((CRC_acc & 0x0000000
) == 0x00000001)
{
// if so, shift the CRC value, and XOR “subtract” the poly
CRC_acc = CRC_acc >> 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc >> 1;
}
/
Return the final remainder (CRC value)
return CRC_acc;
}
he following table lists several input values and the associated outputs using the 32-bit CRC algorithm
(an initial value of 0xFFFFFFFF is used):
Rev. 1.0
161
Si102x/3x
Table 12.2. Example 32-bit CRC Outputs
Input
0x63
Output
0xF9462090
0x41B207B3
0x78D129BC
0xAA, 0xBB, 0xCC
0x00, 0x00, 0xAA, 0xBB, 0xCC
12.3. Preparing
for a CRC Calculation
To
p
repare CRC0 for a CRC calculation, software should select the desired polynomial and s
t the initial
value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7
. The CRC0
result may be initialized to one of two values: 0x00000000 or 0xFFFFFFF
F
.
T
he follow
steps can be
used to initialize CRC0.
1. Select
a polynomial (Set CRC0SEL to 0 for 32-bit or 1 for 16-bit).
2. Select
the initial result value (Set CRC0VAL to 0 for 0x00000000
1 for 0xFFFFFFFF).
3. Set
the result to its initial value (Write 1 to CRC0INIT).
12.4. Performing
a CRC Calculation
Once CRC0 is initialized, the input data stream is sequentially written to CRC0IN, one byte at a time. The
CRC0 result is automatically updated after each byte is written. The CRC engine may also be configured to
automatically perform a CRC on one or more flash sectors. T
ollowing steps can be used to automati-
cally perform a CRC on flash memory.
1. Prepare
CRC0 for a CRC calculation as s
wn above.
2. If
necessary, set the IFBANK bits in the P
NK for the desired code bank.
3. Write
the index of the starting page t
RC0AUTO.
4. Set
the AUTOEN bit in CRC0AUT
.
5. Write
the number of flash sector
erform in the CRC calculation to CRC0CN
T
.
Note: Each flash sector is 1024 bytes.
6. Write
any value to CRC0CN (or OR its contents with 0x00) to initiate the CRC calculation. The
CPU will not execute co
e any additional code until the CRC operation completes.
7. Clear
the AUTOEN bit in CRC0AUTO.
8. Read
the CRC result using the procedure below.
Setting the IFBANK bits in the PSBANK SFR is only necessary when accessing the upper banks on
128 kB code bank devices (Si1020/24/30/34). Multiple CRCs are required to cover the entire 128 kB flash
array. When writing to the PSBANK SFR, the code initiating the auto CRC of flash must be executing from
the common area.
12.5. Accessing
the CRC0 Result
The intern
CRC0 result is 32-bits (CRC0SEL = 0b) or 16-bits (CRC0SEL = 1b). The CRC0PNT bits
sele
e byte that is targeted by read and write operations on CRC0DAT and increment after each read or
write
The calculation result will remain in the internal CR0 result register until it is set, overwritten, or addi-
tional data is written to CRC0IN.
162
Rev. 1.0
Si102x/3x
SFR Definition 12.1. CRC0CN: CRC0 Control
Bit
7
6
5
4
3
2
1
0
CRC0SEL CRC0INIT CRC0VAL
CRC0PNT[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Page = 0xF; SFR Address = 0x92
Bit
7:5
4
Name
Function
Unused
Read = 000b; Write = Don’t Care.
CRC0SEL
CRC0 Polynomial Select Bit.
This bit selects the CRC0 polynomial and result lengt
(32-bit or 16-bit).
0: CRC0 uses the 32-bit polynomial 0x04C11DB7 for calculating the CRC result.
1: CRC0 uses the 16-bit polynomial 0x1021 for calculating the CRC result.
3
2
CRC0INIT
CRC0VAL
CRC0 Result Initialization Bit.
Writing a 1 to this bit initializes the enti
RC result based on CRC0VAL.
CRC0 Set Value Initialization Bit.
This bit selects the set value of
he CRC result.
0: CRC result is set to 0x0000
0 on write of 1 to CRC0INI
T
.
1: CRC result is set to 0xF
FFFFFF on write of 1 to CRC0INI
T
.
1:0 CRC0PNT[1:0]
CRC0 Result Pointe
Specifies the byte of the CRC result to be read/written on the next access to
CRC0DA
T
.
T
he value of these bits will auto-increment upon each read or write.
For CRC0SE
= 0:
00: CRC0DAT accesses bits 7–0 of the 32-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 32-bit CRC result.
10: CRC0DAT accesses bits 23–16 of the 32-bit CRC result.
11: CRC0DAT accesses bits 31–24 of the 32-bit CRC result.
For CRC0SEL = 1:
00: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
10: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
11: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
Rev. 1.0
163
Si102x/3x
SFR Definition 12.2. CRC0IN: CRC0 Data Input
Bit
7
6
5
4
3
2
1
0
CRC0IN[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x93
Bit Name
7:0 CRC0IN[7:0]
CRC0 Data Input.
Function
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described
Section 12.1
SFR Definition 12.3. CRC0DA
T
:
C
RC0 Data Output
Bit
7
6
5
4
3
2
1
0
CRC
DAT[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x91
Bit Name
7:0 CRC0DAT[7:0]
CRC0 Data Output.
Function
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
164
Rev. 1.0
Si102x/3x
SFR Definition 12.4. CRC0AUTO: CRC0 Automatic Control
Bit
7
6
5
4
3
2
1
0
AUTOEN CRCDONE
CRC0ST[5:0]
Name
Type
Reset
R/W
0
R/W
0
0
1
0
0
0
0
SFR Page = 0xF; SFR Address = 0x96
Bit
Name
Function
7
AUTOEN
Automatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at flash sector CRC0ST and continuing for C
0CNT sectors.
6
CRCDONE
CRCDONE Automatic CRC Calculation Complete.
Set to 0 when a CRC calculation is in progress. Note that code execution is
stopped during a CRC calculation, therefore reads from firmware will always
return 1.
5:0 CRC0ST[5:0]
Automatic CRC Calculation Star
ing
sh Sector.
These bits specify the flash sector to start the automatic CRC calculation. The
starting address of the first fla
sector included in the automatic CRC calculation
is CRC0ST x 1024. For 128 kB
evices, pages 32–63 access the upper code
bank as selected by the I
BANK bits in the PSBANK SFR.
SFR Definition 12.5. CRC0CN
T
:
C
RC0 Automatic Flash Sector Count
Bit
7
6
5
4
3
2
1
0
CRC0CNT[5:0]
Name
Type
Reset
R/W
0
R/W
0
0
0
0
0
0
0
SFR Page =
xF; SFR Address = 0x97
Bit
ame
Function
7:6
Unused
Read = 00b; Write = Don’t Care.
5:0 CRC0CNT[5:0]
Automatic CRC Calculation Flash Sector Count.
These bits specify the number of flash sectors to include in an automatic CRC cal-
culation. The starting address of the last flash sector included in the automatic
CRC calculation is (CRC0ST+CRC0CNT) x 1024. The last page should not
exceed page 63. Setting both CRC0ST and CRC0CNT to 0 will perform a CRC
over the 64kB banked memory space.
Rev. 1.0
165
Si102x/3x
12.6. CRC0
Bit Reverse Feature
CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 12.2. Each byte
of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 is written to CRC0FLI
P
,
t
he
data read back is 0x03. Bit reversal is a useful mathematical function used in algorithms such as the FF
T
.
CRC0FLIP
Write
CRC0FLIP
Read
Figure 12.2. Bit Reverse Register
SFR Definition 12.6. CRC0FLIP: CRC0 Bit
ip
Bit
7
6
5
4
3
2
1
0
CRC0FLIP[7:0]
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x95
Bit Name
7:0 CRC0FLIP[7:0]
CRC0 Bit Flip.
Function
Any byte written to CRC0FLIP is read back in a bit-reversed order, i.e. the written
LSB becomes the MSB. For example:
If 0xC0 is written to CRC0FLI
P
,
t
he data read back will be 0x03.
If 0x05 is written to CRC0FLI
P
,
t
he data read back will be 0xA0.
166
Rev. 1.0
Si102x/3x
13. DMA-Enabled
Cyclic Redundancy Check Module (CRC1)
Si102x/3x devices include a DMA-enabled cyclic redundancy check module (CRC1) that can perform a
CRC of data using an arbitrary 16-bit polynomial. This peripheral can compute CRC results using direct
DMA access to data in XRAM.
Using a DMA transfer provides much higher data throughput than using SFR access. Since the CPU ca
be in Idle mode while the CRC is calculated, CRC1 also provides substantial power savings. The CR
module is not restricted to a limited list of fixed polynomials. Instead, the user can specify any valid 16-bit
polynomial.
CRC1 accepts a stream of 8-bit data written to the CRC1IN register. A DMA transfer can be us
d to auton-
omously transfer data from XRAM to the CRC1IN SFR. The CRC1 module may also
ed with SFR
access by writing directly to the CRC1IN SFR. After each byte is written, the CRC resul
updated on
the CRC1OUTH:L SFRs. After writing all data bytes, the final CRC results are available from the
CRC1OUTH:L registers. The final results may be flipped or inverted using the FLIP and INV bits in the
CRC1CN SFR. The initial seed value can be reset to 0x0000 or seeded with 0xFFF
F
.
13.1. Polynomial
Specification
The arbitrary polynomial should be written to the CRC1POLH:L SFRs before writing data to the CRCIN
SFR.
16
0
A valid 16-bit CRC polynomial must have an x
term and an x
term. Theoretically, a 16-bit polynomial
might have 17 terms total. However, the polynomial SFR is o
16-bits wide. The convention used is to
16
omit the x
term. The polynomial should be written in big endian bit order. The most significant bit corre-
15
sponds to the highest order term. Thus, the most signi
icant bit in the CRC1POLH SFR represents the x
0
term, and the least significant bit in the CRC1POLL S
epresents the x
term. The least significant bit of
CRC1POLL should always be set to one. The CR
results are undefined if this bit is cleared to a zero.
16
12
5
Figure 13.1 depicts the polynomial represen
on for the CRC-16-CCIT polynomial x
+ x
+ x + 1, or
0x1021.
CRC1POLH:L
= 0x1021
CRC1POLH
CRC1POLL
7
0
6
0
5
0
4
1
3
0
2
0
1
0
0
0
7
0
6
0
5
1
4
0
3
0
2
0
1
0
0
1
1
x
16
+
x
12
+
x
5
+
1
Figure 13.1. Polynomial Representation
Rev. 1.0
167
Si102x/3x
13.2. Endianness
The CRC1 module is optimized to process big endian data. Data written to the CRC1IN SFR should be in
the normal bit order with the most significant bit stored in bit 7 and the least significant bit stored in bit 0.
The input data is shifted left into the CRC engine. The CRC1 module will process one byte at a time and
update the results for each byte. When used with the DMA, the first byte to be written should be stored in
the lowest address.
Some communications systems may transmit data least significant bit first and may require calculation of
CRC in the transmission bit order. In this case, the bits must be flipped, using the CRC0FLIP SFR, before
writing to the CRC1IN SFR. The final 16-bit result may be flipped using the flip bit in the CRC1CN SFR.
Note that the polynomial is always written in big endian bit order.
168
Rev. 1.0
Si102x/3x
13.3. CRC
Seed Value
Normally, the initial value or the CRC results is cleared to 0x0000. However, a CRC might be specified with
an initial value preset to all ones (0xFFFF).
The steps to preset the CRC with all ones is as follows:
1. Set the SEED bit to 1.
2. Reset the CRC1 module by setting the CLR bit to 1 in CRC1CN.
3. Clear the SEED bit to 0.
The CRC1 module is not ready to calculate a CRC using a CRC seed value of 0xFFF
F
.
13.4. Inverting
the Final Value
Sometimes it is necessary to invert the final value. This will take the ones complement o
inal result.
The steps to flip the final CRC results are as follows:
1. Clear the CRC module by setting the CLR bit in CRC1CN SFR.
2. Write the polynomial to CRC1POLH:L.
3. Write all data bytes to CRC1IN.
4. Set the INV bit in the CRC1CN SFR to invert the final results.
5. Read the final CRC results from CRC1OUTH:L.
Clear the FLIP bit in the CRC1CN SFR.
13.5. Flipping
the Final Value
The steps to flip the final CRC results are as follows:
1. Clear the CRC module by setting the CLR bit in
C1CN SFR.
2. Write the polynomial to CRC1POLH:L.
3. Write all data bytes to CRC1IN.
4. Set the FLIP bit in the CRC1CN SFR to
the final results.
5. Read the final CRC results from CRC1OUTH:L.
6. Clear the FLIP bit in the CRC1
N SFR.
The flip operation will exchange bit 15 with bit 0, bit 14 with bit 1, bit 13 with bit 2, and so on.
Rev. 1.0
169
Si102x/3x
13.6. Using
CRC1 with SFR Access
The steps to perform a CRC using SFR access with the CRC1 module is as follow:
1. If desired, set the SEED bit in the CRC1CN SFR to seed with 0xFFF
F
.
2. Clear the CRC module by setting the CLR bit in the CRC1CN SFR.
3. Clear the SEED bit, if set previously in step 1.
4. Write the polynomial to CRC1POLH:L.
5. Write all data bytes to CRC1IN.
6. If desired, invert and/or flip the final results using the INV and FLIP bits.
7. Read the final CRC results from CRC1OUTH:L.
8. Clear the INV and/or FLIP bits, if set previously in step 6.
Note that all of the CRC1 SFRs are on SFR page 0x2.
13.7. Using
the CRC1 module with the DMA
The steps to computing a CRC using the DMA are as follows.
1. If desired, set the SEED bit in CRC1CN to seed with 0xFFF
F
.
2. Clear the CRC module by setting the CLR bit in CRC1CN SFR.
3. Clear the SEED bit, if set previously in step 1.
4. Write the polynomial to CRC1POLH:L.
5. Configure the DMA for the CRC operation:
a. Disable
the desired DMA channel by cleari
he corresponding bit in DMA0EN.
b. Select
the desired DMA channel by writi
g to DMA0SEL.
c. Configure
the selected DMA channel to use the CRC1IN peripheral request by writing 0x2 to
DMA0NC
F
.
d. Enable
the DMA interrupt on the selected channel by setting bit 7 of DMA0NC
F
.
e. Write
0 to DMA0NMD to di
ble wrapping.
f. Write
the address of the first byte of CRC data to DMA0NBAH:L.
g. Write
the size of the CRC data in bytes to DMA0NSZH:L.
h. Clear
the address offset SFRs DMA0A0H:L.
i. Enable
the interrupt on the desired channel by setting the corresponding bit in DMA0IN
T
.
j. Enable
th
desired channel by setting the corresponding bit in DMA0EN.
k. Enable
D
interrupts by setting bit 5 of EIE2.
6. Set the DMA mode bit (bit 3) in the CRC1CN SFR to initiate the CRC operation.
7. Wait
n the DMA interrupt.
desired, invert and/or flip the final results using the INV and FLIP bits.
9. Read the final results from CRC1OUTH:L.
10. Clear the INV and/or FLIP bits, if set previously in step 8.
170
Rev. 1.0
Si102x/3x
SFR Definition 13.1. CRC1CN: CRC1 Control
Bit
7
6
5
4
3
2
1
0
CLR
DMA
FLIP
INV
SEED
Name
Type
Reset
R/W
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xBE; Not Bit-Addressable
Bit
Name
Function
7
RST
Reset.
Setting this bit to 1 will reset the CRC module and set the CRC results SFR to
the seed value as specified by the SEED bit. The CRC module should be reset
before starting a new CRC.
This bit is self-clearing.
6:4
3
Reserved
DMA
DMA Mode.
Setting this bit will configure the CRC
module for DMA mode.
Once a DMA channel has been confi
ed to use accept peripheral requests
from CRC1, setting this bit will initiate a DMA CRC operation.
This bit should be cleared af
each CRC DMA transfer.
2
1
0
FLIP
INV
Flip.
Setting this bit will flip th
contents of the 16-bit CRC result SFRs.
(CRC0OUTH:CRC
TL)
This operation is nor
ally performed only on the final CRC results.
This bit should be cleared before starting a new CRC computation.
Invert.
Setting this bit will invert the contents of the 16-bit CRC result SFR.
(CRC0OUTH:CRC0OUTL)
This operation is normally performed only on the final CRC results.
This bit should be cleared before starting a new CRC computation.
SEED
Seed Polarity.
If this bit is zero, a seed value or 0x0000 will be used.
If this bit is 1, a seed value of 0xFFFF will be used.
This bit should be set before setting the RST bit.
Rev. 1.0
171
Si102x/3x
SFR Definition 13.2. CRC1IN: CRC1 Data IN
Bit
7
6
5
4
3
2
1
0
CRC1IN[7:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xB9; Not Bit-Addressable
Bit
Name
Function
7:0
CRC1IN[7:0]
CRC1Data IN.
CRC Data should be sequentially written, one byte at a time, to the CRC1IN
Data input SFR.
When the CRC1 module is used with the DMA, the DMA will write directly to this
SFR.
SFR Definition 13.3. CRC1POLL: CRC1 Polynom
LSB
Bit
7
6
5
4
3
2
1
0
C1POLL[7:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0x
C; Not Bit-Addressable
Bit Name
7:0 CRC1POLL[7:0]
Function
CRC1 Polynomial LSB.
SFR Definition
4. CRC1POLH: CRC1 Polynomial MSB
Bit
7
6
5
4
3
2
1
0
CRC1POLH[7:0]
Na
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xBD; Not Bit-Addressable
Bit Name
7:0 CRC1POLH[7:0]
Function
CRC1 Polynomial MSB.
172
Rev. 1.0
Si102x/3x
SFR Definition 13.5. CRC1OUTL: CRC1 Output LSB
Bit
7
6
5
4
3
2
1
0
CRC1OUTL[7:0]
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SFR Page = 0x2; SFR Address = 0xBA; Not Bit-Addressable
Bit Name
7:0 CRC1OUTL[7:0]
Function
CRC1 Output LSB
SFR Definition 13.6. CRC1OUTH: CRC1 Output MSB
Bit
7
6
5
4
3
2
1
0
CRC1OUTH
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SFR Page = 0x2; SFR Address = 0xBB; Not Bit-Addressable
Bit Name
7:0 CRC1OUTH[7:0]
Function
CRC1 Output MSB.
Rev. 1.0
173
Si102x/3x
14. Advanced
Encryption Standard (AES) Peripheral
The Si102x/3x devices include a hardware implementation of the Advanced Encryption Standard Block
Cipher as specified in NIST publication FIPS 197 “Advanced Encryption Standard (AES), November 2001.
The Rijndael encryption algorithm was chosen by NIST for the AES block cipher. The AES block cipher
can be used to encrypt data for wireless communications. Data can be encrypted before transmission and
decrypted upon reception. This provides security for private networks.
The AES block cipher is a Symmetric key encryption algorithm. Symmetric Key encryption relies on secret
keys that are known by both the sender and receiver. The decryption key may be obtained using a simple
transformation of the encryption key. AES is not a public key encryption algorithm.
The AES block Cipher uses a fixed 16 byte block size. So data less than 16 bytes m
padded with
zeros to fill the entire block. Wireless data must be padded and transmitted in 16-byte
s. The entire
16-byte block must be transmitted to successfully decrypt the information.
The AES engine supports key lengths of 128-bits, 192-bits, or 256-bits. A key size of 128-bits is sufficient
to protect the confidentiality of classified secret information. The Advanced Encryption Standard was
designed to be secure for at least 20 to 30 years. The 128-bit key provides f
stest encryption. The 192-bit
and 256-bit key lengths may be used to protect highly sensitive classified top secret information.
Since symmetric key encryption relies on secret keys, the security of the data can only be protected if the
key remains secret. If the encryption key is stored in flash memory, then the entire flash should be locked
to ensure the encryption key cannot be discovered. (See flash
ecurity.)
The basic AES block cipher is implemented in hardware. This h
rdware accelerator provides performance
that may be 1000 times faster than a software implementation. The higher performance translates to a
power savings for low-power wireless applications.
The AES block cipher, or block cipher modes b
d on the AES block cipher, is used in many wireless
standards. These include several IEEE standards in the wireless PAN (802.15) and wireless LAN (802.11)
working groups.
Rev. 1.0
174
Si102x/3x
14.1. Hardware
Description
AES0BIN
internal state
machine
AES0XIN
+
AES0DCF
Data In
AES
Core
Key
In
Key
Out
AES0KIN
Data Out
AES0BCFG
+
AES0YOUT
Figure 14.1. AES Peripheral Block Diagram
The AES Encryption module consists of the following elements:
AES Encryption/Decryption Core
Configuration SF
s
Key input SFR
Data SFRs
Input M
iplexer
ut Multiplexer
In
ut Exclusive OR block
Output Exclusive OR block
Internal State Machine
175
Rev. 1.0
Si102x/3x
14.1.1. AES Encryption/Decryption Core
The AES Encryption/Decryption Core is a digital implementation of the Advanced Encryption Standard
block cipher. The core may be used for either encryption or decryption. Encryption may be selected by set-
ting bit 5 in the AES0BCFG SFR. When configured for encryption, plaintext is written to the AES Core data
input and the encrypted ciphertext is read from the Data Output. Conversely, when configured for Decryp-
tion, encrypted ciphertext is written to the data input and decrypted plaintext is read form the Data Output.
When configured for Encryption, the encryption key must be written to the Key Input. When configured f
decryption, the decryption key must be written to the Key Input.
The AES core may also be used to generate a decryption key from a known encryption key.
T
o
enerate a
decryption key, the core must be configured for encryption, the encryption key is written to th
Key Input,
and the Decryption Key may be read from the Key output.
AES is a symmetric key encryption algorithm. This means that the decryption key may be
enerated from
an encryption key using a simple algorithm. Both keys must remain secret. If security of the encryption key
is compromised, one can easily generate the decryption key.
Since it is easy to generate the decryption key, only the encryption key may
stored in flash memory.
14.1.2. Data SFRs
The data SFRs are used for the data flow into and out of the AES module. When used with the DMA, the
DMA itself will write to and read from the data SFRs. When used in manual mode, the data must be written
to the data SFRs one byte at a time in the proper sequence.
The AES0KIN SFR provides a data path for the AES core Key input. For an encryption operation, the
encryption key is written to the AES0KIN SFR, either by the DMA or direct SFR access. For a decryption
operation, the decryption key must be written to the A
0KIN SFR.
The AES0BIN is the direct data input SFR for the
ES block. For a simple encryption operation, the plain-
text is written to the AES0BIN SFR – either b
the DMA or direct SFR access. For decryption, the cipher-
text to be decrypted is written to the AES0
SFR. The AES0BIN SFR is also used together with the
AES0XIN when an exclusive OR operation is required on the input data path.
The AES0XIN SFR provides an input
ata path to the exclusive OR operator. The AES0XIN is not used for
simple AES block cipher encryption or decryption. It is only use for block cipher modes that require an
exclusive OR operator on the input or output data.
The AES core requires that the input data bytes are written in a specific order. When used with the DMA,
this is managed by the internal state machine. When using direct SFR access, each of input data must be
written one byte at a time to each SFR in this particular order.
1. Write AES0B
2. Write AES0XIN (optional)
3. Write
S0KIN
This
uence is repeated 16 times. When using a 192-bit or 256-bit key length, the remaining additional
key
tes are written after writing all sixteen of the AES0BIN and AES0XIN bytes.
After encryption or decryption is completed, the resulting data may be read from the AES0YOU
T
.
O
ption-
ally, exclusive OR data may be written to the AES0XIN SFR before reading the AES0YOUT SFR.
1. Write AES0XIN (optional)
2. Read AES0YOUT
Rev. 1.0
176
Si102x/3x
14.1.3. Configuration SFRs
The AES Module has two configuration SFRs. The AES0BCFG SFR is used to configure the AES core.
Bits 0 and 1 are used to select the key size. The AES core supports 128-bit, 192-bit and 256-bit encryption.
Bit 2 selects encrypt or decrypt. The AES enable bit (bit 3) is used to enable the AES module and start new
encryption operation. The AES DONE bit (bit 5) is the AES interrupt flag that signals a block of data has
been completely encrypted or decrypted and is ready to be read from the AES0YOUT SFR. Note that the
AES DONE interrupt is not normally used when the AES module is used with the DMA. Instead, the DM
interrupt is used to signal that the encrypted or decrypted data has been transferred completely to memory.
The DMA done interrupt is normally only used with direct SFR access.
The AES0DCFG SFR is used to select the data path for the AES module. Bits 0 through 2
e used to
select the input and output multiplexer configuration. The AES data path should be confi
d prior to initi-
ating a new encryption or decryption operation.
14.1.4. Input Multiplexer
The input multiplexer is used to select either the contents of the AES0BIN SFR or the contents of the
AES0BIN SFR exclusive ORed with the contents of the AES0XIN SFR. The exclus
ve OR input data path
provides support for CBC encryption.
14.1.5. Output Multiplexer
The output multiplexer selects the data source for the AES0YOUT SFR. The three possible sources are
the AES Core data output, the AES core key output, and the AES core data output exclusive ORed with
the AES0XIN SFR.
The AES core data output is used for simple encryption and decryption.
The exclusive OR output data path provides support
r CBC mode decryption and CTR mode encryp-
tion/decryption. The AES0XIN is the source for bo
nput and output exclusive OR data. When the
AES0XIN is used with the input exclusive OR d
path, the AEXIN data is written in sequence with the
AES0BIN data. When used with the output X
O data path, the AES0XIN data is written after the encryp-
tion or decryption operation is complete.
The Key output is used to generate an inverse key.
T
o
g
enerate a decryption key from an encryption key,
the AES core should be configured
r an encryption operation.
T
o
g
enerate an encryption key from a
decryption key, the AES core should be configured for a decryption operation.
14.1.6. Internal State Machine
The AES module has an internal state machine that manages the data flow. The internal state machine
accommodates the two different usage scenarios. When using the DMA, the internal state machine will
send peripheral requests to the DMA requesting the DMA to transfer data from XRAM to the AES module
input SFRs. Upon
completion of one block of data, the AES module will send peripheral requests
requesting data to be transferred from the AES0YOUT SFR to XRAM. These peripheral requests are man-
aged by the internal state machine.
When
ot using the DMA, data must be written and read in a specific order. The DMA state machine will
adv
e with each byte written or read.
The internal state machine may be reset by clearing the enable bit in the AESBGFG SFR. Clearing the
enable bit before encryption or decryption operation will ensure that the state machine starts at the proper
ate.
When encrypting or decrypting multiple blocks it is not necessary to disable the AES module between
blocks, as long as the proper sequence of events is obeyed.
177
Rev. 1.0
Si102x/3x
14.2. Key
Inversion
The key output is used to generate an inverse key.
T
o
g
enerate a decryption key from an encryption key,
the AES core should be configured for an encryption operation. Dummy data and the encryption key are
written to the AES0BIN and AES0KIN SFRs respectively. The output multiplexer should be configured to
output the decryption key to the AES0YOUT SFR.
AES0BIN
internal state
machine
AES0XIN
+
AES0DCFG
Data In
AES
Core
Key
In
Key
Out
AES0KIN
Data Out
AES0BCFG
+
AES0YOUT
Figure 14.2. Key Inversion Data Flow
The dummy data may be zeros or arbitrary data. The content of the dummy data does not matter. But six-
teen bytes
data must be written to the AES0BIN SFR to generate the inverse key.
Rev. 1.0
178
Si102x/3x
14.2.1. Key Inversion using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are listed here for completeness.
Steps to generate the Decryption Key from Encryption Key
Prepare encryption key and dummy data in XRAM.
Reset AES module by clearing bit 3 of AES0BCF
G
.
Disable the first three DMA channels by clearing bits 0 to 2 in the DMA0EN SFR.
Configure the first DMA channel for the AES0KIN SFR.
Select the first DMA channel by writing 0x00 to the DMA0SEL SFR.
Configure the first DMA channel to move XRAM to AES0KIN by writing 0x05 to DMA0NC
F
.
Clear DMA0NMD to disable wrapping.
Write the XRAM address of the encryption key to the DMA0NBAH and DMA0NBAL SFRs.
Write the key length in bytes to the DMA0NSZL SFR.
Clear DMA0NSZH
Clear DMA0NAOH and DMA0NAOL.
Configure the second DMA channel for the AES0BIN SFR.
Select the second DMA channel by writing 0x01 to the DMA0SEL SFR.
Configure the second DMA channel to move xram to AES0BIN SFR by writing 0x06 to the DMA0NCF SFR.
Clear DMA0NMD to disable wrapping.
Write the xram address of dummy data to the DMA0NBAH and
A0NBAL SFRs.
Write 0x10 (16) to DMA0NSZL.
Clear DMA0NSZH
Clear DMA0NAOH and DMA0NAOL
Configure the third DMA channel for the AES
OUT SFR.
Select the third DMA channel by writing 0x02
o the DMA0SEL SFR.
Configure the third DMA channel to move t
ntents of the AES0YOUT SFR to XRAM by writing 0x08 to the
DMA0NCF SFR.
Enable transfer complete interrupt by setting bit 7 of the DMA0NCF SFR.
Clear DMA0NMD to disable wrap
g.
Write the XRAM address for the decryption key to DMA0NBAH and DMA0NBAL.
Write the key length in bytes to the DMA0NSZL SFR.
Clear DMA0NSZH.
Clear DMA0NAOH and DMA0NAOL.
Clear first three DMA interrupts by clearing bits 0 to 2 in the DMA0INT SFR.
Enable first thre
MA channels setting bits 0 to 2 in the DMA0EN SFR.
Configure the AES module data flow for inverse key generation by writing 0x04 to the AES0DCFG
SFR.
Write ke
size to bits 1 and 0 of AES0BCF
G
.
igure the AES core for encryption by setting bit 2 of AES0BCF
G
.
Initiate the encryption operation by setting bit 3 of AES0BCF
G
.
Wait on the DMA interrupt from DMA channel 2.
Disable the AES module by clearing bit 2 of AES0BCF
G
.
Disable the DMA by writing 0x00 to DMA0EN.
179
Rev. 1.0
Si102x/3x
The key and data to be encrypted should be stored as an array with the first byte to be encrypted at the
lowest address. The value of the big endian bit of the DMACF0 SFR does not matter. The AES block uses
only one byte transfers, so there is no particular endianness associated with a one byte transfer.
The dummy data can be zeros or any value. The encrypted data is discarded, so the value of the dummy
data does not mater.
It is not strictly required to use DMA channels 0, 1, and 2. Any three DMA channels may be used. T
internal state machine of the AES module will send the peripheral requests in the required order.
If the other DMA channels are going to be used concurrently with encryption, then only the bits corre-
sponding to the encryption channels should be manipulated in DM0AEN and DMA0NT
SFR
s.
14.2.2. Key Inversion using SFRs
Normally, the AES block is used with the DMA. This provides the best performance and l
st power con-
sumption. However, it is also possible to use the DMA with direct SFR access. The steps are documented
in the data sheet for completeness.
Steps to generate the decryption key from the encryption key using SFR acce
follow:
First configure the AES block for key inversion:
Reset AES module by writing 0x00 to AES0BCF
G
.
Configure the AES Module data flow for inverse key generation by writing 0x04 to the AES0DCFG SFR.
Write key size to bits 1 and 0 of AES0BCF
G
.
Configure the AES core for encryption by setting bit 2 of AES0
G
.
Enable the AES core by setting bit 3 of AES0BCF
G
.
Write the dummy data alternating with key data:
Write the first dummy byte to AES0BIN
Write the first key byte to AES0KIN
Repeat until all dummy data bytes are written
If using 192-bit and 256-bit key, write rem
ng key bytes to AES0KIN:
Wait on AES done interrupt or poll bit 5 of A
S0BCFG
Read first byte of the decryption key from the AES0YOUT SFR.
Rev. 1.0
180
Si102x/3x
14.2.3. Extended Key Output Byte Order
When using a key length of 128-bits, the key output is in the same order as the bytes were written. When
using an extended key of 192-bits or 256-bits. The extended portion of the key comes out first, before the
first 16-bytes of the extended key.This is illustrated in
T
a
ble 14.1.
Table 14.1. Extended Key Output Byte Order
Size
Bytes
Input
Output
Order
Bits
128
192
256
Order
16
24
32
K0…15
K0…15
K0…15
K0…15
K0…23
K0…31
K16…23
K24…31
K16…23
181
Rev. 1.0
Si102x/3x
14.2.4. Using the DMA to unwrap the extended Key
When used with the DMA, the address offset SFR DMANAOH/L may be manipulated to store the extended
key in the desired order. This requires two DMA transfers for the AES0YOUT channel. When using a 192-
bit key, the DMA0NSZ can be set to 24 bytes and the DMA0NA0 set to 16. This will place the last 8 bytes
of the 192-bit key in the desired location as shown in
T
a
ble 14.2. The Yout arrow indicates the address off-
set position after each 8 bytes are transferred. Enabling the WRAP bit in DMA0NMD will reset the
DMA0NAO value after byte 23. Then the DMA0NZ can be reset to 16 for the remaining sixteen bytes.
Table 14.2. 192-Bit Key DMA Usage
Y
o
ut
Y
o
ut
K16…23
Y
o
ut
K0…7
K0…7
K16…23
out
K16…23
K8…15
When using a 256-bit key, DMA0NSZ can be set to 32
nd DMA0NAOL set to 16 This will place the last 16
bytes of the 256-bit key in the desired location a
own in
T
a
ble
14.3. Enabling the WRAP bit in
DMA0NMD will reset the DMA0NAO value after b
e 31. Then DMA0NZ can be set to 16 for the remaining
sixteen bytes.
Table 14.3. 256-bit Key DMA Usage
?
Y
o
ut
Y
o
ut
K16…23
Y
o
ut
K16…23
K16…23
K24…31
K24…31
K24…31
Y
o
ut
K0…7
K0…7
Y
o
ut
K16…23
K8…15
Rev. 1.0
182
Si102x/3x
14.3. AES
Block Cipher
The basic AES Block Cipher is the basic encryption/decryption algorithm as defined by the NIST standard.
A clock cipher mode is a method of encrypting and decrypting one block of data. The input data and output
data are not manipulated, chained, or exclusive ORed with other data. This simple block cipher mode is
sometimes called the Electronic Code Book (ECB) mode. This mode is illustrated in Figure 14.3
Each operation represents one block (sixteen bytes) of data. The plaintext is the plain unencrypted da
The ciphertext is the encrypted data. The encryption key and decryption keys are symmetric. The decryp
tion key is the inverse key of the decryption key. Note that the Encryption operation is not the same as the
decryption operation. The two operations are different and the AES core operates differently depending on
whether encryption or decryption is selected.
Note that each encryption or decryption operation is independent of other operations.
note that the
same key is used over and over again for each operation.
183
Rev. 1.0
Si102x/3x
14.4. AES
Block Cipher Data Flow
The AES0 module data flow for AES Block Cipher encryption and decryption shown in Figure 14.3. The
data flow is the same for encryption and decryption. The AES0DCF SFR is always configured to route the
AES core output to AES0YOU
T
.
T
he XOR on the input and output paths are not used.
For an encryption operation, the core is configured for an encryption cipher, the encryption key is written to
AES0KIN, the plaintext is written to the AES0BIN
SFR
. and the ciphertext is read from AES0YOU
T
.
For a decryption operation, the core is configured for an decryption cipher, the decryption key is written t
AES0KIN, the ciphertext is written to the AES0BIN
SFR
. and the plaintext is read from AES0YOU
T
.
The key size is set to the desired key size.
AES0BIN
internal state
machine
AES0XIN
+
AES0DCFG
Data In
ES
Core
Key
In
Key
Out
AES0KIN
Data Out
AES0BCFG
+
AES0YOUT
Figure 14.3. AES Block Cipher Data Flow
Rev. 1.0
184
Si102x/3x
14.4.1. AES Block Cipher Encryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are listed here for completeness.
Steps to encrypt data using Simple AES block encryption (ECB mode)
Prepare encryption Key and data to be encrypted in xram.
Reset AES module by clearing bit 2 of AES0BCF
G
.
Disable the first three DMA channels by clearing bits 0 to 2 in the DMA0EN SFR.
Configure the first DMA channel for the AES0KIN SFR.
Select the first DMA channel by writing 0x00 to DMA0SEL
Configure the second DMA channel to move XRAM to the AES0KIN SFR by writing 0x05 to
A0NCF SFR.
Write 0x01 to DMA0NMD to enable wrapping
Write the XRAM location of the encryption key to the DMA0NBAH and DMA0NBAL SFRs.
Write the key length in bytes to the DMA0NSZL SFR.
Clear the DMA0NSZH SFR.
Clear the DMA0NAOH and DMA0NAOL SFRs.
Configure the second DMA channel for the AES0BIN SFR.
Select the second DMA channel by writing 0x01 to the DMA0SEL SFR.
Configure the second DMA channel to move XRAM to the AES0BIN SFR by writing 0x06 to the DMA0NCF SFR.
Clear DMA0NMD to disable wrapping.
Write the XRAM address of the data to be encrypted to the DM
BAH and DMA0NBAL SFRs.
Write the number of bytes to be encrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL SFRs.
Clear the DMA0NAOH and DMA0NAOL SFRs.
Configure the third DMA channel for the AES0YO
FR.
Select the third DMA channel by writing 0x02 to
DMA0SEL SFR.
Configure the third DMA channel to move the contents of the AES0YOUT SFR to XRAM by writing 0x08 to the
DMA0NCF SFR.
Enable transfer complete interrupt by setting bit 7 of the DMA0NCF SFR.
Clear DMA0NMD to disable wrapping.
Write the XRAM address for the e
rypted data to the DMA0NBAH and DMA0NBAL SFRs.
Write the number of bytes to be encrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL SFRs.
Clear DMA0NAOH and DMA0NAOL.
Clear first three DMA interrupts by clearing bits 0 to 2 in the DMA0INT SFR.
Enable first three DMA channels by setting bits 0 to 2 in the DMA0EN SFR.
Configure the AES module data flow for AES Block Cipher by writing 0x00 to AES0DCF
G
.
Write key size t
1 and 0 of the AES0BCFG SFR.
Configure the AES core for encryption by setting bit 2 of AES0BCF
G
.
Initiate t
encryption operation be setting bit 3 of AES0BCFG
W
on the DMA interrupt from DMA channel 2.
D
able the AES module by clearing bit 2 of AES0BCF
G
.
Disable the DMA by writing 0x00 to DMA0EN.
185
Rev. 1.0
Si102x/3x
14.4.2. AES Block Cipher Encryption using SFRs
First Configure AES module for AES Block Cipher
Reset AES module by writing 0x00 to AES0BCF
G
.
Configure the AES module data flow for AES Block Cipher by writing 0x00 to AES0DCF
G
.
Write key size to bits 1 and 0 of AES0BCF
G
.
Configure the AES core for encryption by setting bit 2 of AES0BCF
G
.
Enable the AES core by setting bit 3 of AES0BCF
G
.
Repeat alternating write sequence 16 times
Write plaintext byte to AES0BIN.
Write encryption key byte to AES0KIN.
Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit encryption
.
Wait on AES done interrupt or poll bit 5 of AES0BCF
G
.
Read 16 encrypted bytes from the AES0YOUT SFR.
If encrypting multiple blocks, this process may be repeated. It is not necessary reconfigure the AES mod-
ule for each block.
Rev. 1.0
186
Si102x/3x
14.5. AES
Block Cipher Decryption
14.5.1. AES Block Cipher Decryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are listed here for completeness.
Prepare decryption key and data to be decryption in XRAM.
Reset AES module by clearing bit 2 of AES0BCF
G
.
Disable the first three DMA channels by clearing bits 0 to 2 in DMA0EN.
Configure the first DMA channel for AES0KIN
Select the first DMA channel by writing 0x00 to DMA0SEL
Configure the first DMA channel to move XRAM to AES0KIN by writing 0x05 to DMA0NCF
Write 0x01 to DMA0NMD to enable wrapping
Write the XRAM location of the decryption key to DMA0NBAH and DMA0NBAL.
Write the key length in bytes to DMA0NSZL
Clear DMA0NSZH
Clear DMA0NAOH and DMA0NAOL.
Configure the second DMA channel for AES0BIN.
Select the second DMA channel by writing 0x01 to DMA0SEL.
Configure the second DMA channel to move XRAM to AES0BIN by writing 0x06 to DMA0NC
F
.
Clear DMA0NMD to disable wrapping.
Write the XRAM address of the data to be decrypted to DMA0N
and DMA0NBAL.
Write the number of bytes to be decrypted in multiples of 16 bytes to DMA0NSZH and DMA0NSZL.
Clear DMA0NAOH and DMA0NAOL.
Configure the third DMA channel for AES0YOUT
Select the third DMA channel by writing 0x02 to
A0SEL
Configure the third DMA channel to move the contents of AES0YOUT to XRAM by writing 0x08 to DMA0NCF
Enable transfer complete interrupt by settin
7 of DMA0NCF
Clear DMA0NMD to disable wrapping
Write the XRAM address for decrypted data to DMA0NBAH and DMA0NBAL.
Write the number of bytes to be d
ryp
ed in multiples of 16 bytes to DMA0NSZH and DMA0NSZL.
Clear DMA0NSZH
Clear DMA0NAOH and DMA0NAOL.
Clear first three DMA interrupts by clearing bits 0 to 2 in DMA0IN
T
.
Enable first three DMA channels setting bits 0 to 2 in DMA0EN
Configure the AES module data flow for AES Block Cipher by writing 0x00 to AES0DCF
G
.
Write key size t
1 and 0 of AES0BCFG
Configure the AES core for decryption by clearing bit 2 of AES0BCFG
Initiate
encryption operation be setting bit 3 of AES0BCFG
W
on the DMA interrupt from DMA channel 2
D
able the AES Module by clearing bit 2 of AES0BCFG
Disable the DMA by writing 0x00 to DMA0EN
187
Rev. 1.0
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14.5.2. AES Block Cipher Decryption using SFRs
First, configure AES module for AES Block Cipher
Reset AES module by writing 0x00 to AES0BCF
G
.
Configure the AES Module data flow for AES Block Cipher by writing 0x00 to AES0DCF
G
.
Write key size to bits 1 and 0 of AES0BCF
G
.
Configure the AES core for decryption by setting bit 2 of AES0BCF
G
.
Enable the AES core by setting bit 3 of AES0BCF
G
.
Repeat alternating write sequence 16 times
Write ciphertext byte to AES0BIN.
Write decryption key byte to AES0KIN.
Write remaining decryption key bytes to AES0KIN for 192-bit and 256-bit decryption
.
Wait on AES done interrupt or poll bit 5 of AES0BCF
G
.
Read 16 plaintext bytes from AES0YOU
T
.
If decrypting multiple blocks, this process may be repeated. It is not necessary reconfigure the AES mod-
ule for each block.
Rev. 1.0
188
Si102x/3x
14.6. Block
Cipher Modes
14.6.1. Cipher Block Chaining Mode
The Cipher Block Chaining (CBC) algorithm significantly improves the strength of basic AES encryption by
making each block encryption be a function of the previous block in addition to the current plaintext and
key. This algorithm is shown inFigure 14.4
Plain Text
XOR
Plain Text
XOR
Initialization Vector (IV)
Encryption
Encryption
Cipher
Encryption
Cipher
Encryption
Key
Encryption
Key
Cipher Text
Cipher Text
Ciphe
Tex
Cipher Text
Decryption
Cipher
Decryption
Cipher
Decryption
Key
Decryption
Key
Decryption
Initialization Vector (IV)
XOR
Plain Text
Plain Text
Figure 14.4. Cipher Block Chaining Mode
189
Rev. 1.0
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14.6.1.1. CBC
Encryption Data Flow
The AES0 module data flow for CBC encryption is shown in Figure
14.5. The plaintext is written to
AES0BIN. For the first block, the initialization vector is written to AES0XIN. For subsequent blocks, the
previous block ciphertext is written to the AES0XIN SFR. The AES0DCFG SFR is configured to XOR
AES0XIN with AES0BIN for the AES core data input. The XOR on the output is not used. The AES core is
configured for an encryption operation. The encryption key is written to AES0KIN. The key size is set to the
desired key size.
AES0BIN
internal state
machine
AES0XIN
+
AES0DCFG
Data In
AES
Core
Key
In
Key
Out
AES0KIN
Out
AES0BCFG
+
AES0YOUT
Figure 14.5. CBC Encryption Data Flow
Rev. 1.0
190
Si102x/3x
14.6.2. CBC Encryption Initialization Vector Location
The first block to be encrypted uses the initialization vector for the AES0XIN data. Subsequent blocks will
use the encrypted ciphertext from the previous block. The DMA is capable of encrypting multiple blocks. If
the initialization is located at an arbitrary location in XRAM, the DMA base address location will need to be
changed to the start of the encrypted ciphertext after encrypting the first block. However, if the initialization
vector is located in XRAM immediately before the encrypted ciphertext, the pointer will be advanced to the
start of the encrypted ciphertext, and multiple blocks can be encrypted autonomously.
14.6.3. CBC Encryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA
It is highly
recommended to use the code examples. The steps are listed here for completeness.
Prepare encryption key, initialization vector, and data to be encrypted in XRAM.
(The initialization vector should be located immediately before the data to be encrypted to encrypt multiple
blocks.)
Reset AES module by clearing bit 2 of AES0BCF
G
.
Disable the first four DMA channels by clearing bits 0 to 3 in the DMA0EN SFR.
Configure the first DMA channel for the AES0KIN SFR.
Select the first DMA channel by writing 0x00 to the DMA0SEL SFR.
Configure the first DMA channel to move XRAM to the AES0KIN SFR by writing 0x05 to the DMA0NCF SFR.
Write 0x01 to DMA0NMD to enable wrapping
Write the XRAM location of the encryption key to the DMA0NBAH and DMA0NBAL SFRs.
Write the key length in bytes to the DMA0NSZL SFR.
Clear the DMA0NSZH SFR.
Clear the DMA0NAOH and DMA0NAOL SFRs.
Configure the second DMA channel for the AE
0BIN SFR.
Select the second DMA channel by writing
to the DMA0SEL SFR.
Configure the second DMA channel to move XRAM to the AES0BIN SFR by writing 0x06 to the DMA0NCF SFR.
Clear DMA0NMD to disable wrapping.
Write the XRAM address of the da
o be encrypted to the DMA0NBAH and DMA0NBAL SFRs.
Write the number of bytes to be encrypted in multiples of 16 bytes to DMA0NSZH and DMA0NSZL.
Clear DMA0NAOH and DMA0NAOL.
Configure the third DMA channel for the AES0XIN SFR.
Select the third DMA channel by writing 0x02 to DMA0SEL.
Configure the third DMA channel to move xram to AES0XIN SFR by writing 0x07 to the DMA0NCF SFR.
Clear DMA0NM
o disable wrapping.
Write the XRAM
dress of the initialization vector to the DMA0NBAH and DMA0NBAL SFRs.
Write the number of bytes to be encrypted in multiples of 16 bytes to DMA0NSZH and DMA0NSZL.
Clear
DMA0NAOH and DMA0NAOL SFRs.
*
fig
re the fourth DMA channel for the AES0YOUT SFR
elect the fourth channel by writing 0x03 to the DMA0SEL SFR.
Configure the fourth DMA channel to move the contents of AES0YOUT to XRAM by writing 0x08 to the
DMA0NCF SFR.
Enable transfer complete interrupt by setting bit 7 of DMA0NCF
Clear DMA0NMD to disable wrapping
Write the XRAM address for the encrypted data to DMA0NBAH and DMA0NBAL.
Write the number of bytes to be encrypted in multiples of 16 bytes to DMA0NSZH and DMA0NSZL.
Clear the DMA0NAOH and DMA0NAOL SFRs.
Clear first four DMA interrupts by clearing bits 0 to 2 in the DMA0INT SFR.
Enable first four DMA channels by setting bits 0 to 2 in the DMA0EN SFR.
191
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Configure the AES module data flow for XOR on input data by writing 0x01 to the AES0DCFG SFR.
Write key size to bits 1 and 0 of the AES0BCFG SFR.
Configure the AES core for encryption by setting bit 2 of AES0BCF
G
.
Initiate the encryption operation be setting bit 3 of AES0BCF
G
.
Wait on the DMA interrupt from DMA channel 3.
Disable the AES Module by clearing bit 2 of AES0BCF
G
.
Disable the DMA by writing 0x00 to DMA0EN.
Rev. 1.0
192
Si102x/3x
14.6.3.1. CBC
Encryption using SFRs
First Configure the AES module for CBC Block Cipher Mode encryption
Reset AES module by writing 0x00 to AES0BCF
G
.
Configure the AES module data flow for XOR on input data by writing 0x01 to the AES0DCFG SFR.
Write key size to bits 1 and 0 of AES0BCF
G
.
Configure the AES core for encryption by setting bit 2 of AES0BCF
G
.
Enable the AES core by setting bit 3 of AES0BCF
G
.
Repeat alternating write sequence 16 times
Write plaintext byte to AES0BIN.
Write initialization vector to AES0XIN
Write encryption key byte to AES0KIN.
Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit decryption
Wait on AES done interrupt or poll bit 5 of AES0BCF
G
.
Read 16 encrypted bytes from the AES0YOUT SFR.
If encrypting multiple blocks, this process may be repeated. It is not necessary reconfigure the AES mod-
ule for each block. When using Cipher Block Chaining, the initialization vec
is written to the AES0XIN
SFR for the first block only, as described. Additional blocks will chain the encrypted data from the previous
block.
193
Rev. 1.0
Si102x/3x
14.6.4. CBC Decryption
The AES0 module data flow for CBC decryption is shown in Figure
14.6. The ciphertext is written to
AES0BIN. For the first block, the initialization vector is written to AES0XIN. For subsequent blocks, the
previous block ciphertext is written to AES0XIN. AES0DCFG is configured to XOR AES0XIN with the AES
core data output. The XOR on the input is not used. The AES core is configured for a decryption operation.
The decryption key is written to AES0KIN. The key size is set to the desired key size.
AES0BIN
internal state
machine
AES0XIN
+
AES0DCFG
Data In
AES
Core
Key
In
Key
Out
AES0KIN
Data Out
AES0BCFG
+
AES0YOUT
Figure 14.6. CBC Decryption Data Flow
Rev. 1.0
194
Si102x/3x
14.6.4.1. CBC
Decryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are documented in the data sheet for completeness.
Prepare decryption key, initialization vector, and data to be decrypted in XRAM.
The initialization vector should be located immediately before the data to be decrypted to decrypt
multiple blocks.
Reset the AES module by clearing bit 2 of AES0BCF
G
.
Disable the first four DMA channels by clearing bits 0 to 3 in the DMA0EN SFR.
Configure the first DMA channel for the AES0KIN SFR.
Select the first DMA channel by writing 0x00 to the DMA0SEL SFR.
Configure the first DMA channel to move XRAM to the AES0KIN SFR by writing 0x05 to the
0NCF SFR.
Write 0x01 to DMA0NMD to enable wrapping.
Write the XRAM location of the decryption key to DMA0NBAH and DMA0NBAL.
Write the key length in bytes to DMA0NSZL.
Clear the DMA0NSZH SFR.
Clear the DMA0NAOH and DMA0NAOL SFRs.
Configure the second DMA channel for the AES0BIN SFRs.
Select the second DMA channel by writing 0x01 to the DMA0SEL SFR.
Configure the second DMA channel to move XRAM to AES0BIN by writing 0x06 to DMA0NC
F
.
Clear DMA0NMD to disable wrapping.
Write the XRAM address of the data to be decrypted to the DM
BAH and DMA0NBAL SFRs.
Write the number of bytes to be decrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL SFRs.
Clear the DMA0NAOH and DMA0NAOL SFRs.
Configure the third DMA channel for AES0XIN.
Select the third DMA channel by writing 0x02 to
DMA0SEL SFR.
Configure the third DMA channel to move XR
M to the AES0XIN SFR by writing 0x07 to the DMA0NCF SFR.
Clear DMA0NMD to disable wrapping.
Write the XRAM address of the initialization vector to the DMA0NBAH and DMA0NBAL SFRs.
Write the number of bytes to be decrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL SFRs.
Clear the DMA0NAOH and DMA0
AOL SFRs.
Configure the fourth DMA channel for the AES0YOUT SFR.
Select the fourth channel by writing 0x03 to the DMA0SEL SFR.
Configure the fourth DMA channel to move the contents of the AES0YOUT SFR to XRAM by writing 0x08 to the
DMA0NCF SFR.
Enable transfer complete interrupt by setting bit 7 of DMA0NC
F
.
Clear DMA0N
disable wrapping.
Write the XRAM
ddress for the decrypted data to the DMA0NBAH and DMA0NBAL SFRs.
Write the number of bytes to be decrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL SFRs.
Clear
DMA0NAOH and DMA0NAOL SFRs.
C
first four DMA interrupts by clearing bits 0 to 2 in the DMA0INT SFR.
E
able first four DMA channels setting bits 0 to 2 in the DMA0EN SFR.
Configure the AES module data flow for XOR on output data by writing 0x02 to AES0DCF
G
.
Write key size to bits 1 and 0 of AES0BCF
G
.
Configure the AES core for decryption by clearing bit 2 of AES0BCF
G
.
Initiate the decryption operation be setting bit 3 of AES0BCF
G
.
Wait on the DMA interrupt from DMA channel 3.
Disable the AES Module by clearing bit 2 of AES0BCF
G
.
Disable the DMA by writing 0x00 to DMA0EN.
195
Rev. 1.0
Si102x/3x
14.6.4.2. CBC
Decryption using SFRs
First Configure AES Module for CBC Block Cipher Mode Decryption
Reset the AES module by writing 0x00 to AES0BCF
G
.
Configure the AES Module data flow for XOR on output data by writing 0x02 to the AES0DCFG SFR.
Write key size to bits 1 and 0 of AES0BCF
G
.
Configure the AES core for decryption by setting bit 2 of AES0BCF
G
.
Enable the AES core by setting bit 3 of AES0BCF
G
.
Repeat alternating write sequence 16 times
Write plaintext byte to AES0BIN.
Write encryption key byte to AES0KIN.
Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit decryption
.
Wait on AES done interrupt or poll bit 5 of AES0BCF
G
.
Repeat alternating write read sequence 16 times
Write initialization vector to AES0XIN
Read decrypted data from AES0YOUT
If decrypting multiple blocks, this process may be repeated. It is not necess
y reconfigure the AES mod-
ule for each block. When using Cipher Block Chaining the initialization vector is written to the AES0XIN
SFR for the first block only, as described. Additional blocks will chain the ciphertext data from the previous
block.
Rev. 1.0
196
Si102x/3x
14.6.5. Counter Mode
The Counter (CTR) Mode uses a sequential counter which is incremented after each block. This turns the
block cipher into a stream cipher. This algorithm is shown inFigure 14.4. Note that the decryption operation
actually uses the encryption key and encryption block cipher. The XOR operation is always on the output
of the cipher. The counter is a 16-byte block. The several bytes of the counter are initialized to a nonce
(number used once). The last byte of the counter is incremented and propagated. Thus, the counter is
treated as a 16-byte big endian integer.
Counter
(0x00…00)
Counter
(0x00
1)
Encryption
Encryption
Cipher
E
ryption
Cipher
Encryption Key
Plaintext
Encryption Key
Pla
xt
XOR
XOR
Ciphertext
Ciphertext
Counter
Counter
(0x00…00)
(0x00…01)
Decryption
Encryption
Encryp
n
Encryption
Encryption
Key
C
her
Key
Cipher
Ciphertext
XOR
Ciphertext
XOR
Plaintext
Plaintext
Figure 14.7. Counter Mode
197
Rev. 1.0
Si102x/3x
14.6.5.1. CTR
Data Flow
The AES0 module data flow for CTR encryption and decryption shown in Figure 14.5. The data flow is the
same for encryption and decryption. The AES0DCFG SFR is always configured to XOR AES0XIN with the
AES core output.The XOR on the input is not used. The AES core is configured for an encryption opera-
tion. The encryption key is written to AES0KIN. The key size is set to the desired key size.
For an encryption operation, the plaintext is written to the AES0BIN SFR and the ciphertext is read from
AES0YOU
T
.
F
or decryption, the ciphertext is written to AES0BIN and the plaintext is read fro
AES0YOU
T
.
Note the counter must be incremented after each block using software.
AES0BIN
internal state
machine
AES0XIN
+
AES0DCFG
Data In
AES
ore
Key
In
Key
Out
AES0KIN
Data Out
AES0BCFG
+
AES0YOUT
Figure 14.8. Counter Mode Data Flow
Rev. 1.0
198
Si102x/3x
14.6.6. CTR Encryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are documented in the data sheet for completeness.
Prepare encryption key, counter, and data to be encrypted in XRAM.
Reset the AES module by clearing bit 2 of AES0BCF
G
.
Disable the first four DMA channels by clearing bits 0 to 3 in the DMA0EN SFR.
Configure the first DMA channel for the AES0KIN SFR.
Select the first DMA channel by writing 0x00 to the DMA0SEL SFR.
Configure the first DMA channel to move XRAM to the AES0KIN SFR by writing 0x05 to the DMA
CF SFR.
Clear DMA0NMD to disable wrapping.
Write the XRAM location of the encryption key to the DMA0NBAH and DMA0NBAL SFRs.
Write the key length in bytes to the DMA0NSZL SFR.
Clear the DMA0NSZH SFR.
Clear the DMA0NAOH and DMA0NAOL SFRs.
Configure the second DMA channel for the AES0BIN SFR.
Select the second DMA channel by writing 0x01 to the DMA0SEL SFR.
Configure the second DMA channel to move xram to AES0BIN SFR by writing 0x06 to the DMA0NCF SFR.
Clear DMA0NMD to disable wrapping.
Write the XRAM address of the data to be encrypted to the DMA0NBAH and DMA0NBAL SFRs.
Write the number of bytes to be encrypted in multiples of 16 by
to DMA0NSZH and DMA0NSZL
Clear the DMA0NSZH SFR
Clear the DMA0NAOH and DMA0NAOL SFR.
Configure the third DMA channel for the AES0XIN
FR.
Select the third DMA channel by writing 0x02 to the D
SEL SFR.
Configure the third DMA channel to move XRAM
the AES0XIN SFR by writing 0x07 to the DMA0NCF SFR.
Clear DMA0NMD to disable wrapping.
Write the XRAM address of the counter to D
NBAH and DMA0NBAL.
Write the number of bytes to be encrypted in multiples of 16 bytes to DMA0NSZH and DMA0NSZL.
Clear the DMA0NSZH SFR.
Clear the DMA0NAOH and DMA0
AOL SFRs.
Configure the fourth DMA channel for the AES0YOUT SFR.
Select the fourth channel by writing 0x03 to the DMA0SEL SFR.
Configure the fourth DMA channel to move the contents of the AES0YOUT SFR to XRAM by writing 0x08 to the
DMA0NCF SFR.
Enable transfer complete interrupt by setting bit 7 of DMA0NCF
Clear DMA0N
disable wrapping
Write the number of bytes to be encrypted in multiples of 16 bytes to DMA0NSZH and DMA0NSZL.
Clear the DMA0NSZH SFR.
Clear
DMA0NAOH and DMA0NAOL SFRs.
C
first four DMA interrupts by clearing bits 0 to 3 in the DMA0INT SFR.
E
able first four DMA channels setting bits 0 to 3 in the DMA0EN SFR.
Configure the AES module data flow for XOR on output data by writing 0x02 to AES0DCF
G
.
Write key size to bits 1 and 0 of AES0BCF
G
.
Configure the AES core for encryption by setting bit 2 of AES0BCF
G
.
Initiate the encryption operation be setting bit 3 of AES0BCF
G
.
Wait on the DMA interrupt from DMA channel 3.
Disable the AES Module by clearing bit 2 of AES0BCF
G
.
Disable the DMA by writing 0x00 to DMA0EN.
Increment counter and repeat all steps for additional blocks
199
Rev. 1.0
Si102x/3x
14.6.6.1. CTR
Encryption using SFRs
First Configure AES module for CTR Block Cipher Mode encryption.
Reset the AES module by writing 0x00 to AES0BCF
G
.
Configure the AES module data flow for XOR on output data by writing 0x02 to the AES0DCFG SFR.
Write key size to bits 1 and 0 of AES0BCF
G
.
Configure the AES core for encryption by setting bit 2 of AES0BCF
G
.
Enable the AES core by setting bit 3 of AES0BCF
G
.
Repeat alternating write sequence 16 times
Write plaintext byte to AES0BIN.
Write counter byte to AES0XIN
Write encryption key byte to AES0KIN.
Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit decryption
Wait on AES done interrupt or poll bit 5 of AES0BCF
G
.
Read 16 encrypted bytes from the AES0YOUT SFR.
If encrypting multiple blocks, increment the counter and repeat this process. It is not necessary reconfigure
the AES module for each block.
Rev. 1.0
200
Si102x/3x
SFR Definition 14.1. AES0BCFG: AES Block Configuration
Bit
7
6
5
4
3
2
1
0
DONE
BUSY
EN
ENC
KSIZE
R/W
Name
Type
Reset
R
0
R
0
R/W
0
R
0
R/W
0
R/W
0
0
0
SFR Address = 0xE9; SFR page = 0x2; Not bit-Addressable
Bit
Name
Function
5
DONE
Done Flag.
This bit is set upon completion of an encryption operation. When used with the DMA,
the DONE bit signals the start of the out transfer. When us
without the DMA, the
done flag indicates data is ready to be read from AES0YOU
T
.
T
he DONE bit is not
cleared by hardware and must be cleared to zero b
software at the start of the next
encryption operation.
4
3
2
BUSY
EN
AES BUS
Y
.
This bit is set while the AES block is en
ag
an encryption or decryption operation.
This bit is read only.
AES Enable.
This bit should be set to 1 to initiate
encryption or decryption operation. Clearing this
bit to 0 will reset the AES mod
e.
ENC
Encryption/Decryption S
t.
This is set to 1 to select an encryption operation. Clearing this bit to 0 will select a
decryption operation.
1:0 SIZE[1:0]
AES Key Size.
These bits select the key size for encryption/decryption. The encryption/decryption time
depends on the key size selected.
00: Select 128-bits (16 bytes). Encryption/decryption takes 218 clocks.
01: Select 198-bits (24 bytes). Encryption/decryption takes 274 clocks.
elect 256-bits (32 bytes). Encryption/decryption takes 298 clocks.
11: Reserved.
201
Rev. 1.0
Si102x/3x
SFR Definition 14.2. AES0DCFG: AES Data Configuration
Bit
7
6
5
4
3
2
1
0
OUTSEL[1:0]
R/W
XORIN
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R/W
0
0
0
SFR Address = 0xEA; SFR page = 0x2; Not bit-Addressable
Bit
Name
Function
2:1
OUTSEL[1:0]
DATA Select.
These bits select the output data source for the AES0YOUT SFR.
00: Direct AES Data
01: AES Data XOR with AES0XIN
10: Inverse Key
11: reserved
0
XORIN
XOR Input Enable.
Setting this bit with enable the XOR d
path on the AES input. If enabled,
AES0BIN will be XORed with the AES0XIN and the results will feed into the AES
data input. Clearing this bit to
will disable the XOR gate on the input. The con-
tents of AES0BIN will go dire
into the AES data input.
Rev. 1.0
202
Si102x/3x
SFR Definition 14.3. AES0BIN: AES Block Input
Bit
7
6
5
4
3
2
1
0
AES0BIN[7:0]
R/W R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0xEB; SFR page = 0x2; Not bit-Addressable
Bit Name
Function
7:0 AES0BIN[7:0]
AES Block Input.
During an encryption operation, the plaintext is written to the AES0BIN SFR. During
an decryption operation, the ciphertext is written to the
S0BIN SFR. During a key
inversion the encryption key is written to AES0BIN.
When used with the DMA, the DMA will write di
ectly to this SFR.
The AES0BIN may be used in conjunction with the AES0XIN SFR for some cipher
block modes.
When used without the DMA, AES0BIN
S0XIN, and AES0KIN must be written
in sequence.
Reading this register will yield the last value written. This can be used for debug
purposes.
203
Rev. 1.0
Si102x/3x
SFR Definition 14.4. AES0XIN: AES XOR Input
Bit
7
6
5
4
3
2
1
0
AES0XIN[7:0]
R/W R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0xEC; SFR page = 0x2; Not bit-Addressable
Bit Name
Function
7:0 AES0XIN[7:0]
AES XOR Input.
The AES0XIN may be used in conjunction with the AES0BIN SFR for some cipher
block modes.
When used with the DMA, the DMA will write directly to this SFR.
When used without the DMA – AES0BIN, AES0XIN, and AES0KIN must be written
in sequence.
Reading this register will yield the last value written. This can be used for debug
purposes.
SFR Definition 14.5. AES0KIN: AES Key In
t
Bit
7
6
5
4
3
2
1
0
AES0KIN[7:0]
R/W R/W
Name
Type
Reset
R/W
0
R/W
0
W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Address = 0xED; SFR page = 0x2; Not bit-Addressable
Bit Name
Function
7:0 AES0KIN[7:
ES Key Input.
During an encryption operation, the plaintext is written to the AES0BIN SFR. During
an decryption operation, the ciphertext is written to the AES0BIN SFR. During a key
inversion the encryption key is written to AES0BIN.
When used with the DMA, the DMA will write directly to this SFR.
The AES0BIN may be used in conjunction with the AES0XIN SFR for some cipher
block modes.
When used without the DMA – AES0BIN, AES0XIN, and AES0KIN must be written
in sequence.
Rev. 1.0
204
Si102x/3x
SFR Definition 14.6. AES0YOU
T
:
A
ES Y Output
Bit
7
6
5
4
3
2
1
0
AES0YOUT[7:0]
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SFR Address = 0xF5; SFR page = 0x2; Not bit-Addressable
Bit Name
7:0 AES0YOUT[7:0]
AES Y Output.
Function
Upon completion of an encryption/decryption operation The output data may be
read, one byte at a time, from the AES0YOUT SFR
When used with the DMA, the DMA will read directly from this SFR.
The AES0YOUT SFR may be used in conjunction with the AES0XIN SFR for
some cipher block modes.
When used without the DMA, the firmware should wait on the DONE flag before
reading from the AES0YOUT SFR.
When used without the DMA and usin
OR on the output, one byte should be
written to AES0XIN before reading each byte from AES0YOU
T
.
Reading this register over th
2 interface will not increment the output data.
205
Rev. 1.0
Si102x/3x
15. Encoder/Decoder
The Encoder/Decoder consists of three 8-bit data registers, a control register and an encoder/decoder
logic block.
The size of the input data depends on the mode. The input data for Manchester encoding is one byte. For
Manchester decoding it is two bytes. Three-out-of-Six encoding is two bytes. Three-out-of six decoding i
three bytes.
The output size also depends on the mode selected. The input and output data size are shown below:
Table 15.1. Encoder Input and Output Data Sizes
Input
Output
Data Size
Data Size
Operation
Bytes
Bytes
Manchester Encode
Manchester Decode
1
2
2
3
2
1
3
2
Three out of Six Encode
Three out of Six Decode
The input and output data is always right justified. So for Manc
er mode the input uses only ENC0L and
the output data is only in ENC0M and ENC0L. ENC0H is not used for Manchester mode
Rev. 1.0
206
Si102x/3x
15.1. Manchester
Encoding
To
e
ncode Manchester Data, first clear the MODE bit for Manchester encoding or decoding.
To
e
ncode, one byte of data is written to the data register ENC0L.
Setting the ENC bit will initiate encoding. After encoding, the encoded data will be in ENC0M and ENC0L.
The upper nibble of the input data is encoded and placed in ENC0M. The lower nibble is encoded an
placed in ENC0L.
Note that the input data should be readable in the data register until the encode bit is set. Once the READY
bit is set, the input data has been replaced by the output data.
The ENC and DEC bits are self clearing. The READY bit is not cleared by hardware and
ust be cleared
manually. The control register does not need to be bit addressable. The READY bit c
leared while
setting the ENC or DEC bit using a direct or immediate SFR mov instruction.
Table 15.2. Manchester Encoding
Input Data
nibble
hex
Encoded Output
byte
hex
dec
bin
bin
dec
0
1
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0001
0010
0011
01
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
10101010
10101001
1
0110
10100101
10011010
10011001
10010110
10010101
01101010
01101001
01100110
01100101
01011010
01011001
01010110
01010101
AA
A9
A6
A5
9A
99
96
95
6A
69
66
65
5A
59
56
55
170
169
166
165
154
153
150
149
106
105
102
101
90
2
3
4
5
6
7
8
9
10
12
13
14
15
89
86
85
207
Rev. 1.0
Si102x/3x
15.2. Manchester
Decoding
Two bytes of Manchester data are written to ENC0M and ENC0L SFRs. Then the DEC bit is set to initiate
decoding. After decoding the READY bit will be set. If the data is not a valid encoded Manchester data, the
ERROR bit will be set, and the output will be all FFs.
The encoding and decoding process should be symmetric. Data can be written to the ENC0L SFR, then
encoded, then decoding will give the original data.
Table 15.3. Manchester Decoding
Input
Byte
Decoded Output
Nibble
bin
hex
dec
dec
hex
b
n
55
56
59
5A
65
66
69
6A
95
9
99
9A
A5
A6
A9
AA
85
15
F
1111
01010101
01010110
01011001
01011010
01100101
01100110
01101001
01101010
10010101
10010110
10011001
10011010
1
101
10100110
10101001
10101010
86
14
13
12
11
10
9
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
89
90
101
102
1
6
149
150
153
154
165
166
169
170
8
7
6
5
4
3
2
1
0
Rev. 1.0
208
Si102x/3x
15.3. Three-out-of-Six
Encoding
Three out of six encoding is similar to Manchester encoding. In Three-out-of-Six encoding a nibble is
encoded as a six-bit symbol. Four nibbles are encoded as 24-bits (three bytes).
Two bytes of data to be encoded are written to ENC0M and ENC0L. The MODE bit is set to 1 for Three-
out-of-Six encoding. Setting the ENC bit will initiate encoding.
After encoding, the three encoded bytes are in ENC2-0.
Table 15.4. Three-out-of-Six Encoding Nibble
Input
Encoded Output
symbol
nibble
hex
bin
bin
dec
22
13
14
11
28
25
26
19
44
37
38
35
52
49
50
41
hex
16
0D
0E
0B
1C
19
1A
13
2C
25
26
23
34
31
32
29
octal
26
15
16
13
34
31
32
23
54
45
46
43
64
61
62
51
dec
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
001
1010
1011
1100
1101
1110
1111
010110
001101
001110
001011
011100
01100
0
10
10011
101100
100101
100110
100011
110100
110001
110010
101001
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
209
Rev. 1.0
Si102x/3x
15.4. Three-out-of-Six
Decoding
Three-out-of-Six decoding is a similar inverse process. Three bytes of encoded data are written to ENC2-
0. The DEC bit is set to initiate decoding. The READY bit will be set when decoding is complete. The
ERROR bit will be set if the input date is not valid Three-out-of-Six data.
The Three-out-of-Six encoder decode process is also symmetric. Two bytes of arbitrary data may be writ-
ten to ENC0M-ENC0L, then encoded, then decoding will yield the original data.
Table 15.5. Three-out-of-Six Decoding
Input
Decoded Output
Symbol
Nibble
octal
dec
dec
hex
bin
bin
001011
001101
001110
010011
010110
011001
011010
011100
100011
100101
100110
101001
101100
110001
110010
110100
13
15
16
23
26
31
32
34
43
45
46
5
54
61
62
64
11
13
14
19
22
25
26
28
3
7
38
41
44
49
50
52
3
1
3
1
2
7
0
5
6
4
B
9
A
F
8
D
E
C
0011
0001
0010
0111
0000
0101
0110
0100
1011
1001
1010
1111
1000
1101
1110
1100
2
7
0
5
6
4
11
9
10
15
8
13
14
12
Rev. 1.0
210
Si102x/3x
15.5. Encoding/Decoding
with SFR Access
The steps to perform a Encode/Decode operation using SFR access with the ENC0 module are as follow:
1. Clear ENC0CN by writing 0x00.
2. Write the input data to ENC0H:M:L.
3. Write the operation value to ENC0CN setting ENC, DEC, and MODE bits as desired and clearing all
other bits.
a. Write
0x10 for Manchester Decode operation.
b. Write
0x11 for Three-out-of-Six Decode operation.
c. Write
0x20 for Manchester Encode operation.
d. Write
0x21 for Three-out-of-Six Encode operation.
4. Wait on the READY bit in ENC0CN.
5. For a decode operation only, check the ERROR bit in ENC0CN for a decode error.
6. Read the results from ENC0H:M:L.
7. Repeat steps 2-6 for all remaining data.
Note that all of the ENC0 SFRs are on SFR page 0x2. The READY and ERROR must be cleared in
ENC0CN with each operation.
15.6. Decoder
Error Interrupt
The Encoder/Decoder peripheral is capable of generating an interrupt on a decoder error. Normally, when
used with the DMA, the DMA will transfer the entire specified transfer size to and from the
Encoder/Decoder peripheral. If a decoder error oc
decoding will continue until all data has been
decoded. The error bit in the ENC0CN SFR will
dicate if an error has occurred anywhere in the DMA
transfer. Some applications will discard the entire
acket after a single decoder error. Aborting the decoder
operation at the first decoder error will cons
e energy and minimize packet receiver turn-around time.
The decoder interrupt service routine should
rst stall the ENC0 DMA channels by selecting the ENC0
DMA channels and then setting the STALL bit. Then disable the DMA channels by clearing the relevant
DMA0EN bits. In addition, clear a
ENC DMA channel interrupts by clearing the respective bits in
DMA0NIN
T
.
211
Rev. 1.0
Si102x/3x
15.7. Using
the ENC0 module with the DMA
The steps for Encoding/Decoding using the DMA are as follows.
1. Clear the ENC module by writing 0x00 to the ENC0CN SFR.
2. Configure the first DMA channel for the XRAM-to-ENC0 input transfer:
a. Disable
the first DMA channel by clearing the corresponding bit in DMA0EN.
b. Select
the first DMA channel by writing to DMA0SEL.
c. Configure
the selected DMA channel to use the XRAM-to-ENC0 input peripheral request by
writing 0x00 to DMA0NC
F
.
d. Set
the ENDIAN bit in DMA0NCF to enable big-endian multi-byte DMA transfers.
e. Write
0 to DMA0NMD to disable wrapping.
f. Write
the address of the first byte of input data DMA0NBAH:L.
g. Write
the size of the input data transfer in bytes to DMA0NSZH:L.
h. Clear
the address offset SFRs DMA0A0H:L.
3. Configure the second DMA channel for the ENC0-to-XRAM output tran
er:
a. Disable
the second DMA channel by clearing the corresponding bit in DMA0EN.
b. Select
the second DMA channel by writing to DMA0SEL.
c. Configure
the selected DMA channel to use the SPI1DAT-to-XRAM output peripheral request by
writing 0x01 to DMA0NC
F
.
d. Set
the ENDIAN bit in DMA0NCF to enable big-endi
multi-byte DMA transfers.
e. Enable
DMA interrupts for the second channel by setting bit 7 of DMA0NC
F
.
f. Write
0 to DMA0NMD to disable wrapping.
g. Write
the address for the first byte of th
utput data to DMA0NBAH:L.
h. Write
the size of the output data tra
fer in bytes to DMA0NSZH:L.
i. Clear
the address offset SFRs DM
0H:L.
j. Enable
the interrupt on the second channel by setting the corresponding bit in DMA0IN
T
.
4. Clear the interrupt bits in DMA
NT for both channels.
5. Enable DMA interrupts by setting bit 5 of EIE2.
6. If desired for a decode operation, enable the ERROR interrupt bit by setting bit 6 of EIE2.
7. Write the operation value to ENC0CN setting ENC, DEC, and MODE bits for the desired operation.
The DMA bit and ENDIAN bits must be set. The READY bits and ERROR bits must be cleared.
a. Write
0x1
r Manchester Decode operation.
b. Write
0x17 for Three-out-of-Six Decode operation.
c. Write
0x26 for Manchester Encode operation.
d. Write
0x27 for Three-out-of-Six Encode operation.
ait on the DMA interrupt.
9. Clear the DMA enables in the DMA0EN SFR.
10. Clear the DMA interrupts in the DMA0INT SFR.
11. For a decode operation only, check the ERROR bit in ENC0CN for a decode error.
Note that the encoder and all DMA channels should be configured for Big-Endian mode.
Rev. 1.0
212
Si102x/3x
SFR Definition 15.1. ENC0CN: Encoder Decoder 0 Control
Bit
7
6
5
4
3
2
1
0
READY
ERROR
ENC
DEC
DMA
ENDIAN
MODE
Name
Type
Reset
R
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xC5; SFR page = 0x2; Not bit-Addressable
Bit Name
Function
7
6
5
4
2
1
READY
ERROR
ENC
Ready Flag.
Error Flag.
Encode.
Setting this bit will initiate an Encode operation.
DEC
Decode.
Setting this bit will initiate a Decode operation.
DMA
DMA Mode Enable.
This bit should be set when us
the encoder/decoder with the DMA.
ENDIAN
Big-Endian DMA Mode S
ct.
This bit should be set when using the DMA with big-endian multiple byte DMA trans-
fers. The DMA must also be configured for the same endian mode.
0
MODE
Mode.
0: Select Manchester encoding or decoding.
1:Select Three-out-of-Six encoding or decoding.
213
Rev. 1.0
Si102x/3x
SFR Definition 15.2. ENC0L: ENC0 Data Low Byte
Bit
7
6
5
4
3
2
1
0
ENC0L[7:0]
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xC2; Bit-Addressable
Bit
Name
Function
7:0
ENC0L[7:0]
ENC0 Data Low Byte.
SFR Definition 15.3. ENC0M: ENC0 Data Middle Byte
Bit
7
6
5
4
3
2
1
0
ENC0M[7:
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xC3; Bit-Addressable
Bit
Name
Function
7:0
ENC0M[7:0]
ENC0 Data Middle Byte.
SFR Definition 15.4. ENC0H: ENC0 Data High Byte
Bit
7
6
5
4
3
2
1
0
ENC0H[7:0]
Name
Type
Res
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xC4; Bit-Addressable
Bit
Name
Function
7:0
ENC0H[7:0]
ENC0 Data High Byte.
Rev. 1.0
214
Si102x/3x
16. Special
Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the Si102x/3x’s resources and peripherals. The
CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as implementing
additional SFRs used to configure and access the sub-systems unique to the Si102x/3x. This allows the
addition of new functionality while retaining compatibility with the MCS-51™ instruction set.
T
a
ble 16.3 li
the SFRs implemented in the Si102x/3x device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xF
F
.
S
FRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE,
.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable
y. Unoccupied
addresses in the SFR space are reserved for future use. Accessing unoccupied add
in the SFR
space will have an indeterminate effect and should be avoided. Refer to the correspond
pages of the
data sheet, as indicated in
T
a
ble 16.3, for a detailed description of each register.
16.1. SFR
Paging
The CIP-51 features SFR paging
,
allowing the device to map many SFRs i
o the 0x80 to 0xFF memory
address space. The SFR memory space has 256
pages
. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFRs. The Si102x/3x family of devices utilizes two SFR pages: 0x00 and 0x0
F
.
SFR pages are selected using the Special Function Register Page Selection register, SFRPAGE (see SFR
Definition 11.3). The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page number using the SFR
E register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
16.2. Interrupts
and SFR Paging
When an interrupt occurs, the current SFRPAGE
pushed onto the SFR page stack. Upon execution of
the RETI instruction, the SFR page is automa
cally restored to the SFR Page in use prior to the interrupt.
This is accomplished via a three-byte
SFR P
Stack
. The top byte of the stack is SFRPAGE, the current
SFR Page. The second byte of the SFR Page Stack is SFRNEX
T
.
T
he third, or bottom byte of the SFR
Page Stack is SFRLAS
T
.
U
pon an interrupt, the current SFRPAGE value is pushed to the SFRNEXT byte,
and the value of SFRNEXT is push
d to SFRLAS
T
.
O
n a return from interrupt, the SFR Page Stack is
popped resulting in the value of SFRNEXT returning to the SFRPAGE register, thereby restoring the SFR
page context without software intervention. The value in SFRLAST (0x00 if there is no SFR Page value in
the bottom of the stack) of the stack is placed in SFRNEXT register. If desired, the values stored in
SFRNEXT and SFRLAST may be modified during an interrupt, enabling the CPU to return to a different
SFR Page upon execution of the RETI instruction (on interrupt exit). Modifying registers in the SFR Page
Stack does not cau
push or pop of the stack. Only interrupt calls and returns will cause push/pop oper-
ations on the SFR Page Stack.
On the Si10
x/3x devices, the SFRPAGE must be explicitly set in the interrupt service routine.
Rev. 1.0
215
Si102x/3x
SFRPGCN Bit
Interrupt
Logic
SFRPAGE
CIP-51
SFRNEXT
S
LAST
Figure 16.1
SFR Page Stack
Automatic hardware switching of the SFR Pa
n interrupts may be enabled or disabled as desired using
the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFR0CN). This
function defaults to “enabled” upon reset. In this way, the autoswitching function will be enabled unless dis-
abled in software.
A summary of the SFR locations (address and SFR page) are provided in
T
a
ble 16.3 in the form of an SFR
memory map. Each memory location in the map has an SFR page row, denoting the page in which that
SFR resides. Certain SFRs are accessible from ALL SFR pages, and are denoted by the “(ALL PAGES)”
designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “(ALL PAGES)” designa-
tion, indicating thes
FRs are accessible from all SFR pages regardless of the SFRPAGE register value.
216
Rev. 1.0
Si102x/3x
SFR Definition 16.1. SFRPGCN: SFR Page Control
Bit
7
6
5
4
3
2
1
0
SFRPGE
R/W
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
1
;SFR Page = 0xF; SFR Address = 0x8E
Bit
7:1
0
Name
Function
Unused
Read = 0000000b; Write = Don’t Care
SFRPGEN
SFR Automatic Page Control Enable.
Upon interrupt, the C8051 Core will vector to the speci
d
nterrupt service routine.
This bit controls the automatic preservation and restoration of the SRFPAGE by hard-
ware.
0: SFR Automatic Paging disabled. The C8051 core will neither preserve the SRF-
PAGE upon entering an interrupt service
outine, nor restore the SFRPAGE upon
exiting the interrupt service routine. The in
pt service routine should preserve and
restore the active SFRPAGE in firmware.
1: SFR Automatic Paging enable
he C8051 core will preserve the SRFPAGE upon
entering an interrupt service routin
nd restore the SFRPAGE upon exiting the Inter-
rupt service routine. The firm
are does not need to preserve and restore the SFRP-
AGE in the interrupt se
ce routing. However, firmware must set the SFRPAGE
within the interrupt servic
utine before accessing SFRs.
Rev. 1.0
217
Si102x/3x
SFR Definition 16.2. SFRPAGE: SFR Page
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SFRPAGE[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xA7
Bit Name
7:0 SFRPAGE[7:0]
SFR Page Bits.
Function
Represents the SFR Page the C8051 core uses when reading or modifying
SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
When enabled in the SFR Page Control Register (SFR0CN), the C8051 core will
automatically switch to the SFR Pag
t contains the SFRs of the correspond-
ing peripheral/function that caused the interrupt, and return to the previous SFR
page upon return from interrupt (unless SFR Stack was altered before a return-
ing from the interrupt). SFR
GE is the top byte of the SFR Page Stack, and
push/pop events of this stack
e caused by interrupts (and not by reading/writ-
ing to the SFRPAGE re
te
)
218
Rev. 1.0
Si102x/3x
SFR Definition 16.3. SFRNEX
T
:
S
FR Next
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SFRNEXT[7:0]
R/W
0
0
0
0
0
0
0
0
;SFR Page = All Pages; SFR Address = 0x85
Bit Name
7:0 SFRNEXT[7:0]
SFR Page Bits.
Function
This is the value that will go to the SFR Page register upon a return from inter-
rupt.
Write: Sets the SFR Page contained in the second byte of the SFR Stack. This
will cause the SFRPAGE SFR to have this SFR page value upon a return from
interrupt.
Read: Returns the value of the SFR
age contained in the second byte of the
SFR stack.
SFR page context is retained upon interrupts/return from interrupts in a 3 byte
SFR Page Stack: SFRPAG
s the first entry, SFRNEXT is the second, and
SFRLAST is the third entry. T
SFR stack bytes may be used alter the context
in the SFR Page Stack
and will not cause the stack to “push” or “pop”. Only
interrupts and retur
om interrupts cause pushes and pops of the SFR Page
Stack.
Rev. 1.0
219
Si102x/3x
SFR Definition 16.4. SFRLAS
T
:
S
FR Last
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SFRLAST[7:0]
R/W
0
0
0
0
0
0
0
0
;SFR Page = All Pages; SFR Address = 0x86
Bit Name
7:0 SFRLAST[7:0]
SFR Page Stack Bits.
Function
This is the value that will go to the SFRNEXT register upon a return from inter-
rupt.
Write: Sets the SFR Page in the last entry of the SFR Stack. This will cause the
SFRNEXT SFR to have this SFR page value upon a return from interrupt.
Read: Returns the value of the SFR page contained in the last entry of the SFR
stack.
SFR page context is retained upon in
errupts/return from interrupts in a 3 byte
SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and
SFRLAST is the third entry.
e SFR stack bytes may be used alter the context
in the SFR Page Stack, and
ill not cause the stack to “push” or “pop”. Only
interrupts and return fro
interrupts cause pushes and pops of the SFR Page
Stack.
220
Rev. 1.0
Si102x/3x
Table 16.1. SFR Map (0xC0–0xFF)
Addr. Page
0(8)
1(9)
PCA0L
2(A)
PCA0H
3(B)
PCA0CPL0
PC0INT0
P6MDOUT
P2MDIN
4(C)
5(D)
6(E)
7(F)
0xF8
0xF0
0xE8
0xE0
0xD8
0xD0
0xC8
0xC0
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
xF
SPI0CN
SPI1CN
PCA0CPH0
PC0INT1
P7MDOUT
SMB0ADR
PC0HIST
P6MDIN
PCA0CPL4
DC0RDY
PCA0CPH4
VDM0CN
PC0DCL
P4MDOUT
P0MDIN
PC0DCH
P5MDOUT
P1MDIN
CLKMODE
SMB0ADM
AES0YOUT
PCLKACT
PCA0CPL3
AES0KIN
PCLKEN
EIP1
EIP2
RSTSRC
EIE2
PC0CMP1L PC0CMP1M
P3MDIN P4MDIN
PC0CMP1H
P5MDIN
ADC0CN PCA0CPL1 PCA0CPH1
AES0BCFG AES0DCFG
PCA0CPL2
AES0BIN
PCA0CPH2
AES0XIN
PCA0CPH3
DEVICEID
XBR0
REVID
XBR1
ACC
XBR2
PC0CMP0H
XBR2
IT01CF
PC0TH
EIE1
PC0CMP0L PC0CMP0M
XBR0
PCA0MD
PC0MD
P4
XBR1
PCA0CPM0
PC0CTR0L
P5
CF
PCA0CN
PSW
PCA0CPM1
PC0TR
P6
PCA0CPM2
PC0CTR0H
P7
PCA0CPM3
PC0CTR1L
PCA0CPM4
PC0TRMH
PCA0PWM
PC0CTR1H
REF0CN
DMA0SEL
PCA0CPL5
DMA0EN
A0CPH5
DMA0INT
P0SKIP
P1SKIP
P2SKIP
P0MAT
DMA0MINT
DMA0BUSY
DMA0NMD
PC0PCF
TMR2CN
SMB0C
REG0CN
TMR2RLL
TMR2RLH
TMR2L
TMR2H
PCA0CPM5
DMA0NSZL
P1MAT
DMA0NCF DMA0NBAL
DMA0NBAH
DMA0NAOL
DMA0NAOH
DMA0NSZH
SMB0CF
PC0STAT
SMB0DAT
ENC0L
ADC0GTL
ENC0M
ADC0GTH
ENC0H
ADC0LTL
ENC0CN
ADC0LTH
P0MASK
VREGINSDL VREGINSDH
Rev. 1.0
221
Si102x/3x
Table 16.2. SFR Map (0x80–0xBF)
Addr. Page
0(8)
1(9)
IREF0CN
CRC1IN
IREF0CF
OSCXCN
DC0CN
2(A)
ADC0AC
CRC1OUTL
ADC0PWR
OSCICN
DC0CF
3(B)
ADC0MX
CRC1OUTH
ADC0TK
PMU0MD
DC0MD
4(C)
5(D)
ADC0L
6(E)
ADC0H
CRC1CN
TOFFH
7(F)
0xB8
0xB0
0xA8
0xA0
0x98
0x90
0x88
0x80
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
0x0
0x2
0xF
IP
ADC0CF
P1MASK
CRC1POLL
CRC1POLH
TOFFL
P3
IE
PMU0CF
PMU0FL
FLKEY
LCD0CHPCN
BUFMD
CL
P3MDOUT
CLKSEL
OSCIFL
OSCICL
EMI0CN
EMI0CF
RTC0ADR
LCD0MSCF
LCD0BUFCF
P0MDOUT
LCD
PWR
RV
RTC0DAT
RTC0KEY
EMI0TC
LCD0CLKDIVL LCD0CLKDIVH
LCD0MSCN
LCD0CHP
F LCD0CHPMD
LCD0VBMCF
CLKSEL
SPI0CFG
SPI1CFG
P3DRV
P6DRV
SPI0CKR
SPI1CKR
P4DRV
P7DRV
SPI0DAT
SPI1DAT
P5DRV
P2
P1MDOUT
LCD0CF
P1DRV
P2MDOUT
LCD0VBMCN
P2DRV
SFRPAGE
SCON0
SBUF0
CPT1CN
LCD0DE
CPT0CN
LCD
CPT1MD
CPT0MD
LCD0CN
CPT1MX
CPT0MX
LCD0DD
LCD0CNTRST
LCD0BUFCN
TMR3L
LCD0BLINK
LCD0TOGR
P1
TMR3CN
LCD0D6
CRC0DAT
TMOD
TMR3RLL
LCD0D7
C0CN
TL0
MR3RLH
LCD0D8
CRC0IN
TL1
TMR3H
LCD0D9
LCD0DA
LCD0DB
CRC0AUTO
CKCON
LCD0DC
CRC0CNT
PSCTL
CRC0FLIP
TH0
TCON
TH1
LCD0D0
LCD0D1
LCD0D2
LCD0D3
LCD0D4
LCD0D5
SFRPGCN
SFRLAST
P0
SP
DPL
DPH
PSBANK
SFRNEXT
PCON
222
Rev. 1.0
Si102x/3x
Table 16.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
ADC0AC
ADC0CF
ADC0CN
ADC0GTH
ADC0GTL
ADC0H
Address SFR
Page
Description
ADC0 Accumulator Configuration
ADC0 Configuration
Page
0xBA
0xBC
0xE8
0xC4
0xC3
0xBE
0xBD
0xC6
0xC5
0xBB
0xBA
0xBB
0xE9
0xEB
0xEA
0xED
0xEC
0xF5
0x8E
0xFD
0xA9
0x0
0x0
87
86
85
All pages
0x0
ADC0 Control
91
ADC0 Greater-Than Compare High
ADC0 Greater-Than Compare Low
ADC0 High
0x0
91
0x0
90
0x0
90
ADC0L
ADC0 Low
0x0
92
ADC0LTH
ADC0LTL
ADC0MX
ADC0PWR
ADC0TK
ADC0 Less-Than Compare Word High
ADC0 Less-Than Compare Word
ow
ADC0 MUX
0x0
92
0x0
95
0xF
0xF
0x2
88
ADC0 Burst Mode Power-Up Time
ADC0 Tracking Control
AES0 Block Config
ion
AES0 Block Input
89
AES0BCFG
AES0BIN
AES0DCFG
AES0KIN
AES0XIN
AES0YOUT
CKCON
201
203
202
204
204
205
484
262
291
0x2
0x2
AES0 Da
nfiguration
AES0
ey Input
0x2
0x2
A
0 XOR Input
0x2
AES Y Out
0x
Clock Control
CLKMODE
CLKSEL
0xF
Clock Mode
0x0 and
0xF
Clock Select
CPT0CN
CPT0MD
CPT0MX
CPT1C
1MD
CPT1MX
CRC0AUTO
CRC0CNT
CRC0CN
CRC0DAT
CRC0FLIP
CRC0IN
0x9B
x9D
0x9F
0x9A
0x9C
0x9E
0x96
0x97
0x92
0x91
0x94
0x93
0x0
0x0
0x0
0x0
0x0
0x0
0xF
0xF
0xF
0xF
0xF
0xF
107
108
112
109
110
113
165
165
163
164
166
164
Comparator0 Control
Comparator0 Mode Selection
Comparator0 Mux Selection
Comparator1 Control
Comparator1 Mode Selection
Comparator1 Mux Selection
CRC0 Automatic Control
CRC0 Automatic Flash Sector Count
CRC0 Control
CRC0 Data
CRC0 Flip
CRC0 Input
Rev. 1.0
223
Si102x/3x
Table 16.3. Special Function Registers
(Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address SFR
Page
Description
Page
CRC1CN
0xBE
0xB9
0xBB
0xBA
0xBD
0xBC
0xB2
0xB1
0xB3
0xFD
0xE9
0xD5
0xD2
0xD3
0xD4
0xCD
0xCC
0xCB
0xCA
0xC9
0xD6
0xCF
0xCE
0xD1
0x83
0x82
0xE6
0xE7
0xF6
0xF7
0xAB
0xAA
0xAF
0xC5
0x2
0x2
171
CRC1 Control
CRC1 In
CRC1IN
CRC1OUTH
CRC1OUTL
CRC1POLH
CRC1POLL
DC0CF
172
173
173
172
172
274
273
275
276
248
152
149
150
151
157
157
156
156
155
153
158
158
153
120
120
237
239
238
240
132
131
137
213
0x2
CRC1 Out High
CRC1 Out Low
0x2
0x2
CRC1 Polynomial High
CRC1 Polynomial Low
DC0 Configuration
0x2
0x2
DC0CN
0x2
DC0 Control
DC0MD
0x2
DC0 Mode
DC0RDY
DEVICEID
DMA0BUSY
DMA0EN
DMA0INT
DMA0MINT
DMA0NAOH
DMA0NAOL
DMA0NBAH
DMA0NBAL
DMA0NCF
DMA0NMD
DMA0NSZH
DMA0NSZL
DMA0SEL
DPH
0x2
DC0 Ready
0xF
Device ID
0x2
DMA0 Busy
0x2
DMA0 Enable
0x2
DMA0 Interrupt
0x2
DMA0 Mid
e Interrupt
DMA0 Add
s Offset High (Selected Channel)
DMA0 Address Offset Low (Selected Channel)
D
Base Address High (Selected Channel)
DMA0 Base Address Low (Selected Channel)
DMA0 Configuration
0x2
0x2
0x2
0x2
0
0x2
DMA0 Mode (Selected Channel)
DMA0 Size High (Selected Channel)
DMA0 Size Low (Selected Channel)
DMA0 Channel Select
Data Pointer High
0x2
0x2
0x2
All Pages
All Pages
All Pages
All Pages
All Pages
All Pages
0x0
DPL
Data Pointer Low
E1
Extended Interrupt Enable 1
Extended Interrupt Enable 2
Extended Interrupt Priority 1
Extended Interrupt Priority 2
EMIF Configuration
EIE2
EIP1
EIP2
EMI0CF
EMI0CN
0x0
EMIF Control
EMI0TC
0x0
EMIF Timing Control
ENC0CN
0x2
ENC0 Control
224
Rev. 1.0
Si102x/3x
Table 16.3. Special Function Registers
(Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address SFR
Page
Description
Page
ENC0H
0xC4
0xC2
0xC3
0xB7
0xB6
0xE5
0xB5
0xA8
0xB8
0xB9
0xB9
0xE4
0x2
0x2
214
ENC0 High
ENC0L
ENC0M
FLKEY
FLSCL
FLWR
FRBCN
IE
214
214
254
255
255
256
235
236
103
102
242
ENC0 Low
0x2
ENC0 Middle
All Pages
0xF
Flash Lock And Key
Flash Scale Register
Flash Write Only
0x0
0xF
Flash Read Buffer Control
Interrupt Enable
All Pages
All Pages
0xF
IP
Interrupt Priority
IREF0CF
IREF0CN
IT01CF
Current Reference IREF0 Configuration
Current Reference IREF0 Configuration
INT0/INT1 Configuration
0x0
0x0 and
0xF
LCD0BLINK
LCD0BUFCF
LCD0BUFCN
LCD0BUFMD
LCD0CF
0x9E
0xAC
0x9C
0xB6
0xA5
0xAD
0xB5
0xAE
0xAA
0xA9
0x9D
9C
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x91
0x92
0x93
0x2
0xF
0xF
0x2
0x2
0x2
0x
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
346
350
349
350
348
349
348
349
345
345
337
341
335
335
335
335
335
335
335
335
335
LCD0 Blink Mask
LCD0 Buffer Configuration
LCD0 Bu
ontrol
LCD0
uffer Mode
L
0 Configuration
LCD0 Charge Pump Configuration
LCD0 Charge Pump Control
LCD0 Charge Pump Mode
LCD0 Clock Divider High
LCD0 Clock Divider Low
LCD0 Control
LCD0CHPCF
LCD0CHPCN
LCD0CHPMD
LCD0CLKDIVH
LCD0CLKDIVL
LCD0CN
LCD0CNTRST
LCD0D0
LCD0 Contrast
LCD0 Data 0
LCD0
LCD0 Data 1
D0D2
LCD0 Data 2
LCD0D3
LCD0 Data 3
LCD0D4
LCD0 Data 4
LCD0D5
LCD0 Data 5
LCD0D6
LCD0 Data 6
LCD0D7
LCD0 Data 7
LCD0D8
LCD0 Data 8
Rev. 1.0
225
Si102x/3x
Table 16.3. Special Function Registers
(Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address SFR
Page
Description
Page
LCD0D9
0x94
0x95
0x96
0x97
0x99
0x9A
0x9B
0xAC
0xAB
0xA4
0x9F
0xAF
0xA6
0xB3
0xB2
0xB1
0xA4
0xC7
0xD7
0xF1
0xA4
0xD4
0x80
0xA5
0xBF
0xCF
0xF2
0xA5
0xD5
0x90
0xA6
0xF3
0xA6
0xD6
0x2
0x2
335
LCD0 Data 9
LCD0 Data A
LCD0 Data B
LCD0 Data C
LCD0 Data D
LCD0 Data E
LCD0 Data F
LCD0DA
LCD0DB
LCD0DC
LCD0DD
LCD0DE
LCD0DF
LCD0MSCF
LCD0MSCN
LCD0PWR
LCD0TOGR
LCD0VBMCF
LCD0VBMCN
OSCICL
OSCICN
OSCXCN
P0DRV
335
335
335
335
335
335
343
342
343
347
350
344
293
292
294
366
361
361
365
365
364
364
368
362
362
367
368
367
366
371
370
370
369
0x2
0x2
0x2
0x2
0x2
0x2
LCD0 Master Configuration
LCD0 Master Control
LCD0 Power
0x2
0x2
0x2
LCD0
T
o
ggle Rate
0x2
LCD0 VBAT Monitor Configuration
LCD0 VBAT Monit
ontrol
Internal Oscillator Calibration
Internal Os
illator Control
External O
llator Control
Port 0 Drive Strength
P
Mask
0x2
0xF
0x0
0x0
0xF
0x0
P0MASK
P0MAT
0x0
Port 0 Match
P0MDIN
P0MDOUT
P0SKIP
0
Port 0 Input Mode Configuration
Port 0 Output Mode Configuration
Port 0 Skip
0x0
0x0
P0
All Pages
0xF
0x0
Port 0 Latch
P1DRV
Port 1 Drive Strength
Port 1 Mask
P1MASK
P1MAT
0x0
Port 1 Match
MDIN
P
MDOUT
P1SKIP
0x0
Port 1 Input Mode Configuration
Port 1 Output Mode Configuration
Port 1 Skip
0x0
0x0
P1
All Pages
0xF
0x0
Port 1 Latch
P2DRV
Port 2 Drive Strength
Port 2 Input Mode Configuration
Port 2 Output Mode Configuration
Port 2 Skip
P2MDIN
P2MDOUT
P2SKIP
0x0
0x0
226
Rev. 1.0
Si102x/3x
Table 16.3. Special Function Registers
(Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address SFR
Page
Description
Page
P2
0xA0
0xA1
0xF1
0xB1
0xB0
0xA2
0xF2
0xF9
0xD9
0xA3
0xF3
0xFA
0xDA
0xAA
0xF4
0xFB
0xDB
0xAB
0xFC
0xDC
0xE3
0xE1
0xE2
0xF3
0xF1
0xF2
0xDC
0xDA
0xD8
0xDF
0xDD
0xFA
0xF9
0xF4
All Pages
0xF
0xF
0xF
All Pages
0xF
0xF
0xF
0xF
0xF
0xF
0xF
0xF
0xF
0xF
0xF
0xF
0xF
0xF
0
0x2
369
Port 2 Latch
P3DRV
P3MDIN
P3MDOUT
P3
373
372
372
371
375
374
374
373
377
376
376
375
379
378
378
377
380
380
379
329
329
329
330
330
330
327
327
327
328
328
325
326
331
Port 3 Drive Strength
Port 3 Input Mode Configuration
P3 Mode Out
Port 3
P4DRV
Port 4 Drive Strength
Port 4 Input Mode Configuration
P4 Mode Out
P4MDIN
P4MDOUT
P4
Port 4 Latch
P5DRV
Port 5 Drive Strength
Port 5 Input Mode Configuration
P5 Mode Out
P5MDIN
P5MDOUT
P5
Port 5 Latch
P6DRV
Port 6 Drive Strength
Port 6 Inpu
Mode Configuration
P6 Mode O
P6MDIN
P6MDOUT
P6
Port 6 Latch
P7DRV
P
Drive Strength
P7 Mode Out
P7MDOUT
P7
Port 7 Latch
PC0CMP0H
PC0CMP0L
PC0CMP0M
PC0CMP1H
PC0CMP1L
PC0CMP1M
P
TR0H
P
0CTR0L
PC0CTR0M
PC0CTR1H
PC0CTR1L
PC0DCH
PC0DCL
PC0HIST
PC0 Comparator 0 High
PC0 Comparator 0 Low
PC0 Comparator 0 Middle
PC0 Comparator 1 High
PC0 Comparator 1 Low
PC0 Comparator 1 Middle
PC0 Counter 0 High
PC0 Counter 0 Low
PC0 Counter 0 Middle
PC0 Counter 1 High
PC0 Counter 1 Low
PC0 Debounce Configuration High
PC0 Debounce Configuration Low
PC0 History
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x2
Rev. 1.0
227
Si102x/3x
Table 16.3. Special Function Registers
(Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address SFR
Page
Description
Page
PC0INT0
0xFB
0xFC
0xD9
0xD7
0xC1
0xE4
0xD8
0xFC
0xEA
0xEC
0xEE
0xFE
0xD3
0xFB
0xE9
0xEB
0xED
0xFD
0xD2
0xDA
0xDB
0xDC
0xDD
0xDE
0xCE
0x2
0x2
332
PC0 Interrupt 0
PC0 Interrupt 1
PC0 Mode
PC0INT1
PC0MD
333
321
322
324
323
519
524
524
524
524
524
524
524
524
524
524
524
524
522
522
522
522
522
522
523
523
520
521
260
261
268
265
266
0x2
PC0PCF
0x2
PC0 Pull-up Configuration
PC0 Status
PC0STAT
PC0TH
0x2
0x2
PC0 Threshold
PCA0CN
All Pages
0x0
PCA0 Control
PCA0CPH0
PCA0CPH1
PCA0CPH2
PCA0CPH3
PCA0CPH4
PCA0CPH5
PCA0CPL0
PCA0CPL1
PCA0CPL2
PCA0CPL3
PCA0CPL4
PCA0CPL5
PCA0CPM0
PCA0CPM1
PCA0CPM2
PCA0CPM3
PCA0CPM4
PCA0CPM5
PCA0H
PCA0 Capture 0 High
PCA0 Capture 1 High
PCA0 Capture 2 High
PCA0 Capture 3 High
PCA0 Capture 4 High
PCA0 Capture 5 H
PCA0 Capture 0 Low
PCA0 Cap
re 1 Low
PCA0 Cap
e 2 Low
PCA0 Capture 3 Low
P
Capture 4 Low
PCA0 Capture 5 Low
PCA0 Module 0 Mode Register
PCA0 Module 1 Mode Register
PCA0 Module 2 Mode Register
PCA0 Module 3 Mode Register
PCA0 Module 4 Mode Register
PCA0 Module 5 Mode Register
PCA0 Counter High
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0
0x0
0x0
0x0
0x0
0x0
0x0
A0L
0xF9
0xD9
0xDF
0xF5
0xFE
0x87
0xB5
0xB6
0x0
PCA0 Counter Low
CA0MD
0x0
PCA0 Mode
PCA0PWM
PCLKACT
PCLKEN
0x0
PCA0 PWM Configuration
Peripheral Clock Enable Active Mode
Peripheral Clock Enables (LP Idle)
Power Control
0xF
0xF
All Pages
0x0
PCON
PMU0CF
PMU0 Configuration 0
PMU0 flag
PMU0FL
0x0
228
Rev. 1.0
Si102x/3x
Table 16.3. Special Function Registers
(Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address SFR
Page
Description
Internal Oscillator Calibration
Page
PMU0MD
0xB3
0x84
0x8F
0xD0
0xD1
0xC9
0xEA
0xEF
0xAC
0xAD
0xAE
0x99
0x98
0x86
0x85
0xA7
0x8E
0xF5
0xF4
0xC1
0xC0
0xC2
0xA1
0xA2
0xF8
0xA3
0xA1
0xA2
0xF8
0xA3
0x81
0x88
0x8C
0x8D
0x0
All Pages
All Pages
All Pages
0x0
267
PSBANK
PSCTL
126
253
122
101
277
249
285
298
299
298
408
407
220
219
218
217
392
391
387
389
393
418
420
419
420
431
433
432
433
121
489
492
492
Flash Page Switch Bank SFR
Program Store R/W Control
Program Status Word
Voltage Reference Control
Voltage Regulator (REG0) Control
Revision ID
PSW
REF0CN
REG0CN
REVID
0x0
0xF
RSTSRC
RTC0ADR
RTC0DAT
RTC0KEY
SBUF0
0x0
Reset Source Configuration/Status
RTC0 Address
0x0
0x0
RTC0 Data
0x0
RTC0 Key
0x0
UART0 Data Buffer
UART0 Control
SCON0
All Pages
All Pages
All Pages
All Pages
0xF
SFRLAST
SFRNEXT
SFRPAGE
SFRPGCN
SMB0ADM
SMB0ADR
SMB0CF
SMB0CN
SMB0DAT
SPI0CFG
SPI0CKR
SPI0CN
SPI0DAT
S
1CFG
S
I1CKR
SPI1CN
SPI1DAT
SP
SFR Page Stack Last
SFR Page
tack Next
SFR Page
SFR Page Control
S
s Slave Address Mask
SMBus Slave Address
SMBus0 Configuration
SMBus0 Control
0x0
0x0
0
All Pages
0x0
SMBus0 Data
0x0
SPI0 Configuration
SPI0 Clock Rate Control
SPI0 Control
0x0
0x0
0x0
SPI0 Data
0x2
SPI1 Configuration
SPI1 Clock Rate Control
SPI1 Control
0x2
0x2
0x2
SPI1 Data
All Pages
All Pages
0x0
Stack Pointer
TCON
Timer/Counter Control
Timer/Counter 0 High
Timer/Counter 1 High
TH0
TH1
0x0
Rev. 1.0
229
Si102x/3x
Table 16.3. Special Function Registers
(Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address SFR
Page
Description
Page
TL0
0x8A
0x8B
0x89
0xC8
0xCD
0xCC
0xCB
0xCA
0x91
0x95
0x94
0x93
0x92
0xBB
0xBD
0xFF
0xE1
0x0
0x0
491
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
TL1
491
490
496
498
498
497
497
502
504
504
503
503
98
TMOD
0x0
TMR2CN
TMR2H
TMR2L
All Pages
0x0
Timer/Counter 2 Control
Timer/Counter 2 High
0x0
Timer/Counter 2 Low
TMR2RLH
TMR2RLL
TMR3CN
TMR3H
TMR3L
0x0
Timer/Counter 2 Reload High
Timer/Counter 2 Reload Low
Timer/Counter 3 Control
Timer/Counter 3 High
0x0
0x0
0x0
0x0
Timer/Counter 3 Low
0x0
TMR3RLH
TMR3RLL
TOFFH
Timer/Counter 3 Reload High
Timer/Counter 3 R
ad Low
T
e
mperature Offset High
T
e
mperatu
Offset Low
VDD Monit
Control
0x0
0xF
0xF
98
TOFFL
All Pages
282
358
VDM0CN
XBR0
0x0 and
0xF
Port I/O Crossbar Control 0
0xE2
0xE3
0x0 and
0xF
359
360
XBR1
XBR2
Port I/O Crossbar Control 1
Port I/O Crossbar Control 2
0x0
nd
0xF
230
Rev. 1.0
Si102x/3x
17. Interrupt
Handler
The Si102x/3x microcontroller family includes an extended interrupt system supporting multiple interrupt
sources and two priority levels. The allocation of interrupt sources between on-chip peripherals and exter-
nal input pins varies according to the specific version of the device. Refer to
T
a
ble 17.1, “Interrupt Sum-
mary,” on page 233 for a detailed listing of all interrupt sources supported by the device. Refer to the data
sheet section associated with a particular on-chip peripheral for information regarding valid interrupt con
tions for the peripheral and the behavior of its interrupt-pending flag(s).
Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR or an indi-
rect register. When a peripheral or external source meets a valid interrupt condition, the asso
ted inter-
rupt-pending flag is set to logic 1. If both global interrupts and the specific interrupt sou
e is enabled, a
CPU interrupt request is generated when the interrupt-pending flag is set.
As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predeter-
mined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt
nding flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt’s enable/disable state.)
Some interrupt-pending flags are automatically cleared by hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU
pletes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediate
y and the CPU will re-enter the ISR after
the completion of the next instruction.
17.1. Enabling
Interrupt Sources
Each interrupt source can be individually enable
or disabled through the use of an associated interrupt
enable bit in the Interrupt Enable and Exten
Interrupt Enable SFRs. However, interrupts must first be
globally enabled by setting the EA bit (IE.7)
ogic 1 before the individual interrupt enables are recog-
nized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-
enable settings. Note that interrupts
ich occur when the EA bit is set to logic 0 will be held in a pending
state, and will not be serviced until th
EA bit is set back to logic 1.
17.2. MCU
Interrupt Sources and Vectors
The CPU services interrupts by generating an LCALL to a predetermined address (the interrupt vector
address) to begin execution of an interrupt service routine (ISR). The interrupt vector addresses associ-
ated with each interrupt source are listed in
T
a
ble 17.1 on page 233. Software should ensure that the inter-
rupt vector for each
bled interrupt source contains a valid interrupt service routine.
Software can s
mulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled
for the flag
n interrupt request will be generated and the CPU will vector to the ISR address associated
with t
interrupt-pending flag.
Rev. 1.0
231
Si102x/3x
17.3. Interrupt
Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. If a high priority interrupt preempts a low priority interrupt, the low priority interrupt will finish
execution after the high priority interrupt completes. Each interrupt has an associated interrupt priority bit in
in the Interrupt Priority and Extended Interrupt Priority registers used to configure its priority level. Low pri
ority is the default.
If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both
interrupts have the same priority level, a fixed priority order is used to arbitrate. See
T
a
ble
17.1 on
page 233 to determine the fixed priority order used to arbitrate between simultaneously reco
ized inter-
rupts.
17.4. Interrupt
Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 7
system clock cycles: 1 clock cycle to detect the interrupt, 1 clock cycle to ex
te a single instruction, and
5 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a sin-
gle instruction is executed before an LCALL is made to service the pending
nterrupt. Therefore, the maxi-
mum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt
is of greater priority) occurs when the CPU is performing an RETI
nstruction followed by a DIV as the next
instruction. In this case, the response time is 19 system clock
cles: 1 clock cycle to detect the interrupt,
5 clock cycles to execute the RETI, 8 clock cycles to comple
e DIV instruction and 5 clock cycles to
execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority,
the new interrupt will not be serviced until the curren
ISR completes, including the RETI and following
instruction.
232
Rev. 1.0
Si102x/3x
Table 17.1. Interrupt Summary
Interrupt Source
Interrupt Priority
Vector Order
Pending Flag
Enable
Flag
Priority
Control
Reset
0x0000
T
o
p
None
N/A N/A
Always
Ena
Always
Highest
External Interrupt 0 (INT0)
0x0003
Timer 0 Overflow
0x000B
External Interrupt 1 (INT1)
0x0013
0
1
2
3
4
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
EX0 (
PX0 (I
P
.
0)
ET0 (IE.1)
PT0 (I
P
.
1)
EX1 (IE.2)
PX1 (I
P
.
2)
ET1 (IE.3)
PT1 (I
P
.
3)
ES0 (IE.4)
PS0 (I
P
.
4)
Timer 1 Overflow
UART0
0x001B
0x0023
RI0 (SCON0.0)
TI0 (SCON0.1)
Timer 2 Overflow
SPI0
0x002B
0x0033
5
6
TF2H (TMR2CN.7)
TF2L (TMR
.6)
Y
Y
N
N
ET2 (IE.5)
PT2 (I
P
.
5)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MO
(SPI0CN.5)
R
OVRN (SPI0CN.4)
ESPI0
(IE.6)
PSPI0
(I
P
.
6)
SMB0
0x003B
0x0043
7
SI (SMB0CN.0)
Y
N
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
SmaRTClock Alarm
8
ALRM (RTC0CN.2)*
EARTC0
(EIE1.1)
PARTC0
(EIP1.1)
ADC0 Window Compara-
0x004B
tor
9
AD0WINT
(ADC0CN.3)
EWADC0 PWADC0
(EIE1.2)
(EIP1.2)
ADC0 End of Conversion
0x0053
0x005B
0x0063
0x006B
0x0073
10
11
12
13
14
15
16
AD0INT (ADC0STA.5)
EADC0
(EIE1.3)
PADC0
(EIP1.3)
Programmable Co
r
Array
CF (PCA0CN.7)
CCFn (PCA0CN.n)
EPCA0
(EIE1.4)
PPCA0
(EIP1.4)
Comparator0
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
ECP0
(EIE1.5)
PCP0
(EIP1.5)
Co
rator1
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
ECP1
(EIE1.6)
PCP1
(EIP1.6)
Timer 3 Overflow
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
ET3
(EIE1.7)
PT3
(EIP1.7)
1
VDD/VBAT Supply Monitor
0x007B
Early Warning
VDDOK (VDM0CN.5)
VBOK (VDM0CN.2)
EWARN
(EIE2.0)
PWARN
(EIP2.0)
1
Port Match
0x0083
None
EMAT
PMAT
(EIE2.1)
(EIP2.1)
Rev. 1.0
233
Si102x/3x
Table 17.1. Interrupt Summary
Interrupt Source
Interrupt Priority
Vector Order
Pending Flag
Enable
Flag
Priority
Control
SmaRTClock Oscillator
Fail
0x008B
0x0093
17
18
OSCFAIL
(RTC0CN.5)
N
N
N
N
ERTC0F PFRTC0F
2
(EIE2.2)
(EIP2.2)
SPI1
SPIF (SPI1CN.7)
WCOL (SPI1CN.6)
MODF (SPI1CN.5)
RXOVRN (SPI1CN.4)
E
PSPI1
(EIE2
(EIP2.3)
Pulse Counter
DMA0
0x009B
0x00A3
0x00AB
0x00B3
19
20
21
22
C0ZF (PC0CN.4)
C1ZF (PC0CN.6)
N
N
N
N
N
N
N
EPC0
(EIE2.4)
PPC0
(EIP2.4)
DMAINT0…7
DMAMINT0…7
EDMA0
(EIE2.5)
PDMA0
(EIP2.5)
Encoder0
AES
ENCERR(ENCCN.6)
EENC0
(EIE2.6)
PENC0
(EIP2.6)
AESDONE
EAES0
PAES0
(EIE2.7)
(EIP2.7)
(
ESBC
F
.
5)
Notes:
1.
Indicates a read-only interrupt pending flag. Th
interrupt enable may be used to prevent software from
vectoring to the associated interrupt servic
utine.
2.
Indicates a register located in an indirect m
ory space.
17.5. Interrupt
Register Descriptions
The SFRs used to enable the interr
pt sources and set their priority level are described in the following
register descriptions. Refer to the data sheet section associated with a particular on-chip peripheral for
information regarding valid in
errupt conditions for the peripheral and the behavior of its interrupt-pending
flag(s).
234
Rev. 1.0
Si102x/3x
SFR Definition 17.1. IE: Interrupt Enable
Bit
7
EA
R/W
0
6
ESPI0
R/W
0
5
4
3
2
1
0
Name
Type
Reset
ET2
R/W
0
ES0
R/W
0
ET1
R/W
0
EX1
R/W
0
ET0
R/W
0
EX0
R/W
0
SFR Page = All Pages; SFR Address = 0xA8; Bit-Addressable
Bit
Name
Function
7
EA
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6
5
4
3
2
1
0
ESPI0
Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by S
ET2
ES0
ET1
EX1
ET0
EX0
Enable Timer 2 Interrupt.
This bit sets the masking of the Tim
interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests ge
erated by the TF2L or TF2H flags.
Enable UART0 Interrupt.
This bit sets the mask
ng of the UART0 interrupt.
0: Disable UART0
errupt.
1: Enable UART0
terrupt.
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
E
le External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
Rev. 1.0
235
Si102x/3x
SFR Definition 17.2. IP: Interrupt Priority
Bit
7
6
PSPI0
R/W
0
5
4
3
2
1
0
Name
Type
Reset
PT2
R/W
0
PS0
R/W
0
PT1
R/W
0
PX1
R/W
0
PT0
R/W
0
PX0
R/W
0
R
1
SFR Page = 0x0; SFR Address = 0xB8; Bit-Addressable
Bit
Name
Function
7
Unused Read
= 1b, Write = don’t care.
6
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5
4
3
2
1
0
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interr
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
UART0 Interrupt Priority Contro
This bit sets the priority of the
RT0 interrupt.
0: UART0 interrupt set to lo
priority level.
1: UART0 interrupt set to
priority level.
Timer 1 Interrupt Priority Control.
This bit sets the p
rity of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0
xternal Interrupt 1 set to low priority level.
1
ternal Interrupt 1 set to high priority level.
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
236
Rev. 1.0
Si102x/3x
SFR Definition 17.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
ECP1
R/W
0
5
ECP0
R/W
0
4
EPCA0
R/W
0
3
EADC0
R/W
0
2
1
0
ESMB0
R/W
0
Name
Type
Reset
ET3
R/W
0
EWADC0 ERTC0A
R/W
0
R/W
0
SFR Page = All Pages; SFR Address = 0xE6
Bit
Name
Function
7
ET3
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6
5
4
3
2
1
0
ECP1
ECP0
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by t
P1RIF or CP1FIF flags.
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP
terrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests ge
erated by the CP0RIF or CP0FIF flags.
EPCA0
Enable Programmable C
er Array (PCA0) Interrupt.
This bit sets the mask
ng of the PCA0 interrupts.
0: Disable all PCA
nterrupts.
1: Enable interrup
requests generated by PCA0.
EADC0
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
EWADC0
E
ble Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
ERTC0A
Enable SmaRTClock Alarm Interrupts.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by a SmaRTClock Alarm.
ESMB0
Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Rev. 1.0
237
Si102x/3x
SFR Definition 17.4. EIP1: Extended Interrupt Priority 1
Bit
7
6
PCP1
R/W
0
5
PCP0
R/W
0
4
PPCA0
R/W
0
3
PADC0
R/W
0
2
1
0
PSMB0
R/W
0
Name
Type
Reset
PT3
R/W
0
PWADC0 PRTC0A
R/W
0
R/W
0
SFR Page = All Pages; SFR Address = 0xF6
Bit
Name
Function
7
PT3
Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6
5
4
3
2
1
0
PCP1
PCP0
Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0
rrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high pri
ity level.
PPCA0
Programmable Counter
y (PCA0) Interrupt Priority Control.
This bit sets the priori
y of the PCA0 interrupt.
0: PCA0 interrupt
t to low priority level.
1: PCA0 interrupt
et to high priority level.
PADC0
ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
PWADC0
A
0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
PRTC0A
SmaRTClock Alarm Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
PSMB0
SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
238
Rev. 1.0
Si102x/3x
SFR Definition 17.5. EIE2: Extended Interrupt Enable 2
Bit
7
EAES0
R/W
0
6
EENC0
R/W
0
5
EDMA0
R/W
0
4
EPC0
R/W
0
3
ESPI1
R/W
0
2
ERTC0F
R/W
1
EMAT
R/W
0
0
EWARN
R/W
0
Name
Type
Reset
0
SFR Page = All Pages;SFR Address = 0xE7
Bit
Name
Function
7
EAES0
Enable AES0 Interrupt.
This bit sets the masking of AES0 interrupts.
0: Disable all AES0 interrupts.
1: Enable interrupt requests generated by AES0.
6
5
4
3
2
1
0
EENC0
Enable Encoder (ENC0) Interrupt.
This bit sets the masking of ENC0 interrupts.
0: Disable all ENC0 interrupts.
1: Enable interrupt requests generated by
0.
EDMA0
Enable DMA0 Interrupt.
This bit sets the masking of DMA0
errupts.
0: Disable all DMA0 interrupts.
1: Enable interrupt requests g
nerated by DMA0.
EPC0
Enable Pulse Counter (P
Interrupt.
This bit sets the masking of PC0 interrupts.
0: Disable all PC0
terrupts.
1: Enable interrup
requests generated by PC0.
ESPI1
Enable Serial Peripheral Interface (SPI1) Interrupt.
This bit sets the masking of the SPI1 interrupts.
0: Disable all SPI1 interrupts.
1: Enable interrupt requests generated by SPI1.
ERTC0F
ble SmaRTClock Oscillator Fail Interrupt.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by SmaRTClock Alarm.
EMAT
Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
EWARN
Enable VDD/DC+ Supply Monitor Early Warning Interrupt.
This bit sets the masking of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: Disable the VDD/DC+ Supply Monitor Early Warning interrupt.
1: Enable interrupt requests generated by VDD/DC+ Supply Monitor.
Rev. 1.0
239
Si102x/3x
SFR Definition 17.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
5
4
PPC0
R
3
PSPI1
R/W
0
2
PRTC0F
R/W
1
PMAT
R/W
0
0
PWARN
R/W
0
Name
Type
Reset
PAES0
PENC0
PDMA0
R
0
R
0
R
0
0
0
SFR Page = All Pages; SFR Address = 0xF7
Bit
Name
Function
7
PAES0
AES0 Interrupt Priority Control.
This bit sets the priority of the AES0 interrupt.
0: AES0 interrupt set to low priority level.
1: AES0 interrupt set to high priority level.
6
5
4
3
2
1
0
PENC0
Encoder (ENC0) Interrupt Priority Control.
This bit sets the priority of the ENC0 interrupt.
0: ENC0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
PDMA0
DMA0 Interrupt Priority Control.
This bit sets the priority of the DM
nterrupt.
0: DMA0 interrupt set to low priority level.
1: DMA0 interrupt set to high p
ior
ty level.
PPC0
Pulse Counter (PC0) Int
pt Priority Control.
This bit sets the prior
ty of the PC0 interrupt.
0: PC0 interrupt s
to low priority level.
1: PC0 interrupt s
t to high priority level.
PSPI0
Serial Peripheral Interface (SPI1) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI1 interrupt set to low priority level.
1: SPI1 interrupt set to high priority level.
PRTC0F
RTClock Oscillator Fail Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
PMAT
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
PWARN
VDD/DC+ Supply Monitor Early Warning Interrupt Priority Control.
This bit sets the priority of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: VDD/DC+ Supply Monitor Early Warning interrupt set to low priority level.
1: VDD/DC+ Supply Monitor Early Warning interrupt set to high priority level.
240
Rev. 1.0
Si102x/3x
17.6. External
Interrupts INT0 and INT1
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “33.1. Timer 0 and Timer 1” on page 485) select level or
edge sensitive. The table below lists the possible configurations.
IT0
1
IN0PL
INT0 Interrupt
IT1
1
IN1PL
INT1 Interrupt
0
1
0
1
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
0
1
0
1
Active low, edge sensitive
Active high, edge
ensitive
Active low,
ensitive
Active high, level sensitive
1
1
0
0
0
0
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 17.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar
ssignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar.
T
o
a
ssign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “27.3. Priority Crossbar
Decoder” on page 355 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pendin
gs for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the
ardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending fla
mains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL
he flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input acti
e until the interrupt request is recognized. It must then
deactivate the interrupt request before exec
of the ISR completes or another interrupt request will be
generated.
Rev. 1.0
241
Si102x/3x
SFR Definition 17.7. IT01CF: INT0/INT1 Configuration
Bit
7
IN1PL
R/W
0
6
5
IN1SL[2:0]
R/W
4
3
IN0PL
R/W
0
2
1
IN0SL[2:0]
R/W
0
Name
Type
Reset
0
0
0
0
0
1
SFR Page = 0x0; SFR Address = 0xE4
Bit
Name
Function
7
IN1PL
INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
6:4 IN1SL[2:0]
INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned t
Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral i
s configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P1.6
111: Select P1.7
3
IN0PL
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
2:0 IN0SL[2:0]
INT0 Port Pin Selection Bits.
se bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P1.6
111: Select P1.7
242
Rev. 1.0
Si102x/3x
18. Flash
Memory
On-chip, re-programmable flash memory is included for program code and non-volatile data storage. The
flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft-
ware using the MOVX write instruction. Once cleared to logic 0, a flash bit must be erased to set it back to
logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and
erase operations are automatically timed by hardware for proper execution; data polling to determine t
end of the write/erase operations is not required. Code execution is stalled during flash write/erase opera
tions. Refer to
T
a
ble 4.8 for complete flash memory electrical characteristics.
18.1. Programming
the Flash Memory
The simplest means of programming the flash memory is through the C2 interface
programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means f
gramming a
non-initialized device. For details on the C2 commands to program flash memory, see Section “35. C2
Interface” on page 525.
The flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before progr
mming flash memory using
MOVX, flash programming operations must be enabled by: (1) setting the PSWE Program Store Write
Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target flash memory); and (2) Writing the
flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by
software.
For detailed guidelines on programming flash from firmware, please see Section “18.5. Flash
Write and Erase Guidelines” on page 249.
To
e
nsure the integrity of the flash contents, the on-chip VDD Monitor must be enabled and enabled as a
reset source in any system that includes code that wri
es and/or erases flash memory from software. Fur-
thermore, there should be no delay between enablin
V Monitor
and enabling the V
Monitor as a
DD
DD
reset source. Any attempt to write or erase flash
mory while the V
Monitor is disabled, or not enabled
DD
as a reset source, will cause a flash error devi
e reset.
18.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The flash lock and key
register (FLKEY) must be written wi
the correct key codes, in sequence, before flash operations may be
performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be written in
order. If the key codes are written out of order, or the wrong codes are written, flash writes and erases will
be disabled until the next system reset. Flash writes and erases will also be disabled if a flash write or
erase is attempted before the key codes have been written properly. The flash lock resets after each write
or erase; the key codes must be written again before a following flash operation can be performed. The
FLKEY register is d
led in SFR Definition 18.4.
18.1.2. Flash Erase Procedure
The flash m
mory is organized in 1024-byte pages. The erase operation applies to an entire page (setting
all byt
s in
he page to 0xFF).
T
o
e
rase an entire 1024-byte page, perform the following steps:
1
ave current interrupt state and disable interrupts.
2. Set the PSEE bit (register PSCTL).
3. Set the PSWE bit (register PSCTL).
4. If writing to an address in Banks 1, 2, or 3, set the COBANK[1:0] bits (register PSBANK) for the
appropriate bank.
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a data byte to any location within the 1024-byte page to be erased.
8. Clear the PSWE and PSEE bits.
Rev. 1.0
243
Si102x/3x
9. Restore previous interrupt state.
Steps 4–7 must be repeated for each 1024-byte page to be erased.
Notes:
1.
Flash security settings may prevent erasure of some flash pages, such as the reserved area and the page
containing the lock bytes. For a summary of flash security settings and restrictions affecting flash erase
operations, please see Section “18.3. Security Options” on page 246.
2.
8-bit MOVX instructions cannot be used to erase or write to flash memory at addresses higher than 0x00F
F
.
18.1.3. Flash Write Procedure
A write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in flash.
A byte location to be programmed should be erased before a new valu
s written.
The recommended procedure for writing a single byte in flash is as follows:
1. Save current interrupt state and disable interrupts.
2. Set the PSWE bit (register PSCTL).
3. Clear the PSEE bit (register PSCTL).
4. If writing to an address in Banks 1, 2, or 3, set the COBANK[1:0] bits (r
gis
er PSBANK) for the
appropriate bank.
5. Ensure that the flash byte has been erased (has a value of 0xFF).
6. Write the first key code to FLKEY: 0xA5.
7. Write the second key code to FLKEY: 0xF1.
8. Using the MOVX instruction, write a single data byte to the desired location within the 1024-byte
sector.
9. Clear the PSWE bit.
10. Restore previous interrupt state.
Steps 2–8 must be repeated for each byte to
written.
Notes:
1.
Flash security settings may preve
writes to some areas of flash, such as the reserved area. For a summary of
flash security settings and restrict
ons affecting flash write operations, please see Section “18.3. Security
Options” on page 246.
2.
8-bit MOVX instructions cannot be used to erase or write to flash memory at addresses higher than 0x00F
F
.
244
Rev. 1.0
Si102x/3x
18.1.4. Flash Write Optimization
The flash write procedure includes a block write option to optimize the time to perform consecutive byte
writes. When block write is enabled by setting the CHBLKW bit (FLRBCN.0), writes to flash will occur in
blocks of 4 bytes and require the same amount of time as a single byte write. This is performed by caching
the bytes whose address end in 00b, 01b, and 10b that is written to flash and then committing all four bytes
to flash when the byte with address 11b is written. When block writes are enabled, if the write to the byte
with address 11b does not occur, the other three data bytes written is not committed to flash.
A write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in flash.
The flash block to be programmed should be erased before a new value is writ
en.
The recommended procedure for writing a 4-byte flash block is as follows:
1. Save current interrupt state and disable interrupts.
2. Set the CHBLKW bit (register FLRBCN).
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. If writing to an address in Banks 1, 2, or 3, set the COBANK[1:0] bits (r
gis
er PSBANK) for the
appropriate bank
6. Write the first key code to FLKEY: 0xA5.
7. Write the second key code to FLKEY: 0xF1.
8. Using the MOVX instruction, write the first data byte to t
esired location within the 1024-byte
sector whose address ends in 00b.
9. Write the first key code to FLKEY: 0xA5.
10. Write the second key code to FLKEY: 0xF1.
11. Using the MOVX instruction, write the sec
d data byte to the next higher flash address ending in
01b.
12. Write the first key code to FLKEY: 0xA
13. Write the second key code to FLKEY: 0xF1.
14. Using the MOVX instruction,
te the third data byte to the next higher flash address ending in 10b.
15. Write the first key code to FLKEY: 0xA5.
16. Write the second key code to FLKEY: 0xF1.
17. Using the MOVX instruction, write the final data byte to the next higher flash address ending in 11b.
18. Clear the PSWE bit.
19. Clear the C
KW bit.
20. Restore previous interrupt state.
Steps 5–17
ust be repeated for each flash block to be written.
Note
1
Flash security settings may prevent writes to some areas of flash, such as the reserved area. For a summary of
flash security settings and restrictions affecting flash write operations, please see Section “18.3. Security
Options” on page 246.
2.
8-bit MOVX instructions cannot be used to erase or write to flash memory at addresses higher than 0x00F
F
.
Rev. 1.0
245
Si102x/3x
18.2. Non-volatile
Data Storage
The flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
18.3. Security
Options
The CIP-51 provides security options to protect the flash memory from inadvertent modification by so
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the flash memory from accidental modification by software. PSWE must
explicitly
set to 1 before software can modify the flash memory; both PSWE and PSEE must be se
o 1 before soft-
ware can erase flash memory. Additional security features prevent proprietary program
nd data con-
stants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of flash user space offers protection of the flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The flash security
mechanism allows the user to lock
n
1024-byte flash pages, starting at p
e 0 (addresses 0x0000 to
0x03FF), where
n
is the 1s complement number represented by the Security Lock Byte.
The page con-
taining the Flash Security Lock Byte is unlocked when no other
lash pages are locked (all bits of
the Lock Byte are 1) and locked when any other flash pages are locked (any bit of the Lock Byte is
0).
See example in Figure 18.1. The 128 kB flash devices (Si1020/24/30/34) do not have a reserved area.
The lock byte is at the top of the flash area (0x1FFFF). Writing
x80 to the lock byte of the 128 kB devices
will lock the entire flash.
Security Lock Byte:
ones Complement:
Flash pages locked:
11111101b
00000010b
3 (F
rst two flash pages + Lock Byte Page)
Reserved Area
Lock Byte
Locked when
any other FLASH
es are locked
Lock Byte Page
Unlocked FLASH Pages
Locked Flash Pages
Access limit set
according to the
FLASH security
lock byte
Figure 18.1. Flash Security Example
246
Rev. 1.0
Si102x/3x
The level of flash security depends on the flash access method. The three flash access methods that can
be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages.
T
a
ble 18.1 summarizes the flash security
features of the Si102x/3x devices.
Table 18.1. Flash Security Summary
Action
C2 Debug
Interface
User Firmware executing from:
an unlocked page
a locked page
Read, Write or Erase unlocked pages
(except page with Lock Byte)
Permitted
Permitted
P
rmitted
Permitted
Permitted
Permitted
Permitted
Permitted
Read, Write or Erase locked pages
(except page with Lock Byte)
Not Permitted
Flash Error Reset
Permitted Permitted
Not Permitted
Flash Error Reset
Permitted Permitted
Not Permitted
Flash Error Reset
P
mitted
Read or Write page containing Lock Byte
(if no pages are locked)
Read or Write page containing Lock Byte
(if any page is locked)
Read contents of Lock Byte
(if no pages are locked)
Read contents of Lock Byte
(if any page is locked)
Erase page containing Lock Byte
(if no pages are locked)
Flash Error Reset
Flash Error Reset
Erase page containing Lock Byte—Unlock a
pages (if any page is locked)
C2 Device Erase
Flash Error Reset
Flash Error Reset
Only
Lock additional pages
(change 1s to 0s in the Lock Byte)
Not Permitted
Flash Error Reset
Flash Error Reset
Not Permitted
Flash Error Reset
Flash Error Reset
Not Permitted
Flash Error Reset
Flash Error Reset
Unlock individual pages
(change 0s to 1s in the Lock Byte)
Read, Write or Erase Reserved Area
C2 Device Erase—
ses all flash pages including the page containing the Lock Byte.
Flash Error Reset—Not permitted; Causes flash error device reset (FERROR bit in RSTSRC is 1 after
reset).
– A
hibited operations that are performed via the C2 interface are ignored (do not cause device reset).
– Locking any flash page also locks the page containing the Lock Byte.
– Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
– If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
Rev. 1.0
247
Si102x/3x
18.4. Determining
the Device Part Number at Run Time
In many applications, user software may need to determine the MCU part number at run time in order to
determine the hardware capabilities. The part number can be determined by reading the value of the
DEVICEID Special Function Register.
The value of the DEVICEID register can be decoded as follows:
0xE0—Si1020
0xE1—Si1021
0xE2—Si1022
0xE3—Si1023
0xE4—Si1024
0xE5—Si1025
0xE6—Si1026
0xE7—Si1027
0xE8—Si1030
0xE9—Si1031
0xEA—Si1032
0xEB—Si1033
0xEC—Si1034
0xED—Si1035
0xEE—Si1036
0xEF—Si1037
SFR Definition 18.1. DEVICEID: Device Identification
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
DEVICEID[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xE9
Bit
Name
Function
7:0
DEVICEID[
Device Identification.
These bits contain a value that can be decoded to determine the device part
number.
248
Rev. 1.0
Si102x/3x
SFR Definition 18.2. REVID: Revision Identification
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
REVID[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xEA
Bit
Name
Function
7:0
REVID[7:0]
Revision Identification.
This register indicates the MCU revision.
0x00: Rev A
0x01: Rev B
18.5. Flash
Write and Erase Guidelines
Any system which contains routines which write or erase flash memory from software involves some risk
that the write or erase routines will execute unintentionally if
he CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperat
This accidental execution of flash modi-
fying code can result in alteration of flash memory contents causing a system failure that is only recover-
able by re-flashing the code in the device.
To
h
elp prevent the accidental modification of flash b
rmware, the VDD Monitor must be enabled and
enabled as a reset source on Si102x/3x devices f
the flash to be successfully modified.
If either the VDD
Monitor or the VDD Monitor reset source i
ot enabled, a flash error device reset will be generated
when the firmware attempts to modify the
h.
The following guidelines are recommended for any system that contains routines which write or erase flash
from code.
18.5.1. VDD Maintenance and
he VDD Monitor
1. If the system power supply is subject to voltage or current “spikes,” add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum
Ratings table are not exceeded.
2. Make certain
the minimum VDD rise time specification of 1 ms is met. If the system cannot meet
this rise time s
cification, then add an external VDD brownout circuit to the RST pin of the device
that holds the device in reset until VDD reaches the minimum device operating voltage and re-
asser
RST if VDD drops below the minimum device operating voltage.
3
ep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as early in
ode as possible. This should be the first set of instructions executed after the Reset Vector. For C-
based systems, this will involve modifying the startup code added by the ‘C’ compiler. See your
compiler documentation for more details. Make certain that there are no delays in software between
enabling the VDD Monitor and enabling the VDD Monitor as a reset source. Code examples showing
this can be found in “AN201: Writing to Flash from Firmware,” available from the Silicon Laboratories
web site.
Notes:
On Si102x/3x devices, both the VDD Monitor and the VDD Monitor reset source must be enabled to write
or erase flash without generating a flash error device reset.
Rev. 1.0
249
Si102x/3x
On Si102x/3x devices, both the VDD Monitor and the VDD Monitor reset source are enabled by hardware
after a power-on reset.
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a reset
source inside the functions that write and erase flash memory. The VDD Monitor enable instructions
should be placed just after the instruction to set PSWE to a 1, but before the flash write or erase
operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operator
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, “RSTSRC =
0x02″ is correct, but “RSTSRC |= 0x02” is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a ‘1’.
eas to
check are initialization code which enables other reset sources, such as the missin
k detector or
comparator, for example, and instructions which force a Software Reset. A global s
h on
“RSTSRC” can quickly verify this.
250
Rev. 1.0
Si102x/3x
18.5.2. PSWE Maintenance
1. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should
be exactly one routine in code that sets PSWE to a 1 to write flash bytes and one routine in code that
sets both PSWE and PSEE both to a 1 to erase flash pages.
2. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop maintenance outside the “PSWE = 1;… PSWE = 0;” area. Code examples showing this can
be found in “AN201: Writing to Flash from Firmware,
”
available from the Silicon Laboratories web
site.
3. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
reset to 0. Any interrupts posted during the flash write or erase operation will be serviced
n priority
order after the flash operation has been completed and interrupts have been re-en
d by software.
4. Make certain that the flash write and erase pointer variables are not located in XRA
ee your
compiler documentation for instructions regarding how to explicitly locate variables in different
memory areas.
5. Add address bounds checking to the routines that write or erase flash memory to ensure that a
routine called with an illegal address does not result in modification of
flash.
18.5.3. System Clock
1. If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is operating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
2. If operating from the external oscillator, switch to the inte
oscillator during flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the flash operation has completed
Additional flash recommendations and example
de can be found in “AN201: Writing to Flash from Firm-
ware,” available from the Silicon Laboratories
ebsite.
Rev. 1.0
251
Si102x/3x
18.6. Minimizing
Flash Read Current
The flash memory in the Si102x/3x devices is responsible for a substantial portion of the total digital supply
current when the device is executing code. Below are suggestions to minimize flash read current.
1. Use idle, low power idle, suspend, or sleep modes while waiting for an interrupt, rather than polling
the interrupt flag. Idle mode and low power idle mode is particularly well-suited for use in
implementing short pauses, since the wake-up time is no more than three system clock cycles. Se
the Power Management chapter for details on the various low-power operating modes.
2. The flash memory is organized in 4-byte words starting with a byte with address ending in 00b and
ending with a byte with address ending in 11b. A 4-byte pre-fetch buffer is used to read 4
ytes of
flash in a single read operation. Short loops that straddle word boundaries or have an inst
uction byte
with address ending in 11b should be avoided when possible. If a loop executes i
more clock
cycles, any resulting increase in operating current due to mis-alignment will be negl
e.
3.
T
o
m
inimize the power consumption of small loops, it is best to locate them such that the number of
4-byte words to be fetched from flash is minimized. Consider a 2-byte, 3-cycle loop (e.g., SJMP $, or
while(1);). The flash read current of such a loop will be minimized if both address bytes are contained
in the first 3 bytes of a single 4-byte word. Such a loop should be manu
lly
ocated at an address
ending in 00b or the number of bytes in the loop should be increased (by padding with NOP
instructions) in order to minimize flash read current.
252
Rev. 1.0
Si102x/3x
SFR Definition 18.3. PSCTL: Program Store R/W Control
Bit
7
6
5
4
3
2
1
PSEE
R/W
0
0
PSWE
R/W
0
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
SFR Page =0x0; SFR Address = 0x8F
Bit
7:2
1
Name
Unused Read
= 000000b, Write = don’t care.
PSEE
Program Store Erase Enable.
Function
Setting this bit (in combination with PSWE) allows an enti
page of flash program
memory to be erased. If this bit is logic 1 and flash writes are enabled (PSWE is logic
1), a write to flash memory using the MOVX instruction will erase the entire page that
contains the location addressed by the MOVX instruction. The value of the data byte
written does not matter.
0: Flash program memory erasure disabled
1: Flash program memory erasure enabled.
0
PSWE
Program Store Write Enable.
Setting this bit allows writing a byte
data to the flash program memory using the
MOVX write instruction. The fl
h location should be erased before writing data.
0: Writes to flash program
mory disabled.
1: Writes to flash program
mory enabled; the MOVX write instruction targets flash
memory.
Rev. 1.0
253
Si102x/3x
SFR Definition 18.4. FLKEY: Flash Lock and Key
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
FLKEY[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB6
Bit Name
Function
7:0 FLKEY[7:0]
Flash Lock and Key Register.
Write:
This register provides a lock and key function for flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed
0xF1 to the FLKEY regis-
ter. Flash writes and erases are automatically disabled after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a flash write or erase
operation is attempted while these operations are disabled, the flash will be perma-
nently locked from writes or erasures until the next device reset. If an application
never writes to flash, it can intentionally lo
he flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the
ent flash lock state.
00: Flash is write/erase locked.
01: The first key code has be
n written (0xA5).
10: Flash is unlocked (w
/erases allowed).
11: Flash writes/erases disabled until the next reset.
254
Rev. 1.0
Si102x/3x
SFR Definition 18.5. FLSCL: Flash Scale
Bit
7
6
BYPASS
R/W
5
4
3
2
1
0
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
SFR Page = 0x0; SFR Address = 0xB6
Bit
Name
Function
7
Reserved Always
Write to 0.
6
BYPASS
Flash Read Timing One-Shot Bypass.
0: The one-shot determines the flash read time.
1: The system clock determines the flash read time.
Leaving the one-shot enabled will provide the lowest power consumption up to
25 MHz.
5:0 Reserved
Always Write to 000000.
Note:
Operations which clear the BYPASS bit do not need to be imm
tely followed by a benign 3-byte instruction.
For code compatibility with C8051F930/31/20/21 devices, a benign 3-byte instruction whose third byte is a
don’t care should follow the clear operation. See the C8051F93x-C8051F92x data sheet for more details.
SFR Definition 18.6. FLWR: Flash W
ite Only
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
FLWR[7:0]
W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xE5
Bit Name
7:0 FLWR[7:0]
Flash Write Only.
Function
All writes to this register have no effect on system operation.
Rev. 1.0
255
Si102x/3x
SFR Definition 18.7. FRBCN: Flash Read Buffer Control
Bit
7
6
5
4
3
2
1
FRBD
R/W
0
0
CHBLKW
R/W
Name
Type
Reset
R
0
R
0
R
1
R
0
R
0
R
0
0
SFR Page = 0xF; SFR Address = 0xB5
Bit
7:2
1
Name
Unused
FRBD
Function
Read = 000000b. Write = don’t care.
Flash Read Buffer Disable Bit.
0: Flash read buffer is enabled and being used.
1: Flash read buffer is disabled and bypassed.
0
CHBLKW
Block Write Enable Bit.
This bit allows block writes to flash memory from firmware.
0: Each byte of a software flash write is wr
n individually.
1: Flash bytes are written in groups of four.
256
Rev. 1.0
Si102x/3x
19. Power
Management
Si102x/3x devices support 6 power modes: Normal, Idle, Stop, Low Power Idle, Suspend, and Sleep. The
power management unit (PMU0) allows the device to enter and wake-up from the available power modes.
A brief description of each power mode is provided in
T
a
ble 19.1. Detailed descriptions of each mode can
be found in the following sections.
Table 19.1. Power Modes
Power Mode
Description
Wake-Up
Sources
Power Savings
Normal
Idle
Device fully functional
N/A
Excellent M
mW
All peripherals fully functional.
Very easy to wake up.
Any Interrupt.
Good
No Code Execution
Stop
Legacy 8051 low power mode.
A reset is required to wake up.
Any Reset.
Good
No Code Execution
Precision Oscillator Disabled
Low Power
Idle
Improved Idle mode that uses
clock gating to save power.
Any Interrupt
Very Good
No Code Execution
Selective Clock Gating
Suspend
Similar to Stop Mode, but very fast
maRTClock,
Very Good
wake-up time and code resumes
execution at the next instructio
rt Match,
Comparator0,
RST pin,
No Code Execution
All Internal Oscillators Disabled
System Clock Gated
Pulse Counter
VBAT Monitor.
Sleep
Ultra Low Power a
d flexible
wake-up sources. Code resumes
execution at the next instruction.
SmaRTClock,
Port Match,
Comparator0,
RST pin,
Excellent
Power Supply Gated
All Oscillators except SmaRT-
Clock Disabled
Pulse Counter
VBAT Monitor.
In battery powered systems, the system should spend as much time as possible in sleep mode in order to
preserve ba
ry life. When a task with a fixed number of clock cycles needs to be performed, the device
should swit
h to normal mode, finish the task as quickly as possible, and return to sleep mode. Idle mode,
low
er idle mode, and suspend mode provide a very fast wake-up time; however, the power savings in
these modes will not be as much as in sleep Mode. Stop Mode is included for legacy reasons; the system
will be more power efficient and easier to wake up when idle, low power idle, suspend, or sleep mode is
used.
Although switching power modes is an integral part of power management, enabling/disabling individual
peripherals as needed will help lower power consumption in all power modes. Each analog peripheral can
be disabled when not in use or placed in a low power mode. Digital peripherals such as timers or serial
busses draw little power whenever they are not in use. Digital peripherals draw no power in Sleep Mode.
Rev. 1.0
257
Si102x/3x
19.1. Normal
Mode
The MCU is fully functional in Normal Mode. Figure 19.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the chip: VBA
T
,
D
COU
T
,
a
nd the
1.8 V internal core supply (output of VREG0). All analog peripherals are directly powered from the VBAT
pin. All digital peripherals and the CIP-51 core are powered from the 1.8 V internal core supply (output of
VREG0). The Pulse counter, RAM, PMU0, and the SmaRTClock are powered from the internal core suppl
when the device is in normal mode. The input to VREG0 is controlled by software and depends on the s
tings of the power select switch. The power select switch may be configured to power VREG0 from VBAT
or from the output of the DC0.
IND
VDC
VBAT
1.8 to 3.6 V
VIO/VIORF must be <= VBAT
VIO
VBATDC
GNDDC
1.9 V
DC0
Buck
Converter
Analog Peripherals
Power
Select
VRE
LCD
A
M
ADC
+
–
+
–
Pulse
Counter
TEMP
SENSOR
VOLTAGE
COMPARATORS
VIORF
Sleep
VRE
RAM
PMU0
Digital Peripherals
Flash
UART
1.8 V
Ac
dle/
CIP-51
Core
AES
SPI
Stop/Suspend
Timers
SMBus
SmaRTClock
Figure 19.1. Si102x/3x Power Distribution
19.2. Idle
Mode
Setting the
le Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as th
struction that sets the bit completes execution. All internal registers and memory maintain their
origi
l data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
peration. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the watchdog timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
258
Rev. 1.0
Si102x/3x
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “22.6. PCA Watchdog Timer
Reset” on page 283 for more information on the use and configuration of the WD
T
.
19.3. Stop
Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc
tion that sets the bit completes execution. In Stop mode the precision internal oscillator and CPU are
stopped; the state of the low power oscillator and the external oscillator circuit is not affected. Each analog
peripheral (including the external oscillator circuit) may be shut down individually prior to e
ering Stop
Mode. Stop mode can only be terminated by an internal or external reset. On reset, th
-51 performs
the normal reset sequence and begins program execution at address 0x0000.
If enabled, the missing clock detector will cause an internal reset and thereby terminate the stop mode.
The missing clock detector should be disabled if the CPU is to be put to in stop mode for longer than the
MCD timeout.
Stop mode is a legacy 8051 power mode; it will not result in optimal power savings. Sleep, suspend, or low
power idle mode will provide more power savings if the MCU needs to be inactive for a long period of time.
19.4. Low
Power Idle Mode
Low power idle mode uses clock gating to reduce the supply current when the device is placed in Idle
mode. This mode is enabled by configuring the clock tree ga
using the PCLKEN register, setting the
LPMEN bit in the CLKMODE register, and placing the device in Idle mode. The clock is automatically gated
from the CPU upon entry into Idle mode when the LPMEN bit is set. This mode provides substantial power
savings over the standard Idle Mode especially at hig
stem clock frequencies.
The clock gating logic may also be used to reduc
power when executing code. Low power active mode is
enabled by configuring the PCLKACT and P
KEN registers, then setting the LPMEN bit. The PCLKACT
register provides the ability to override the P
KEN setting to force a clock to certain peripherals in low
power active mode. If the PCLKACT register is left at its default value, then PCLKEN determines which
peripherals will be clocked in this mo
. The CPU is always clocked in low power active mode.
System
Clock
SmaRTClock
Pulse Counter
PMU0
CPU
Timer 0, 1, 2
CRC0
ADC0
PCA0
UART0
Timer 3
SPI0
SMBus
Figure 19.2. Clock Tree Distribution
Rev. 1.0
259
Si102x/3x
SFR Definition 19.1. PCLKAC
T
:
P
eripheral Active Clock Enable
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCLKACT[3:0]
R/W
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xF5
Bit
7:4
3
Name
Function
Unused
Read = 0b; Write = don’t care.
PCLKACT3
Clock Enable Controls for Peripherals in Low Power Active Mode.
0: Clocks to the SmaRTClock, Pulse Counter, and PMU
evert to the PCLKEN set-
ting in Low Power Active Mode.
1: Enable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Active
Mode.
2
1
0
PCLKACT2
Clock Enable Controls for Peripherals in Low Power Active Mode.
0: Clocks to Timer 0, Timer 1, Timer 2, and
C0 revert to the PCLKEN setting in Low
Power Active Mode.
1: Enable clocks to Timer 0, Timer
, Timer 2, and CRC0 in Low Power Active Mode.
PCLKACT1
Clock Enable Controls for P
ipherals in Low Power Active Mode.
0: Clocks to ADC0 and PCA0
evert to the PCLKEN setting in Low Power Active
Mode.
1: Enable clocks to ADC0 and PCA0 in Low Power Active Mode.
PCLKACT0
Clock Enable Co
trols for Peripherals in Low Power Active Mode.
0: Clocks to UART0, Timer 3, SPI0, and the SMBus revert to the PCLKEN setting in
Low Power Active Mode.
1: Enable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Active
Mode
260
Rev. 1.0
Si102x/3x
SFR Definition 19.2. PCLKEN: Peripheral Clock Enable
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCLKEN[3:0]
R/W
R/W
R/W
R/W
R/W
SFR Page = 0xF; SFR Address = 0xFE
Bit
7:4
3
Name
Function
Unused
Read = 0b; Write = don’t care.
PCLKEN3
Clock Enable Controls for Peripherals in Low Power Idle Mode.
0: Disable clocks to the SmaRTClock, Pulse Counter, an
PMU0 in Low Power Idle
Mode.
1: Enable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Idle
Mode.
2
1
0
PCLKEN2
Clock Enable Controls for Peripherals in Low Power Idle Mode.
0: Disable clocks to Timer 0, Timer 1, Time
and CRC0 in Low Power Idle Mode.
1: Enable clocks to Timer 0, Timer 1, Timer 2, and CRC0 in Low Power Idle Mode.
PCLKEN1
Clock Enable Controls for Peri
als in Low Power Idle Mode.
0: Disableclocks to ADC0 and
CA0 in Low Power Idle Mode.
1: Enable clocks to ADC0 and PCA0 in Low Power Idle Mode.
PCLKEN0
Clock Enable Controls f
Peripherals in Low Power Idle Mode.
0: Disable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Idle Mode.
1: Enable clocks
UART0, Timer 3, SPI0, and the SMBus in Low Power Idle Mode.
Rev. 1.0
261
Si102x/3x
SFR Definition 19.3. CLKMODE: Clock Mode
Bit
7
6
5
4
3
2
LPMEN
R/W
0
1
0
Name
Reserved Reserved Reserved Reserved Reserved
Reserved Reserve
Type
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
SFR Page = 0xF; SFR Address = 0xFD; Bit-Addressable
Bit
7:3
2
Name
Reserved
LPMEN
Function
Read = 0b; Write = Must write 00000b.
Low Power Mode Enable.
Setting this bit allows the device to enter Low Powe
Active or Idle Mode.
1
0
Reserved
Reserved
Read = 0b; Must write 0b.
Read = 0b; Must write 0b.
262
Rev. 1.0
Si102x/3x
19.5. Suspend
Mode
Setting the Suspend Mode Select bit (PMU0C
F
.
6) causes the system clock to be gated off and all internal
oscillators disabled. The system clock source must be set to the low power internal oscillator or the preci-
sion oscillator prior to entering Suspend Mode. All digital logic (timers, communication peripherals, inter-
rupts, CPU, etc.) stops functioning until one of the enabled wake-up sources occurs.
The following wake-up sources can be configured to wake the device from Suspend Mode:
Pulse Counter Count Reached Event
VBAT Monitor (part of LCD logic)
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
Note:
Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the PMU0CF wake-
up flags. All flags will read back a value of ‘0’ during the first two system clock
ollowing a wake-up from
suspend mode.
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit
suspend. In order for the MCU to respond to the pin reset event, software must not place the device back
into suspend mode for a period of 15 µs. The PMU0CF registe
ay be checked to determine if the wake-
up was due to a falling edge on the /RST pin. If the wake-up
rce is not due to a falling edge on RS
T
,
there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 kW
pullup resistor to VDD is recommend for RST to preve
noise glitches from waking the device.
19.6. Sleep
Mode
Setting the Sleep Mode Select bit (PMU0C
F
.
7
turns off the internal 1.8 V regulator (VREG0) and switches
the power supply of all on-chip RAM to the V
pin (see Figure 19.1). Power to most digital logic on the
chip is disconnected; only PMU0, LCD, Power Select Switch, Pulse Counter, and the SmaRTClock remain
powered. Analog peripherals remain powered; however, only the Comparators remain functional when the
device enters Sleep Mode. All other
nalog peripherals (ADC0, IREF0, External Oscillator, etc.) should be
disabled prior to entering Sleep Mode. The system clock source must be set to the low power internal
oscillator or the precision osci
lator prior to entering Sleep Mode.
GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,
they will maintain the same current drive capability in sleep mode as they have in normal mode.
GPIO pins configu
s digital inputs can be used during sleep mode as wakeup sources using the port
match feature. In two-cell mode, they will maintain the same input level specs in sleep mode as they have
in normal mode.
‘Si102x/3x
evices support a wakeup request for external devices. Upon exit from sleep mode, the wake-
up
est signal is driven low, allowing other devices in the system to wake up from their low power
mode
.
RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT does not fall
elow V
. The PC counter and all other volatile state information is preserved allowing the device to
POR
resume code execution upon waking up from Sleep mode.
Rev. 1.0
263
Si102x/3x
The following wake-up sources can be configured to wake the device from sleep mode:
Pulse Counter Count Reached Event
VBAT Monitor (part of LCD logic)
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
The comparator requires a supply voltage of at least 1.8 V to operate properly. On Si102x/3x devices, the
POR supply monitor can be disabled to save power by writing 1 to the MONDIS (PMU0MD.
bit. When
the POR supply monitor is disabled, all reset sources will trigger a full POR and will re
nab
e the POR
supply monitor.
In addition, any falling edge on RST (due to a pin reset or a noise glitch) will cause the device to exit sleep
mode. In order for the MCU to respond to the pin reset event, software must not place the device back into
sleep mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-up was
due to a falling edge on the RST pin. If the wake-up source is not due to a fa
g edge on RS
T
,
t
here is no
time restriction on how soon software may place the device back into sleep mode. A 4.7 k
pullup resistor
to VDD is recommend for RST to prevent noise glitches from waking t
e device.
19.7. Configuring
Wakeup Sources
Before placing the device in a low power mode, one or more
akeup sources should be enabled so that
the device does not remain in the low power mode indefinitel
r idle mode, this includes enabling any
interrupt. For stop mode, this includes enabling any reset source or relying on the RST pin to reset the
device.
Wake-up sources for suspend and sleep modes are
nfigured through the PMU0CF register. Wake-up
sources are enabled by writing 1 to the correspo
ing wake-up source enable bit. Wake-up sources must
be re-enabled each time the device is placed
Suspend or Sleep mode, in the same write that places the
device in the low power mode.
The reset pin is always enabled as a wake-up source. On the falling edge of RS
T
,
t
he device will be
awaken from sleep mode. The devic
must remain awake for more than 15 µs in order for the reset to take
place.
19.8. Determining
the Event that Caused the Last Wakeup
When waking from idle mode, the CPU will vector to the interrupt which caused it to wake up. When wak-
ing from stop mode, the RSTSRC register may be read to determine the cause of the last reset.
Upon exit from sus
d or sleep mode, the wake-up flags in the PMU0CF register can be read to deter-
mine the event which caused the device to wake up. After waking up, the wake-up flags will continue to be
updated if any of the wake-up events occur. Wake-up flags are always updated, even if they are not
enabled as
ake-up sources.
All
e-up flags enabled as wake-up sources in PMU0CF must be cleared before the device can enter
suspend or sleep mode. After clearing the wake-up flags, each of the enabled wake-up events should be
checked in the individual peripherals to ensure that a wake-up event did not occur while the wake-up flags
were being cleared.
264
Rev. 1.0
Si102x/3x
1,2,3
SFR Definition 19.4. PMU0CF: Power Management Unit Configuration
Bit
7
6
5
CLEAR
W
4
3
2
1
0
Name
SLEEP SUSPEND
RSTWK RTCFWK
RTCAWK PMATWK CPT0W
Type
W
0
W
0
R
R/W
R/W
R/W
R/W
Reset
0
Varies
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xB5
Bit
Name
Description
Write
R
d
7
SLEEP
Sleep Mode Select
Writing 1 places the
device in Sleep Mode.
N/A
N/A
6
5
4
SUSPEND
Suspend Mode Select
Writing 1 places the
device in Suspend Mode.
CLEAR
RSTWK
Wake-up Flag Clear
Writing 1 clears all wake-
N/A
up flags.
Reset Pin Wake-up Flag
N/A
Set to 1 if a falling edge
has been detected on
RS
T
.
3
RTCFWK
SmaRTClock Oscillator
Fail Wake-up Source
0: D
le wake-up on
maRTClock Osc. Fail.
1: Enable wake-up on
SmaRTClock Osc. Fail.
Set to 1 if the SmaRT-
Clock Oscillator has failed.
Enable and Flag
2
RTCAWK
SmaRTClock Alarm
0: Disable wake-up on
Set to 1 if a SmaRTClock
Alarm has occurred.
Wake-up Sour
Enable
SmaRTClock Alarm.
and Flag
1: Enable wake-up on
SmaRTClock Alarm.
1
PMATWK
Port Match Wake-up
0: Disable wake-up on
Set to 1 if a Port Match
Event has occurred.
Source Enable and Flag
Port Match Event.
1: Enable wake-up on
Port Match Event.
0
CPT0WK
Comparator0 Wake-up
0: Disable wake-up on
Set to 1 if Comparator0
Source Enable and Flag
Comparator0 rising edge.
rising edge has occurred.
1: Enable wake-up on
Comparator0 rising edge.
Notes:
1.
Read-modify-write operations (ORL, ANL, etc.) should not be used on this register. Wake-up sources must
be re-enabled each time the SLEEP or SUSPEND bits are written to 1.
2.
The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in Suspend or Sleep
Mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
3.
PMU0 requires two system clocks to update the wake-up source flags after waking from Suspend mode. The
wake-up source flags will read ‘0’ during the first two system clocks following the wake from Suspend mode.
Rev. 1.0
265
Si102x/3x
1,2
SFR Definition 19.5. PMU0FL: Power Management Unit Flag
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
BATMWK Reserved
PC0WK
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
Varies
SFR Page = 0x0; SFR Address = 0xB6
Bit
7:3
2
Name
Description
Write
R
d
Unused
Unused
Don’t Care.
0000000
BATMWK
VBAT Monitor (inside
LCD Logic) Wake-up
0: Disable wake-up on
VBAT Monitor event.
1: Enable wake-up on CS0
event.
Set to 1 if VBAT Monitor
event caused the last
wake-up.
Source Enable and Flag
1
0
Reserved
Reserved
Must write 0.
Always reads 0.
CS0WK
Pulse Counter Wake-up
0: Disab
e w
up on
Source Enable and Flag
PC0 event.
1: Enable wake-up on PC0
Set to 1 if PC0 event
caused the last wake-up.
eve
Notes:
1.
The Low Power Internal Oscillator cannot b
disabled and the MCU cannot be placed in suspend or sleep
mode if any wake-up flags are set to 1. S
e should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
2.
PMU0 requires two system clocks to update the wake-up source flags after waking from suspend mode. The
wake-up source flags will read 0
ring the first two system clocks following the wake from suspend mode.
266
Rev. 1.0
Si102x/3x
SFR Definition 19.6. PMU0MD: Power Management Unit Mode
Bit
7
6
5
MONDIS
R/W
4
3
2
1
0
Name
RTCOE WAKEOE
Type
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0
SFR Page = 0x0; SFR Address = 0xB6
Bit
Name
Function
7
RTCOE
Buffered SmaRTClock Output Enable.
Enables the buffered SmaRTClock oscillator output on P0.2.
0: Buffered SmaRTClock output not enabled.
1: Buffered SmaRTClock output not enabled.
6
WAKEOE
Wakeup Request Output Enable.
Enables the Sleep Mode wake-up request signal on P0.3.
0: Wake-up request signal is not enabled.
1: Wake-up request signal is enabled.
5
MONDIS
Unused
POR Supply Monitor Disable.
Writing a 1 to this bit disables th
R supply monitor.
4:0
Read = 00000b. Write = Do
Care.
Rev. 1.0
267
Si102x/3x
SFR Definition 19.7. PCON: Power Management Control Register
Bit
7
6
5
GF[4:0]
R/W
0
4
3
2
PWRSEL
R/W
1
STOP
W
0
IDLE
W
Name
Type
Reset
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0x87
Bit
7:3
2
Name
Description
Write
d
Returns the logic value.
GF[5:0]
General Purpose Flags
Sets the logic value.
PWRSEL
Power Select
0: VBAT is selected as the input to VREG0.
1: VDC is selected as the i
ut to VREG0.
1
0
STOP
IDLE
Stop Mode Select
Idle Mode Select
Writing 1 places the
device in Stop Mode.
N/A
Writing 1 places the
device in Idl
ode.
N/A
19.9. Power
Management Specifications
See
T
a
ble 4.7 on page 61 for detailed Power Manage
t Specifications.
268
Rev. 1.0
Si102x/3x
20. On-Chip
DC-DC Buck Converter (DC0)
Si102x/3x devices include an on-chip step down dc-dc converter to efficiently utilize the energy stored in
the battery, thus extending the operational life time. The dc-dc converter is a switching buck converter with
an input supply of 1.8 to 3.8 V and an output that is programmable from 1.8 to 3.5 V in steps of 0.1 V. The
battery voltage should be at least 0.4 V higher than the programmed output voltage. The programmed out-
put voltage has a default value of 1.9 V. The dc-dc converter can supply up to 250 mW. The dc-dc co
verter can be used to power the MCU and/or external devices in the system (e.g., an RF transceiver).
The dc-dc converter has a built in voltage reference and oscillator, and will automatically limit or turn off the
switching activity in case the peak inductor current rises beyond a safe limit or the output v
age rises
above the programmed target value. This allows the dc-dc converter output to be safel
verdriven by a
secondary power source (when available) in order to preserve battery life. When enab
e dc-dc con-
verter can source current into the output capacitor, but cannot sink current. The dc-dc con
rter’s settings
can be modified using SFR registers described in Section 20.8.
Figure 20.1 shows a block diagram of the buck converter.
DC/DC Con
erter
VBAT
IND
M1
VBATDC
0.56 uH
MBYP
4.7 uF
+ 0.1uF
+ 0.01uF
VDC
Control Logi
Voltage
2.2 uF
+0.1uF
+0.01uF
SFR
Contro
eference
I
load
Local
Oscillator
GNDDC
GND
Fig
re 20.1. Step Down DC-DC Buck Converter Block Diagram
Rev. 1.0
269
Si102x/3x
20.1. Startup
Behavior
The dc-dc converter is enabled by setting bit DC0EN (DC0MD.0) to logic 1. When first enabled, the M1
switch turns on and continues to supply current into the output capacitor through the inductor until the VDC
output voltage reaches the programmed level set by by the VSEL bits (DC0C
F
.
[6:3]).
The peak transient current in the inductor is limited for safe operation. The peak inductor current is pro-
grammable using the ILIMIT bits (DC0MD.[6:4]). The peak inductor current, size of the output capaci
and the amount of dc load current present during startup will determine the length of time it takes to charg
the output capacitor. The RDYH and RDYL bits (DC0RD
Y
.
7 and DC0DR
Y
.
6) may be used to determine
when the output voltage is within approximately 100 mV of the programmed voltage.
In order to ensure reliable startup of the dc-dc converter, the following restrictions have b
n imposed:
•
The maximum dc load current allowed during startup is given in
T
a
ble 4.20 on page
the dc-dc
converter is powering external sensors or devices through the VDC pin, then the current supplied to
these sensors or devices is counted towards this limit. The in-rush current into capacitors does not
count towards this limit.
•
The maximum total output capacitance is given in
T
a
ble 4.20 on page 69. This value includes the
required 2.2 µF ceramic output capacitor and any additional capa
itance connected to the VDC pin.
The peak inductor current limit is programmable by software as shown in
T
a
ble 20.1. Limiting the peak
inductor current can allow the dc-dc converter to start up usin
high impedance power source (such as
when a battery is near its end of life) or allow inductors with a
current rating to be utilized. By default,
the peak inductor current is set to 500 mA.
.
Table 20.1. IPeak Inducto
urrent Limit Settings
ILIMIT
001
Peak Current (mA)
200
300
400
500
600
011
100
101
The peak inductor c
ent is dependent on several factors including the dc load current and can be esti-
mated using following equation:
2
I
LOAD
VDC
–
VBATDC
efficiency
inductance
frequency
————————————————————————————————–
=
I
PK
efficiency = 0.80
nductance = 0.68 µH
frequency = 2.4 MHz
270
Rev. 1.0
Si102x/3x
20.2. High
Power Applications
The dc-dc converter is designed to provide the system with 150 mW of output power. At high output power,
an inductor with low dc resistance should be chosen in order to minimize power loss and maximize effi-
ciency. At load currents higher than 20 mA, efficiency improvents may be achieved by placing a schottky
diode (e.g. MBR052LT1) between the IND pin and GND in parallel with the internal diode (see
Figure 20.1).
20.3. Pulse
Skipping Mode
The dc-dc converter allows the user to set the minimum pulse width such that if the duty cycle needs to
decrease below a certain width in order to maintain regulation, an entire “clock pulse” will be s
pped.
Pulse skipping can provide substantial power savings, particularly at low values of loa
nt. The con-
verter will continue to maintain a minimum output voltage at its programmed value when
se skipping is
employed, though the output voltage ripple can be higher. Another consideration is that the dc-dc will oper-
ate with pulse-frequency modulation rather than pulse-width modulation, which makes the switching fre-
quency spectrum less predictable; this could be an issue if the dc-dc converte
is used to power a radio.
20.4. Optimizing
Board Layout
The PCB layout does have an effect on the overall efficiency. The following guidelines are recommended
to acheive the optimum layout:
Place the input capacitor stack as close as possible to the VBATDC pin. The smallest capacitors in the
stack should be placed closest to the VBATDC pin.
Place the output capacitor stack as close as possible to the VDC pin. The smallest capacitors in the
stack should be placed closest to the VDC pin.
Minimize the trace length between the IND pin, th
uctor, and the VDC pin.
20.5. Selecting
the Optimum Switch Siz
The dc-dc converter provides the ability to c
e the size of the built-in switches.
T
o
m
aximize efficiency,
one of two switch sizes may be selected. The large switches are ideal for carrying high currents and the
small switches are ideal for low current applications. The ideal switchover point to switch from the small
switches to the large switches is at a
roximately 5 mA total output current.
20.6. DC-DC
Converter Clocking Options
The dc-dc converter may be clocked from its internal oscillator, or from any system clock source, select-
able by the CLKSEL bit (DC0C
F
.
0). The dc-dc converter internal oscillator frequency is approximately
2.4 MHz. For a more accurate clock source, the system clock, or a divided version of the system clock may
be used as the dc
clock source. The dc-dc converter has a built in clock divider (configured using
DC0CF[6:5]) which
ws any system clock frequency over 1.6 MHz to generate a valid clock in the range
of 1.9 to 3.8 MHz.
When the
ecision internal oscillator is selected as the system clock source, the OSCICL register may be
use
fine tune the oscillator frequency and the dc-dc converter clock. The oscillator frequency should
only
e decreased since it is factory calibrated at its maximum frequency. The minimum frequency which
can be reached by the oscillator after taking into account process variations is approximately 16 MHz. The
system clock routed to the dc-dc converter clock divider also may be inverted by setting the CLKINV bit
DC0C
F
.
3) to logic 1. These options can be used to minimize interference in noise sensitive applications.
Rev. 1.0
271
Si102x/3x
20.7. Bypass
Mode
The dc-dc converter has a bypass switch (MBYP), see Figure 20.1, which allows the output voltage (VDC)
to be directly tied to the input supply (VBATDC), bypassing the dc-dc converter. The bypass switch may be
used independently from the dc-dc converter. For example, applications that need to power the VDC sup-
ply in the lowest power Sleep mode can turn on the bypass switch prior to turning off the dc-dc converter in
order to avoid powering down the external circuitry connected to VDC.
There are two ways to close the bypass switch. Using the first method, Forced Bypass Mode, the FORBY
bit is set to a logic 1 forcing the bypass switch to close. Clearing the FORBYP bit to logic 0 will allow the
switch to open if it is not being held closed using Automatic Bypass Mode.
The Automatic Bypass Mode, enabled by setting the AUTOBYP to logic 1, closes the by
s switch when
the difference between VBATDC and the programmed output voltage is less than a
mately 0.4
V
.
Once the difference exceeds approximately 0.5 V, the bypass switch is opened unless b
g held closed
by Forced Bypass Mode. In most systems, Automatic Bypass Mode will be left enabled, and the Forced
Bypass Mode will be used to close the switch as needed by the system.
20.8. DC-DC
Converter Register Descriptions
The SFRs used to configure the dc-dc converter are described in the following register descriptions.
272
Rev. 1.0
Si102x/3x
SFR Definition 20.1. DC0CN: DC-DC Converter Control
Bit
7
6
5
4
3
2
1
0
Name
CLKSEL
CLKDIV[1:0]
AD0CKINV CLKINV
ILIMIT
R/W
0
MIN_PW[1:0]
R/W
Type
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
1
1
SFR Page = 0x0; SFR Address = 0x97
Bit
Name
Function
7
CLKSEL
DC
–
DC Converter Clock Source Select.
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system cloc
6:5 CLKDIV[1:0]
DC
–
DC Clock Divider.
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. Ignored all other
mes.
00: The dc-dc converter clock is system c
k divided by 1.
01: The dc-dc converter clock is system c
divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is
stem clock divided by 8.
4
AD0CKINV
ADC0 Clock Inversion (Clo
Invert During Sync).
Inverts the ADC0 SAR cl
ck derived from the dc-dc converter clock when the SYNC
bit (DC0CN.3) is enable
his bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
3
2
CLKINV
DC
–
DC Converter Clock Invert.
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
SYNC
DC0 Synchronization Enable.
hen synchronization is enabled, the ADC0SC[4:0] bits in the ADC0CF register
must be set to 00000b.
0: The ADC is not synchronized to the dc-dc converter.
1: The ADC is synchronized to the dc-dc converter. ADC0 tracking is performed
during the longest quiet time of the dc-dc converter switching cycle and ADC0 SAR
clock is also synchronized to the dc-dc converter switching cycle.
1:0 MINPW[1:0]
DC
–
DC Converter Minimum Pulse Width.
Specifies the minimum pulse width.
00: Minimum pulse detection logic is disabled (no pulse skipping).
01: Minimum pulse width is 10 ns.
10: Minimum pulse width is 20 ns.
11: Minimum pulse width is 40 ns.
Rev. 1.0
273
Si102x/3x
SFR Definition 20.2. DC0CF: DC-DC Converter Configuration
Bit
7
6
5
4
3
2
OSCDIS
R/W
0
1
0
Name
Type
Reset
BYPASS
VSEL[3:0]
R/W
SWSEL[1:0]
R
0
0
0
0
1
1
1
SFR Page = 0x0; SFR Address = 0x96
Bit
Name
Function
7
BYPASS
DC
–
DC Converter Bypass Switch Active Indicator.
0: The bypass switch is open.
1: The bypass switch is closed (VDC is connected to
ATDC).
6:3
VSEL[3:0]
DC
–
DC Converter Output Voltage Select.
Specifies the target output voltage.
0000:
T
a
rget output voltage is 1.8 V.
0001:
T
a
rget output voltage is 1.9 V.
0010:
T
a
rget output voltage is 2.0 V.
0011:
T
a
rget output voltage is 2.1 V.
0100:
T
a
rget output voltage is
V.
0101:
T
a
rget output voltag
s 2.3
V
.
0110:
T
a
rget output voltag
is 2.4 V.
0111: Target output v
e is 2.5 V.
1000:
T
a
rget output voltage is 2.6 V.
1:
T
a
rget output voltage is 2.7 V.
1010:
T
a
rget output voltage is 2.8 V.
1011:
T
a
rget output voltage is 2.9 V.
1100:
T
a
rget output voltage is 3.0 V.
1101:
T
a
rget output voltage is 3.1 V.
1110: Target output voltage is 3.3 V.
1111: Target output voltage is 3.5 V.
2
VSEL[2:0]
DC
–
DC Converter Local Oscillator Disabled.
0: The local o
illator inside the dc-dc converter is enabled.
1: The local oscillator inside the dc-dc converter is disabled.
1:0
SWSEL[1:0]
DC
–
DC Converter Power Switch Select.
Selects the size of the power switches (M1, M2). Using smaller switches will resut
n higher efficiency at low supply currents.
00: Minimum switch size, optimized for load currents smaller than 5 mA.
01: Reserved.
10: Reserved.
11: Maximum switch size, optimized for load currents greater than 5 mA.
274
Rev. 1.0
Si102x/3x
SFR Definition 20.3. DC0MD: DC-DC Converter Mode
Bit
7
6
5
ILIMIT
R/W
0
4
3
2
1
0
DC0EN
R/W
0
Name
Reserved
FORBYP AUTOBYP Reserved
Type
R/W
0
R/W
0
R/W
0
R/W
0
Reset
1
0
SFR Page = 0x2; SFR Address = 0xB3
Bit
Name
Function
7
Reserved Read
= 0b; Must write 0b.
6:4
ILIMIT
Peak Current Limit Threshold.
000: Reserved
001: Peak Inductor current is limited to 200 mA
010: Peak Inductor current is limited to 300 mA
011: Peak Inductor current is limited to 400 mA
100: Peak Inductor current is limited to 500 mA
101: Peak Inductor current is limited to
mA
110: Reserved
111: Reserved
3
2
FORBYP
Enable Forced Bypass Mode.
0: Forced bypass mode is
isabled.
1: Forced bypass mo
enabled.
AUTOBYP
Enable Automat
c Bypass Mode.
0: Automatic Bypass mode is disabled.
1: Automatic
ypass mode is enabled.
1
0
Reserved Read
= 1b; Must write 1b.
DC0EN
DC
–
DC Converter Enable.
0: DC-DC converter is disabled.
1: DC-DC converter is enabled.
Rev. 1.0
275
Si102x/3x
SFR Definition 20.4. DC0RDY: DC-DC Converter Ready Indicator
Bit
7
RDYH
R
6
RDYL
R
5
4
3
2
1
0
Name
Type
Reset
Reserved
R/W
0
0
0
1
1
1
1
1
SFR Page = 0x2; SFR Address = 0xFD
Bit
Name
Function
7
RDYH
DC0 Ready Indicator (High Threshold).
Indicates when VDC is 100 mV higher than the target output value.
0: VDC pin voltage is less than the DC0 High Thresh
.
1: VDC pin voltage is higher than the DC0 High Threshold.
6
RDYL
DC0 Ready Indicator (Low Threshold).
Indicates when VDC is 100 mV lower than
he target output value.
0: VDC pin voltage is less than the DC0
ow Threshold.
1: VDC pin voltage is higher than the D
Low Threshold.
5:0
Reserved Read
= 011111b; Must write 011111b.
20.9. DC-DC
Converter Specifications
See
T
a
ble 4.20 on page 69 for a detailed listin
of dc-dc converter specifications.
276
Rev. 1.0
Si102x/3x
21. Voltage
Regulator (VREG0)
Si102x/3x devices include an internal voltage regulator (VREG0) to regulate the internal core supply to
1.8 V from a VDD/DC+ supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are speci-
fied in the Electrical Specifications chapter.
The REG0CN register allows the Precision Oscillator Bias to be disabled, reducing supply current in a
non-sleep power modes. This bias should only be disabled when the precision oscillator is not being use
The internal regulator (VREG0) is disabled when the device enters sleep mode and remains enabled when
the device enters suspend mode. See Section “19. Power Management” on page 257 for complete details
about low power modes.
SFR Definition 21.1. REG0CN: Voltage Regulator Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
OSCBIAS
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
1
SFR Page = 0x0; SFR Address = 0xC9
Bit
Name
Fun
on
7:5
4
Reserved Read
= 000b. Must Write 000b.
OSCBIAS
Precision Oscillator Bias.
When set to 1, the bias use
y the precision oscillator is forced on. If the precision
oscillator is not being used, this bit may be cleared to 0 to to save supply current in
all non-Sleep power mo
3:0
Reserved Read
= 0000b. Must Write 0000b.
21.1. Voltage
Regulator Elec
rical Specifications
See
T
a
ble 4.17 on page 67 for detailed Voltage Regulator Electrical Specifications.
Rev. 1.0
277
Si102x/3x
22. Reset
Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled
All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RA
are unaf-
fected during a reset; any previously stored data is preserved as long as power is not los
Since the stack
pointer SFR is reset, the stack is effectively lost, even though the data on the stack is n
ed.
The port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled after
the reset. For V
Monitor resets, the RST pin is driven low until the device exits the reset state.
DD
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. Refer to Section “23. Clocking Sources” on page 286 for informati
n on selecting and configur-
ing the system clock source. The watchdog timer is enabled with the system clock divided by 12 as its
clock source (Section “34.4. Watchdog Timer Mode” on page 516 details the use of the watchdog timer).
program execution begins at location 0x0000.
VBAT
Supply
Monitor
VDC VBAT
swi
VBAT
+
–
Enable
Power On
Reset
Supply
Monitor
(wired-OR)
Enable
Comparator 0
Px.x
Px.x
+
–
‘0’
RST
+
–
C0RSEF
SmaRTClock
RTC0RE
Reset
Funnel
Mi
sing
Clock
Detector
(one-
shot)
PCA
WDT
(Software Reset)
SWRSF
EN
EN
Illegal Flash
Operation
System
Clock
CIP-51
System Reset
System Reset
Microcontroller
Core
Power Management
Block (PMU0)
Power-On Reset
Reset
Extended Interrupt
Handler
Figure 22.1. Reset Sources
Rev. 1.0
278
Si102x/3x
22.1. Power-On
Reset
During power-up, the device is held in a reset state and the RST pin voltage tracks the supply voltage
(through a weak pull-up) until the device is released from reset. After the supply settles above VPOR, a
delay occurs before the device is released from reset; the delay decreases as the supply ramp time
increases (ramp time is defined as how fast the supply ramps from 0 V to V
). Figure 22.2 plots the
POR
power-on and supply monitor reset timing. For valid ramp times (less than 3 ms), the power-on reset dela
(T )
is typically 7 ms (V
= 1.8 V) or 15 ms (V
= 3.6 V).
PORDelay
DD
DD
Note:
The maximum supply ramp time is 3 ms; slower ramp times may cause the device to be released from reset
before the supply reaches the V
level.
POR
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. Whe
PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
d by all other
resets). Since all resets cause program execution to begin at the same location (0x00
software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
The POR supply monitor will continue to monitor the VBAT supply, even in S
ep Mode, to reset the sys-
tem if the supply voltage drops below VPOR. It can be disabled to save pow
by writing 1 to the MONDIS
(PMU0MD.5) bit. When the POR supply monitor is disabled, all reset sources will trigger a full POR and will
re-enable the POR supply monitor.
Supply voltage
V
POR
See specification
table for min/max
voltages.
t
RST
Logic HIGH
T
PORDelay
T
PORDelay
Lo
c LOW
Power-On
Reset
Power-On
Reset
Figure 22.2. Power-On Reset Timing Diagram
279
Rev. 1.0
Si102x/3x
22.2. Power-Fail
Reset
Si102x/3x devices have two Active Mode Supply Monitors that can hold the system in reset if the supply
voltage drops below V
. The first of the two identical supply monitors is connected to the output of the
RST
supply select switch (which chooses the VBAT or VDC pin as the source of the digital supply voltage) and
is enabled and selected as a reset source after each power-on or power-fail reset. This supply monitor will
be referred to as the digital supply monitor. The second supply monitor is connected directly to the VBA
pin an is disabled after each power-on or power-fail reset. This supply monitor will be referred to as t
analog supply monitor. The analog supply monitor should be enabled any time the supply select switch is
set to the VDC pin to ensure that the VBAT supply does not drop below V
.
RST
When enabled and selected as a reset source, any power down transition or power irregularity
hat causes
the monitored supply voltage to drop below V
will cause the RST pin to be driven
d the CIP-51
RST
will be held in a reset state (see Figure 22.2). When the supply voltage returns to a level
ove V
, the
RST
CIP-51 will be released from the reset state.
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and
he digital supply moni-
tor is enabled and selected as a reset source. The enable state of either supp
monitor and its selection as
a reset source is only altered by power-on and power-fail resets. For example, if the supply monitor is de-
selected as a reset source and disabled by software, then a software reset is performed, the supply moni-
tor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in Sleep Mode prior to a power-
ail
occurring. When the device is in Sleep
Mode, the power-fail reset is automatically disabled, both active mode supply monitors are turned off, and
the contents of RAM are preserved as long as the supply does not fall below V
. A large capacitor can
POR
be used to hold the power supply voltage above V
ile the user is replacing the battery. Upon waking
PO
from Sleep mode, the enable and reset source s
ct state of the V
supply monitor are restored to the
DD
value last set by the user.
To
a
llow software early notification that a pow
failure is about to occur, the VDDOK bit is cleared when
the supply falls below the V
threshold. The VDDOK bit can be configured to generate an interrupt.
WARN
Each of the active mode supply mo
rs have their independent VDDOK and V
“17. Interrupt Handler” on page 231 for more details.
flags. See Section
WARN
Important Note:
T
o
p
rotect the integrity of Flash contents,
the active mode supply monitor(s) must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory.
If the digital supply monitor is not enabled, any erase or write performed on Flash memory will
cause a Flash Error device reset.
Rev. 1.0
280
Si102x/3x
Important Notes:
The Power-on Reset (POR) delay is not incurred after a supply monitor reset. See Section “4. Electrical
Characteristics” on page 48 for complete electrical characteristics of the active mode supply monitors.
Software should take care not to inadvertently disable the supply monitor as a reset source when
writing to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC
should explicitly set PORSF to 1 to keep the supply monitor enabled as a reset source.
The supply monitor must be enabled before selecting it as a reset source
.
Selecting the supply monito
as a reset source before it has stabilized may generate a system reset. In systems where this reset
would be undesirable, a delay should be introduced between enabling the supply monitor and selecting
it as a reset source. See Section “4. Electrical Characteristics” on page 48 for minimum su
ly monitor
turn-on time.
No delay should be introduced in systems where software contain
utines that
erase or write Flash memory.
The procedure for enabling the V
supply monitor an
ecting it as a
DD
reset source is shown below:
1. Enable the Supply Monitor (VDMEN bit in VDM0CN = 1).
2. Wait for the Supply Monitor to stabilize (optional).
3. Select the Supply Monitor as a reset source (PORSF bit in RSTSRC =
).
281
Rev. 1.0
Si102x/3x
SFR Definition 22.1. VDM0CN: VDD Supply Monitor Control
Bit
7
6
5
4
3
2
1
VBOK
R
0
VBOKIE
R/W
0
Name
VDMEN VDDSTAT VDDOK VDDOKIE VBMEN
VBSTAT
Type
R/W
1
R
R
R/W
0
R/W
0
R
0
Reset
Varies
Varies
0
SFR Page = 0x0; SFR Address = 0xFF
Bit
Name
Function
7
VDMEN
Digital Supply Monitor Enable (Power Select Switch Output).
0: Digital Supply Monitor Disabled.
1: Digital Supply Monitor Enabled.
6
5
4
VDDSTAT
VDDOK
Digital Supply Status.
This bit indicates the current digital power supply status.
0: Digital supply is at or below the V
1: Digital supply is above the V
threshold.
threshold.
RST
RST
Digital Supply Status (Early Warning)
This bit indicates the current digital power supply status.
0: Digital supply is at or below
VDD
1: Digital supply is above the VDD
threshold.
WARN
threshold.
WARN
VDDOKIE
Digital Early Warning
nterrupt Enable.
Enables the V
Early
rning Interrupt.
DD
0: V
Early Warning Interrupt is disabled.
DD
1: V
Early W
rning Interrupt is enabled.
DD
3
2
VBMEN
VBSTAT
Analog Supply Monitor Enable (VBAT Pin).
0: Analog Supply Monitor Disabled.
1: Analog Supply Monitor Enabled.
Analog Supply Status.
This bit indicates the analog (VBAT) power supply status.
0: VBAT is at or below the V
threshold.
RST
1: VBAT is above the V
threshold.
RST
1
0
BOK
Analog Supply Status (Early Warning).
This bit indicates the current VBAT power supply status.
0: VBAT is at or below the VDD
threshold.
WARN
1: VBAT is above the VDD
threshold.
WARN
VBOKIE
Analog Early Warning Interrupt Enable.
Enables the VBAT Early Warning Interrupt.
0: VBAT Early Warning Interrupt is disabled.
1: VBAT Early Warning Interrupt is enabled.
Rev. 1.0
282
Si102x/3x
22.3. External
Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See
T
a
ble 4.6 for complete RST pin spec-
ifications. The external reset remains functional even when the device is in the low power suspend and
sleep modes. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
22.4. Missing
Clock Detector Reset
The missing clock detector (MCD) is a one-shot circuit that is triggered by the system clock. If the sys
em
clock remains high or low for more than 100 µs, the one-shot will time out and generate a r
t. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset s
rce; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the missing clock detector; wr
0 disables it.
The missing clock detector reset is automatically disabled when the device is in the low p
er suspend or
sleep mode. Upon exit from either low power state, the enabled/disabled state of this reset source is
restored to its previous value. The state of the RST pin is unaffected by this reset.
22.5. Comparator0
Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Com-
parator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC
ill read 1 signifying Comparator0 as the
reset source; otherwise, this bit reads 0. The Comparator0 rese
source remains functional even when the
device is in the low power suspend and sleep states as long as Comparator0 is also enabled as a wake-up
source. The state of the RST pin is unaffected by this
et.
22.6. PCA
Watchdog Timer Reset
The programmable watchdog timer (WDT) fu
ion of the programmable counter array (PCA) can be used
to prevent software from running out of contr
uring a system malfunction. The PCA WDT function can
be enabled or disabled by software as described in Section “34.4. Watchdog Timer Mode” on page 516;
the WDT is enabled and clocked by
YSCLK / 12 following any reset. If a system malfunction prevents
user software from updating the WD
, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to 1.
The PCA watchdog timer reset source is automatically disabled when the device is in the low power sus-
pend or sleep mode. Upon ex
t from either low power state, the enabled/disabled state of this reset source
is restored to its previous value.The state of the RST pin is unaffected by this reset.
283
Rev. 1.0
Si102x/3x
22.7. Flash
Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above the Lock Byte address.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above the Lock Byte address.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the Lock Byte address.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see
tion
“18.3. Security Options” on page 246).
A Flash write or erase is attempted while the V
Monitor is disabled.
DD
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
22.8. SmaRTClock
(Real Time Clock) Reset
The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or SmaRT-
Clock Alarm. The SmaRTClock Oscillator Fail event occurs when
he SmaRTClock missing clock detector
is enabled and the SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm event occurs
when the SmaRTClock Alarm is enabled and the SmaRTClo
mer value matches the ALARMn regis-
ters. The SmaRTClock can be configured as a reset source by writing a 1 to the RTC0RE flag
(RSTSRC.7). The SmaRTClock reset remains functio
al even when the device is in the low power Sus-
pend or Sleep mode. The state of the RST pin is una
d by this reset.
22.9. Software
Reset
Software may force a reset by writing a 1 to
SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
Rev. 1.0
284
Si102x/3x
SFR Definition 22.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
PINRSF
R
Name
RTC0RE FERROR C0RSEF
SWRSF WDTRSF
MCDRSF
PORSF
R/W
Type
R/W
R
R/W
R/W
R
R/W
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xEF.
Bit
Name
Description
Write
d
7
RTC0RE
SmaRTClock Reset Enable
0: Disable SmaRTClock
Set to 1 if SmaRTClock
alarm or oscillator fail
aused the last reset.
and Flag
as a reset source.
1: Enable SmaRTClock as
a reset source.
6
5
FERROR
Flash Error Reset Flag.
N/A
Set to 1 if Flash
read/write/erase error
caused the last reset.
C0RSEF
Comparator0 Reset Enable
0: Disable C
arator0 as
Set to 1 if Comparator0
and Flag.
a reset source.
caused the last reset.
1: Enable Comparator0 as
a r
source.
4
3
2
SWRSF
Software Reset Force and
Writing a 1 forces a sys-
tem reset.
Set to 1 if last reset was
caused by a write to
SWRS
F
.
Flag.
WDTRSF
Watchdog Timer Reset Flag.
N/A
Set to 1 if watchdog timer
overflow caused the last
reset.
MCDRSF
Missing Clock Detector
0: Disable the MCD.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
(MCD) Enable and Flag.
1: Enable the MCD.
The MCD triggers a reset
if a missing clock condition
is detected.
1
PORSF
Power-On / Power-Fail
0: Disable the VDD Supply
Set to 1 anytime a power-
Reset Flag, and Power-Fail
Monitor as a reset source.
on or V
monitor reset
DD
2
Reset Enable.
occurs.
1: Enable the VDD Supply
Monitor as a reset
source.
3
0
PINRSF
HW Pin Reset Flag.
N/A
Set to 1 if RST pin caused
the last reset.
Notes:
1.
It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2.
If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3.
Writing a 1 to PORSF before the VDD Supply Monitor is stabilized may generate a system reset.
285
Rev. 1.0
Si102x/3x
23. Clocking
Sources
Si102x/3x devices include a programmable precision internal oscillator, an external oscillator drive circuit,
a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal oscilla-
tor can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 23.1. The external oscillator can be configured using the OSCXCN register. The low power internal
oscillator is automatically enabled and disabled when selected and deselected as a clock source. SmaR
Clock operation is described in the SmaRTClock oscillator chapter.
The system clock (SYSCLK) can be derived from the precision internal oscillator, external oscillator, low
power internal oscillator, low power internal oscillator divided by 8, or SmaRTClock oscillator
he global
clock divider can generate a system clock that is 1, 2, 4, 8, 16, 32, 64, or 128 times slowe
at the selected
input clock source. Oscillator electrical specifications can be found in the Electrical Spe
ons Chapter.
OSCICL
OSCICN
CLKSE
Option 2
VDD
Option 3
XTAL2
XTAL2
EN
Precision
Internal Oscillator
Prec
sion Internal Oscillator
External Oscillator
CLKRDY
Option 1
XTAL1
External
Oscillator
10M
Drive Circuit
n
SYSCLK
Low Power Internal Oscillator
XTAL2
Low Power Internal
Clock Divider
Oscillator Divided by 8
8
Option 4
XTAL2
SmaRTClock Oscillator
SmaRTClock
Oscillator
Low Power
Internal Oscillator
OSCXCN
Figure 23.1. Clocking Sources Block Diagram
The proper way of changing the system clock when both the clock source and the clock divide value are
being chan
d is as follows:
If s
ing from a fast “undivided” clock to a slower “undivided” clock:
1. Change the clock divide value.
2. Poll for CLKRDY > 1.
3. Change the clock source.
If switching from a slow “undivided” clock to a faster “undivided” clock:
1. Change the clock source.
2. Change the clock divide value.
3. Poll for CLKRDY > 1.
Rev. 1.0
286
Si102x/3x
23.1. Programmable
Precision Internal Oscillator
All Si102x/3x devices include a programmable precision internal oscillator that may be selected as the sys-
tem clock. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. See Section “4. Electrical Charac-
teristics” on page 48 for complete oscillator specifications.
The precision oscillator supports a spread spectrum mode which modulates the output frequency in order
to reduce the EMI generated by the system. When enabled (SSE = 1), the oscillator output frequency
modulated by a stepped triangle wave whose frequency is equal to the oscillator frequency divided by 38
(63.8 kHz using the factory calibration). The deviation from the nominal oscillator frequency is +0%, –1.6%,
and the step size is typically 0.26% of the nominal frequency. When using this mode, the typical average
oscillator frequency is lowered from 24.5 MHz to 24.3 MHz.
23.2. Low
Power Internal Oscillator
All Si102x/3x devices include a low power internal oscillator that defaults as the system clock after a sys-
tem reset. The low power internal oscillator frequency is 20 MHz ± 10% and is automatically enabled when
selected as the system clock and disabled when not in use. See Section “4. Electrical Characteristics” on
page 48 for complete oscillator specifications.
23.3. External
Oscillator Drive Circuit
All Si102x/3x devices include an external oscillator circuit that may drive an external crystal, ceramic reso-
nator, capacitor, or RC network. A CMOS clock may also provide a clock input. Figure 23.1 shows a block
diagram of the four external oscillator options. The external os
lator is enabled and configured using the
OSCXCN register.
The external oscillator output may be selected as the system clock or used to clock some of the digital
peripherals (e.g., Timers, PCA, etc.). See the data s
et chapters for each digital peripheral for details.
See Section “4. Electrical Characteristics” on page 48 f
complete oscillator specifications.
23.3.1. External Crystal Mode
If a crystal or ceramic resonator is used as th
ternal oscillator, the crystal/resonator and a 10 M
resis-
tor must be wired across the XTAL1 and XTAL2 pins as shown in Figure 23.1, Option 1. Appropriate load-
ing capacitors should be added to XTAL1 and XTAL2, and both pins should be configured for analog I/O
with the digital output drivers disable
.
Figure 23.2 shows the external oscillator circuit for a 20 MHz quartz crystal with a manufacturer recom-
mended load capacitance of 12.5 p
F
.
L
oading capacitors are “in series” as seen by the crystal and “in par-
allel” with the stray capacitance of the XTAL1 and XTAL2 pins. The total value of the each loading
capacitor and the stray capacitance of each XTAL pin should equal 12.5 pF x 2 = 25 p
F
.
W
ith a stray
capacitance of 10
p
per pin, the 15
pF capacitors yield an equivalent series capacitance of 12.5
pF
across the crystal.
Note:
The recommended load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal
data
eet when completing these calculations.
287
Rev. 1.0
Si102x/3x
15 pF
XTAL1
XTAL2
10 Mohm
25 MHz
15 pF
Figure 23.2. 25 MHz External Crystal Example
Important Note on External Crystals:
Crystal oscillator circuits are quite
nsitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the dev
e. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
When using an external crystal, the external oscillator drive circuit must be configured by software for
Crys-
tal Oscillator Mode
or
Crystal Oscillator Mode with divide by 2
e
. The divide by 2 stage ensures that the
clock derived from the external oscillator has a duty cycle o
50
The External Oscillator Frequency Con-
trol value (XFCN) must also be specified based on the crystal frequency. The selection should be based on
T
a
ble 23.1. For example, a 25 MHz crystal requires an
FCN setting of 111b.
Table 23.1. Recommended XFCN Settings for Crystal Mode
XFCN
Crystal Frequency
Bias Current
Typical Supply Current
(VDD = 2.4 V)
000
001
010
011
100
101
110
111
f
20 kH
0.5 µA
1.5 µA
4.8 µA
14 µA
3.0 µA, f = 32.768 kHz
4.8 µA, f = 32.768 kHz
9.6 µA, f = 32.768 kHz
28 µA, f = 400 kHz
71 µA, f = 400 kHz
193 µA, f = 400 kHz
940 µA, f = 8 MHz
20 kHz
f
58 kHz
58 kHz
f
155 kHz
155 kHz
f
415 kHz
415 kHz
f
1.1 MHz
MHz
f
3.1 MHz
3.1 MHz
f
8.2 MHz
8.2 MHz
f
25 MHz
40 µA
120 µA
550 µA
2.6 mA
3.9 mA, f = 25 MHz
Wh
e crystal oscillator is first enabled, the external oscillator valid detector allows software to deter-
mine when the external system clock has stabilized. Switching to the external oscillator before the crystal
oscillator has stabilized can result in unpredictable behavior. The recommended procedure for starting the
crystal is as follows:
1. Configure XTAL1 and XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
3. Poll for XTLVLD => 1.
4. Switch the system clock to the external oscillator.
Rev. 1.0
288
Si102x/3x
23.3.2. External RC Mode
If an RC network is used as the external oscillator, the circuit should be configured as shown in
Figure 23.1, Option 2. The RC network should be added to XTAL2, and XTAL2 should be configured for
analog I/O with the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The resistor should be no smaller tha
10 k
. The oscillation frequency can be determined by the following equation:
1.23
10
3
R
C
————————
f
=
where
f = frequency of clock in MHzR = pull-up resistor value in k
= power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
V
DD
To
d
etermine the required External Oscillator Frequency Control value (XFC
in the OSCXCN Register,
first select the RC network value to produce the desired frequency of oscill
ion. For example, if the fre-
quency desired is 100 kHz, let R = 246 k
and C = 50 pF:
1.23
10
3
R
C
1.23
10
3
246
50
————————
————————
= 100
kHz
f
=
=
where
f = frequency of clock in MHz
= power supply voltage in Volts
R = pull-up resistor value in k
C = capacitor v
lue on the XTAL2 pin in pF
V
DD
Referencing
T
a
ble 23.2, the recommended XFCN
etting is 010.
Table 23.2. Recommend
XFCN Settings for RC and C modes
XFCN
Approximate
K Factor (C Mode)
Typical Supply Current/ Actual
Frequency Rang
(RC
and C Mod
Measured Frequency
(C Mode, VDD = 2.4 V)
000
001
010
011
100
101
110
11
f
25 kHz
K Factor = 0.87
K Factor = 2.6
K Factor = 7.7
K Factor = 22
K Factor = 65
K Factor = 180
K Factor = 664
K Factor = 1590
3.0 µA, f = 11 kHz, C = 33 pF
5.5 µA, f = 33 kHz, C = 33 pF
13 µA, f = 98 kHz, C = 33 pF
32 µA, f = 270 kHz, C = 33 pF
82 µA, f = 310 kHz, C = 46 pF
242 µA, f = 890 kHz, C = 46 pF
1.0 mA, f = 2.0 MHz, C = 46 pF
4.6 mA, f = 6.8 MHz, C = 46 pF
25 kHz
f
50 kHz
50 kHz
f
100 kHz
100 kHz
f
200 kHz
kHz
f
400 kHz
400 kHz
f
800 kHz
800 kHz
f
1.6 MHz
1.6 MHz
f
3.2 MHz
When the RC oscillator is first enabled, the external oscillator valid detector allows software to determine
when oscillation has stabilized. The recommended procedure for starting the RC oscillator is as follows:
1. Configure XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
3. Poll for XTLVLD > 1.
4. Switch the system clock to the external oscillator.
289
Rev. 1.0
Si102x/3x
23.3.3. External Capacitor Mode
If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 23.1,
Option 3. The capacitor should be added to XTAL2, and XTAL2 should be configured for analog I/O with
the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however, for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The oscillation frequency and the require
External Oscillator Frequency Control value (XFCN) in the OSCXCN Register can be determined by t
following equation:
KF
C
V
DD
——————-
–
–
f
=
where
f = frequency of clock in MHzR = pull-up resistor value in k
= power supply voltage in VoltsC = capacitor value on the XTAL2 pin in
V
DD
Below is an example of selecting the capacitor and finding the frequency of oscillation Assume V
= 3.0 V
DD
and f = 150 kHz:
KF
C
V
DD
——————-
–
–
f
=
KF
C
3.0
—————–
0.150 MHz
=
Since a frequency of roughly 150 kHz is des
select the K Factor from
T
a
ble 23.2 as KF = 22:
22
C
3.0 V
———————
–
–
0.150 MHz
=
22
———————————————-
C =
0.150 MHz
3.0 V
C = 48.8
pF
Theref
re,
e XFCN value to use in this example is 011 and C is approximately 50 p
F
.
The
commended startup procedure for C mode is the same as RC mode.
23.3.4. External CMOS Clock Mode
If an external CMOS clock is used as the external oscillator, the clock should be directly routed into XTAL2.
he XTAL2 pin should be configured as a digital input. XTAL1 is not used in external CMOS clock mode.
The external oscillator valid detector will always return zero when the external oscillator is configured to
External CMOS Clock mode.
Rev. 1.0
290
Si102x/3x
23.4. Special
Function Registers for Selecting and Configuring the System Clock
The clocking sources on Si102x/3x devices are enabled and configured using the OSCICN, OSCICL,
OSCXCN and the SmaRTClock internal registers. See Section “24. SmaRTClock (Real Time Clock)” on
page 295 for SmaRTClock register descriptions. The system clock source for the MCU can be selected
using the CLKSEL register.
T
o
m
inimize active mode current, the oneshot timer which sets Flash read time
should by bypassed when the system clock is greater than 10 MHz. See the FLSCL register description fo
details.
The clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching
between two clock divide values, the transition may take up to 128 cycles of the undivided clock source.
The CLKRDY flag can be polled to determine when the new clock divide value has been applie
. The clock
divider must be set to “divide by 1” when entering Suspend or Sleep Mode.
The system clock source may also be switched on-the-fly. The switchover takes effect
ter one clock
period of the slower oscillator.
SFR Definition 23.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
1
0
Name
CLKRDY
CLKDIV[2:0]
R/W
CLKSEL[2:0]
R/W
R
0
R/W
0
Type
0
0
1
0
1
0
Reset
SFR Page = All Pages; SFR Address = 0xA9
Bit
Name
Function
7
CLKRDY
System Clock Divi
Clock Ready Flag.
0: The selected clock divide setting has not been applied to the system clock.
1: The selec
d clock divide setting has been applied to the system clock.
6:4
CLKDIV[2:0]
System Cl
ck Divider Bits.
Selects the clock division to be applied to the undivided system clock source.
000: System clock is divided by 1.
001: System clock is divided by 2.
010: System clock is divided by 4.
011: System clock is divided by 8.
100: System clock is divided by 16.
101: System clock is divided by 32.
110: System clock is divided by 64.
111: System clock is divided by 128.
Read = 0b. Must Write 0b.
3
Unused
2:0
CLKSEL[2:0]
System Clock Select.
Selects the oscillator to be used as the undivided system clock source.
000: Precision Internal Oscillator.
001: External Oscillator.
010: Low Power Oscillator divided by 8.
011: SmaRTClock Oscillator.
100: Low Power Oscillator.
All other values reserved.
291
Rev. 1.0
Si102x/3x
SFR Definition 23.2. OSCICN: Internal Oscillator Control
Bit
7
6
5
4
3
2
1
0
Name
IOSCEN
IFRDY
R
R/W
0
R/W
R/W
R/W
R/W
R/W
R/W
Type
0
Varies
Varies
Varies
Varies
Varies
Varies
Reset
SFR Page = 0x0; SFR Address = 0xB2
Bit
Name
Function
7
IOSCEN
Internal Oscillator Enable.
0: Internal oscillator disabled.
1: Internal oscillator enabled.
6
IFRDY
Internal Oscillator Frequency Ready Flag.
0: Internal oscillator is not running at its programmed frequency.
1: Internal oscillator is running at its programmed frequency.
5:0
Reserved Must
perform read-modify-write.
Notes:
1.
Read-modify-write operations such as ORL and ANL must be used to set or clear the enable bit of this
register.
2.
OSCBIAS (REG0CN.4) must be set to 1 before
abling the precision internal oscillator.
Rev. 1.0
292
Si102x/3x
SFR Definition 23.3. OSCICL: Internal Oscillator Calibration
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SSE
R/W
OSCICL
[6:0]
R/W
R
R/W
R/W
R/W
R/W
R/W
0
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xB3
Bit
Name
Function
7
SSE
Spread Spectrum Enable.
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
6:0
OSCICL
Internal Oscillator Calibration.
Factory calibrated to obtain a frequency of 24.5 MHz. Incrementing this register
decreases the oscillator frequency and decrementing this register increases the
oscillator frequency. The step size is app
mately 1% of the calibrated frequency.
The recommended calibration frequency r
ge is between 16 and 24.5 MHz.
Note:
If the Precision Internal Oscillator is selected as the system clock, the following procedure should be used
when changing the value of the internal oscillator c
ation bits.
1. Switch to a different clock source.
2. Disable the oscillator by writing OSCICN.7 t
0.
3. Change OSCICL to the desired setting.
4. Enable the oscillator by writing OSCICN
1.
293
Rev. 1.0
Si102x/3x
SFR Definition 23.4. OSCXCN: External Oscillator Control
Bit
7
6
5
4
3
2
1
0
Name
XCLKVLD
XOSCMD[2:0]
R/W
XFCN[2:0]
R/W
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Type
0
0
Reset
SFR Page = 0x0; SFR Address = 0xB1
Bit
Name
XCLKVLD
External Oscillator Valid Flag.
Function
7
Provides External Oscillator status and is valid at all times for all modes of operation
except External CMOS Clock Mode and External CMO
Clock Mode with divide by
2. In these modes, XCLKVLD always returns 0.
0: External Oscillator is unused or not yet stable.
1: External Oscillator is running and stable.
6:4
XOSCMD
External Oscillator Mode Bits.
Configures the external oscillator circuit t
e selected mode.
00x: External Oscillator circuit disabled.
010: External CMOS Clock Mode
011: External CMOS Clock Mode
h divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillato
ode.
110: Crystal Oscillator M
e.
111: Crystal Oscillator Mode with divide by 2 stage.
3
Reserved Read
= 0b. Mu
Write 0b.
2:0
XFCN
External Oscillator Frequency Control Bits.
Controls the external oscillator bias current.
000-111: See
T
a
ble 23.1 on page 288 (Crystal Mode) or
T
a
ble 23.2 on page 289 (RC
or C Mode) for recommended settings.
Rev. 1.0
294
Si102x/3x
24. SmaRTClock
(Real Time Clock)
Si102x/3x devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time Clock) with alarm.
The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a crystal.
No external resistor or loading capacitors are required. The on-chip loading capacitors are programmable
to 16 discrete levels allowing compatibility with a wide range of crystals. The SmaRTClock can operate
directly from a 1.8–3.6 V battery voltage and remains operational even when the device goes into its lo
est power down mode. The SmaRTClock output can be buffered and routed to a GPIO pin to provide a
accurate, low frequency clock to other devices while the MCU is in its lowest power down mode (see
“PMU0MD: Power Management Unit Mode” on page 267 for more details). Si102x/3x devices also support
an ultra low power internal LFO that reduces sleep mode current.
The SmaRTClock allows a maximum of 36
hour 32-bit independent time-keeping
used with a
32.768 kHz Watch Crystal. The SmaRTClock provides an Alarm and Missing SmaRTClo
events, which
could be used as reset or wakeup sources. See Section “22. Reset Sources” on page 278 and Section
“19. Power Management” on page 257 for details on reset sources and low power mo
e wake-up sources,
respectively.
XTAL3
RTCOUT
XTAL4
SmaRTClock
Power/
Clock
Mgmt
LFO
Programmable Load Capacitors
SmaRTClock Oscillator
32-Bit
SmaRTClock
Timer
SmaRTClock State Machine
w/ 3 Independe
Alarms
Wake-Up
Interrupt
Interface
CAPTUREn
RTC0CN
Registers
RTC0KEY
RTC0ADR
RTC0DAT
Internal
R
ters
RTC0XCN
RTC0XCF
RTC0CF
ALARMnBn
Figure 24.1. SmaRTClock Block Diagram
Rev. 1.0
295
Si102x/3x
24.1. SmaRTClock
Interface
The SmaRTClock Interface consists of three registers: RTC0KE
Y
,
R
TC0ADR, and RTC0DA
T
.
T
hese inter-
face registers are located on the CIP-51’s SFR map and provide access to the SmaRTClock internal regis-
ters listed in
T
a
ble 24.1. The SmaRTClock internal registers can only be accessed indirectly through the
SmaRTClock Interface.
Table 24.1. SmaRTClock Internal Registers
SmaRTClock SmaRTClock
Register Name
Description
Address
Register
0x00–0x03
CAPTUREn SmaRTClock
Capture
Registers
Four Registers used for setti
32-bit
SmaRTClock timer or reading i
rrent value.
0x04
0x05
0x06
RTC0CN
SmaRTClock Control
Register
Controls the operation of the SmaRTClock State
Machine.
RTC0XCN SmaRTClock
Oscillator Controls
the opera
n of the SmaRTClock
Control Register
Oscillator.
RTC0XCF SmaRTClock
Oscillator Controls
the value of the progammable
Configuration Register
oscillato
load capacitance and
enables/disables AutoStep.
0x07
RTC0CF
SmaRTClock
Configuration Register
Conta
ns an alarm enable and flag for each
SmaRTClock alarm.
0x08–0x0B
0x0C–0x0F
0x10–0x13
ALARM0Bn SmaRTClock
Alarm
Registers
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
ALARM1Bn SmaRTClock
rm
Registers
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
ALARM2Bn SmaRTClock
Alarm
Reg
ers
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
296
Rev. 1.0
Si102x/3x
24.1.1. SmaRTClock Lock and Key Functions
The SmaRTClock Interface has an RTC0KEY register for legacy reasons, however, all writes to this regis-
ter are ignored. The SmaRTClock interface is always unlocked on Si102x/3x.
24.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DA
T
.
T
he
RTC0ADR register selects the SmaRTClock internal register that will be targeted by subsequent reads
writes. A SmaRTClock Write operation is initiated by writing to the RTC0DAT register. Below is an exampl
of writing to a SmaRTClock internal register.
1. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Add
ss 0x05.
2. Write 0x00 to RTC0DA
T
.
T
his operation writes 0x00 to the internal RTC0CN regist
A SmaRTClock Read operation is initiated by writing the register address to RTC0ADR
reading from
RTC0DA
T
.
B
elow is an example of reading a SmaRTClock internal register.
1. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTC
ock Address 0x05.
2. Read data from RTC0DA
T
.
T
his data is a copy of the RTC0CN register.
24.1.3. SmaRTClock Interface Autoread Feature
When Autoread is enabled, each read from RTC0DAT initiates the next indirect read operation on the
SmaRTClock internal register selected by RTC0ADR. Software should set the register address once at the
beginning of each series of consecutive reads. Autoread is enabled by setting AUTORD (RTC0ADR.6) to
logic 1.
24.1.4. RTC0ADR Autoincrement Feature
For ease of reading and writing the 32-bit CAPTURE
nd ALARM values, RTC0ADR automatically incre-
ments after each read or write to a CAPTUREn or AL
n register. This speeds up the process of setting
an alarm or reading the current SmaRTClock tim
alue. Autoincrement is always enabled.
Recommended Instruction Timing for a multi-
e register read with auto read enabled:
mov RTC0ADR, #040h
mov A, RTC0DAT
mov A, RTC0DAT
mov A, RTC0DAT
mov A, RTC0DAT
Recommended Instruction Timing for a multi-byte register write:
mov RTC0ADR, #010h
mov RTC0DAT, #
mov RTC0DAT, #06h
mov RTC0DAT, #07h
mov RTC0
AT, #08h
Rev. 1.0
297
Si102x/3x
SFR Definition 24.1. RTC0KEY: SmaRTClock Lock and Key
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
RTC0ST[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAE
Bit
Name
Function
7:0
RTC0ST
SmaRTClock Interface Status.
Provides lock status when read.
Read:
0x02:
SmaRTClock Interface is unlocked.
Write:
Writes to RTC0KEY have no effect.
SFR Definition 24.2. RTC0ADR: SmaRTCl
Address
Bit
7
6
AUTORD
R/W
5
4
3
2
ADDR[4:0]
R/W
1
0
Name
Type
Reset
R
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAC
Bit
Name
Function
7
Reserved
ead = 0; Write = don’t care.
6
AUTORD
SmaRTClock Interface Autoread Enable.
Enables/disables Autoread.
0: Autoread Disabled.
1: Autoread Enabled.
5
Unused Read
= 0b; Write = Don’t Care.
4:0 ADDR[4:0]
SmaRTClock Indirect Register Address.
Sets the currently selected SmaRTClock register.
See
T
a
ble 24.1 for a listing of all SmaRTClock indirect registers.
Note:
The ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMnBn
internal SmaRTClock register.
298
Rev. 1.0
Si102x/3x
SFR Definition 24.3. RTC0DA
T
:
S
maRTClock Data
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
RTC0DAT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xAD
Bit
Name
Function
7:0
RTC0DAT
SmaRTClock Data Bits.
Holds data transferred to/from the internal SmaRTClock register selected by
RTC0ADR.
Note:
Read-modify-write instructions (orl, anl, etc.) should not be used on this register.
Rev. 1.0
299
Si102x/3x
24.2. SmaRTClock
Clocking Sources
The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The
SmaRTClock timebase can be derived from an external CMOS clock, the internal LFO, or the SmaRT-
Clock oscillator circuit, which has two modes of operation: Crystal Mode, and Self-Oscillate Mode. The
oscillation frequency is 32.768 kHz in Crystal Mode and can be programmed in the range of 10 kHz to
40 kHz
in Self-Oscillate Mode. The internal LFO frequency is 16.4
kHz ±20%.
The frequency of th
SmaRTClock oscillator can be measured with respect to another oscillator using an on-chip timer. S
Section “33. Timers” on page 483 for more information on how this can be accomplished.
Note:
The SmaRTClock timebase can be selected as the system clock and routed to a port pin. See Section
“23. Clocking Sources” on page 286 for information on selecting the system clock source and Sec
n “27. Port
Input/Output” on page 351 for information on how to route the system clock to a port pin. T
maRTClock
timebase can also be routed to a port pin while the device is in its ultra low power sleep m
e the
PMU0MD register description for details.
24.2.1. Using the SmaRTClock Oscillator with a Crystal or External CMOS Clock
When using Crystal Mode, a 32.768 kHz crystal should be connected between XTAL3 and XTAL4. No
other external components are required. The following steps show how to
rt the SmaRTClock crystal
oscillator in software:
1. Configure the XTAL3 and XTAL4 pins for Analog I/O.
2. Set SmaRTClock to Crystal Mode (XMODE = 1).
3. Disable Automatic Gain Control (AGCEN) and enable Bia
Doubling (BIASX2) for fast crystal startup.
4. Set the desired loading capacitance (RTC0XCF).
5. Enable power to the SmaRTClock oscillator circuit (RTC0EN = 1).
6. Wait 20 ms.
7. Poll the SmaRTClock Clock Valid Bit (CLKV
) until the crystal oscillator stabilizes.
8. Poll the SmaRTClock Load Capacitance Ready Bit (LOADRDY) until the load capacitance reaches
its programmed value.
9. Enable Automatic Gain Control (AGCEN) and disable Bias Doubling (BIASX2) for maximum power
savings.
10. Enable the SmaRTClock missing clock detector.
11. Wait 2 ms.
12. Clear the PMU0CF wake-up source flags.
In Crystal Mode, the SmaRTClock oscillator may be driven by an external CMOS clock. The CMOS clock
should be applied
AL3. XTAL34 should be left floating. In this mode, the external CMOS clock is ac
coupled into the SmaRTClock and should have a minimum voltage swing of 400 mV. The CMOS clock sig-
nal voltage should not exceed VDD or drop below GND. Bias levels closer to VDD will result in lower I/O
power con
mption because the XTAL3 pin has a built-in weak pull-up. The SmaRTClock oscillator should
be c
ured to its lowest bias setting with AGC disabled. The CLKVLD bit is indeterminate when using a
CMO
clock, however, the OSCFAIL bit may be checked 2 ms after SmaRTClock oscillator is powered on
to ensure that there is a valid clock on XTAL3. The CLKVLD bit is forced low when BIASX2 is disabled.
300
Rev. 1.0
Si102x/3x
24.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode
When using Self-Oscillate Mode, the XTAL3 and XTAL4 pins are internally shorted together. The following
steps show how to configure SmaRTClock for use in Self-Oscillate Mode:
1. Configure the XTAL3 and XTAL4 pins for analog I/O and disable the digital driver.
2. Set SmaRTClock to Self-Oscillate Mode (XMODE = 0).
3. Set the desired oscillation frequency:
For oscillation at about 20 kHz, set BIASX2 = 0.
For oscillation at about 40 kHz, set BIASX2 = 1.
4. The oscillator starts oscillating instantaneously.
5. Fine tune the oscillation frequency by adjusting the load capacitance (RTC0XCF).
24.2.3. Using the Low Frequency Oscillator (LFO)
The low frequency oscillator provides an ultra low power, on-chip clock source to the SmaRTClock. The
typical frequency of oscillation is 16.4 kHz ±20%. No external components are required to use the LFO and
the XTAL3 and XTAL4 pins may be used for general purpose I/O without any effect on the LFO.
The following steps show how to configure SmaRTClock for use with the LFO
1. Enable and select the Low Frequency Oscillator (LFOEN = 1).
2. The LFO starts oscillating instantaneously.
When the LFO is enabled, the SmaRTClock oscillator increments bit 1 of the 32-bit timer (instead of bit 0).
This effectively multiplies the LFO frequency by 2, making th
C timebase behave as if a 32.768 kHz
crystal is connected at the output.
24.2.4. Programmable Load Capacitance
The programmable load capacitance has 16 values to
pport crystal oscillators with a wide range of rec-
ommended load capacitance. If Automatic Load
apacitance Stepping is enabled, the crystal load capaci-
tors start at the smallest setting to allow a fa
tartup time, then slowly increase the capacitance until the
final programmed value is reached. The fina
ogrammed loading capacitor value is specified using the
LOADCAP bits in the RTC0XCF register. The LOADCAP setting specifies the amount of on-chip load
capacitance and does not include an
stray PCB capacitance. Once the final programmed loading capaci-
tor value is reached, the LOADRDY
ag will be set by hardware to logic 1.
When using the SmaRTClock oscillator in Self-Oscillate mode, the programmable load capacitance can be
used to fine tune the oscillation frequency. In most cases, increasing the load capacitor value will result in
a decrease in oscillation
requency.
T
a
ble 24.2 shows the crystal load capacitance for various settings of
LOADCA
P
.
Rev. 1.0
301
Si102x/3x
Table 24.2. SmaRTClock Load Capacitance Settings
LOADCAP
Crystal Load Capacitance
Equivalent Capacitance seen on
XTAL3 and XTAL4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4.0 pF
4.5 pF
5.0 pF
5.5 pF
6.0 pF
6.5 pF
7.0 pF
7.5 pF
8.0 pF
8.5 pF
9.0 pF
9.5 pF
10.5 pF
11.5 pF
12.5 p
13.5 pF
8.0 pF
9.0 pF
10.0 pF
11.0 pF
12.0 pF
13.0 pF
14.0 pF
15
pF
16.0 pF
17.0 pF
18.0 pF
19.0 pF
21.0 pF
23.0 pF
25.0 pF
27.0 pF
24.2.5. Automatic Gain Control (C
stal Mode Only) and SmaRTClock Bias Doubling
Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in
order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects
when the oscillation amplitude has reached a point where it safe to reduce the drive current, therefore, it
may be enabled during crystal startup. It is recommended to enable Automatic Gain Control in most sys-
tems which use the SmaRTClock oscillator in Crystal Mode. The following are recommended crystal spec-
ifications and oper
conditions when Automatic Gain Control is enabled:
ESR < 50 k
Load Ca
citance < 10 pF
Su
ly Voltage < 3.0 V
T
perature > –20 °C
When using Automatic Gain Control, it is recommended to perform an oscillation robustness test to ensure
that the chosen crystal will oscillate under the worst case condition to which the system will be exposed.
he worst case condition that should result in the least robust oscillation is at the following system condi-
tions: lowest temperature, highest supply voltage, highest ESR, highest load capacitance, and lowest bias
current (AGC enabled, Bias Double Disabled).
To
p
erform the oscillation robustness test, the SmaRTClock oscillator should be enabled and selected as
the system clock source. Next, the SYSCLK signal should be routed to a port pin configured as a push-pull
digital output. The positive duty cycle of the output clock can be used as an indicator of oscillation robust-
302
Rev. 1.0
Si102x/3x
ness. As shown in Figure 24.2, duty cycles less than 65% indicate a robust oscillation. As the duty cycle
approaches 68%, oscillation becomes less reliable and the risk of clock failure increases. Increasing the
bias current (by disabling AGC) will always improve oscillation robustness and will reduce the output
clock’s duty cycle. This test should be performed at the worst case system conditions, as results at very
low temperatures or high supply voltage will vary from results taken at room temperature or low supply
voltage.
Low Risk of Clock
Failure
High Risk of Clock
Failure
Safe Operating Zone
Duty Cycle
25%
65%
68%
Figure 24.2. Interpreting Oscillation Robustness (Duty Cy
le) Test Results
As an alternative to performing the oscillation robustness test, Automatic Gain Control may be disabled at
the cost of increased power consumption (approximately 200 nA
. Disabling Automatic Gain Control will
provide the crystal oscillator with higher immunity against external factors which may lead to clock failure.
Automatic Gain Control must be disabled if using the SmaRTC
oscillator in self-oscillate mode.
T
a
ble 24.3 shows a summary of the oscillator bias settings. The SmaRTClock Bias Doubling feature allows
the self-oscillation frequency to be increased (almost
bled) and allows a higher crystal drive strength in
crystal mode. High crystal drive strength is recommen
when the crystal is exposed to poor environmen-
tal conditions such as excessive moisture. Sm
TClock Bias Doubling is enabled by setting BIASX2
(RTC0XCN.5) to 1.
.
Table 24
3. SmaRTClock Bias Settings
Mode
Setting
Power
Consumption
Crystal
Bias Double Off, AGC On
Bias Double Off, AGC Off
Bias Double On, AGC On
Bias Double On, AGC Off
Bias Double Off
Lowest
Low
High
Highest
Low
Self-Oscillate
Bias Double On
High
Rev. 1.0
303
Si102x/3x
24.2.6. Missing SmaRTClock Detector
The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN.6) to 1.
When the SmaRTClock missing clock detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if
SmaRTClock oscillator remains high or low for more than 100 µs.
A SmaRTClock Missing Clock detector timeout can trigger an interrupt, wake the device from a low power
mode, or reset the device. See Section “17. Interrupt Handler” on page 231, Section “19. Power Manag
ment” on page 257, and Section “22. Reset Sources” on page 278 for more information.
Note:
The SmaRTClock missing clock detector should be disabled when making changes to the oscillator settings in
RTC0XCN.
24.2.7. SmaRTClock Oscillator Crystal Valid Detector
The SmaRTClock oscillator crystal valid detector is an oscillation amplitude detector
used during
crystal startup to determine when oscillation has started and is nearly stable. The outpu
f this detector
can be read from the CLKVLD bit (RTX0XCN.4).
Notes:
1.
The CLKVLD bit has a blanking interval of 2 ms. During the first 2 ms after tur
g on the crystal oscillator, the
output of CLKVLD is not valid.
2.
This SmaRTClock crystal valid detector (CLKVLD) is not intended for
etecti
g an oscillator failure. The
missing SmaRTClock detector (CLKFAIL) should be used for this purpose.
3.
The CLKVLD bit output is driven low when BIASX2 is disabled.
24.3. SmaRTClock
Timer and Alarm Function
The SmaRTClock timer is a 32-bit counter that, when running (RTC0TR = 1), is incremented every
SmaRTClock oscillator cycle. The timer has an alarm function that can be set to generate an interrupt,
wake the device from a low power mode, or reset th
vice at a specific time. See Section “17. Interrupt
Handler” on page 231, Section “19. Power Manageme
” on page 257, and Section “22. Reset Sources”
on page 278 for more information.
The SmaRTClock timer includes an auto re
eature, which automatically resets the timer to zero one
SmaRTClock cycle after the alarm 0 signal is deasserted. When using auto reset, the alarm match value
should always be set to 2 counts less than the desired match value. When using the LFO in combination
with auto reset, the right-justified ala
match value should be set to 4 counts less than the desired match
value. Auto reset can be enabled by writing a 1 to ALRM (RTC0CN.2).
24.3.1. Setting and Reading the SmaRTClock Timer Value
The 32-bit SmaRTClock t
mer can be set or read using the six CAPTUREn internal registers. Note that the
timer does not need to be stopped before reading or setting its value. The following steps can be used to
set the timer value:
1. Write the desired 32-bit set value to the CAPTUREn registers.
2. Write 1 to RTC0SE
T
.
T
his will transfer the contents of the CAPTUREn registers to the SmaRTClock
timer
peration is complete when RTC0SET is cleared to 0 by hardware.
The following steps can be used to read the current timer value:
1. Write 1 to RTC0CA
P
.
T
his will transfer the contents of the timer to the CAPTUREn registers.
2. Poll RTC0CAP until it is cleared to 0 by hardware.
3. A snapshot of the timer value can be read from the CAPTUREn registers
Notes:
1.
If the system clock is faster than 4x the SmaRTClock, then the HSMODE bit should be set to allow the set and
capture operations to be concluded quickly (system clock used for transfers).
2.
If the system clock is slower than 4x the SmaRTClock, then HSMODE should be set to zero, and RTC must be
304
Rev. 1.0
Si102x/3x
running (RTC0TR = 1) in order to set or capture the main timer. The transfer can take up to 2 smaRTClock
cycles to complete.
24.3.2. Setting a SmaRTClock Alarm
The SmaRTClock alarm function compares the 32-bit value of SmaRTClock Timer to the value of the
ALARMnBn registers. An alarm event is triggered if the SmaRTClock timer is
equal to
the ALARMnBn
registers. If Auto Reset is enabled, the 32-bit timer will be cleared to zero one SmaRTClock cycle after the
alarm 0 event.
The SmaRTClock alarm event can be configured to reset the MCU, wake it up from a low power mode, or
generate an interrupt. See Section “17. Interrupt Handler” on page 231, Section “19. Power Management”
on page 257, and Section “22. Reset Sources” on page 278 for more information.
The following steps can be used to set up a SmaRTClock Alarm:
1. Disable SmaRTClock Alarm Events (RTC0AEN = 0).
2. Set the ALARMn registers to the desired value.
3. Enable SmaRTClock Alarm Events (RTC0AEN = 1).
Notes:
1.
The ALRM bit, which is used as the SmaRTClock Alarm Event flag, is cleared by disabling SmaRTClock Alarm
Events (RTC0AEN = 0).
2.
If AutoReset is disabled, disabling (RTC0AEN = 0) then Re-enabling Alarm Events (RTC0AEN = 1) after a
SmaRTClock Alarm without modifying ALARMn registers will
matically schedule the next alarm after 2^32
SmaRTClock cycles (approximately 36 hours using a 32.768 k
rystal).
24.3.3. Software Considerations for using the SmaRTClock Timer and Alarm
The SmaRTClock timer and alarm have two operatin
odes to suit varying applications. The two modes
are described below:
Mode 1:
The first mode uses the SmaRTClock timer a
erpetual timebase which is never reset to zero. Every 36
hours, the timer is allowed to overflow without being stopped or disrupted. The alarm interval is software
managed and is added to the ALRMnBn registers by software after each alarm. This allows the alarm
match value to always stay ahead o
the timer by one software managed interval. If software uses 32-bit
unsigned addition to increment the alarm match value, then it does not need to handle overflows since
both the timer and the alarm match value will overflow in the same manner.
This mode is ideal for applications which have a long alarm interval (e.g., 24 or 36 hours) and/or have a
need for a perpetual timebase. An example of an application that needs a perpetual timebase is one
whose wake-up interval is constantly changing. For these applications, software can keep track of the
number of timer ov
ws in a 16-bit variable, extending the 32-bit (36 hour) timer to a 48-bit (272 year)
perpetual timebase.
Mode 2:
The s
ond mode uses the SmaRTClock timer as a general purpose up counter which is auto reset to zero
by h
dware after each alarm 0 event. The alarm interval is managed by hardware and stored in the
ALRM0Bn registers. Software only needs to set the alarm interval once during device initialization. After
each alarm 0 event, software should keep a count of the number of alarms that have occurred in order to
keep track of time. Alarm 1 and alarm 2 events do not trigger the auto reset.
This mode is ideal for applications that require minimal software intervention and/or have a fixed alarm
interval. This mode is the most power efficient since it requires less CPU time per alarm.
Rev. 1.0
305
Si102x/3x
Internal Register Definition 24.4. RTC0CN: SmaRTClock Control
Bit
7
6
5
4
3
2
1
0
Name
RTC0EN MCLKEN OSCFAIL RTC0TR
HSMODE RTC0SET RTC0CAP
Type
R/W
0
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Varies
SmaRTClock Address = 0x04
Bit
Name
Function
7
RTC0EN
SmaRTClock Enable.
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
6
5
4
MCLKEN
Missing SmaRTClock Detector Enable.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
OSCFAIL
SmaRTClock Oscillator Fail Event Flag.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be
cleared by software. The value of th
s bit is not defined when the SmaRTClock
oscillator is disabled.
RTC0TR
SmaRTClock Timer Run Co
rol.
Controls if the SmaRTClo
imer is running or stopped (holds current value).
0: SmaRTClock timer is st
ed.
1: SmaRTClock timer is running.
3
2
Reserved Read
= 0b; Must
ite 0b.
HSMODE
High Speed Mode Enable.
Should be set to 1 if the system clock is faster than 4x the SmaRTClock frequency.
0: High Speed Mode is disabled.
1: H
gh Speed Mode is enabled.
1
0
RTC0SET
aRTClock Timer Set.
W
ting 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hard-
ware to indicate that the timer set operation is complete.
RTC
CAP
SmaRTClock Timer Capture.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by
hardware to indicate that the timer capture operation is complete.
306
Rev. 1.0
Si102x/3x
Internal Register Definition 24.5. RTC0XCN: SmaRTClock Oscillator Control
Bit
7
6
XMODE
R/W
0
5
BIASX2
R/W
0
4
3
LFOEN
R/W
0
2
1
0
Name
AGCEN
CLKVLD
Type
R/W
0
R
0
R
0
R
0
R
0
Reset
SmaRTClock Address = 0x05
Bit
Name
Function
7
AGCEN
SmaRTClock Oscillator Automatic Gain Control (AGC) Enable.
0: AGC disabled.
1: AGC enabled.
6
5
XMODE
SmaRTClock Oscillator Mode.
Selects Crystal or Self Oscillate Mode.
0: Self-Oscillate Mode selected.
1: Crystal Mode selected.
BIASX2
SmaRTClock Oscillator Bias Double Ena
Enables/disables the Bias Double feature.
0: Bias Double disabled.
1: Bias Double enabled.
4
3
CLKVLD
SmaRTClock Oscillator Crys
al Valid Indicator.
Indicates if oscillation am
e is sufficient for maintaining oscillation. This bit always
reads 0 when BIASX2 is disabled.
0: Oscillation has not started or oscillation amplitude is too low to maintain oscillation.
1: Sufficient oscil
ion amplitude detected.
LFOEN
Low Frequency Oscillator Enable and Select.
Overrides XMODE and selects the internal low frequency oscillator (LFO) as the
SmaRTClock oscillator source.
0: XMODE determines SmaRTClock oscillator source.
1
LFO enabled and selected as SmaRTClock oscillator source.
2:0
Unused Read
= 000b; Write = Don’t Care.
Rev. 1.0
307
Si102x/3x
Internal Register Definition 24.6. RTC0XCF: SmaRTClock Oscillator Configuration
Bit
7
6
5
4
3
2
1
0
Name
AUTOSTP LOADRDY
LOADCAP
R/W
Type
R/W
0
R
0
R
0
R
0
Reset
Varies
Varies
Varies
Varies
SmaRTClock Address = 0x06
Bit
Name
Function
7
AUTOSTP
Automatic Load Capacitance Stepping Enable.
Enables/disables automatic load capacitance stepping.
0: Load capacitance stepping disabled.
1: Load capacitance stepping enabled.
6
LOADRDY
Load Capacitance Ready Indicator.
Set by hardware when the load capacitance matches the programmed value.
0: Load capacitance is currently stepping.
1: Load capacitance has reached it pro
mmed value.
5:4
3:0
Unused
Read = 00b; Write = Don’t Care.
LOADCAP
Load Capacitance Programm
Value.
Holds the user’s desired va
e of the load capacitance. See
T
a
ble 24.2 on
page 302.
308
Rev. 1.0
Si102x/3x
Internal Register Definition 24.7. RTC0CF: SmaRTClock Configuration
Bit
7
6
ALRM2
R/W
0
5
ALRM1
R/W
0
4
3
2
1
0
Name
Type
Reset
ALRM0 AUTORST
RTC2EN RTC1EN RTC0EN
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SmaRTClock Address = 0x07
Bit
Name
Function
7
Reserved Read
= 0b; Must write 0b.
6
ALRM2
Event Flag for Alarm 2.
This bit must be cleared by software. Writing a 1 to this bit has no effect.
0: An Alarm 2 event has not occurred since the last time
flag was cleared.
1: An Alarm 2 event has occurred.
5
4
3
ALRM1
Event Flag for Alarm 1.
This bit must be cleared by software. Writing a 1 to this bit has no effect.
0: An Alarm 1 event has not occurred since the last time the flag was cleared.
1: An Alarm 1 event has occurred.
ALRM0
Event Flag for Alarm 0.
This bit must be cleared by softwa
Writing a 1 to this bit has no effect.
0: An Alarm 0 event has not occurr
since the last time the flag was cleared.
1: An Alarm 0 event has occu
d.
AUTORST
Auto Reset Enable.
Enables the Auto Reset function to clear the counter when an Alarm 0 event occurs.
0: Auto Reset is disabled
1: Auto Reset is
abled.
2
1
0
ALRM2EN
Alarm 2 Enable.
0: Alarm 2 is disabled.
1: Alarm 2 is enabled.
ALRM1EN
Alarm 1 Enable.
arm 1 is disabled.
1
Alarm 1 is enabled.
ALRM0EN
Alarm 0 Enable.
0: Alarm 0 is disabled.
1: Alarm 0 is enabled.
Rev. 1.0
309
Si102x/3x
Internal Register Definition 24.8. CAPTUREn: SmaRTClock Timer Capture
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CAPTURE[31:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SmaRTClock Addresses: CAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPTURE2 =0x02;
URE3: 0x03.
Bit Name
Function
7:0 CAPTURE[31:0]
SmaRTClock Timer Capture.
These 4 registers (CAPTURE3–CAPTURE0) are used to read or set the 32-bit
SmaRTClock timer. Data is transferred to or from th
maRTClock timer when
the RTC0SET or RTC0CAP bits are set.
Note:
The least significant bit of the timer capture value is CAPTURE0.0.
Internal Register Definition 24.9. ALARM0Bn: Sm
TClock Alarm 0 Match Value
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
LARM0[31:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SmaRTClock Address: ALARM0B0
0x08; ALARM0B1 = 0x09; ALARM0B2 = 0x0A; ALARM0B3 = 0x0B
Bit Name
Function
7:0 ALARM0[31:0]
SmaRTClock Alarm 0 Programmed Value.
These 4 registers (ALARM0B3–ALARM0B0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (ALRM0EN=0)
when updating these registers.
Note:
The leas
significant bit of the alarm programmed value is ALARM0B0.0.
310
Rev. 1.0
Si102x/3x
Internal Register Definition 24.10. ALARM1Bn: SmaRTClock Alarm 1 Match Value
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
ALARM1[31:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SmaRTClock Address: ALARM1B0 = 0x0C; ALARM1B1 = 0x0D; ALARM1B2 = 0x0E;
M1B3 = 0x0F
Bit Name
Function
7:0 ALARM1[31:0]
SmaRTClock Alarm 1 Programmed Value.
These 4 registers (ALARM1B3–ALARM1B0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should b
isabled (ALRM1EN=0)
when updating these registers.
Note:
The least significant bit of the alarm programmed value is iALARM1B0.0.
Internal Register Definition 24.11. ALARM2Bn: S
RTClock Alarm 2 Match Value
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
LARM2[31:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SmaRTClock Address: ALARM2B0
0x10; ALARM2B1 = 0x11; ALARM2B2 = 0x12; ALARM2B3 = 0x13
Bit Name
Function
7:0 ALARM2[31:0]
SmaRTClock Alarm 2 Programmed Value.
These 4 registers (ALARM2B3–ALARM2B0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (ALRM2EN=0)
when updating these registers.
Note:
The leas
significant bit of the alarm programmed value is ALARM2B0.0.
Rev. 1.0
311
Si102x/3x
25. Low-Power
Pulse Counter
The Si102x/3x family of microcontrollers contains a low-power pulse counter module with advanced fea-
tures, such as ultra low power input comparators, a wide range of pull up values with a self calibration
engine, asymmetrical integrators for low pass filtering and switch debounce, single, dual, and quadrature
modes of operation, two 24-bit counters, and a variety of interrupt and sleep wake-up capabilities. This
combination of features provides water, gas, and heat metering system designers with an optimal tool
saving power while collecting meter usage data.
VBAT
Comparat
0
PC0DCH
PC0DCL
PC0C
:M:L
PC0PCF
PC0
debounce
debounce
Counter 0
PC0CTR0H:M:L
Logic
PC1
Counter 1
PC0CTR1H:M:L
PC0TH
PC0MD
Comparator 1
PC0CMP1H:M:L
PC0INT0
Figure 25.1. Pulse Counter Block Diagram
The low-power pulse counter is a low-power sleep-mode peripheral designed primarily to work meters
using reed switches, including water and gas meters. The pulse counter is very flexible and can count
pulses from many different types of sources.
The pulse counter
ates in sleep mode to enable ultra-low power metering systems. The MCU does not
have to wake up on every edge or transition and can remain in sleep mode while the pulse counter counts
pulses for an extended period of time. The pulse counter includes two 24-bit counters. These counters can
24
count up to 16,777,215 (2
-1) transitions in sleep mode before overflowing. The pulse counter can wake
up
CU when one of the counters overflows. The pulse counter also has two 24-bit digital compara-
tors. The comparators have the ability to wake up the MCU when the one of the counters reaches a prede-
termined count.
The pulse counter uses the RTC clock for sampling, de-bouncing, and managing the low-power pull-up
esistors. The RTC must be enabled when counting pulses. The RTC alarms can wake up the MCU peri-
odically to read the pulse counters instead of using the pulse counter digital comparators. For example, the
RTC can wake up the MCU every five minutes. The MCU can then read the pulse counter and transmit the
information using the UART or a wireless transceiver.
Rev. 1.0
312
Si102x/3x
25.1. Counting
Modes
The pulse counter supports three different counting modes: single counter mode, dual counter mode, and
quadrature counter mode. Figure 25.2 illustrates the three counter modes.
Single Counter Mode Example
PC0
Dual Counter Mode Example
PC1
PC0
Quadrature Counter
ode Example
clockwise
counter-clockwise
clockwise
PC1
PC0
Figure 25.2. Mode Examples
The single counter mode uses only one pulse counter pin PC0 (P1.0) to count pulses from a single input
channel. This mode uses only Counter 0 and Comparator 0. (Counter 1 and Comparator 1 are not used.)
The single
unter mode supports only one meter-encoder with a single-channel output. A single-channel
enco
is an effective solution when the metered fluid flows only in one direction. A single-channel
enco
er does not provide any direction information and does not support bidirectional fluid metering.
The dual counter mode supports two independent single-channel meters. Each meter has its own indepen-
dent counter and comparator. Some of the global configuration settings apply to both channels, such as
ull-up current, sampling rate, and debounce time. The dual mode may also be used for a redundant count
using a two-channel non-quadrature encoder.
Quadrature counter mode supports a single two-channel quadrature meter encoder. The quadrature
counter mode supports bidirectional encoders and applications with bidirectional fluid flow. In quadrature
counter mode, clockwise counts will increment Counter 0, while counterclockwise counts will increment
Counter 1. Subtracting Counter 1 from Counter 0 will yield the net position. If the normal fluid flow is clock-
313
Rev. 1.0
Si102x/3x
wise, then the counterclockwise Counter 1 value represents the cumulative backflow. Firmware may use
the backflow counter with the corresponding comparator to implement a backflow alarm. The clockwise
sequence is (LL-HL-HH-LH), and the counterclockwise sequence is (LL-LH-HH-HL). (For this sequence
LH means PC1 = Low and PC0 = High.)
Firmware cannot write to the counters. The counters are reset when PC0MD is written and have their
counting enabled when the PC0MD[7:6] mode bits are set to either single, dual, or quadrature modes. The
counters only increment and will roll over to 0x000000 after reaching 0xFFFFF
F
.
F
or single mode, the P
input connects to Counter 0. In dual mode, the PC0 input connects to Counter 0 while the PC1 input con-
nects to Counter 1. In Quadrature mode, clockwise counts are sent to Counter 0 while counterc
ockwise
counts are sent to Counter 1.
25.2. Reed
Switch Types
The pulse counter works with both Form-A and Form-C reed switches. A Form-A swit
a Normally-
Open Single-Pole Single-Throw (NO SPST) switch. A Form-C reed switch is a Single-Pole Double-Throw
(SPDT) switch. Figure 25.3 illustrates some of the common reed switch configurations for a single-channel
meter.
The Form-A switch requires a pull-up resistor. The energy used by the pull-u
es
stor may be a substantial
portion of the energy budget.
T
o
m
inimize energy usage, the pulse counter has a programmable pull-up
resistance and an automatic calibration engine. The calibration engine can automatically determine the
smallest usable pull-up strength setting. A Form-C switch does not require a pull-up resistor and will pro-
vide a lower power solution. However, the Form-C switches are more expensive and require an additional
wire for VBA
T
.
VBAT
Form A
pull-up required
PC0
Form C
V
no pull-up
PC0
Figure 25.3. Reed Switch Configurations
Rev. 1.0
314
Si102x/3x
25.3. Programmable
Pull-Up Resistors
The pulse counter features low-power pull-up resistors with a programmable resistance and duty-cycle.
The average pull-up current will depend on the selected resistor, sample rate, and pull-up duty-cycle multi-
plier. Example code is available that will calculate the values for the pull-up configuration SFR (PC0PCF).
T
a
ble 25.1through
T
a
ble 25.3 are used with Equation 25.1 to calculate the average pull-up resistor current.
T
a
ble 25.4through
T
a
ble 25.7 give the average current for all combinations.
I
=
I
D
D
pull-up
R
SR
PU
Equation 25.1. Average Pull-Up Current
Where:
I =
Pull-up Resistor current selected by PC0PCF[4:2].
R
D
D
= Sample Rate Duty Cycle Multiplier selected by PC0MD[5:4].
= Pull-Up Duty Cycle Multiplier selected by PC0PCF[4:2].
SR
PU
Table 25.1. Pull-Up Resistor Current
PC0PCF[4:2]
I
R
000
001
010
011
100
10
11
111
0
1
A
4
A
16
A
64
A
256
A
1 mA
4 mA
Table 25.2. Sample Rate Duty-Cycle Multiplier
PC0MD[5:4]
D
SR
00
01
10
11
1
1/2
1/4
1/8
Table 25.3. Pull-Up Duty-Cycle Multiplier
PC0PCF[1:0]
D
PU
00
01
10
11
1/4
3/8
1/2
3/4
315
Rev. 1.0
Si102x/3x
Table 25.4. Average Pull-Up Current (Sample Rate = 250 µs)
PC0PCF[4:2]
Duty
Cycle
000
001
010
011
100
101
110
111
PC0PCF[1:0]
disabled 250
nA 1.0
µA
disabled 375
nA 1.5
µA
disabled 500
nA 2.0
µA
4.0 µA
6.0 µA
8.0 µA
16 µA
24 µA
32 µA
64 µA
96 µA
250 µA
1000 µA
25%
00
01
10
11
375 µA
1500 µA
37.5%
128 µA
500 µA
2000 µA
192 µA
750 µA
3000 µA
50%
75%
disabled 750
nA 3.0
µA 12.0
µA 48
µA
Table 25.5. Average Pull-Up Current (Sample Rate = 500 µs)
PC0PCF[4:2]
Duty
Cycle
000
001
010
011
100
101
110
111
PC0PCF[1:0]
disabled 125
nA 0.50
µA 2.0
µA
disabled 188
nA 0.75
µA 3.0
µA
8 µA
32 µA
48 µA
64 µA
96 µA
125 µA
500 µA
12.5%
188 µA
750 µA
18.8%
00
01
10
11
12 µA
16 µA
24 µA
disabled 250
nA 1.0
µA
disabled 375
nA 1.5
µA
4.0 µA
6.0 µA
250 µA
1000 µA
25%
375 µA
1500 µA
37.5%
Table 25.6.
Average Pull-Up Current (Sample Rate = 1 ms)
PC0PCF[4:2]
Duty
Cycle
000
001
010
011
100
4 µA
6 µA
8 µA
12 µA
101
110
111
PC0PCF[1:0]
disabled 63
nA
disabled 94
nA
2
0 nA
1.0 µA
375 nA
1.5 µA
16 µA
24 µA
32 µA
48 µA
63 µA
94 µA
250 µA
375 µA
6.3%
9.4%
00
01
10
11
disabled 125
nA 500
nA 2.0
µA
disabled 188
nA 750
nA 3.0
µA
125 µA
500 µA
12.5%
188 µA
750 µA
18.8%
T
ble 25.7. Average Pull-Up Current (Sample Rate = 2 ms)
PC0PCF[4:2]
Duty
Cycle
PC0
F[1:
]
000
001
010
011
100
101
110
111
disabled 31
nA
disabled 47
nA
disabled 63
nA
disabled 94
nA
125 nA
0.50 µA
2.0 µA
8 µA
31 µA
125 µA
3.1%
4.7%
6.3%
9.4%
0
188 nA
0.75 µA
3.0 µA
12 µA
16 µA
24 µA
47 µA
63 µA
94 µA
188 µA
250 µA
375 µA
01
10
11
250 nA
1.0 µA
375 nA
1.5 µA
4.0 µA
6.0 µA
Rev. 1.0
316
Si102x/3x
25.4. Automatic
Pull-Up Resistor Calibration
The pulse counter includes an automatic calibration engine which can automatically determine the mini-
mum pull-up current for a particular application. The automatic calibration is especially useful when the
load capacitance of field wiring varies from one installation to another.
The automatic calibration uses one of the pulse counter inputs (PC0 or PC1) for calibration. The CAL-
PORT bit in the PC0PCF SFR selects either PC0 or PC1 for calibration. The reed switch on the selecte
input should be in the open state to allow the node to charge during calibration. The calibration engine c
calibrate the pull-ups with the meter connected normally, provided that the reed switch is open during cali-
bration. During calibration, the integrators will ignore the input comparators, and the counters will no
be
incremented. Using a 250 µs sample rate and a 32 kHz RTCCLK, the calibration time will b
21 ms (28
tests @ 750 µs each) or shorter depending on the pull up strength selected. The calibr
will fail if the
reed switch remains closed during this entire period. If the reed switch is both opened
osed during
the calibration period, the value written into PCCF[4:0] may be larger than what is actual
required. The
transition flag in the PC0INT1 can detect when the reed switch opens, and most systems with a wheel
rotation of 10 Hz or slower should have sufficient high time for the calibration to complete before the next
closing of the reed switch. Slowing the sample rate will also increase the cali
ation time. The same drive
strength will used for both PC0 and PC1.
The example code for the pulse counter includes code for managing t
e automatic calibration engine.
25.5. Sample
Rate
The pulse counter has a programmable sampling rate. The p
se counter samples the state of the reed
switches at discrete time intervals based on the RTC clock. T
C0MD SFR sets the sampling rate. The
system designer should carefully consider the maximum pulse rate for the particular application when set-
ting the sampling rate and debounce time. Sample rates from 250 µs to 2 ms can be selected to either fur-
ther reduce power consumption or work with shorter
e widths. The slowest sampling rate (2 ms) will
provide the lowest possible power consumption.
25.6. Debounce
Like most mechanical switches, reed switches exhibit switch bouncing that could potentially result in false
counts or quadrature errors. The pulse counter includes digital debounce logic using a digital integrator
that can eliminate false counts due
switch bounce. The input of the integrator connects to the pulse
counter inputs with the programmable pull-ups. The output connects to the counters.
The debounce integrator has two independent programmable thresholds: one for the rising edge
(Debounce High) and one for the falling edge (Debounce Low). The PC0DCH (PC0 Debounce Config
High) SFR sets the threshold for the rising edge. This SFR sets the number of cumulative high samples
required to output a logic high to the counter. The PC0DCL (PC0 Debounce Config Low) SFR sets the
threshold for the fa
edge. This SFR sets the number of cumulative low samples required to output a
logic low to the counter.
Note that the debounce does count consecutive samples. Requiring consecutive samples would be sus-
ceptible to
oise. The digital integrator inherently filters out noise.
The
em designer should carefully consider the maximum anticipated counter frequency and duty-cycle
when setting the debounce time. If the debounce configuration is set too large, the pulse counter will not
count short pulses. The debounce-high configuration should be set to less than one-half the minimum
input pulse high-time. Similarly, the debounce-low configuration should be set to less than one-half the
inimum input pulse low-time.
Figure 25.4 illustrates the operation of the debounce integrator. The top waveform is the representation of
the reed switch (high: open, low: closed) which shows some random switch bounce. The bottom waveform
is the final signal that goes into the counter which has the switch bounce removed. Based on the actual
reed switch used and sample rate, the switch bounce time may appear shorter in duration than the exam-
ple in Figure 25.4. The second waveform is the pull-up resistor enable signal. The enable signal enables
317
Rev. 1.0
Si102x/3x
the pull-up resistor when high and disables when low. PC0 is the line to the reed switch. On the right side
of PC0 waveform, the line voltage is decreasing towards ground when the pull-up resistors are disabled.
Beneath the charging waveform, the arrows represent the sample points. The pulse counter samples the
PC0 voltage once the charging completes. The sensed ones and zeros are the sampled data. Finally the
integrator waveform illustrates the output of the digital integrator. The integrator is set to 4 initially and
counts to down to 0 before toggling the output low. Once the integrator reaches the low state, it needs to
count up to 4 before toggling its output to the high state. The debounce logic filters out switch bounce
noise that appears for a short duration.
Debounce
Debounce
Switch
Charging
Samples
PC0
Sensed
1
4
1
4
0
3
1
4
1
4
0
3
0
2
0
1
0
0
1
1
0
0
1
1
1
2
1
3
1
4
Integrator
(set to 4)
Integrator
Integrator Output
Figure 25.4. Debounce Timing
25.7. Reset
Behavior
Unlike most MCU peripherals, an MCU reset does not completely reset the pulse counter. This includes a
power on reset and all other reset
urces. An MCU reset does not clear the counter values. The pulse
counter SFRs do not reset to a default value upon reset. The 24-bit counter values are persistent unless
cleared manually by writing to the PC0MD SFR. Note that if the VBAT voltage ever drops below the mini-
mum operating voltage, this may compromise contents of the counters.
The PC0MD register should normally be written only once after reset. The PC0MD SFR is the master
mode register. This register sets the counter mode and sample rate. Writing to the PC0MD SFR also
resets the other PC
SFRs.
Note that the RTC clock will reset on an MCU reset, so counting cannot resume until the RTC clock has
been re-sta
d.
Firm
e should read the reset sources SFR RSTSRC to determine the source of the last reset and initial-
ize t
pulse counter accordingly.
When the pulse counter resets, it takes some time (typically two RTC clock cycles) to synchronize between
internal clock domains. The counters do not increment during this synchronization time.
5.8. Wake
up and Interrupt Sources
The pulse counter has multiple interrupt and wake-up source conditions.
T
o
e
nable an interrupt, enable the
source in the PC0INT0/1 SFRs and enable the pulse counter interrupt using bit 4 of the EIE2 register. The
pulse counter interrupt service routine should read the interrupt flags in PC0INT0/1 to determine the
source of the interrupt and clear the interrupt flags.
Rev. 1.0
318
Si102x/3x
To
e
nable the pulse counter as a wake up source, enable the source in the PC0INT0/1 SFRs and enable
the pulse counter as a wake-up source by setting bit 0 (PC0WK) to 1 in the PMU0FL SFR. Upon waking,
firmware should read the PMCU0CF and PMU0FL SFRs to determine the wake-up source. If the PC0WK
bit is set indicating that the pulse counter has woke the MCU, firmware should read the flag bits PC0INT0/1
SFRs to determine the pulse counter wake-up source and clear the flag bits before going back to sleep.
PC0INT0 includes the more common interrupt and wake-up sources. These include comparator match,
counter overflow, and quadrature direction change. PC0INT1 includes interrupt and wake-up sources
the advanced features, including flutter detection and quadrature error.
25.9. Real-Time
Register Access
Several of the pulse counter registers values change in real-time synchronous to the RTC cloc
. Hardware
synchronization between the RTC clock domain and the system clock domain hardw
uld result in
long delays when reading real-time registers. Instead, real-time register values are a
ble instanta-
neously, but the read must be qualified using the read valid bit (PC0TH bit 0). If the register value does not
change during the read access, the read valid bit will be set indicating the last was va
id. If the value of the
real-time register changes during the read access, the read valid bit is 0, indicating the read was invalid.
After an invalid read, firmware must read the register and check the read val
bit again.
These 8-bit counter registers need to be qualified using the read valid bit:
PC0STAT
PC0HIST
PC0INT0
PC0INT1
PC0CTR0L
PC0CTC1L
The 24-bit counters are three-byte real-time read
nly registers that require a special access method for
reading. Firmware must read the low-byte (PC0
TR0L and PC0CTR1L) first and qualify using the read
valid bit. Reading the low-byte latches the mi
and high bytes. If the read valid bit is 0, the read is invalid
and firmware must read the low-byte and check the read valid bit again. If the read valid bit is set, the read
is valid and the middle and high bytes are also safe to read. Firmware should read the middle and high
bytes only after reading the low byte
d qualifying with the read valid bit.
The 24-bit comparators are three-byte real-time read-write registers that require a special access method
for writing. Firmware must write the low-byte last. After writing the low-byte, it might take up to two RTC
clock cycles for the new comparator value to take effect. System designers should consider the synchroni-
zation delay when setting the comparator value. The counter may be incremented before new comparator
value takes effect. Setting the comparator to at least 2 counts above the current count will eliminate the
chance of missing
omparator match during synchronization.
Example code is provided with accessor functions for all the real-time pulse counter registers.
25.10. A
anced Features
25.1
Quadrature Error
The quadrature encoder must only send valid quadrature codes. A valid quadrature sequence consists of
four valid states. The quadrature codes are only permitted to transition to one of the adjacent states, and
an invalid transition will result in a quadrature error. Note that a quadrature error is likely to occur when first
nabling the quadrature counter mode, since the pulse counter state machine starts at the LL state and the
initial state of the quadrature is arbitrary. It is safe to ignore the first quadrature error immediately after ini-
tialization.
319
Rev. 1.0
Si102x/3x
25.10.2. Flutter Detection
T
he flutter detection can be used with either quadrature counter mode or dual counter mode when the two
inputs are expected to be in step. Flutter refers to the case where one input continues toggling while the
other input stops toggling. This may indicate a broken reed switch or a pressure oscillation when the wheel
magnet stops at just the right distance from the reed switch. If a pressure oscillation causes a slight rota-
tional oscillation in the wheel, it could cause a number of pulses on one of the inputs, but not on the other.
All four edges are checked by the flutter detection feature (PC1 positive, PC1 negative, PC0 positive, a
PC0 negative).When enabled, Flutter detection may be used as an interrupt or wake-up source.
0
+1
+2
+3
+4
PC1
PC0
Next expected pulse
Flutter detected
Next expected pulse with direction change
Figure 25.5. Flutter Example
For example, flutter detected on the PC0 positive edge means that 4 edges (positive or negative) were
detected on PC1 since the last PC0 positive edge. Each P
ositive edge resets the flutter detection
counter while either PC1 edge increments the counter. There are similar counters for all four edges.
The flutter detection circuit provides interrupts or wak
p sources, but firmware must also read the pulse
counter registers to determine what corrective action,
ny, must be taken.
On the start of flutter event, the firmware should s
ve both counter values and the PC0HIST register. Once
the end of flutter event occurs the firmware s
ld also save both counter values and the PC0HIST regis-
ter. The stop count on flutter, STPCNTFLTR (P
MD[2]), be used to stop the counters when flutter is occur-
ring (quadrature mode only). For quadrature mode, the opposite counter should be decremented by one.
In other words, if the direction was
kwise, the counterclockwise counter (Counter 1) should be decre-
mented by one to correct for one increment before flutter was detected. For dual mode, two reed switches
can be used to get a redundant count. If flutter starts during dual mode, both counters should be saved by
firmware. After flutter stops, both counters should be read again. The counter that incremented the most
was the one that picked up the flutter. There is also a mode to switch from quadrature to dual (PC0MD[1])
when flutter occurs. This changes the counter style from quadrature (count on any edge of PC1 or PC0) to
dual to allow all cou
s to be recorded. Once flutter ends, this mode switches the counters back to quadra-
ture mode. STPCN
TR does not function when PC0MD[1] is set.
Rev. 1.0
320
Si102x/3x
SFR Definition 25.1. PC0MD: PC0 Mode Configuration
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCMODE[1:0]
R/W
PCRATE[1:0]
R/W
DUALCMPL
STPCNTFLTR
DUALSTCH
R/W
0
R
1
R/W
0
R
0
0
0
0
0
SFR Address = 0xD9; SFR Page = 0x2
Bit Name
7:6 PCMODE[1:0]
Counter Mode
Function
00: Pulse Counter disabled.
01: Single Counter mode.
10: Dual Counter mode.
11: Quadrature Counter mode.
5:4 PCRATE[1:0]
PC Sample Rate
00: 250 µs
01: 500 µs
10: 1 ms
11: 2 ms
3
2
Reserved
STPCNTFLTR
Stop Counting on Flu
er
(Only valid for quadrat
counter mode and DUALSTCH off.)
0: Disabled.
1: Enabled.
1
0
DUALSTCH
Dual Mode Switch During Flutter
(Only valid for quadrature counter mode.)
0: Disabled—quadrature mode remains set during flutter.
1: Enabled—quadrature mode changes to dual during flutter.
Reserved
Note that writing to this register will clear the counter registers PC0CTR0H:M:L and PC0CTR1H:M:L.
321
Rev. 1.0
Si102x/3x
SFR Definition 25.2. PC0PCF: PC0 Mode Pull-Up Configuration
Bit
7
6
5
4
3
RES[2:0]
R/W
2
1
0
Name
PUCAL
CALRES CALPORT
DUTY[1:0]
Type
R/W
0
R
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
Reset
0
SFR Address = 0xD7; SFR Page = 0x2
Bit
Name
Function
7
PUCAL
Pull-Up Driver Calibration
0: Calibration complete or not running.
1: Start calibration of pull up (Self clearing).
Calibration determines the lowest usable pull-up strength.
6
CALRES
Calibration Result
0: Fail (switch may be closed preventing detection of pull ups).
Writes value of 0x11111 to PC0
4:0]
1: Pass (writes calibrated value into PC0PCF[4:0]).
5
CALPORT
RES[2:0]
Calibration Port
0: Calibration on PC0 only.
1: Calibration on P
1 only.
4:2
Pull-Up Resis
elect
Current w
th force pull-up on bit set (PC0TH.2=1) and VBAT=3.6V.
000: P
-up disabled.
001: 1
A.*
010: 4
A.*
011: 16
A.*
100: 64
A.*
101: 256
A.*
110: 1 mA.*
111: 4 mA.*
*The effective average pull-up current depends on selected resistor, pull-up
resistor duty-cycle multiplier, and sample rate duty-cycle multiplier.
1:
DUTY[1:0]
Pull-Up Resistor Duty Cycle Multiplier
000: 1/4 (25%)*
001: 3/8 (37.5%)*
010: 1/2 (50%)*
011: 3/4 (75%)*
*The final pull-up resistor duty cycle is the sample rate duty-cycle multiplier
times the pull-up duty-cycle multiplier.
Rev. 1.0
322
Si102x/3x
SFR Definition 25.3. PC0TH: PC0 Threshold Configuration
Bit
7
6
5
4
3
PDOWN
R/W
0
2
1
0
RDVALI
R/W
Name
Type
Reset
PCTTHRESHI[1:0]
R/W
PCTHRESLO
[1:0]
PUP
R/W
0
R/W
R
0
0
0
0
0
1
SFR Address = 0xE4; SFR Page = 0x2
Bit
Name
Function
7:6
PCTTHRESHI[1:0]
Pulse Counter Input Comparator VIH Threshold
(Percentage of VIO.)
10: 50%
11: 55%
00: 59%
01: 63%
5:4
PCTHRESLO
[1:0]
Pulse Counter Input Comparator VIL Threshold
(percentage of VIO.)
10: 34%
11: 38%
00: 42%
01: 46%
3
2
PDOWN
PUP
Force Pull-Do
On
0: PC0 and PC1 pull-down not forced on.
1: PC0 and PC1 grounded.
Force Pull-Up
0: PC0 and PC1 pull-up not forced on continuously. See PC0PCF[1:0] for
duty cycle.
1: PC0 and PC1 pulled high continuously to the PC0PCF[4:2] setting.
PDOWN overrides PUP setting.
1
0
Reser
RDVALID
Read Valid
Holds the status of the last read for real-time registers PC0STA
T
,
P
C0HIS
T
,
PC0CTR0L, PC0CTR1L, PC0INT0, and PC0INT1.
0: The last read was invalid.
1: The last read was valid.
RDVALID is set back to 1 upon reading.
323
Rev. 1.0
Si102x/3x
SFR Definition 25.4. PC0STA
T
:
P
C0 Status
Bit
7
6
5
4
3
2
1
0
Name
FLUTTER
STATE[1:0]
RO
PC1PREV PC0PREV
PC1
PC0
DIRECTION
Type
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Reset
0
0
SFR Address = 0xC1; SFR Page = 0x2
Bit
Name
Function
7
FLUTTER
Flutter
During quadrature mode, a disparity may occur between the number of neg-
ative edges of PC1 and PC0 or the number of
sitive edges of PC1 and
PC0. This could indicate flutter on one reed switch or one reed switch may
be faulty.
0: No flutter detected.
1: Flutter detected.
6
Direction
DIRECTION
Only applicable for quadrature mode.
(First letter is PC1; seco
d letter is PC0)
0: Counter clock-wise –
LH-HH-HL)
1: Clock-wise – (LL
L-HH-LH)
5:4
3
STATE[1:0]
PC1PREV
PC0PREV
PC1
PC0 State
Current State of Internal State Machine.
PC1 P
vious
Previous Output of PC1 Integrator.
2
PC0 Previous
Previous Output of PC0 Integrator.
1
PC1
Current Output of PC1 Integrator.
0
PC0
PC0
Current Output of PC0 Integrator.
Rev. 1.0
324
Si102x/3x
SFR Definition 25.5. PC0DCH: PC0 Debounce Configuration High
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PC0DCH[7:0]
R/W
0
0
0
0
0
1
0
0
SFR Address = 0xFA; SFR Page = 0x2
Bit
Name
Function
7:0
PC0DCH[7:0]
Pulse Counter Debounce High
Number of cumulative good samples seen by the integrator before recogniz-
ing the input as high. Sampling a low will decr
ent the count while sam-
pling a high will increment the count. The actual value used is PC0DCH plus
one. Switch bounce produces a random looking signal. The worst case
would be to bounce low at each sample point and not start incrementing the
integrator until the switch bounce settled. Therefore, minimum pulse width
should account for twice the deb
unce time. For example, using a sample
rate of 250 µs and a PC0DCH v
of 0x13 will look for 20 cumulative
highs before recognizing the input as high (250 µs x (16+3+1) = 5 ms).
325
Rev. 1.0
Si102x/3x
SFR Definition 25.6. PC0DCL: PC0 Debounce Configuration Low
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PC0DCL[7:0]
R/W
0
0
0
0
0
1
0
0
SFR Address = 0xF9; SFR Page = 0x2
Bit
Name
Function
7:0
PC0DCL[7:0]
Pulse Counter Debounce Low
Number of cumulative good samples seen by the integrator before recogniz-
ing the input as low. Setting PC0DCL to 0x00 w
disable integrators on both
PC0 and PC1. The actual value used is PC0DCL plus one. Sampling a low
decrements while sampling a high increments the count. Switch bounce
produces a random looking signal. The worst case would be to bounce high
at each sample point and not start decrementing the integrator until the
switch bounce settled. Therefore
minimum pulse width should account for
twice the debounce time. For ex
le, using a sample rate of 1 ms and a
PC0DCL value of 0x09 will look for 10 cumulative lows before recognizing
the input as low (1 ms x
0 = 10 ms). The minimum pulse width should be
20 ms or greater for thi
ample. If PC0DCL has a value of 0x03 and the
sample rate is 500
, the integrator would need to see 4 cumulative lows
before recogniz
ng the low (500 µs x 4 = 2 ms). The minimum pulse width
should be 4 m
this example.
Rev. 1.0
326
Si102x/3x
SFR Definition 25.7. PC0CTR0H: PC0 Counter 0 High (MSB)
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PC0CTR0H[23:16]
R
0
0
0
0
0
0
0
0
SFR Address = 0xDC; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CTR0H[23:16]
PC0 Counter 0 High Byte
Bits 23:16 of Counter 0.
SFR Definition 25.8. PC0CTR0M: PC0 Counter 0 Middle
Bit
7
6
5
4
2
1
0
Name
Type
Reset
PC0CTR0M[15:8]
0
0
0
0
0
0
0
0
SFR Address = 0xD8; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CTR0M[15:8]
PC0 C
unter 0 Middle Byte
Bits 15:8 of Counter 0.
SFR Definition 25.9. PC0CTR0L: PC0 Counter 0 Low (LSB)
Bit
7
6
5
4
3
2
1
0
Name
Ty
Reset
PC0CTR0L[7:0]
R
0
0
0
0
0
0
0
0
FR Address = 0xDA; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CTR0L[7:0]
PC0 Counter 0 Low Byte
Bits 7:0 of Counter 0.
Note:
PC0CTR0L must be read before PC0CTR0M and PC0CTR0H to latch the count for reading. PC0CTRL must
be qualified using the RDVALID bit (PC0TH[0]).
327
Rev. 1.0
Si102x/3x
SFR Definition 25.10. PC0CTR1H: PC0 Counter 1 High (MSB)
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PC0CTR1H[23:16]
R
0
0
0
0
0
0
0
0
SFR Address = 0xDF; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CTR1H[23:16]
PC0 Counter 1 High Byte
Bits 23:16 of Counter 1.
SFR Definition 25.11. PC0CTR1M: PC0 Counter 1 Middle
Bit
7
6
5
4
2
1
0
Name
Type
Reset
PC0CTR1M[15:8]
0
0
0
0
0
0
0
0
SFR Address = 0xDE; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CTR1M[15:8]
PC0 C
unter 1 Middle Byte
Bits 15:8 of Counter 1.
SFR Definition 25.12. PC0CTR1L: PC0 Counter 1 Low (LSB)
Bit
7
6
5
4
3
2
1
0
Name
Ty
Reset
PC0CTR1L[7:0]
R
0
0
0
0
0
0
0
0
FR Address = 0xDD; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CTR1L[7:0]
PC0 Counter 1 Low Byte
Bits 7:0 of Counter 1.
Note:
PC0CTR1L must be read before PC0CTR1M and PC0CTR1H to latch the count for reading.
Rev. 1.0
328
Si102x/3x
SFR Definition 25.13. PC0CMP0H: PC0 Comparator 0 High (MSB)
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PC0CMP0H[23:16]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xE3; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CMP0H[23:16]
PC0 Comparator 0 High Byte
Bits 23:16 of Counter 0.
SFR Definition 25.14. PC0CMP0M: PC0 Comparator 0 Middle
Bit
7
6
5
4
2
1
0
Name
Type
Reset
PC0CMP0M[15:8]
/W
0
0
0
0
0
0
0
SFR Address = 0xE2; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CMP0M[15:8]
PC0 C
mparator 0 Middle Byte
Bits 15:8 of Counter 0.
SFR Definition 25.15. PC0CMP0L: PC0 Comparator 0 Low (LSB)
Bit
7
6
5
4
3
2
1
0
Name
Ty
Reset
PC0CMP0L[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xE1; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CMP0L[7:0]
PC0 Comparator 0 Low Byte
Bits 7:0 of Counter 0.
Note:
PC0CMP0L must be written last after writing PC0CMP0M and PC0CMP0H. After writing PC0CMP0L, the
synchronization into the PC clock domain can take 2 RTC clock cycles.
329
Rev. 1.0
Si102x/3x
SFR Definition 25.16. PC0CMP1H: PC0 Comparator 1 High (MSB)
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PC0CMP1H[23:16]
R/W
0
0
0
0
0
0
0
0
SFR Address = 0xF3; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CMP1H[23:16]
PC0 Comparator 1 High Byte
Bits 23:16 of Counter 0.
SFR Definition 25.17. PC0CMP1M: PC0 Comparator 1 Middle
Bit
7
6
5
4
2
1
0
Name
Type
Reset
PC0CMP1M[15:8]
W
0
0
0
0
0
0
0
0
SFR Address = 0xF2; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CMP1M[15:8]
PC0 C
mparator 1 Middle Byte
Bits 15:8 of Counter 0.
SFR Definition 25.18. PC0CMP1L: PC0 Comparator 1 Low (LSB)
Bit
7
6
5
4
3
2
1
0
Name
Ty
Reset
PC0CMP1L[7:0]
R/W
0
0
0
0
0
0
0
0
FR Address = 0xF1; SFR Page = 0x2
Bit
Name
Function
7:0
PC0CMP1L[7:0]
PC0 Comparator 1 Low Byte
Bits 7:0 of Counter 0.
Note:
PC0CMP1L must be written last after writing PC0CMP1M and PC0CMP1H. After writing PC0CMP1L the
synchronization into the PC clock domain can take 2 RTC clock cycles.
Rev. 1.0
330
Si102x/3x
SFR Definition 25.19. PC0HIS
T
:
P
C0 History
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PC0HIST[7:0]
R
0
0
0
0
0
0
0
0
SFR Address = 0xF4; SFR Page = 0x2
Bit
Name
Function
7:0
PC0HIST[7:0]
PC0 History.
Contains the last 8 recorded directions (1: clock-wise, 0: counter clock-wise)
on the previous 8 counts. Values of 0x55 or 0x
may indicate flutter during
quadrature mode.
331
Rev. 1.0
Si102x/3x
SFR Definition 25.20. PC0INT0: PC0 Interrupt 0
Bit
7
6
5
4
3
OVRF
R/W
0
2
1
0
Name
CMP1F CMP1EN CMP0F CMP0EN
OVREN DIRCHGF
DIRCHGE
Type
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
SFR Address = 0xFB; SFR Page = 0x2
Bit
Name
Function
7
CMP1F
Comparator 1 Flag
0: Counter 1 did not match comparator 1 value.
1: Counter 1 matched comparator 1 value.
6
5
4
3
2
1
CMP1EN
CMP0F
Comparator 1 Interrupt/Wake-up Source Enable
0:CMP1F not enabled as interrupt or wake-up source.
1:CMP1F enabled as interrupt or wake-up source.
Comparator 0 Flag
0: Counter 0 did not match comp
ator 0 value.
1: Counter 0 matched comparator 0 value.
CMP0EN
OVRF
Comparator 0 Interru
ake-up Source Enable
0:CMP0F not enab
as interrupt or wake-up source.
1:CMP0F enabl
d as interrupt or wake-up source.
Counter Overfl
w Flag
1:Neither of the counters has overflowed.
1:One
f the counters has overflowed.
OVREN
DIRCHGF
Counter Overflow Interrupt/Wake-up Source Enable
0:OVRF not enabled as interrupt or wake-up source.
1:OVRF enabled as interrupt or wake-up source.
Direction Change Flag
Direction changed for quadrature mode only.
0:No change in direction detected.
1:Direction Change detected.
0
DIRCHGEN
Direction Change Interrupt/Wake-up Source Enable
0:DIRCHGF not enabled as interrupt or wake-up source.
1:DIRCHGF enabled as interrupt or wake-up source.
Rev. 1.0
332
Si102x/3x
SFR Definition 25.21. PC0INT1: PC0 Interrupt 1
Bit
7
6
5
4
3
2
1
0
FLTRSTRF FLTRSTREN FLTRSTPF
FLTRSTPEN ERRORF ERROREN TRANSF
TRANSE
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xFC; SFR Page = 0x2
Bit
Name
Function
7
FLTRSTRF
Flutter Start Flag
Flutter detection for quadrature mode or dual mode only.
0: No flutter detected.
1: Start of flutter detected.
6
5
FLTRSTREN
FLTRSTPF
Flutter Start Interrupt/Wake-up Source Enable
0:FLTRSTRF not enabled as interrupt or wake-up source.
1:FLTRSTRF enabled as interrupt or wake-up source.
Flutter Stop Flag
Flutter detection for quadrature mode or dual mode only.
0: No flutter stop detected
1: Flutter stop detected.
4
3
2
1
0
FLTRSTPEN
ERRORF
Flutter Stop Inter
upt/Wake-up Source Enable
0:FLTRSTPF not
bled as interrupt or wake-up source.
1:FLTRSTPF enabled as interrupt or wake-up source.
Quadrat
e Error Flag
0: No Quadrature Error detected.
1: Quadrature Error detected.
ERROREN
TRANSF
Quadrature Error Interrupt/Wake-up Source Enable
0:ERRORF not enabled as interrupt or wake-up source.
1:ERRORF enabled as interrupt or wake-up source.
Transition Flag
0: No transition detected.
1: Transition detected on PC0 or PC1.
TRANSEN
Transition Interrupt/Wake-up Source Enable
0: TRANSF not enabled as interrupt or wake-up source.
1: TRANSF enabled as interrupt or wake-up source.
333
Rev. 1.0
Si102x/3x
26. LCD
Segment Driver (Si102x Only)
Si102x devices contain an LCD segment driver and on-chip bias generation that supports static, 2-mux, 3-
mux and 4-mux LCDs with 1/2 or 1/3 bias. The on-chip charge pump with programmable output voltage
allows software contrast control which is independent of the supply voltage. LCD timing is derived from the
SmaRTClock oscillator to allow precise control over the refresh rate.
The Si102x uses special function registers (SFRs) to store the enabled/disabled state of individual LC
segments. All LCD waveforms are generated on-chip based on the contents of the LCD0Dn registers. An
LCD blinking function is also supported. A block diagram of the LCD segment driver is shown in
Figure 26.1.
10 uF
VLCD
VBAT
LCD Segment Driver
Charge
Pump
Power
Management
Bias
Generat
r
32 Segment
Pins
SmaRTClock
Clock
Divider
LCD Clock
LCD State Machine
Port
Drivers
Configuration
Registers
Data Registers
4 COM Pins
Figure 26.1. LCD Segment Driver Block Diagram
26.1. Configuring
the LCD Segment Driver
The LCD segment
er supports multiple mux options: static, 2-mux, 3-mux, and 4-mux mode. It also
supports 1/2 and 1/3 bias options. The desired mux mode and bias is configured through the LCD0CN reg-
ister. A divid
value may also be applied to the SmaRTClock output before being used as the LCD0 clock
source
The
llowing procedure is recommended for using the LCD segment driver:
1. Initialize the SmaRTClock and configure the LCD clock divide settings in the LCD0CN register.
2. Determine the GPIO pins which will be used for the LCD function.
3. Configure the port I/O pins to be used for LCD as analog I/O.
4. Configure the LCD size, mux mode, and bias using the LCD0CN register.
5. Enable the LCD bias and clock gate by writing 0x50 to the LCD0MSCN register.
6. Configure the device for the desired Contrast Control Mode.
7. If VIO is internally or externally shorted to VBA
T
,
d
isable the VLCD/VIO supply comparator using the
Rev. 1.0
334
Si102x/3x
LCD0CF register.
8. Set the LCD contrast using the LCD0CNTRST register.
9. Set the desired threshold for the VBAT supply monitor.
10. Set the LCD refresh rate using the LCD0DIVH:LCD0DIVL registers.
11. Write a pattern to the LCD0Dn registers.
12. Enable the LCD by setting bit 0 of LCD0MSCN to logic 1 (LCD0MSCN |= 0x01).
26.2. Mapping
Data Registers to LCD Pins
The LCD0 data registers are organized as 16 byte-wide special function registers (LCD0Dn),
ach half-
byte or nibble in these registers controls 1 LCD output pin. There are 32 nibbles used to control
he 32 seg-
ment pins.
Each LCD0 segment pin can control 1, 2, 3, or 4 LCD segments depending on the selec
ed mux mode.
The least significant bit of each nibble controls the segment connected to the backplane signal COM0. The
next to least significant bit controls the segment associated with COM1, the next bit controls the segment
associated with COM2, and the most significant bit in the 4-bit nibble controls
e segment associated with
COM3.
In static mode, only the least significant bit in each nibble is used and the three remaining bits in each nib-
ble are ignored. In 2-mux mode, only the two least significant bits are used; in 3-mux mode, only the three
least significant bits are used, and in 4-mux mode, each of the 4 bits in the nibble controls one LCD seg-
ment. Bits with a value of 1 turn on the associated segment a
bits with a value of 0 turn off the associ-
ated segment.
SFR Definition 26.1. LCD0Dn: LCD0 Data
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
LCD0Dn
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page: 0x2
Addresses: LCD0D
0x89, LCD0D1 = 0x8A, LCD0D2 = 0x8B, LCD0D3 = 0x8C,
LCD0D
0x8D, LCD0D5 = 0x8E, LCD0D6 = 0x91, LCD0D7 = 0x92,
LCD0D8 = 0x93, LCD0D9 = 0x94, LCD0DA = 0x95, LCD0DB = 0x96,
CD0DC = 0x97, LCD0DD = 0x99, LCD0DE = 0x9A, LCD0DF = 0x9B.
B
Name
Function
7:0
LCD0Dn
LCD Data.
Each nibble controls one LCD pin.
See “26.2. Mapping Data Registers to LCD Pins” on page 335 for additional
information.
335
Rev. 1.0
Si102x/3x
Bit:
7
6
5
4
3
2
1
0
LCD0DF
(Pins: LCD31, LCD30)
LCD0DE
(Pins: LCD29, LCD28)
LCD0DD
(Pins: LCD27, L
6)
LCD0DC
(Pins: LCD25, LCD24)
LCD0DB
(Pins:
CD23, LCD22)
LCD0DA
(Pins: LCD21, LCD20)
LCD0D9
(Pins: LCD19, LCD18)
LCD0D8
(Pins: LCD17, LCD16)
LCD0D7
(Pins: LCD15, LCD14)
LCD0D6
(Pins: LCD13, LCD12)
LCD0D5
(Pins: LCD11, LCD10)
LCD0D4
(Pins: LCD9, LCD8)
LCD0D3
(Pins: LCD7, LCD6)
LCD0D2
(Pins: LCD5, LCD4)
LCD0D1
(Pins: LCD3, LCD2)
LCD0D0
(Pins: LCD1, LCD0)
Figure 26.2. LCD Data Register to LCD Pin Mapping
Rev. 1.0
336
Si102x/3x
SFR Definition 26.2. LCD0CN: LCD0 Control Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CLKDIV[1:0]
BLANK
R/W
SIZE
R/W
MUXMD[1:0]
R/W
BIAS
R/W
R/W
0
R/W
0
R/W
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0x9D
Bit
Name
Function
7
Reserved Read
= 0. Must Write 0b.
6:5
CLKDIV[1:0]
LCD0 Clock Divider.
Divides the SmaRTClock output for use by the LCD0
odule. See
T
a
ble 4.18 on
page 68 for LCD clock frequency range.
00: The LCD clock is the SmaRTClock divided by 1.
01: The LCD clock is the SmaRTClock divided by 2.
10: The LCD clock is the SmaRTClock divided by 4.
11: Reserved.
4
3
BLANK
SIZE
Blank All Segments.
Blanks all LCD segments using a single bit.
0: All LCD segments are contr
by the LCD0Dn registers.
1: All LCD segments are
nk (turned off).
LCD Size Select.
Selects whether 16 or
segment pins will be used for the LCD function.
0: P0 and P1 are used as LCD segment pins.
1: P0, P1, P2
nd P3 are used as LCD segment pins.
2:1
MUXMD[1:0]
LCD Bias Power Mode.
Selects the mux mode.
00: Static mode selected.
01: 2-mux mode selected.
10: 3-mux mode selected.
11: 4-mux mode selected.
0
Bias Select
.
BIAS
Selects between 1/2 Bias and 1/3 Bias. This bit is ignored if Static mode is
selected.
0: LCD0 is configured for 1/3 Bias.
1: LCD0 is configured for 1/2 Bias.
337
Rev. 1.0
Si102x/3x
26.3. LCD
Contrast Adjustment
The LCD Bias voltages which determine the LCD contrast are generated using the VBAT supply voltage or
the on-chip charge pump. There are four contrast control modes to accommodate a wide variety of appli-
cations and supply voltages. The target contrast voltage is programmable in 60
mV steps from 1.9 to
3.72 V.
The LCD contrast voltage is controlled by the LCD0CNTRST register and the contrast control
mode is selected by setting the appropriate bits in the LCD0MSCN, LCD0MSC
F
,
L
CD0PWR, an
LCD0VBMCN registers.
Note:
An external 10 µF decoupling capacitor is required on the VLCD pin to create a charge reservoir at the output of
the charge pump.
Table 26.1. Bit Configurations to select Contrast Control Mod
Mode
LCD0MSCN.2
LCD0MSC
F
.
0
LCD0PWR.3
LCD0VBMCN.7
1
2
3
4
0
0
1
1
0
0
0
1
1
0
0
1
1
1
1*
1*
* May be set to 0 to support increased load currents.
26.3.1. Contrast Control Mode 1 (Bypass Mod
In Contrast Control Mode 1, the contrast c
l circuitry is disabled and the VLCD voltage follows the
VBAT supply voltage, as shown in Figure 26.
This mode is useful in systems where the VBAT voltage
always remains constant and will provide the lowest LCD power consumption. Bypass Mode is selected
using the following procedure:
1. Clear Bit 2 of the LCD0MSCN register to 0b (LCD0MSCN &= ~0x04)
2. Set Bit 0 of the LCD0MSCF register to 1b (LCD0MSCF |= 0x01)
3. Clear Bit 3 of the LCD0PWR register to 0b (LCD0PWR &= ~0x08)
4. Clear Bit 7 of the LCD0VBMCN register to 0b (LCD0VBMCN &= ~0x80)
VBAT
VLCD
Figure 26.3. Contrast Control Mode 1
Rev. 1.0
338
Si102x/3x
26.3.2. Contrast Control Mode 2 (Minimum Contrast Mode)
In Contrast Control Mode 2, a minimum contrast voltage is maintained, as shown in Figure 26.4. The
VLCD supply is powered directly from VBAT as long as VBAT is higher than the programmable VBAT mon-
itor threshold voltage. As soon as the VBAT supply monitor detects that VBAT has dropped below the pro-
grammed value, the charge pump will be automatically enabled in order to achieve the desired minimum
contrast voltage on VLCD. Minimum Contrast Mode is selected using the following procedure:
1. Clear Bit 2 of the LCD0MSCN register to 0b (LCD0MSCN &= ~0x04)
2. Set Bit 0 of the LCD0MSCF register to 1b (LCD0MSCF |= 0x01)
3. Set Bit 3 of the LCD0PWR register to 1b (LCD0PWR |= 0x08)
4. Set Bit 7 of the LCD0VBMCN register to 1b (LCD0VBMCN |= 0x80)
VBAT
VLCD
Figure 26.4. Contrast Contr
Mode 2
26.3.3. Contrast Control Mode 3 (Constant Contra
ode)
In Contrast Control Mode 3, a constant contrast vo
age is maintained. The VLCD supply is regulated to the
programmed contrast voltage using a variable
sistor between VBAT and VLCD as long as VBAT is
higher than the programmable VBAT moni
hreshold voltage. As soon as the VBAT supply monitor
detects that VBAT has dropped below the p
ogrammed value, the charge pump will be automatically
enabled in order to achieve the desired contrast voltage on VLCD. Constant Contrast Mode is selected
using the following procedure:
1. Set Bit 2 of the LCD0MSCN register to 1b (LCD0MSCN |= 0x04)
2. Clear Bit 0 of the LCD0MSCF register to 0b (LCD0MSCF &= ~0x01)
3. Set Bit 3 of the LCD0PWR register to 1b (LCD0PWR |= 0x08)
4. Set Bit 7 of the LCD0VBMCN register to 1b (LCD0VBMCN |= 0x80)
VBAT
VLCD
Figure 26.5. Contrast Control Mode 3
339
Rev. 1.0
Si102x/3x
26.3.4. Contrast Control Mode 4 (Auto-Bypass Mode)
In Contrast Control Mode 4, behavior is identical to Constant Contrast Mode as long as VBAT is greater
than the VBAT monitor threshold voltage. When VBAT drops below the programmed threshold, the device
automatically enters bypass mode powering VLCD directly from VBA
T
.
T
he charge pump is always dis-
abled in this mode. Auto-Bypass Mode is selected using the following procedure:
1. Set Bit 2 of the LCD0MSCN register to 1b (LCD0MSCN |= 0x04)
2. Clear Bit 0 of the LCD0MSCF register to 0b (LCD0MSCF &= ~0x01)
3. Clear Bit 3 of the LCD0PWR register to 0b (LCD0PWR &= ~0x08)
4. Set Bit 7 of the LCD0VBMCN register to 1b (LCD0VBMCN |= 0x80)
VBAT
VLCD
Figure 26.6. Contrast Con
Mode 4
Rev. 1.0
340
Si102x/3x
SFR Definition 26.3. LCD0CNTRS
T
:
L
CD0 Contrast Adjustment
Bit
7
6
5
4
3
2
CNTRST
R/W
1
0
Name
Reserved Reserved Reserved
Type
R/W
0
R/W
0
R/W
0
Reset
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0x9C
Bit
7:5
4:0
Name
Function
Reserved Read
= 000. Write = Must write 000.
CNTRST
Contrast Setpoint.
Determines the setpoint for the VLCD voltage necessary to achieve the desired
contrast.
00000: 1.90
00001: 1.96
00010: 2.02
00011: 2.08
00100: 2.13
00101: 2.19
00110: 2.25
00111: 2.31
01000: 2.37
01001: 2.43
01010: 2.49
01011: 2.55
01100: 2.60
01101: 2
01110: 2.72
01111: 2.78
10000: 2.84
10001: 2.90
10010: 2.96
10011: 3.02
10100: 3.07
10101: 3.13
10110: 3.19
10111: 3.25
11000: 3.31
11001: 3.37
11010: 3.43
11011: 3.49
11100: 3.54
11101: 3.60
11110: 3.66
11111: 3.72
341
Rev. 1.0
Si102x/3x
SFR Definition 26.4. LCD0MSCN: LCD0 Master Control
Bit
7
6
5
4
3
2
1
0
BIASEN DCBIASOE CLKOE
LOWDRV LCDRST
LCDEN
Name
Type
Reset
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xAB
Bit
Name
Function
7
6
Reserved
BIASEN
Read = 0b. Must write 0b.
LCD0 Bias Enable.
LCD0 bias may be disabled when using a static LCD
ngle backplane), contrast
control mode 1 (Bypass Mode) is selected, and the VLCD/VIO Supply Comparator
is disabled (LCD0C
F
.
5 = 1). It is required for all other modes.
0: LCD0 Bias is disabled.
1: LCD0 Bias is enabled
5
4
DCBIASOE
CLKOE
DCDC Converter Bias Output Enabl
ote 1)
0: The bias for the DCDC converter is gated off.
1: LCD0 provides the bias for th
DCDC converter.
LCD Clock Output Enable
0: The clock signal to the LCD0 module is gated off.
1: The SmaRTClock
des the undivided clock to the LCD0 Module.
3
2
Reserved
LOWDRV
Read = 0b. Must write 0b.
Charge Pum
Reduced Drive Mode.
This bit should be set to 1 in Contrast Control Mode 3 and Mode 4 for minimum
power consumption. This bit may be set to 0 in these modes to support higher load
current requirements.
0: The charge pump operates at full power.
1: The charge pump operates at reduced power.
1
0
LCDRST
LCDEN
LCD0 Reset.
Writing a 1 to this bit will clear all the LCD0Dn registers to 0x00. This bit must be
cleared by software.
LCD0 Enable.
0: LCD0 is disabled.
1: LCD0 is enabled.
Note 1:
T
o
s
ame bias generator is shared by the dc-dc converter and LCD0.
Rev. 1.0
342
Si102x/3x
SFR Definition 26.5. LCD0MSCF: LCD0 Master Configuration
Bit
7
6
5
4
3
2
1
0
DCENSLP CHPBY
Name
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
SFR Page = 0x2; SFR Address = 0xAC
Bit
Name
Function
7:2
1
Reserved
Read = 111111b. Must write 111111b.
DCENSLP
DCDC Converter Enable in Sleep Mode
0: DCDC is disabled in Sleep Mode.
1: DCDC is enabled in Sleep Mode.
0
CHPBYP
LCD0 Charge Pump Bypass
This bit should be set to 1b in Contrast Control Mode 1 and Mode 2.
0: LCD0 Charge Pump is not bypassed.
1: LCD0 Charge Pump is bypassed.
SFR Definition 26.6. LCD0PWR: LCD0 Pow
r
Bit
7
6
5
4
3
2
1
0
MODE
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
SFR Page = 0x2; SFR Address = 0xA4
Bit
Name
Function
7:4
3
Unused
MODE
Read = 0000b. Write = don’t care.
LCD0 Contrast Control Mode Selection.
0: LCD0 Contrast Control Mode 1 or Mode 4 is selected.
1: LCD0 Contrast Control Mode 2 or Mode 3 is selected.
Read = 001b. Must write 001b.
2:
Reserved
343
Rev. 1.0
Si102x/3x
26.4. Adjusting
the VBAT Monitor Threshold
The VBAT monitor is used primarily for the contrast control function, to detect when VBAT has fallen below
a specific threshold. The VBAT monitor threshold may be set independently of the contrast setting or it may
be linked to the contrast setting. When the VBAT monitor threshold is linked to the contrast setting, an off-
set (in 60mV steps) may be configured so that the VBAT monitor generates a VBAT low condition prior to
VBAT dropping below the programmed contrast voltage. The LCD0VBMCN register is used to enable an
configure the VBAT monitor. The VBAT monitor may be enabled as a wake-up source to wake up t
device from Sleep mode when the battery is getting low. See “19. Power Management” on page 257 for
more details.
SFR Definition 26.7. LCD0VBMCN: LCD0 VBAT Monitor Control
Bit
7
6
5
4
3
2
1
0
Name
VBATMEN OFFSET
THRL
:0]
R/W
R/W
0
R/W
0
R/W
0
Type
0
0
0
0
0
Reset
SFR Page = 0x2; SFR Address = 0xA6
Bit
Name
Function
7
VBATMEN
VBAT Monitor Enable
The VBAT Monitor should be en
led in Contrast Control Mode 2, Mode 3, and
Mode 4.
0: The VBAT Monitor i
sabled.
1: The VBAT Monitor is
abled.
6
5
OFFSET
Unused
VBAT Monitor Offset Enable
0: The VBAT
on
tor Threshold is independent of the contrast setting.
1: The VBAT Monitor Threshold is linked to the contrast setting.
Read = 0. Write = Don’t Care.
4:0 THRLD[4:0]
VBAT Monitor Threshold
If OFFSET is set to 0b, this bit field has the same definition as the CNTRST bit field
nd can be programmed independently of the contrast.
If OFFSET is set to 1b, this bit field is interpreted as an offset to the currently pro-
grammed contrast setting.
The LCD0CNTRST register should be written before
setting OFFSET to logic 1 and should not be changed as long as VBAT Moni-
tor Offset is enabled.
When THRLD[4:0] is set to 00000b, the VBAT monitor
threshold is equal to the contrast voltage. When THRLD[4:0] is set to 00001b, the
VBAT monitor threshold is one step higher than the contrast voltage. The step size
is equal to the step size of the CNTRST bit field.
Rev. 1.0
344
Si102x/3x
26.5. Setting
the LCD Refresh Rate
The clock to the LCD0 module is derived from the SmaRTClock and may be divided down according to the
settings in the LCD0CN register. The LCD refresh rate is derived from the LCD0 clock and can be pro-
grammed using the LCD0DIVH:LCD0DIVL registers. The LCD mux mode must be taken into account
when determining the prescaler value. See the LCD0DIVH/LCD0DIVL register descriptions for more
details. For maximum power savings, choose a slow LCD refresh rate and the minimum LCD0 clock fre
quency. For the least flicker, choose a fast LCD refresh rate.
SFR Definition 26.8. LCD0CLKDIVH: LCD0 Refresh Rate Prescaler High B
te
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
LCD0DIV[9:8]
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
SFR Page = 0x2; SFR Address = 0xAA
Bit
Name
Function
7:2
Unused
Read = 000000. Write = Don’t Ca
e.
1:0 LCD0DIV[9:8]
LCD Refresh Rate Prescaler
.
Sets the LCD refresh rate acc
ding to the following equation:
LCD0 Clock Frequency
mux_mode
LCD
0
DIV
+ 1
–
—————————————————————————–
–
–
LCD Refresh Rate
=
SFR Definition 26.9. LCD0CLKDIVL: LCD Refresh Rate Prescaler Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
LCD0DIV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR
age = 0x2; SFR Address = 0xA9
Bit Name
7:0 LCD0DIV[7:0]
LCD Refresh Rate Prescaler
.
Function
Sets the LCD refresh rate according to the following equation:
LCD0 Clock Frequency
4
mux_mode
LCD
0
DIV
+ 1
———————————————————————————
–
–
LCD Refresh Rate
=
345
Rev. 1.0
Si102x/3x
26.6. Blinking
LCD Segments
The LCD driver supports blinking LCD applications such as clock applications where the “:” separator tog-
gles on and off once per second. If the LCD is only displaying the hours and minutes, then the device only
needs to wake up once per minute to update the display. The once per second blinking is automatically
handled by the Si102x/3x.
The LCD0BLINK register can be used to enable blinking on any LCD segment connected to the LCD0
LCD1 segment pin. In static mode, a maximum of 2 segments can blink. In 2-mux mode, a maximum of
segments can blink; in 3-mux mode, a maximum of 6 segments can blink; and in 4-mux mode, a maximum
of 8 segments can blink. The LCD0BLINK mask register targets the same LCD segments as the LCD0D0
register. If an LCD0BLINK bit corresponding to an LCD segment is set to 1, then that segment
ill toggle at
the frequency set by the LCD0TOGR register without any software intervention.
SFR Definition 26.10. LCD0BLINK: LCD0 Blink Mask
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
LCD0BLINK[7:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0x9E
Bit
Name
Function
7:0
LCD0BLINK[7:0]
LCD0 Blink Mask.
Each bit maps t
pecific LCD segment connected to the LCD0 and LCD1
segment pins. A v
ue of 1 indicates that the segment is blinking. A value of 0
indicates that the segment is not blinking. This bit to segment mapping is the
same a
e LCD0D0 register.
Rev. 1.0
346
Si102x/3x
SFR Definition 26.11. LCD0TOGR: LCD0 Toggle Rate
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TOGR[3:0]
R/W
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0x9F
Bit
7:4
3:0
Name
Function
Unused
Read = 0000. Write = Don’t Care.
TOGR[3:0]
LCD Toggle Rate Divider.
Sets the LCD
T
o
ggle Rate according to the following equation:
Refresh Rate
mux_mode
2
————————————————————————-
LCD Toggle Rate
=
Toggle Rate Divider
0000: Reserved.
0001: Reserved.
0010:
T
o
ggle Rate Divider is set t
divide by 2.
0011:
T
o
ggle Rate Divider is set
vide by 4.
0100:
T
o
ggle Rate Divider
et to divide by 8.
0101:
T
o
ggle Rate Divid
r is set to divide by 16.
0110:
T
o
ggle Rate Div
set to divide by 32.
0111: Toggle Rate Divider is set to divide by 64.
1000:
T
o
ggle Rate Divider is set to divide by 128.
1001:
T
o
ggle
ate Divider is set to divide by 256.
1010:
T
o
ggle Rate Divider is set to divide by 512.
1011:
T
o
ggle Rate Divider is set to divide by 1024.
1100: Toggle Rate Divider is set to divide by 2048.
1101: Toggle Rate Divider is set to divide by 4096.
All other values reserved.
347
Rev. 1.0
Si102x/3x
26.7. Advanced
LCD Optimizations
The special function registers described in this section should be left at their reset value for most systems.
Some systems with specific low power or large load requirements will benefit from tweaking the values in
these registers to achieve minimum power consumption or maximum drive level.
SFR Definition 26.12. LCD0CF: LCD0 Configuration
Bit
7
6
5
4
3
2
1
0
CMPBYP
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xA5
Bit
Name
Function
7
:
6
5
Reserved
CMPBYP
Read = 00b. Must write 00b.
VLCD/VIO Supply Comparator Disable.
Setting this bit to ‘1’ disables the supply
tage comparator which determines if the
VIO supply is lower than VLCD. Th
s co
arator should only be disabled, as a
power saving measure, if VIO is internally or externally shorted to VBA
T
.
4
:
0
Reserved
Read = 00b. Must write 00000
SFR Definition 26.13. LCD0CHPCN
D0 Charge Pump Control
Bit
7
6
4
3
2
1
0
Name
Type
Reset
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
SFR Page = 0x2; S
Address = 0xB5
Bit
Name
Function
7
:
0
R
erved
Must write 0x4B.
Rev. 1.0
348
Si102x/3x
SFR Definition 26.14. LCD0CHPCF: LCD0 Charge Pump Configuration
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x2; SFR Address = 0xAD
Bit
Name
Function
7
:
0
Reserved
Must write 0x60.
SFR Definition 26.15. LCD0CHPMD: LCD0 Charge Pump Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
SFR Page = 0x2; SFR Address = 0xAE
Bit
Name
Function
7
:
0
Reserved
Must write 0xE9.
SFR Definition 26.16. LCD0BUFCN: LCD0 Buffer Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
SFR
age = 0xF; SFR Address = 0x9C
Bit
Name
Function
7
:
0
Reserved
Must write 0x44.
349
Rev. 1.0
Si102x/3x
SFR Definition 26.17. LCD0BUFCF: LCD0 Buffer Configuration
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
SFR Page = 0xF; SFR Address = 0xAC
Bit
Name
Function
7
:
0
Reserved
Must write 0x32.
SFR Definition 26.18. LCD0BUFMD: LCD0 Buffer Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
SFR Page = 0x2; SFR Address = 0xB6
Bit
Name
Function
7
:
0
Reserved
Must write 0x4A.
SFR Definition 26.19. LCD0VBMCF: LCD0 VBAT Monitor Configuration
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
SFR
age = 0x2; SFR Address = 0xAF
Bit
Name
Function
7
:
0
Reserved
Must write 0x0B.
Rev. 1.0
350
Si102x/3x
27. Port
Input/Output
Digital and analog resources are available through 53 I/O pins. Port pins are organized as eight byte-wide
ports. Port pins can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the inter-
nal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal ana-
log resources. P7.0 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See
Section “35. C2 Interface” on page 525 for more details.
The designer has complete control over which digital and analog functions are assigned to individual port
pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See
Section 27.3 for more information on the Crossbar.
For port I/Os configured as push-pull outputs, current is sourced from the VIO or VIO
pply pin. See
Section 27.1 for more information on port I/O operating modes and the electrical specific
s chapter for
detailed electrical specifications.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
PnMDOU
PnMDIN Re
ters
External Interrupts
EX0 and EX1
P0.0
P0
I/O
8
Priority
Cells
Decoder
P0.7
P1.0
2
UART
Highest
Priority
P1
I/O
Cells
8
8
4
2
SPI0
SPI1
P1.7
P2.0
SMBus
P2
I/O
Cells
D
gital
Crossbar
CP0
CP1
Outputs
4
P2.7
P3.0
P3
I/O
Cells
8
8
8
SYSCLK
PCA
P3.7
P4.0
7
2
P4
I/O
Cells
Lowest
Priority
T0, T1
P4.7
P5.0
P5
I/O
8
P
Cells
P5.7
P6.0
P6
I/O
Cells
8
8
1
(P6.0-P6.7)
P6
P7
P6.7
P7.0
1
P7
(P7.0)
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
To LCD
To EMIF
Figure 27.1. Port I/O Functional Block Diagram
Rev. 1.0
351
Si102x/3x
27.1. Port
I/O Modes of Operation
Port pins P0.0–P6.7 use the port I/O cell shown in Figure 27.2. The supply pin for P1.5–P2.3 is VIORF and
the supply for all other GPIOs is VIO. Each port I/O cell can be configured by software for analog I/O or dig-
ital I/O using the PnMDIN registers. P7.0 can only be used for digital functions and is shared with the C2D
signal. On reset, all port I/O cells default to a digital high impedance state with weak pull-ups enabled.
27.1.1. Port Pins Configured for Analog I/O
Any pins to be used as comparator or ADC input, external oscillator input/output, or AGND, VRE
F
,
o
r cur-
rent reference output should be configured for analog I/O (PnMDIN.n = 0). When a pin is configured for
analog I/O, its weak pullup and digital receiver are disabled. In most cases, software should a
o disable
the digital output drivers. port pins configured for analog I/O will always read back a value of
regardless
of the actual voltage on the pin.
Configuring pins as analog I/O saves power and isolates the port pin from digital interfer
nce. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
27.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UAR
T
,
S
PI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOU
T
.
n = 1) drive the port pad to the su
ply or GND rails based on the output logic
value of the port pin. Open-drain outputs have the high side d
disabled; therefore, they only drive the
port pad to GND when the output logic value is 0 and become high impedance inputs (both high and low
drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance
ate, a weak pull-up transistor pulls the port pad to
the supply voltage to ensure the digital input is a
a defined logic state. Weak pull-ups are disabled when
the I/O cell is driven to GND to minimize p
er consumption and may be globally disabled by setting
WEAKPUD to 1. The user must ensure that d
l I/O are always internally or externally pulled or driven to
a valid logic state. Port pins configured for digital I/O always read back the logic state of the port pad,
regardless of the output logic value o
he port pin.
WEAKPUD
(Weak Pull-Up Disable)
PnMDOUT.x
(1 for push-pull)
(0 for open-drain)
Supply
Supply
XBARE
(Crossbar
Enable)
(WEAK)
PORT
PAD
Pn.x – Ou
t
Lo
alue
(P
Latch or
Cro
sbar)
PnMDIN.x
(1 for digital)
(0 for analog)
GND
To/From Analog
Peripheral
Pn.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
Figure 27.2. Port I/O Cell Block Diagram
352
Rev. 1.0
Si102x/3x
27.1.3. Interfacing Port I/O to High Voltage Logic
All port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage up to VIO + 2
V
.
A
n external pull-up resistor to the higher supply voltage is typically
required for most systems.
27.1.4. Increasing Port I/O Drive Strength
Port I/O output drivers support a high and low drive strength; the default is low drive strength. The dri
strength of a port I/O can be configured using the PnDRV registers. See Section “4. Electrical Characteris
tics” on page 48 for the difference in output drive strength between the two modes.
27.2. Assigning
Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P2.6 can be assigned to various analog, digital, and external inter
nctions. The
port pins assigned to analog functions should be configured for analog I/O, and port pins
ned to digital
or external interrupt functions should be configured for digital I/O.
27.2.1. Assigning Port I/O Pins to Analog Functions
T
a
ble 27.1 shows all available analog functions that need port I/O assignm
ts.
Port pins selected for
these analog functions should have their digital drivers disabled (PnMDOU
T
.
n = 0 and Port Latch =
1) and their corresponding bit in PnSKIP set to 1.
This reserves the pin for use by the analog function
and does not allow it to be claimed by the crossbar.
T
a
ble 27.1 shows the potential mapping of port I/O to
each analog function.
Table 27.1. Port I/O Assignmen
fo
alog Functions
Analog Function
Potentially
As
able Port Pins
SFR(s) used for
Assignment
ADC Input
P0.0–P0.7,
P1.4–P2.3
ADC0MX, PnSKIP
CPT0MX, PnSKIP
CPT1MX, PnSKIP
Comparator0 Input
Comparator1 Input
P0.0–P0.7,
P1.4–P2.3
P0.0–P0.7,
P1.4–P2.3
LCD Pins (LCD0)
P2.4–P6.7
P1.0, P1.1
P0.0
PnMDIN, PnSKIP
P1MDIN, PnSKIP
REF0CN, PnSKIP
REF0CN, PnSKIP
IREF0CN, PnSKIP
OSCXCN, PnSKIP
OSCXCN, PnSKIP
P1MDIN, PnSKIP
P1MDIN, PnSKIP
Pulse Count
(PC0)
Voltage Reference (VREF0)
Ana
g Ground Reference (AGND)
Current Reference (IREF0)
External Oscillator Input (XTAL1)
External Oscillator Output (XTAL2)
SmaRTClock Input (XTAL3)
SmaRTClock Output (XTAL4)
P0.1
P0.7
P0.2
P0.3
P1.2
P1.3
Rev. 1.0
353
Si102x/3x
27.2.2. Assigning Port I/O Pins to Digital Functions
Any port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the crossbar for pin assignment; however, some digital functions bypass the cross-
bar in a manner similar to the analog functions listed above.
Port pins used by these digital functions
and any port pins selected for use as GPIO should have their corresponding bit in PnSKIP set to 1.
T
a
ble 27.2 shows all available digital functions and the potential mapping of port I/O to each digital func-
tion.
Table 27.2. Port I/O Assignment for Digital Functions
Digital Function
Potentially Assignable Port Pins
SFR(s) u
ed for
nment
UART0, SPI0, SPI1, SMBus,
CP0 and CP1 Outputs, Sys-
tem Clock Output, PCA0,
Timer0 and Timer1 External
Inputs.
Any port pin available for assignment by the
crossbar. This includes P0.0–P2.7 pins which
have their PnSKIP bit set to 0.
Note:
The crossbar will always assign UART0 an
SPI1 pins to fixed locations.
XBR0, XBR1, XBR2
Any pin used for GPIO
P0.0–P7.0
P3.6–P6.7
P0SKI
P
,
P
1SKI
P
,
P2SKIP
External Memory Interface
EMI0CF
27.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used
gger an interrupt or wake the device from a low
power mode when a transition occurs on a digital
pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pin
(PnSKIP = 1) and pins in use by the crossbar (PnSKIP
= 0). External digital even capture functions
ot be used on pins configured for analog I/O.
T
a
ble 27.3
shows all available external digital event capture functions.
Table 27.3. Port I/O Assi
nment for External Digital Event Capture Functions
Digital Function
Potentially Assignable Port Pins
SFR(s) used for
Assignment
External Interrupt 0
External Interrupt
Port Match
P0.0–P0.5, P1.6, P1.7
P0.0–P0.4, P1.6, P1.7
P0.0–P1.7
IT01CF
IT01CF
P0MASK, P0MAT
P1MASK, P1MAT
354
Rev. 1.0
Si102x/3x
27.3. Priority
Crossbar Decoder
The Priority Crossbar Decoder assigns a port I/O pin to each software selected digital function using the
fixed peripheral priority order shown in Figure 27.3. The registers XBR0, XBR1, and XBR2 defined in SFR
Definition 27.1, SFR Definition 27.2, and SFR Definition 27.3 are used to select digital functions in the
crossbar. The port pins available for assignment by the crossbar include all port pins (P0.0–P2.6) which
have their corresponding bit in PnSKIP set to 0.
From Figure 27.3, the highest priority peripheral is UART0. If UART0 is selected in the crossbar (using th
XBRn registers), then P0.4 and P0.5 will be assigned to UART0. The next highest priority peripheral is
SPI1. If SPI1 is selected in the crossbar, then P2.0–P2.2 will be assigned to SPI1. P2.3 will be assigned if
SPI1 is configured for 4-wire mode. The user should ensure that the pins to be assigned by
e crossbar
have their PnSKIP bits set to 0.
For all remaining digital functions selected in the crossbar, starting at the top of Figure 2
going down,
the least-significant unskipped, unassigned port pin(s) are assigned to that function. If a port pin is already
assigned (e.g., UART0 or SPI1 pins), or if its PnSKIP bit is set to 1, then the crossbar will skip over the pin
and find next available unskipped, unassigned port pin. All port pins used for analog functions, GPIO, or
dedicated digital functions such as the EMIF should have their PnSKIP bit se
to 1.
Figure 27.3 shows the crossbar decoder priority with no port pins s
ipped (P0SKI
P
,
P
1SKI
P
,
P
2SKIP =
0x00); Figure 27.4 shows the crossbar decoder priority with the external oscillator pins (XTAL1 and XTAL2)
skipped (P0SKIP = 0x0C).
Important Notes:
The crossbar must be enabled (XBARE = 1) before any port pin is used as a digital output. Port output
drivers are disabled while the crossbar is disabled.
When SMBus is selected in the crossbar, the pins
ociated with SDA and SCL will automatically be
forced into open-drain output mode regardles
f the PnMDOUT setting.
SPI0 can be operated in either 3-wire or 4-
ire modes, depending on the state of the NSSMD1-
NSSMD0 bits in register SPI0CN. The NS
gnal is only routed to a port pin when 4-wire mode is
selected. When SPI0 is selected in the crossbar, the SPI0 mode (3-wire or 4-wire) will affect the pinout
of all digital functions lower in priority than SPI0.
For given XBRn, PnSKI
P
,
a
nd SP
nCN register settings, one can determine the I/O pin-out of the
device using Figure 27.3 and Figure 27.4.
Rev. 1.0
355
Si102x/3x
P0
P1
P2
SF Signals
PIN I/O
TX0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4 5 6 7
RX0
SCK (SPI1)
MISO (SPI1)
MOSI (SPI1)
NSS* (SPI1)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
NSS* (SPI0)
SDA
(*4-Wire SPI Only)
(*4-Wire SPI Only)
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
Figure 27.3. Crossbar Priority Decoder with No Pins Skipped
356
Rev. 1.0
Si102x/3x
P0
P1
P2
SF Signals
PIN I/O
TX0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0 1 2 3 4 5 6 7
RX0
SCK (SPI1)
MISO (SPI1)
MOSI (SPI1)
NSS* (SPI1)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
NSS* (SPI0)
SDA
(*4-Wire SPI
O
nly)
(*4-Wire SPI
O
nly)
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0 0
0 0 0
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
Figure 27.4. Crossbar Priority Decoder with Crystal Pins Skipped
Rev. 1.0
357
Si102x/3x
SFR Definition 27.1. XBR0: Port I/O Crossbar Register 0
Bit
7
CP1AE
R/W
0
6
CP1E
R/W
0
5
CP0AE
R/W
0
4
CP0E
R/W
0
3
SYSCKE
R/W
2
SMB0E
R/W
0
1
SPI0E
R/W
0
0
URT0E
R/W
0
Name
Type
Reset
0
SFR Page = 0x0; SFR Address = 0xE1
Bit
Name
Function
7
CP1AE
Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 output unavailable at Port pin.
1: Asynchronous CP1 output routed to Port pin.
6
5
4
3
2
1
CP1E
Comparator1 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
CP0AE
Comparator0 Asynchronous Output E
le.
0: Asynchronous CP0 output unavailable at Port pin.
1: Asynchronous CP0 output routed to Port pin.
CP0E
Comparator0 Output Enable.
0: CP1 output unavailable a
Port pin.
1: CP1 output routed to
rt pin.
SYSCKE
SYSCLK Output Enable.
0: SYSCLK output unavailable at Port pin.
1: SYSCLK out
ut routed to Port pin.
SMB0E
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pin.
1: SDA and SCL routed to Port pins.
SPI0E
PI0 I/O Enable
SPI0 I/O unavailable at Port pin.
1: SCK, MISO, and MOSI (for SPI0) routed to Port pins.
NSS (for SPI0) routed to Port pin only if SPI0 is configured to 4-wire mode.
URT0E
UART0 Output Enable.
0: UART I/O unavailable at Port pin.
1: TX0 and RX0 routed to Port pins P0.4 and P0.5.
Note:
SPI0 can be assigned either 3 or 4 Port I/O pins.
358
Rev. 1.0
Si102x/3x
SFR Definition 27.2. XBR1: Port I/O Crossbar Register 1
Bit
7
6
SPI1E
R/W
0
5
4
3
ECIE
R/W
0
2
1
0
Name
Type
Reset
T1E
R/W
0
T0E
R/W
0
PCA0ME[2:0]
R/W
0
R/W
0
0
0
SFR Page = 0x0; SFR Address = 0xE2
Bit
Name
Function
7
Unused Read
= 0b; Write = Don’t Care.
6
SPI1E
SPI0 I/O Enable.
0: SPI1 I/O unavailable at Port pin.
1: SCK (for SPI1) routed to P2.0.
MISO (for SPI1) routed to P2.1.
MOSI (for SPI1) routed to P2.2.
NSS (for SPI1) routed to P2.3 only if SPI1 is configured to 4-wire mode.
5
4
T1E
T0E
Timer1 Input Enable.
0: T1 input unavailable at Port pin.
1: T1 input routed to Port pin.
Timer0 Input Enable.
0: T0 input unavailable a
Port pin.
1: T0 input routed to Por
n.
3
ECIE
PCA0 External Counter Input (ECI) Enable.
0: PCA0 extern
l counter input unavailable at Port pin.
1: PCA0 external counter input routed to Port pin.
2:0
PCA0ME
PCA0 Module I/O Enable.
000: All PCA0 I/O unavailable at Port pin.
001: CEX0 routed to Port pin.
0: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2 CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.
111: Reserved.
Note:
SPI1 can be assigned either 3 or 4 Port I/O pins.
Rev. 1.0
359
Si102x/3x
SFR Definition 27.3. XBR2: Port I/O Crossbar Register 2
Bit
7
6
XBARE
R/W
0
5
4
3
2
1
0
Name
WEAKPUD
Type
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
SFR Page = 0x0 and 0xF; SFR Address = 0xE3
Bit
Name
Function
7
WEAKPUD
Port I/O Weak Pullup Disable
0: Weak Pullups enabled (except for Port I/O pins configured for analog mode).
6
XBARE
Unused
Crossbar Enable
0: Crossbar disabled.
1: Crossbar enabled.
5:0
Read = 000000b; Write = Don’t Care.
Note:
The Crossbar must be enabled (XBARE = 1) to use any Port
s a digital output.
360
Rev. 1.0
Si102x/3x
27.4. Port
Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMAT registers specifies the expected or normal logic values of P0
and P1. A port mismatch event occurs if the logic levels of the port’s input pins no longer match the soft-
ware controlled value. This allows software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compare
against the PnMAT registers. A port mismatch event is generated if (P0
& P0MASK)
does not equal
(PnMAT & P0MASK) or if (P1 & P1MASK) does not equal (PnMAT & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a
w power mode.
See Section “17. Interrupt Handler” on page 231 and Section “19. Power Manageme
page 257 for
more details on interrupt and wake-up sources.
SFR Definition 27.4. P0MASK: Port0 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0MASK[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xC7
Bit
Name
Function
7:0
P0MASK[7:0]
Port0 Mask Value.
Selects the P0 pins to be compared with the corresponding bits in P0MA
T
.
0: P0.n pin pad logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin
ad logic value is compared to P0MA
T
.
n.
SFR Definition 27.5. P0MA
T
:
P
ort0 Match Register
Bit
7
6
5
4
3
2
1
0
Name
Typ
Res
t
P0MAT[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page= 0x0; SFR Address = 0xD7
Bit
Name
Function
7
:
0
P0MAT[7:0]
Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
Rev. 1.0
361
Si102x/3x
SFR Definition 27.6. P1MASK: Port1 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MASK[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xBF
Bit
Name
Function
7:0
P1MASK[7:0]
Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MA
T
.
0: P1.n pin logic value is ignored and cannot cause
Port Mismatch event.
1: P1.n pin logic value is compared to P1MA
T
.
n.
Note:
SFR Definition 27.7. P1MA
T
:
P
ort1 Match Register
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MAT[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xCF
Bit
Name
Function
7:0
P1MAT[7:0]
Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
Note:
362
Rev. 1.0
Si102x/3x
27.5. Special
Function Registers for Accessing and Configuring Port I/O
All port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a port, the value written to the SFR is latched to maintain
the output data value at each pin. When reading, the logic levels of the port’s input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the crossbar, the
port register can always read its corresponding port I/O pin). The exception to this is the execution of th
read-modify-write instructions that target a port latch register as the destination. The read-modify-wr
instructions when operating on a port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a port SFR. For these instructions, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Each port has a corresponding PnSKIP register which allows its individual port pins to
igned to digi-
tal functions or skipped by the crossbar. All port pins used for analog functions, GPIO, o
icated digital
functions such as the EMIF should have their PnSKIP bit set to 1.
The port input mode of the I/O pins is defined using the port Input Mode registers (PnMDIN). Each port cell
can be configured for analog or digital I/O. This selection is required even for the digital resources selected
in the XBRn registers, and is not automatic. The only exception to this is P2
, which can only be used for
digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each port output driver can be configured as either op
n drain or push-pull. This selection is
required even for the digital resources selected in the XBRn
egisters, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are
igured as open-drain regardless of the
PnMDOUT settings.
The drive strength of the output drivers are controlle
y the Port Drive Strength (PnDRV) registers. The
default is low drive strength. See Section “4. Electrical
aracteristics” on page 48 for the difference in out-
put drive strength between the two modes.
Rev. 1.0
363
Si102x/3x
SFR Definition 27.8. P0: Port0
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0x80; Bit-Addressable
Bit
Name
P0[7:0]
Port 0 Data.
Sets the port latch logic
Description
Write
0: Set output latch to logic
0: P0.n port pin is logic
LOW. LOW.
1: Set output latch to logic
: P0.n port pin is logic
HIGH. HIGH.
d
7:0
value or reads the port pin
logic state in port cells con-
figured for digital I/O.
SFR Definition 27.9. P0SKIP: Port0 Skip
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0SKIP[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0x
4
Bit Name
7:0 P0SKIP[7:0]
Port 0 Crossbar Skip Enable Bits.
Function
These bits select Port 0 pins to be skipped by the crossbar decoder. Port pins used
for analog, special functions or GPIO should be skipped by the crossbar.
Corresponding P0.n pin is not skipped by the crossbar.
1: Corresponding P0.n pin is skipped by the crossbar.
364
Rev. 1.0
Si102x/3x
SFR Definition 27.10. P0MDIN: Port0 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page= 0x0; SFR Address = 0xF1
Bit Name
Function
7:0 P0MDIN[7:0]
Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 27.11. P0MDOU
T
:
P
ort0 Output M
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
0MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x
4
Bit Name
Function
7:0 P0MDOUT[7:0]
Output Configuration Bits for P0.7–P0.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P0MDIN is logic 0.
0: Corresponding P0.n output is open-drain.
1: Corresponding P0.n output is push-pull.
Rev. 1.0
365
Si102x/3x
SFR Definition 27.12. P0DRV: Port0 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P0DRV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA4
Bit Name
7:0 P0DRV[7:0]
Drive Strength Configuration Bits for
P0.7–P0.0 (respectively).
Function
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P0.n output has low output drive stre
h.
1: Corresponding P0.n output has high output drive strength.
SFR Definition 27.13. P1: Port1
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0x90; Bit-Addressable
Bit
Name
P1[7:0]
Port 1 Data.
Sets the port latch logic
Descri
tion
Write
0: Set output latch to logic
0: P1.n port pin is logic
LOW. LOW.
1: Set output latch to logic
1: P1.n port pin is logic
Read
7:0
value or reads the port pin
logic state in port cells con-
ured for digital I/O.
HIGH.
HIGH.
366
Rev. 1.0
Si102x/3x
SFR Definition 27.14. P1SKIP: Port1 Skip
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1SKIP[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xD5
Bit Name
7:0 P1SKIP[7:0]
Port 1 Crossbar Skip Enable Bits.
Function
These bits select Port 1 pins to be skipped by the crossbar decoder. Port pins used
for analog, special functions or GPIO should be skipped
y the crossbar.
0: Corresponding P1.n pin is not skipped by the crossbar.
1: Corresponding P1.n pin is skipped by the crossbar.
SFR Definition 27.15. P1MDIN: Port1 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0x
2
Bit Name
Function
7:0 P1MDIN[7:0]
Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
Rev. 1.0
367
Si102x/3x
SFR Definition 27.16. P1MDOU
T
:
P
ort1 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA5
Bit Name
Function
7:0 P1MDOUT[7:0]
Output Configuration Bits for P1.7–P1.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P1MDIN is logic 0.
0: Corresponding P1.n output is open-drain.
1: Corresponding P1.n output is push-pull.
SFR Definition 27.17. P1DRV: Port1 Drive Streng
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P1DRV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x
5
Bit Name
7:0 P1DRV[7:0]
Drive Strength Configuration Bits for
P1.7–P1.0 (respectively).
Function
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P1.n output has low output drive strength.
Corresponding P1.n output has high output drive strength.
368
Rev. 1.0
Si102x/3x
SFR Definition 27.18. P2: Port2
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0xA0; Bit-Addressable
Bit
Name
P2[7:0]
Port 2 Data.
Sets the port latch logic
Description
Write
0: Set output latch to logic
0: P2.n port pin is logic
LOW. LOW.
1: Set output latch to logic
1: P2.n port pin is logic
HIGH. HIGH.
d
7:0
value or reads the port pin
logic state in port cells con-
figured for digital I/O.
SFR Definition 27.19. P2SKIP: Port2 Skip
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
2SKIP[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x
6
Bit
Name
Function
7:0
P2SKIP[7:0]
Port 1 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the crossbar decoder. Port pins used
or analog, special functions or GPIO should be skipped by the crossbar.
0: Corresponding P2.n pin is not skipped by the crossbar.
1: Corresponding P2.n pin is skipped by the crossbar.
Rev. 1.0
369
Si102x/3x
SFR Definition 27.20. P2MDIN: Port2 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2MDIN[6:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xF3
Bit
Name
Function
7
Reserved
Read = 1b; Must Write 1b.
6:0
P2MDIN[6:0]
Analog Configuration Bits for P2.6–P2.0 (respectively)
Port pins configured for analog mode have their we
k pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
SFR Definition 27.21. P2MDOU
T
:
P
ort2 Output Mode
Bit
7
6
5
3
2
1
0
Name
Type
Reset
P2MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA6
Bit Name
Function
7:0 P2MDOUT[7:0]
Output Configuration Bits for P2.7–P2.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P2MDIN is logic 0.
0: Corresponding P2.n output is open-drain.
1: Corresponding P2.n output is push-pull.
370
Rev. 1.0
Si102x/3x
SFR Definition 27.22. P2DRV: Port2 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P2DRV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0F; SFR Address = 0xA6
Bit
Name
Function
7:0
P2DRV[7:0]
Drive Strength Configuration Bits for
P2.7–P2.0 (respectively).
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P2.n output has low output drive st
gth.
1: Corresponding P2.n output has high output drive strength.
SFR Definition 27.23. P3: Port3
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0xB0; Bit-Addressable
Bit
Name
P3[7:0]
Port 3 Data.
Sets the port latch logic
Descri
ion
Write
0: Set output latch to logic
0: P3.n port pin is logic
LOW. LOW.
1: Set output latch to logic
1: P3.n port pin is logic
Read
7:0
value or reads the port pin
logic state in port cells con-
ured for digital I/O.
HIGH.
HIGH.
Rev. 1.0
371
Si102x/3x
SFR Definition 27.24. P3MDIN: Port3 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P3MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address = 0xF1
Bit
Name
Function
7:0
P3MDIN[7:0]
Analog Configuration Bits for P3.7–P3.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P3.n pin is configured for analog mode.
1: Corresponding P3.n pin is not configured for analog mode.
SFR Definition 27.25. P3MDOU
T
:
P
ort3 Output M
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
3MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x
1
Bit Name
Function
7:0 P3MDOUT[7:0]
Output Configuration Bits for P3.7–P3.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P3MDIN is logic 0.
0: Corresponding P3.n output is open-drain.
1: Corresponding P3.n output is push-pull.
372
Rev. 1.0
Si102x/3x
SFR Definition 27.26. P3DRV: Port3 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P3DRV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA1
Bit
Name
Function
7:0
P3DRV[7:0]
Drive Strength Configuration Bits for
P3.7–P3.0 (respectively).
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P3.n output has low output drive st
gth.
1: Corresponding P3.n output has high output drive strength.
SFR Definition 27.27. P4: Port4
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address = 0xD9
Bit
Name
P4[7:0]
Port 4 Data.
Sets the port latch logic
Descri
ion
Write
Read
7:0
0: Set output latch to logic
0: P4.n port pin is logic
LOW. LOW.
1: Set output latch to logic
1: P4.n port pin is logic
value or reads the port pin
logic state in port cells con-
ured for digital I/O.
HIGH.
HIGH.
Rev. 1.0
373
Si102x/3x
SFR Definition 27.28. P4MDIN: Port4 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P4MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address = 0xF2
Bit
Name
Function
7:0
P4MDIN[7:0]
Analog Configuration Bits for P4.7–P4.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P4.n pin is configured for analog mode.
1: Corresponding P4.n pin is not configured for analog mode.
SFR Definition 27.29. P4MDOU
T
:
P
ort4 Output M
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
4MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x
9
Bit Name
Function
7:0 P4MDOUT[7:0]
Output Configuration Bits for P4.7–P4.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P4MDIN is logic 0.
0: Corresponding P4.n output is open-drain.
1: Corresponding P4.n output is push-pull.
374
Rev. 1.0
Si102x/3x
SFR Definition 27.30. P4DRV: Port4 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P4DRV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA2
Bit
Name
Function
7:0
P4DRV[7:0]
Drive Strength Configuration Bits for
P4.7–P4.0 (respectively).
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P4.n output has low output drive st
gth.
1: Corresponding P4.n output has high output drive strength.
SFR Definition 27.31. P5: Port5
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address = 0xDA
Bit
Name
P5[7:0]
Port 5 Data.
Sets the port latch logic
Descri
tion
Write
Read
7:0
0: Set output latch to logic
0: P5.n port pin is logic
LOW. LOW.
1: Set output latch to logic
1: P5.n port pin is logic
value or reads the port pin
logic state in port cells con-
ured for digital I/O.
HIGH.
HIGH.
Rev. 1.0
375
Si102x/3x
SFR Definition 27.32. P5MDIN: Port5 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P5MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address = 0xF3
Bit
Name
Function
7:0
P5MDIN[7:0]
Analog Configuration Bits for P5.7–P5.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P5.n pin is configured for analog mode.
1: Corresponding P5.n pin is not configured for analog mode.
Note:
SFR Definition 27.33. P5MDOU
T
:
P
ort5 Output Mode
Bit
7
6
5
3
2
1
0
Name
Type
Reset
P5MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xFA
Bit Name
Function
7:0 P5MDOUT[7:0]
Output Configuration Bits for P5.7–P5.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P5MDIN is logic 0.
0: Corresponding P5.n output is open-drain.
1: Corresponding P5.n output is push-pull.
Not
376
Rev. 1.0
Si102x/3x
SFR Definition 27.34. P5DRV: Port5 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P5DRV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA3
Bit
Name
Function
7:0
P5DRV[7:0]
Drive Strength Configuration Bits for
P5.7–P5.0 (respectively).
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P5.n output has low output drive st
gth.
1: Corresponding P5.n output has high output drive strength.
SFR Definition 27.35. P6: Port6
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address = 0xDB
Bit
Name
P6[7:0]
Port 6 Data.
Sets the port latch logic
Descri
tion
Write
Read
7:0
0: Set output latch to logic
0: P6.n port pin is logic
LOW. LOW.
1: Set output latch to logic
1: P6.n port pin is logic
value or reads the port pin
logic state in port cells con-
ured for digital I/O.
HIGH.
HIGH.
Rev. 1.0
377
Si102x/3x
SFR Definition 27.36. P6MDIN: Port6 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P6MDIN[7:0]
R/W
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address = 0xF4
Bit
Name
Function
7:0
P6MDIN[7:0]
Analog Configuration Bits for P6.7–P6.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P6.n pin is configured for analog mode.
1: Corresponding P6.n pin is not configured for analog mode.
SFR Definition 27.37. P6MDOU
T
:
P
ort6 Output M
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
6MDOUT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x
B
Bit Name
Function
7:0 P6MDOUT[7:0]
Output Configuration Bits for P6.7–P6.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P6MDIN is logic 0.
0: Corresponding P6.n output is open-drain.
1: Corresponding P6.n output is push-pull.
378
Rev. 1.0
Si102x/3x
SFR Definition 27.38. P6DRV: Port6 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P6DRV[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xAA
Bit
Name
Function
7:0
P6DRV[7:0]
Drive Strength Configuration Bits for
P6.7–P6.0 (respectively).
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P6.n output has low output drive st
gth.
1: Corresponding P6.n output has high output drive strength.
SFR Definition 27.39. P7: Port7
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
P7.0
R/W
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address = 0xDC
Bit
7:1
0
Name
Descri
tion
Write
Read
Unused Read
= 0000000b; Write = Don’t Care.
P7.0
Port 7 Data.
0: Set output latch to logic
0: P7.0 port pin is logic
LOW. LOW.
1: Set output latch to logic
1: P7.0 port pin is logic
Sets the port latch logic
alue or reads the port pin
gic state in port cells con-
figured for digital I/O.
HIGH.
HIGH.
Rev. 1.0
379
Si102x/3x
SFR Definition 27.40. P7MDOU
T
:
P
ort7 Output Mode
Bit
7
6
5
4
3
2
1
0
P7MDOU
R/W
Name
Type
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xFC
Bit
7:1
0
Name
Function
Unused
Read = 0000000b; Write = Don’t Care.
P7MDOU
T
.
0
Output Configuration Bits for P7.0.
These bits control the digital driver.
0: P7.0 output is open-drain.
1: P7.0 output is push-pull.
SFR Definition 27.41. P7DRV: Port7 Drive Strength
Bit
7
6
5
4
3
2
1
0
P7DRV
R/W
0
Name
Type
Reset
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xAB
Bit
7:1
0
Name
Unused
P7DRV.0
Function
Read = 0000000b; Write = Don’t Care.
Drive Strength Configuration Bits for
P7.0.
Configures digital I/O port cells to high or low output drive strength.
0: P7.0 output has low output drive strength.
1: P7.0 output has high output drive strength.
380
Rev. 1.0
Si102x/3x
28. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
2
Management Bus Specification Version 1.1 and compatible with the I
C serial bus. Reads and writes to the
interface by the system controller are byte oriented with the SMBus interface autonomously controlling the
serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or slave
(this can be faster than allowed by the SMBus specification, depending on the system clock used).
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with m
tiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation an
nchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can
lly driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardwar
slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 28.1.
SMB0CN
SMB0CF
M T S S A A A S
E
I
B E S S S S
A X T T C R C
S M A O K B K
I
N N U X M M M M
S H S T B B B B
T O
E D
R E
R L
Q O
S
M
B
Y H T F C C
O O T S S
L E E 1 0
D
T
10
11
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
SCL
SMBUS CONTROL LOGIC
Arbitration
FILTER
Interrupt
Request
SCL Synchroniza
SCL Generation
aste
Mode)
SDA Control
SCL
Control
C
R
O
S
S
B
A
R
N
Hardware Slave Address Recognition
Hardware ACK Generation
Port I/O
Data Path
SDA
Control
IRQ Generation
Control
SMB0DAT
7 6 5 4 3 2 1 0
SDA
FILTER
S S S S S S S G
S S S S S S S E
L L L L L L L C
L L L L L L L H
V V V V V
5 4 3 2 1 0
V V V V V V V A
M M M M M M M C
6 5 4 3 2 1 0 K
SMB0ADR
SMB0ADM
N
Figure 28.1. SMBus Block Diagram
Rev. 1.0
381
Si102x/3x
28.1. Supporting
Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
2
1. The I
C-Bus and How to Use It (including specifications), Philips Semiconductor.
2
2. The I
C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
28.2. SMBus
Configuration
Figure 28.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels.
bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive pow
supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must hav
pen-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (reces
e state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V
V
D
= 3 V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Figure
.2. Typical SMBus Configuration
28.3. SMBus
Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface m
perate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as
Master in a system; any device who transmits a START and a slave address becomes the
mas
or the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
igure 28.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a “READ” operation and cleared to logic 0 to indicate a “WRITE” operation.
382
Rev. 1.0
Si102x/3x
All transactions are initiated by a master, with one or more addressed slave devices as the target.
The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 28.3 illustrates a typical
SMBus transaction.
SCL
SDA
SLA6
SLA5-0
R/W
D7
D6-0
START
Slave Address + R/W
ACK
Data Byte
ACK
STOP
Figure 28.3. SMBus Transaction
28.3.1. Transmitter Vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bus. A device is a “receiver
en an address or data byte is being sent
to it from another device on the bus. The transmitter controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK phase of the transfer, durin
hich time the receiver controls the SDA line.
28.3.2. Arbitration
A master may start a transfer only if the bus is
ee. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified tim
ee Section “28.3.5. SCL High (SMBus Free) Timeout” on
page 384). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-
tion scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attemp
ing the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission without interruption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
28.3.3. Clock Low
tension
2
SMBus provides a clock synchronization mechanism, similar to I C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower sla
devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW
extend the clock low period, effectively decreasing the serial clock frequency.
28.3.4. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
he master cannot force the SCL line high to correct the error condition.
T
o
s
olve this problem, the SMBus
rotocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
Rev. 1.0
383
Si102x/3x
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
28.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for th
SMBus clock source). If the SMBus is waiting to generate a Master STAR
T
,
t
he START will be generat
following this timeout. A clock source is required for free timeout detection, even in a slave-only implemen-
tation.
28.4. Using
the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timin
shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus in
rface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data b
or slave address that is transferred. When hardware
acknowledgment is disabled, the point at whi
h the interrupt is generated depends on whether the hard-
ware is acting as a data transmitter or recei
When a transmitter (i.e., sending address/data, receiving
an ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;
when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may de
e the outgoing ACK value. If hardware acknowledgment is enabled,
these interrupts are always generated after the ACK cycle. See Section 28.5 for more details on transmis-
sion sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 28.4.2;
T
a
ble 28.5 provide
uick SMB0CN decoding reference.
28.4.1. SMBus Configuration Register
The SMBu
Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
sele
e SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set,
e SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
384
Rev. 1.0
Si102x/3x
Table 28.1. SMBus Clock Source Selection
SMBCS1 SMBCS0
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
0
0
1
1
0
1
0
1
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from t
selected
source determine the absolute minimum SCL low and high times as defined in Eq
atio
28.1. The
selected clock source may be shared by other peripherals so long as the timer is left r
at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simul
eously. Timer
configuration is covered in Section “33. Timers” on page 483.
1
———————————————
T
HighMin
=
T
LowMin
=
f
ClockSourceOverflow
Equation 28.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 28.1. When the interface is operating as a master
d SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approxi
ted by Equation 28.1.
f
Cloc
ceOverflow
————-
–
———————–
BitRate
=
3
Equation 28.
Typical SMBus Bit Rate
Figure 28.4 shows the typical SCL generatio
escribed by Equation 28.2. Notice that T
is typically
HIGH
twice as large as T
. The actual SCL output may vary due to other devices on the bus (SCL may be
LOW
extended low by slower slave devi
, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by Equation 28.2.
Timer Source
Overflows
SCL
T
Low
T
High
SCL High Timeout
Figure 28.4. Typical SMBus SCL Generation
etting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively.
T
a
ble 28.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Rev. 1.0
385
Si102x/3x
Table 28.2. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
Minimum SDA Hold Time
T
– 4 system clocks
or
low
0
1
3 system clocks
1 system clock + s/w delay*
11 system clocks
12 system clocks
*Note:
Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgement, the s/w delay occurs between the time SMB0D
ACK is written and when SI is cleared. Note that if SI is cleared in the same w
that defines the outgoing ACK value, s/w delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “28.3.4. SCL Low Timeout” on page 383). The SMBus
erface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Ti
er 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enablin
the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10
SMBus clock source periods (see
Figure 28.4).
386
Rev. 1.0
Si102x/3x
SFR Definition 28.1. SMB0CF: SMBus Clock/Configuration
Bit
7
6
INH
R/W
0
5
BUSY
R
4
3
2
1
0
Name
ENSMB
EXTHOLD SMBTOE
SMBFTE
SMBCS[1:0]
R/W
Type
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0
0
0
SFR Page = 0x0; SFR Address = 0xC1
Bit
Name
Function
7
ENSMB
SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
6
INH
SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave
events occur. This effectively removes the SMBus slave from the bus. Master Mode
interrupts are not affected.
5
4
BUSY
SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-tim
t is sensed.
EXTHOLD
SMBus Setup and Hold Ti
Extension Enable.
This bit controls the SDA
etup and hold times according to
T
a
ble 28.2.
0: SDA Extended Setup
Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3
SMBTOE
SMBus SCL T
eout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces
Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low.
If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,
and the Timer 3 interrupt service routine should reset SMBus communication.
2
SMBFTE
Bus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
1
:
0
MBCS[1:0]
SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 28.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10:Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
Rev. 1.0
387
Si102x/3x
28.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see SFR Definition 28.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBu
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a ma
ter. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current trans
r after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed
START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indi
ates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each tran
fer, after each byte frame, or
when an arbitration is lost; see
T
a
ble 28.3 for more details.
Important Note About the SI Bit:
The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
28.4.2.1. Software
ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, th
mware on the device must detect incom-
ing slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a tr
nsmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set ea
me a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, soft
e should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be genera
ed i
software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value imm
tely following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
28.4.2.2. Hardware
ACK Generati
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK gen-
eration is enabled. More deta
l about automatic slave address recognition can be found in Section 28.4.3.
As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received
slave address is
Ked by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
T
a
ble 28.3 lists all sources for hardware changes to the SMB0CN bits. Refer to
T
a
ble 28.5 for SMBus sta-
tus decodi
using the SMB0CN register.
388
Rev. 1.0
Si102x/3x
SFR Definition 28.2. SMB0CN: SMBus Control
Bit
7
6
5
4
3
2
1
0
SI
Name
MASTER TXMODE
STA
R/W
0
STO
R/W
0
ACKRQ ARBLOST
ACK
R/W
0
Type
R
0
R
0
R
0
R
0
R/W
0
Reset
SFR Page = 0x0; SFR Address = 0xC0; Bit-Addressable
Bit
Name
Description
Read
te
7
MASTER
SMBus Master/Slave
Indicator.
This read-only bit
indicates when the SMBus is
operating as a master.
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
N/A
N/A
6
5
4
TXMODE
SMBus Transmit Mode
Indicator.
This read-only bit
indicates when the SMBus is
operating as a transmitter.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
STA
SMBus Start Flag.
0: No Start or repeated
Star
detected.
1:
or repeated Start
etected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated STAR
T
.
STO
SMBus Stop Flag.
0: No Stop condition
detected.
0: No STOP condition is
transmitted.
1: Stop condition detected
1: When configured as a
(if in Slave Mode) or pend-
Master, causes a STOP
ing (if in Master Mode).
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3
2
1
ACKRQ
SMBus Acknowledge
0: No Ack requested
1: ACK requested
N/A
uest.
ARBLOST
SMBus Arbitration Lost
0: No arbitration error.
1: Arbitration Lost
N/A
Indicator.
ACK
SI
SMBus Acknowledge.
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
0
SMBus Interrupt Flag.
0: No interrupt pending
0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
This bit is set by hardware
under the conditions listed in
T
a
ble 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
1: Interrupt Pending
Rev. 1.0
389
Si102x/3x
Table 28.3. Sources for Hardware Changes to SMB0CN
Bit
Set by Hardware When:
•
A START is generated.
Cleared by Hardware When:
•
A STOP is generated.
•
Arbitration is lost.
MASTER
•
A START is detected.
•
Arbitration is lost.
•
SMB0DAT is not written before the
start of an SMBus frame.
•
START is generated.
•
SMB0DAT is written before the start of an
SMBus frame.
TXMODE
•
A START followed by an address byte is
received.
•
A STOP is detected while addressed as a
slave.
STA
STO
•
Must be cleared by softwa
•
A pending STOP is g
ated.
•
Arbitration is lost due to a detected STO
P
.
•
A byte has been received and an ACK
response value is needed (only when hard-
ware ACK is not enabled).
•
A repeated START is detected as a MASTER
when STA is low (unwanted repeated START).
•
SCL is sensed low while attempting to gener-
ate a STOP or repeated START condition.
•
SDA is sensed low while transmitting a 1
(excluding ACK bits).
ACKRQ
•
After each ACK cycle.
Each time SI is cleared.
ARBLOST
ACK
•
The incoming ACK value is low
(ACKNOWLEDGE).
•
The incoming ACK value is high (NOT
ACKNOWLEDGE).
•
A START has been generated.
•
Lost arbitration.
•
A byte has been transmitte
nd an
ACK/NACK received.
•
A byte has been received.
SI
•
Must be cleared by software.
•
A START or repea
d START followed by a
slave address + R
W has been received.
•
A STOP has been received.
28.4.3. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an
ACK without softwar
intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB
M to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK genera
on can be found in Section 28.4.2.2.
The
sters used to define which address(es) are recognized by the hardware are the SMBus Slave
Addr
s register (SFR Definition 28.3) and the SMBus Slave Address Mask register (SFR Definition 28.4).
A single address or range of addresses (including the General Call Address 0x00) can be specified using
these two registers. The most-significant seven bits of the two registers are used to define which
ddresses will be ACKed. A 1 in bit positions of the slave address mask SLVM[6:0] enable a comparison
etween the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit
of the slave address mask means that bit will be treated as a “don’t care” for comparison purposes. In this
case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in
register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00).
T
a
ble 28.4 shows
some example parameter settings and the slave addresses that will be recognized by hardware under
those conditions.
390
Rev. 1.0
Si102x/3x
Table 28.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address
Slave Address Mask
GC bit
Slave Addresses Recognized by
Hardware
SLV[6:0]
SLVM[6:0]
0x34
0x7F
0
1
0
1
0
0x34
0x34
0x7F
0x34, 0x00 (General Call)
0x34, 0x35
0x34
0x7E
0x34
0x7E
0x34, 0x35, 0x00 (General Call)
0x70, 0x74, 0x78, 0
0x70
0x73
SFR Definition 28.3. SMB0ADR: SMBus Slave Address
Bit
7
6
5
4
SLV[6:0]
R/W
0
3
2
1
0
GC
R/W
0
Name
Type
Reset
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xF4
Bit
Name
Function
7
:
1
SLV[6:0]
SMBus Hardware Slave
ddress.
Defines the SMBus S
e Address(es) for automatic hardware acknowledgement.
Only address bits whic
have a 1 in the corresponding bit position in SLVM[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0
GC
General Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
Rev. 1.0
391
Si102x/3x
SFR Definition 28.4. SMB0ADM: SMBus Slave Address Mask
Bit
7
6
5
4
3
2
1
0
EHACK
R/W
0
Name
Type
Reset
SLVM[6:0]
R/W
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xF5
Bit
Name
Function
7
:
1
SLVM[6:0]
SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in S
M[6:0] enables compari-
sons with the corresponding bit in SLV[6:0]. Bits set to 0 are ignored (can be either
0 or 1 in the incoming address).
0
EHACK
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowled
ll incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
392
Rev. 1.0
Si102x/3x
28.4.4. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of receive
data is located at the MSB of SMB0DA
T
.
W
hile data is being shifted out, data on the bus is simultaneous
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DA
T
.
SFR Definition 28.5. SMB0DA
T
:
S
MBus Data
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SMB0DAT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC2
Bit Name
7
:
0 SMB0DAT[7:0]
SMBus Data.
Function
The SMB0DAT register co
ains a byte of data to be transmitted on the SMBus
serial interface or a byt
that has just been received on the SMBus serial interface.
The CPU can read fro
write to this register whenever the SI serial interrupt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting da
in/out and the CPU should not attempt to access this register.
28.5. SMBus
Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. Th
MBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it
es an arbitration or generates a STO
P
.
A
n SMBus interrupt is generated at the end
of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver
depends o
hether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs
befor
he
CK with hardware ACK generation disabled, and
after
the ACK when hardware ACK genera-
tion
nabled. As a transmitter, interrupts occur
after
the ACK, regardless of whether hardware ACK gen-
eration is enabled or not.
28.5.1. Write Sequence (Master)
uring a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface
will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Rev. 1.0
393
Si102x/3x
Figure 28.5 shows a typical master write sequence. Two transmit data bytes are shown, though any num-
ber of bytes may be transmitted. All “data byte transferred” interrupts occur
after
the ACK cycle in this
mode, regardless of whether hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
W
A
Data Byte
A
Data Byte
A
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
W = WRITE
Transmitted by
SLA = Slave Address
SMBus Interface
Figure 28.5. Typical Master Write Sequence
28.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a
e device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction b
/W) will be logic
1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data.
If hardware ACK generation is disabled, the
KRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enab
d, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt.
It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0-
DAT is written whil
active Master Receiver. Figure 28.6 shows a typical master read sequence. Two
received data bytes are shown, though any number of bytes may be received. The “data byte transferred”
interrupts occur at different places in the sequence, depending on whether hardware ACK generation is
enabled. T
interrupt occurs
before
the ACK with hardware ACK generation disabled, and
after
the ACK
when
rdware ACK generation is enabled.
394
Rev. 1.0
Si102x/3x
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
R
A
Data Byte
A
Data Byte
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
N = NACK
R = READ
SLA = Slave Addr
ss
Transmitted by
SMBus Interface
Figure 28.6. Typical Master Read Sequen
28.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a S
T followed by a slave address and direc-
tion bit (WRITE in this case) is received. If hardware ACK ge
eration is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the re
ed slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the AC
or a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt w
l occur after the ACK cycle.
If the received slave address is ignored (by s
are or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disa
ed, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt.
The appropriate ACK or NACK value should be set up by the software
prior to receiving the byte when hardware ACK generation is enabled.
The interface exits
e Receiver Mode after receiving a STO
P
.
N
ote that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 28.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
that the ‘da
byte transferred’ interrupts occur at different places in the sequence, depending on whether
hard
e ACK generation is enabled. The interrupt occurs
before
the ACK with hardware ACK generation
disab
ed, and
after
the ACK when hardware ACK generation is enabled.
Rev. 1.0
395
Si102x/3x
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
W
A
Data Byte
A
Data Byte
A
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
A = ACK
Received by SMBus
Interface
W = WRITE
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 28.7. Typical Slave Write Sequence
28.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this ca
s received. If hardware ACK generation
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled
hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR
nd SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by s
re or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are trans-
mitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmit-
ted. The interface enters Slave Tran
mitter Mode, and transmits one or more bytes of data. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (an error condition may be generated if SMB0DAT is written following a received
NACK while in Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a
STO
P
.
N
ote that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a
Slave Transmitter i
upt. Figure 28.8 shows a typical slave read sequence. Two transmitted data bytes
are shown, though a
y number of bytes may be transmitted. All of the “data byte transferred” interrupts
occur
after
the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled.
396
Rev. 1.0
Si102x/3x
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
R
A
Data Byte
A
Data Byte
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)
S = START
P = STOP
N = NACK
Received by SMBus
Interface
R = READ
SLA = Slave Address
Transmitted by
SMBus Interface
Figure 28.8. Typical Slave Read Sequence
28.6. SMBus
Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled.
T
a
ble 28.5 describes the typ
cal actions when hardware slave address
recognition and ACK generation is disabled.
T
a
ble 28.6 descri
he typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ-
ical responses; application-specific procedures are a
d as long as they conform to the SMBus specifi-
cation. Highlighted responses are allowed by har
are but do not conform to the SMBus specification.
Rev. 1.0
397
Si102x/3x
Table 28.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A master START was gener-
Load slave address + R/W into
1110
1100
0
0
0
0
X
0
0
X
1100
ated.
SMB0DA
T
.
A master data or address byte
Set STA to restart transfer.
0
1
X
X
1110
–
0 was
transmitted; NACK
received.
Abort transfer.
Load next data byte into SMB0-
DAT.
0
0
1
1
0
1
1
0
X
X
X
X
1100
End transfer with STO
P
.
–
–
A master data or address byte
End transfer with STOP and start
0
0
1 was
transmitted; ACK
received.
another transfer.
Send repeated STAR
T
.
1110
Swi
ch t
aster Receiver Mode
(clear SI without writing new data
SMB0DAT).
0
0
X
1000
knowledge received byte;
Read SMB0DA
T
.
0
0
0
1
1
0
1000
–
Send NACK to indicate last byte,
and send STO
P
.
Send NACK to indicate last byte,
and send STOP followed by
START.
1
1
0
1110
Send ACK followed by repeated
START.
A master data byte was
0 X
1
1
0
0
1
0
1110
1110
1000
1
received; ACK requested.
Send NACK to indicate last byte,
and send repeated STAR
T
.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
0
0
0
0
1
0
1100
1100
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
398
Rev. 1.0
Si102x/3x
Table 28.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A slave byte was transmitted;
No action required (expecting
0
0
0
0
0
1
0
1
0
0
0
0
X
X
X
0001
0100
0001
NACK received.
A slave byte was transmitted;
Load SMB0DAT with next data
ACK received.
byte to transmit.
A Slave byte was transmitted;
No action required (expecting
STOP condition).
0100
0101
X
error detected.
Master to end transfer).
An illegal STOP or bus error
X was
detected while a Slave
Transmission was in progress.
0
1
X
0
Clear STO.
0
0
0
0
X
1
–
If Write, Acknowledge received
address
0000
A slave address + R/W was
received; ACK requested.
X
If Read,
ad SMB0DAT with
data byt
CK received address
0
0
0
0
0
0
1
0
1
0100
–
NACK received address.
rite, Acknowledge received
address
0010
0000
If Read, Load SMB0DAT with
data byte; ACK received address
Lost arbitration as mas
r;
X slave
address + R/W r
ed;
ACK requested.
0
0
1
0
0
0
1
0
0
0100
–
1
1
NACK received address.
Reschedule failed transfer;
NACK received address.
1110
A STOP was detected while
0
1
0
1
X addressed
as a Slave Trans-
Clear STO.
mitter or Slave Receiver.
0
0
X
–
0001
0000
Lost arbitration while attempt-
No action required (transfer
0
0
0
0
0
1
–
ng a STO
P
.
complete/aborted).
Acknowledge received byte;
Read SMB0DA
T
.
0000
A slave byte was received;
ACK requested.
0
X
NACK received byte.
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
X
X
X
X
0
–
Abort failed transfer.
–
Lost arbitration while attempt-
ing a repeated STAR
T
.
0010
0001
0000
0
0
1
1
1
1
X
X
X
Reschedule failed transfer.
Abort failed transfer.
1110
–
Lost arbitration due to a
detected STO
P
.
Reschedule failed transfer.
Abort failed transfer.
1110
–
Lost arbitration while transmit-
ting a data byte as master.
Reschedule failed transfer.
0
1110
Rev. 1.0
399
Si102x/3x
Table 28.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A master START was gener-
Load slave address + R/W into
1110
0
0
0
0
X
0
X
1100
ated.
SMB0DA
T
.
A master data or address byte
Set STA to restart transfer.
0
0
1
X
X
1110
–
0 was
transmitted; NACK
received.
Abort transfer.
Load next data byte int
SMB0-
DAT.
0
0
1
1
0
1
1
0
X
X
X
X
1100
End transfer with STO
P
.
–
–
1100
End transfer with STOP and start
another transfer.
A master data or address byte
1 was
transmitted; ACK
received.
0
0
Send re
ed STAR
T
.
1110
Switch to Master Receiver Mode
lear SI without writing new data
MB0DAT). Set ACK for initial
data byte.
0
0
0
0
1
1
1000
1000
Set ACK for next data byte;
Read SMB0DA
T
.
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DA
T
.
0
1
0
0
0
0
0
0
X
1000
1110
1100
A master data byte was
received; ACK sent.
0
0
1
Initiate repeated STAR
T
.
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
1000
Read SMB0DA
T
;
s
end STO
P
.
0
1
1
1
1
0
0
0
0
–
Read SMB0DA
T
;
S
end STOP
followed by STAR
T
.
1110
1110
A master data byte was
0 received;
NACK sent (last
byte).
0
0
Initiate repeated STAR
T
.
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
0
0
X
1100
400
Rev. 1.0
Si102x/3x
Table 28.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A slave byte was transmitted;
No action required (expecting
0
0
0
0
0
1
0
1
0
0
0
0
X
X
X
0001
0100
0001
NACK received.
A slave byte was transmitted;
Load SMB0DAT with next data
ACK received.
byte to transmit.
A Slave byte was transmitted;
No action required (expecting
STOP condition).
0100
0101
X
error detected.
Master to end transfer).
An illegal STOP or bus error
X was
detected while a Slave
Transmission was in progress.
0
0
X
0
Clear STO.
0
0
X
—
If Write, Set ACK for first data
byte.
0
0
0
0
0
0
1
X
1
0000
0100
0000
A slave address + R/W was
received; ACK sent.
X
If Read,
ad SMB0DAT with
data byt
0010
If Write, Set ACK for first data
te.
Lost arbitration as master;
0
1
X slave
address + R/W receiv
; If
Read, Load SMB0DAT with
0
1
0
0
X
X
0100
1110
ACK sent.
data byte
Reschedule failed transfer
A STOP was detected while
0
0
0
1
X addressed
as
Slave Trans-
Clear STO.
mitter or Slav
Receiver.
0
0
X
—
0001
0000
Lost arbitration while attempt-
No action required (transfer
X
0
0
0
0
0
0
0
1
0
—
ing a STO
P
.
complete/aborted).
Set ACK for next data byte;
Read SMB0DA
T
.
0000
0000
0
0
A slave byte was received.
Set NACK for next data byte;
Read SMB0DA
T
.
Abort failed transfer.
0
1
0
1
0
1
0
0
0
0
0
0
X
X
X
X
X
X
—
1110
—
Lost arbitration while attempt-
ing a repeated STAR
T
.
0010
0001
0000
0
0
0
1
1
1
X
Reschedule failed transfer.
Abort failed transfer.
Lost arbitration due to a
detected STO
P
.
X
Reschedule failed transfer.
Abort failed transfer.
1110
—
Lost arbitration while transmit-
ting a data byte as master.
X
Reschedule failed transfer.
1110
Rev. 1.0
401
Si102x/3x
29. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UAR
T
.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “29.1. Enhanced Baud Rate Generation” on page 403). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers.
Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Recei
register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is compl
(TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SBUF
SET
(TX Shift)
D
Q
TX
CLR
Crossbar
Zero D
r
Stop Bit
Shift
Data
Start
Tx
l
Tx Clock
Send
Tx IRQ
SCON
TI
UART Baud
Rate Generator
Serial
Port
Interrupt
Port I/O
RI
Rx IRQ
Rx Clock
Rx Control
Load
SBUF
Start
Shift
0x1FF
RB8
Input Shift Register
(9 bits)
Load SBUF
SBUF
(RX Latch)
Read
SBUF
SFR Bus
RX
Crossbar
Figure 29.1. UART0 Block Diagram
Rev. 1.0
402
Si102x/3x
29.1. Enhanced
Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 29.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer
1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive t
begin any time a START is detected, independent of the TX Timer state.
Timer 1
TL1
UART
Overflow
TX Clock
2
2
TH1
Start
Detected
Overflow
RX Clock
RX Timer
Figure 29.2. UART
ud Rate Logic
Timer 1
should be configured for Mode
2
8-bit auto-reload (see Section “33.1.3.
Mode 2: 8-bit
Counter/Timer with Auto-Reload” on page 4
The Timer 1 reload value should be set so that overflows
will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of
six sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an
external input T1. For any given Tim
1 clock source, the UART0 baud rate is determined by Equation -A
and Equation -B.
1
2
A)
B)
—
UartBaudRate =
T1_Overflow_Rate
T1
CLK
————————-
T1_Overflow_Rate =
256 – TH1
UART0 Baud Rat
Whe
1
is the frequency of the clock supplied to Timer 1, and
T1H
is the high byte of Timer 1 (reload
CLK
value
Timer 1
clock frequency is selected as described in Section “33.1.
Timer 0 and Timer 1” on
page 485. A quick reference for typical baud rates and system clock frequencies is given in
T
a
ble 29.1
through
T
a
ble 29.2. Note that the internal oscillator may still generate the system clock when the external
scillator is driving Timer 1.
403
Rev. 1.0
Si102x/3x
29.2. Operational
Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
TX
RS-232
RS-232
LEVEL
C8051Fxxx
RX
XLTR
OR
TX
RX
TX
RX
MCU
C8051Fxxx
Figure 29.3. UART Interconnect Diagram
29.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one star
t, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and receive
t the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a dat
te to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN0 Receive
nable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into th
BUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the
top bit must be logic 1. In the event of a receive data over-
run, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
MARK
S
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
SPACE
BIT TIMES
IT SAMPLING
Figure 29.4. 8-Bit UART Timing Diagram
9.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Rev. 1.0
404
Si102x/3x
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not m
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur
enabled when either TI0 or RI0 is set to 1.
MARK
START
BIT
STOP
BIT
D0
D1
D2
D3
D4
D5
D6
D7
SPACE
BIT TIMES
BIT SAMPLING
Figure 29.5. 9-Bit UART Timing Diagram
29.3. Multiprocessor
Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a
er processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave process
onfigures its UART such that when a stop bit is
received, the UART will generate an interrupt onl
the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interru
handler, software will compare the received address with
the slave’s own assigned 8-bit address. If the
dresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren’t addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is re
eived, the addressed slave resets its MCE0 bit to ignore all transmis-
sions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling “broadcast” transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is
mporarily reversed to enable half-duplex transmission between the original master
and slave(s).
405
Rev. 1.0
Si102x/3x
Master
Device
Slave
Device
Slave
Device
Slave
Device
V+
RX
TX
RX
TX
RX
TX
RX
TX
Figure 29.6. UART Multi-Processor Mode Interconnect Diagram
Rev. 1.0
406
Si102x/3x
SFR Definition 29.1. SCON0: Serial Port 0 Control
Bit
7
6
5
MCE0
R/W
0
4
REN0
R/W
0
3
TB80
R/W
0
2
RB80
R/W
0
1
TI0
R/W
0
0
RI0
R/W
0
Name
S0MODE
Type
R/W
0
R
1
Reset
SFR Page = 0x0; SFR Address = 0x98; Bit-Addressable
Bit
Name
Function
7
S0MODE
Serial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6
5
Unused Read
= 1b. Write = Don’t Care.
MCE0
Multiprocessor Communication Enable.
For Mode 0 (8-bit UART): Checks for vali
op bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop b
is logic level 1.
For Mode 1 (9-bit UART): Multipr
ssor Communications Enable.
0: Logic level of ninth bit is ign
ed
1: RI0 is set and an interru
s generated only when the ninth bit is logic 1.
4
3
2
1
REN0
TB80
RB80
0
Receive Enable.
0: UART0 reception disabled.
1: UART0 recepti
n enabled.
Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
N
th Receive Bit.
R
0 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
0
RI0
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
407
Rev. 1.0
Si102x/3x
SFR Definition 29.2. SBUF0: Serial (UART0) Port Data Buffer
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SBUF0[7:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0x99
Bit
Name
Function
7:0
SBUF0
Serial Data Buffer Bits 7:0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register
d a receive latch register.
When data is written to SBUF0, it goes to the transmit sh
ft register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
Rev. 1.0
408
Si102x/3x
Table 29.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
Frequency: 24.5 MHz
1
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscilla- Timer
Clock
SCA1–SCA0
(pre-scale
Timer 1
Reload
Value (hex)
T1M
tor Divide
Factor
Source
1
select)
2
230400
–0.32%
106
SYSCLK
1
0xCB
XX
115200
57600
–0.32%
0.15%
212
426
SYSCLK
SYSCLK
XX
XX
01
00
00
10
10
1
0
0
0
0
0
0x96
0x2B
0x96
0xB9
0x96
0x96
0x2B
28800
–0.32%
0.15%
848
SYSCLK/4
SYSCLK/12
SYSCLK/12
SYSCLK/48
SYSCLK/48
14400
1704
2544
10176
20448
9600
–0.32%
–0.32%
0.15%
2400
1200
Notes:
1.
SCA1
–
SCA0 and T1M bit definitions can be found in Section 33.1.
2.
X = Don’t care.
Table 29.2. Timer Setti
gs for Standard Baud Rates
Using an Exter
al 22.1184 MHz Oscillator
Frequency: 22.1184 MHz
1
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscilla- Timer
Clock
SCA1–SCA0
(pre-scale
Timer 1
Reload
Value (hex)
T1M
tor Divide
Factor
Source
1
select)
2
230400
0.00%
96
SYSCLK
1
0xD0
XX
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
192
384
SYSCLK
XX
XX
00
00
00
10
10
1
1
0
0
0
0
0
0xA0
0x40
0xE0
0xC0
0xA0
0xA0
0x40
SYSCLK
768
SYSCLK / 12
SYSCLK / 12
SYSCLK / 12
SYSCLK / 48
SYSCLK / 48
1536
2304
9216
18432
2400
1200
409
Rev. 1.0
Si102x/3x
Table 29.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
Frequency: 22.1184 MHz
1
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscilla- Timer
Clock
SCA1–SCA0
(pre-scale
Timer 1
Reload
Value (hex
T1M
tor Divide
Factor
Source
1
select)
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
96
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
11
11
11
11
11
11
0
0
0
0
0
0xFA
0xF4
0xE8
0xD0
0xA0
0x70
192
384
768
1536
2304
Notes:
1.
SCA1
–
SCA0 and T1M bit definitions can be found in Section 33.1.
2.
X = Don’t care.
Rev. 1.0
410
Si102x/3x
30. Enhanced
Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS c
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SPI0CKR
SPI0CFG
SPI0CN
Clock Divide
Logic
SYSCLK
SPI CONTROL LOGIC
SPI IRQ
Data Path
Control
in Interface
Control
MOSI
Tx Data
C
R
O
S
S
B
A
R
SPI0DAT
SCK
MISO
NSS
Transmit Data Buffer
Pin
Control
Logic
Port I/O
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 30.1. SPI Block Diagram
Rev. 1.0
411
Si102x/3x
30.1. Signal
Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
30.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat-
ing as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
30.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to
aster device.
It is used to serially transfer data from the slave to the master. This signal is an input wh
I0 is operat-
ing as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
30.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 gen-
erates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
30.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dep
ent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible m
es that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave de
, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-
to-point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slav
or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This
configuration
ld only be used when operating SPI0 as a master device.
See Figure 30.2, Figure 30.3, and Figure 30.4 for typical connection diagrams of the various operational
modes.
Not
that the setting of NSSMD bits affects the pinout of the device.
When in 3-wire master or
3-wire slav
mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be
ped to a pin on the device. See Section “27. Port Input/Output” on page 351 for general purpose
port I/O and crossbar information.
30.2. SPI0
Master Mode Operation
SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
412
Rev. 1.0
Si102x/3x
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master’s shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DA
T
.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-w
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSS-
MD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is
used to disable the master SPI0 when another master is accessing the bus. When NSS is pulle
ow in this
mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI mas
device, and a
Mode Fault is generated (MOD
F
,
S
PI0CN.5 = 1). Mode Fault will generate an interru
abled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master syst
s, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-mas-
ter mode, slave devices can be addressed individually (if needed) using gener
l-purpose I/O pins.
Figure 30.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure
30.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.
1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 30
hows a connection diagram for a master device in
4-wire master mode and two slave devices.
Rev. 1.0
413
Si102x/3x
NSS
MISO
MOSI
SCK
GPIO
MISO
MOSI
SCK
Master
Device 1
Master
Device 2
GPIO
NSS
Figure 30.2. Multiple-Master Mode Connection Diagram
Master
Device
Slave
Device
MISO
MOSI
SCK
MISO
MOSI
SCK
Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
MISO
MOSI
SCK
MISO
MOSI
SCK
Master
Device
Slave
Device
NSS
NSS
GPIO
MISO
MOSI
SCK
Slave
Device
NSS
Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
30.3
SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift reg-
ter, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DA
T
. A
s
lave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DA
T
.
W
rites to SPI0DAT are double-
buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
414
Rev. 1.0
Si102x/3x
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig
nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transf
Figure 30.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0
NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Sinc
e is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave devi
esent on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI0 with the SPIEN bit. Figure 30.3 shows a connection diagram between a slave device in 3-
wire slave mode and a master device.
30.4. SPI0
Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set
ogic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to th
PI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit
uffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0
disable SPI0 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
30.5. Serial
Cl
Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CF
G
.
5) selects one of two clock phases
(edge use
o latch the data). The CKPOL bit (SPI0CF
G
.
4) selects between an active-high or active-low
cloc
oth master and slave devices must be configured to use the same clock phase and polarity. SPI0
shoul
be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 30.5. For slave mode, the clock and
data relationships are shown in Figure 30.6 and Figure 30.7. Note that CKPHA should be set to 0 on both
e master and slave SPI when communicating between two Silicon Labs C8051 devices.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 30.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequenc
y
,
p
rovided that the master issues SCK, NSS (in 4-
Rev. 1.0
415
Si102x/3x
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (Must Remain High
in Multi-Master Mode)
Figure 30.5
Master Mode Data/Clock Timing
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 0
MISO
Bit 1
Bit 0
NSS (4-Wire Mode)
Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0)
416
Rev. 1.0
Si102x/3x
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 0
MISO
Bit 1
0
NSS (4-Wire Mode)
Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1)
30.6. SPI
Special Function Registers
SPI0 is accessed and controlled through four special function
isters in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to
he operation of the SPI0 Bus are described in the
following figures.
Rev. 1.0
417
Si102x/3x
SFR Definition 30.1. SPI0CFG: SPI0 Configuration
Bit
7
6
MSTEN
R/W
0
5
CKPHA
R/W
0
4
CKPOL
R/W
0
3
2
1
SRMT
R
0
Name
SPIBSY
SLVSEL
NSSIN
RXBMT
Type
R
0
R
0
R
1
R
1
Reset
1
SFR Page = 0x0; SFR Address = 0xA1
Bit
Name
Function
7
SPIBSY
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6
5
4
3
MSTEN
CKPHA
CKPOL
SLVSEL
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
SPI0 Clock Phase.
*
0: Data centered on first edge of SCK p
d.
1: Data centered on second edge of SCK period.
*
SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle sta
.
Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate t
instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
2
1
NSSIN
SRMT
NSS Instantaneous Pin Input.
Th
s bit mimics the instantaneous value that is present on the NSS port pin at the
t
me that the register is read. This input is not de-glitched.
hift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
0
RXBMT
Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note:
In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See
T
a
ble 30.1 for timing parameters.
418
Rev. 1.0
Si102x/3x
SFR Definition 30.2. SPI0CN: SPI0 Control
Bit
7
SPIF
R/W
0
6
WCOL
R/W
0
5
MODF
R/W
0
4
RXOVRN
R/W
3
2
1
0
SPIEN
R/W
0
Name
Type
Reset
NSSMD[1:0]
R/W
TXBMT
R
1
0
0
1
SFR Page = 0x0; SFR Address = 0xF8; Bit-Addressable
Bit
Name
Function
7
SPIF
SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is
t automatically cleared by
hardware, and must be cleared by software.
6
5
4
WCOL
MODF
Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be
written. If SPI interrupts are enabled, a
rrupt will be generated. This bit is not
automatically cleared by hardware, and must be cleared by software.
Mode Fault Flag.
This bit is set to logic 1 by hard
re when a master mode collision is detected
(NSS is low, MSTEN = 1,
d NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be genera
d. This bit is not automatically cleared by hardware, and
must be cleared by sof
re.
RXOVRN
Receive Overrun Flag (valid in slave mode only).
This bit is set
logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatically cleared by hardware, and must be cleared by software.
3:2 NSSMD[1:0]
Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 30.2 and Section 30.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1
0
TXBMT
SPIEN
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
Rev. 1.0
419
Si102x/3x
SFR Definition 30.3. SPI0CKR: SPI0 Clock Rate
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SCR[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA2
Bit
Name
Function
7:0
SCR[7:0]
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock
equency is a divided ver-
sion of the system clock, and is given in the following equation, where
SYSCLK
is
the system clock frequency and
SPI0CKR
is th
8-bit value held in the SPI0CKR
register.
SYSCLK
2
SPI0CKR[7:0] + 1
———————————————————-
=
f
SCK
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz
SPI0CKR = 0x04,
2000000
———————–
–
–
=
f
SCK
2
4 + 1
f
SCK
= 200
kHz
SFR Definition 30.4. SPI0DA
T
:
S
PI0 Data
Bit
7
6
5
4
3
2
1
0
Name
Type
Re
SPI0DAT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA3
Bit Name
7:0 SPI0DAT[7:0]
SPI0 Transmit and Receive Data.
Function
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
420
Rev. 1.0
Si102x/3x
SCK*
T
T
MCKL
MCKH
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0.
SCK is the opposite polarity for CKPOL = 1.
Figure 30.8. SPI Master Timing (CKPHA = 0)
SCK*
T
T
MCKH
MCKL
T
T
MIH
MIS
MISO
MOSI
* SCK is shown for CKP
= 0.
SCK is the opposite polarity for CKPOL = 1.
Figure 30.9. SPI Master Timing (CKPHA = 1)
Rev. 1.0
421
Si102x/3x
NSS
T
T
T
SD
SE
CKL
SCK*
T
CKH
T
T
SIH
SIS
MOSI
T
T
T
SDZ
SEZ
SOH
MISO
* SCK is shown for CKPOL = 0.
SCK is the opposite polarity for CKPOL = 1.
Figure 30.10. SPI Slave Timing
CKPHA = 0)
NSS
T
T
T
SD
SE
CKL
SCK*
T
CKH
T
T
SIH
SIS
MOSI
T
T
T
SDZ
T
SOH
SLH
MI
O
* SCK is shown for CKPOL = 0.
SCK is the opposite polarity for CKPOL = 1.
Figure 30.11. SPI Slave Timing (CKPHA = 1)
422
Rev. 1.0
Si102x/3x
Table 30.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing
(See Figure 30.8 and Figure 30.9)
T
T
T
T
SCK High Time
1 x T
—
—
—
ns
ns
ns
ns
MCKH
MCKL
MIS
SYSCLK
SYSCLK
SCK Low Time
1 x T
1 x T
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
+ 20
SYSCLK
0
MIH
Slave Mode Timing
(See Figure 30.10 and Figure 30.11)
T
T
T
T
T
T
T
T
T
T
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
2 x T
2 x T
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SE
SYSCLK
SD
SYS
—
4 x T
SYSCLK
SEZ
SDZ
CKH
CKL
SIS
—
4 x T
SYSCLK
5 x T
5 x T
2 x T
2 x T
—
SYSCLK
SYSCLK
SYSCLK
SCK Low Time
—
—
—
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Chang
SCK Shift Edge to MISO Chan
e
SIH
SOH
SLH
SYSCLK
—
4 x T
8 x T
SYSCLK
SYSCLK
Last SCK Edge to MISO Change
6 x T
SYSCLK
(CKPHA = 1 ONLY)
Note:
T
is equal to one period of the device system clock (SYSCLK).
SYSCLK
Rev. 1.0
423
Si102x/3x
31. EZRadioPRO
®
Serial Interface
The EZRadioPRO serial interface (SPI1) provides access to the EZRadioPRO peripheral registers from
software executing on the MCU core. The serial interface consists of two SPI peripherals: a dedicated SPI
Master accessible from the MCU core and a dedicated SPI Slave residing inside the EZRadioPRO
peripheral. The SPI1 peripheral on the MCU core side can only be used in master mode to communicate
with the EZRadioPRO slave device in three-wire mode. NSS for the EZRadioPRO is provided using P
2.3, which is internally routed to the EZRadioPRO peripheral.
SFR Bus
SPI0CKR
SPI0CFG
SPI0CN
Clock Divide
Logic
SYSCLK
SPI CONTROL LOGIC
SPI IRQ
Data Path
Control
Pin Interface
Control
MOSI
Tx Data
C
R
O
S
S
B
A
R
SPI0DAT
SCK
MISO
NSS
Transmit Data Buffer
Pin
Control
Logic
Port I/O
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 31.1. SPI Block Diagram
Rev. 1.0
424
Si102x/3x
31.1. Signal
Descriptions
The four signals used by SPI1 (MOSI, MISO, SCK, NSS) are described below.
31.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output to the MCU core. Data
is transferred most-significant bit first. MOSI is driven by the MSB of the shift register.
31.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the EZRadioPRO to the MCU core. This signal is an
put when
SPI1 is operating as a master and an output when SPI1 is operating as a slave. Data is
nsferred most-
significant bit first. The MISO pin is placed in a high-impedance state when the SPI1 m
s disabled.
31.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to the EZRadioPRO. It is
used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI1
generates this signal.
31.1.4. Slave Select (NSS)
To
i
nterface to the EZRadioPRO, SPI1 operates in three-wire mode. The NSS functionality built into the
SPI state machine is not used. Instead, the port pin P2.3 must be configured to control the chip select on
the EZRadioPRO peripheral under software control.
425
Rev. 1.0
Si102x/3x
31.2. SPI1
Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI1 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI1CN.6). Writing a byte of data to the SPI1 data register (SPI1DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI1 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI1CN.7) flag is set to logi
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF fl
is set. While the SPI1 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-rea
flag. The
data byte received from the slave is transferred MSB-first into the master’s shift registe
When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read b
rocessor by
reading SPI1DA
T
.
31.3. SPI
Slave Operation on the EZRadioPRO Peripheral Side
The EZRadioPRO peripheral presents a standard 4-wire SPI interface: SCK, MISO, MOSI, and NSS. The
SPI master can read data from the device on the MOSI output pin. An SPI tra
saction is a 16-bit sequence
that consists of a Read-Write (R/W) select bit followed by a 7-bit address field (ADDR) and an 8-bit data
field (DATA), as demonstrated in Figure 31.2. The 7-bit address field is used to select one of the 128, 8-bit
control registers. The R/W select bit determines whether the SPI transaction is a read or write transaction.
If R/W = 1, it signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents
(ADDR or DATA) are latched into the transceiver every eight
k cycles. The timing parameters for the
SPI interface are shown in
T
a
ble 31.1. The SCK rate is flexible with a maximum rate of 10 MHz.
31.4. SPI1
Interrupt Sources
When SPI1 interrupts are enabled, the following four f
s will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by s
are.
The SPI Interrupt Flag, SPIF (SPI1CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI1 modes.
The Write Collision Flag, WCOL
PI1CN.6) is set to logic 1 if a write to SPI1DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI1DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI1
modes.
The Mode Fault Flag MODF (SPI1CN.5) is set to logic 1 when SPI1 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI1CN
et to logic 0 to disable SPI1 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI1CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is
t transferred to the receive buffer, allowing the previously received data byte to be read. The
d
byte which caused the overrun is lost.
Rev. 1.0
426
Si102x/3x
31.5. Serial
Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI
Configuration Register (SPI1CFG). The CKPHA bit (SPI1CF
G
.
5) selects one of two clock phases (edge
used to latch the data). The CKPOL bit (SPI1CF
G
.
4) selects between an active-high or active-low clock.
Both CKPOL and CKPHA must be set to zero in order to communicate with the EZRadioPRO peripheral.
The SPI1 Clock Rate Register (SPI1CKR), as shown in SFR Definition 31.3, controls the master mod
serial clock frequency. When the SPI is configured as a master, the maximum data transfer rate (bits/se
is one-half the system clock frequency or 12.5 MHz, whichever is slower.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
t 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (Must Remain High
in Multi-Master Mode)
Figure
.2. Master Mode Data/Clock Timing
427
Rev. 1.0
Si102x/3x
31.6. Using
SPI1 with the DMA
SPI1 is a DMA-enabled peripheral that can provide autonomous data transfers when used with the DMA.
The SPI requires two DMA channels for a bidirectional data transfer and also supports unidirectional data
transfers using a single DMA channel.
There are no additional control bits in the SPI1 control and configuration SFRs. The configuration is the
same in DMA and non-DMA mode. While the SPIF flag and/or SPI interrupts are normally used for no
DMA SPI transfers, a DMA transfer is managed using the DMA enable and DMA full transfer comple
flags.
More information on using the SPI1 peripheral with DMA can be found in the detailed example code for
EZRadioPRO.
31.7. Master
Mode SPI1 DMA Transfers
The SPI interface does not normally have any handshaking or flow control. Therefore, the Master will
transmit all of the output data without waiting on the slave peripheral. The system designer must ensure
that the slave peripheral can accept all of the data at the transfer rate.
31.8. Master
Mode Bidirectional Data Transfer
A bidirectional SPI Master Mode DMA transfer will transmit a specified number of bytes out on the MOSI
pin and receive the same number of bytes on the MISO pin. The MOSI data must be stored in XRAM
before initiating the DMA transfers. The DMA will also transfer all the MISO data to XRAM, overwriting any
data at the target location.
A bidirectional transfer requires two DMA channels. The first DMA channel transfers data from XRAM to
the SPI1DAT SFR and the second DMA channel transf
rs data from the SPI1DAT SFR to XRAM. The sec-
ond channel DMA interrupt indicates SPI transfer com
ion.
The NSS pin is an output, and the hardware does not manage the NSS pin automatically. Firmware should
assert the NSS pin before the SPI transfer a
eassert it upon completion of the transfer.
To
i
nitiate a Master mode Bidirectional data transfer:
1. Configure the SPI1 SFRs norm
lly for Master mode.
a. Enable
Master mode by setting bit 6 in SPI1CF
G
.
b. Configure
the clock polarity (CKPOL = 0) and clock phase (CKPHA = 0) as desired in SPI1CF
G
.
c. Configure
SPI1CKR for the desired SPI clock rate.
d. Configure
3-wire master mode in SPI1CN.
e. Enable
t
PI by setting bit 0 of SPI1CN.
2. Configure the first DMA channel for the XRAM-to-SPI1DATA transfer:
a. D
able the first DMA channel by clearing the corresponding bit in DMA0EN.
Select the first DMA channel by writing to DMA0SEL.
c. Configure
the selected DMA channel to use the XRAM-to-SPI1DAT peripheral request by writing
0x03 to DMA0NC
F
.
d. Write
0 to DMA0NMD to disable wrapping.
e. Write
the address of the first byte of master output (MOSI) data to DMA0NBAH:L.
f. Write
the size of the SPI transfer in bytes to DMA0NSZH:L.
g. Clear
the address offset SFRs CMA0A0H:L.
3. Configure the second DMA channel for the SPI1DAT-to-XRAM transfer:
a. Disable
the second DMA channel by clearing the corresponding bit in DMA0EN.
Rev. 1.0
428
Si102x/3x
b. Select
the second DMA channel by writing to DMA0SEL.
c. Configure
the selected DMA channel to use the SPI1DAT-to-XRAM peripheral request by writing
0x04 to DMA0NC
F
.
d. Enable
DMA interrupts for the second channel by setting bit 7 of DMA0NC
F
.
e. Write
0 to DMA0NMD to disable wrapping.
f. Write
the address for the first byte of master input (MISO) data to DMA0NBAH:L.
g. Write
the size of the SPI transfer in bytes to DMA0NSZH:L.
h. Clear
the address offset SFRs CMA0A0H:L.
i. Enable
the interrupt on the second channel by setting the corresponding bit in DMA
N
T
.
j. Enable
DMA interrupts by setting bit 5 of EIE2.
4. Clear the interrupt bits in DMA0INT for both channels.
5. Enable both channels by setting the corresponding bits in the DMA0EN SFR to initiate the SPI
transfer operation.
6. Wait on the DMA interrupt.
7. Clear the DMA enables in the DMA0EN SFR.
8. Clear the DMA interrupts in the DMA0INT SFR.
429
Rev. 1.0
Si102x/3x
31.9. Master
Mode Unidirectional Data Transfer
A unidirectional SPI master mode DMA transfer will transfer a specified number of bytes out on the MOSI
pin. The MOSI data must be stored in XRAM before initiating the DMA transfers. The SPI1DAT-to-XRAM
peripheral request is not used. Since the DMA does not read the SPI1DAT SFR, the SPI will discard the
MISO data.
A unidirectional transfer only requires one DMA channel to transfer XRAM data to the SPI1DAT SFR. T
DMA interrupt will indicate the completion of the data transfer to the SPI1DAT SFR. When the interrupt
occurs, the DMA has written all of the data to the SPI1DAT SFR, but the SPI has not transmitted the last
byte. Firmware may poll on the SPIBSY bit to determine when the SPI has transmitted the las
yte. Firm-
ware should not deassert the NSS pin until after the SPI has transmitted the last byte.
To
i
nitiate a master mode unidirectional data transfer:
1. Configure the SPI1 SFRs normally for Master mode.
a. Enable
Master mode by setting bit 6 in SPI1CF
G
.
b. Configure
the clock polarity (CKPOL = 0) and clock phase (CKPH
0) as desired in SPI1CF
G
.
c. Configure
SPI1CKR for the desired SPI clock rate.
d. Configure
3-wire master mode in SPI1CN.
e. Enable
the SPI by setting bit 0 of SPI1CN.
2. Configure the desired DMA channel for the XRAM-to-SP
AT transfer.
a. Disable
the desired DMA channel by clearing the corr
sponding bit in DMA0EN.
b. Select
the desired DMA channel by writing to DMA0SEL.
c. Configure
the selected DMA channel to use
XRAM-to-SPI1DAT XRAM peripheral request by
writing 0x03 to DMA0NC
F
.
d. Enable
DMA interrupts for the desir
d channel by setting bit 7 of DMA0NC
F
.
e. Write
0 to DMA0NMD to disable wr
ing.
f. Write
the address for the first byte of master output (MOSI) data to DMA0NBAH:L.
g. Write
the size of the SPI t
sfer in bytes to DMA0NSZH:L.
h. Clear
the address offset SFRs CMA0A0H:L.
i. Enable
the interrup
on the desired channel by setting the corresponding bit in DMA0IN
T
.
j. Enable
DMA in
errupts by setting bit 5 of EIE2.
3. Clear the interrup
bit in DMA0INT for the desired channel.
4. Enable the d
d channel by setting the corresponding bit in the DMA0EN SFR to initiate the SPI
transfer operation.
5. Wait on the DMA interrupt.
6. Clear
he DMA enables in the DMA0EN SFR.
lear the DMA interrupts in the DMA0INT SFR.
8. If desired, wait on the SPIBSY bit in SPI1CFG for the last byte transfer to complete.
31.10. SPI
Special Function Registers
SPI1 is accessed and controlled through four special function registers in the system controller: SPI1CN
Control Register, SPI1DAT Data Register, SPI1CFG Configuration Register, and SPI1CKR Clock Rate
Register. The four special function registers related to the operation of the SPI1 Bus are described in the
following SFR definitions.
Rev. 1.0
430
Si102x/3x
SFR Definition 31.1. SPI1CFG: SPI1 Configuration
Bit
7
6
MSTEN
R/W
0
5
CKPHA
R/W
0
4
CKPOL
R/W
0
3
2
1
0
Name
SPIBSY
Type
R
0
R
0
R
1
R
1
R
1
Reset
SFR Page = 0x2; SFR Address = 0x84
Bit
Name
Function
7
SPIBSY
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6
5
MSTEN
CKPHA
CKPOL
Master Mode Enable.
When set to “1”, enables master mode. This bit must be set to 1 to communicate
with the EZRadioPRO peripheral.
SPI1 Clock Phase.
*
0: Data centered on first edge of SCK period.
1: Data centered on second edge o
SC
eriod.
*
4
SPI1 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3:0
Reserved.
Read = 0111, Write =
t care.
Note:
In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum
settling time for the slave device.
ee
T
a
ble 31.1 for timing parameters.
431
Rev. 1.0
Si102x/3x
SFR Definition 31.2. SPI1CN: SPI1 Control
Bit
7
SPIF
R/W
0
6
WCOL
R/W
0
5
MODF
R/W
0
4
3
2
1
0
SPIEN
R/W
0
Name
Type
Reset
NSSMD[1:0]
R/W
TXBMT
R/W
0
R
1
0
1
SFR Page = 0x2; SFR Address = 0xB0; Bit-Addressable
Bit
Name
Function
7
SPIF
SPI1 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is
t automatically cleared by
hardware, and must be cleared by software.
6
5
4
WCOL
MODF
Write Collision Flag.
This bit is set to logic 1 if a write to SPI1DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI1DAT will be ignored, and the transmit buffer will not be
written. If SPI interrupts are enabled, a
errupt will be generated. This bit is not
automatically cleared by hardware, and
st be cleared by software.
Mode Fault Flag.
This bit is set to logic 1 by har
e when a master mode collision is detected
(NSS is low, MSTEN = 1, a
NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by so
re.
Reserved.
Read = Varies
Write = 0.
3:2 NSSMD[1:0]
Slave Select Mode.
Must be set to 00b. SPI1 can only be used in 3-wire master mode.
Transmit Buffer Empty.
1
TXBMT
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
e set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0
SPIEN
SPI1 Enable.
0: SPI disabled.
1: SPI enabled.
Rev. 1.0
432
Si102x/3x
SFR Definition 31.3. SPI1CKR: SPI1 Clock Rate
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SCR[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0x85
Bit
Name
Function
7:0
SCR[7:0]
SPI1 Clock Rate.
These bits determine the frequency of the SCK output when the SPI1 module is
configured for master mode operation. The SCK clock
equency is a divided ver-
sion of the system clock, and is given in the following
quation, where
SYSCLK
is
the system clock frequency and
SPI1CKR
is the 8-bi
value held in the SPI1CKR
register.
SYSCLK
2
SPI1CKR[7:0] + 1
———————————————————-
=
f
SCK
for 0 <= SPI1CKR <= 255
Example: If SYSCLK = 2 MHz
SPI1CKR = 0x04,
2000000
———————–
–
–
=
f
SCK
2
4 + 1
f
SCK
= 200
kHz
SFR Definition 31.4. SPI1DA
T
:
S
PI1 Data
Bit
7
6
5
4
3
2
1
0
Name
Type
Res
SPI1DAT[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0x86
Bit Name
7:0 SPI1DAT[7:0]
SPI1 Transmit and Receive Data.
Function
The SPI1DAT register is used to transmit and receive SPI1 data. Writing data to
SPI1DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI1DAT returns the contents of the receive buffer.
433
Rev. 1.0
Si102x/3x
SCK*
T
T
MCKL
MCKH
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0.
SCK is the opposite polarity for CKPOL = 1.
Figure 31.3. SPI Master Timing (CKPHA = 0)
Table 31.1. SPI Timing Par
meters
Parameter
Description
Min
Max
Units
Master Mode Timing
(See Figure 31.3)
T
T
T
T
SCK High Time
1 x T
—
—
—
—
ns
ns
ns
ns
MCKH
MCKL
MIS
SYSCLK
SYSCLK
SCK Low Time
1 x T
1 x T
MISO Valid to SCK Shift Edge
SCK Shift Edge to M
O Change
+ 20
SYSCLK
0
MIH
Note:
T
is equal to one per
od of the device system clock (SYSCLK).
SYSCLK
Rev. 1.0
434
Si102x/3x
32. EZRadioPRO
®
240–960 MHz Transceiver
Si102x/3x devices include the EZRadioPRO family of ISM wireless transceivers with continuous frequency
tuning over 240–960 MHz. The wide operating voltage range of 1.8–3.6 V and low current consumption
makes the EZRadioPRO an ideal solution for battery powered applications.
The EZRadioPRO transceiver operates as a time division duplexing (TDD) transceiver where the devi
alternately transmits and receives data packets. The device uses a single-conversion mixer to downco
vert the 2-level FSK/GFSK/OOK modulated receive signal to a low IF frequency. Following a programma-
ble gain amplifier (PGA) the signal is converted to the digital domain by a high performance
ADC
allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in DS
increasing
the receiver’s performance and flexibility versus analog based architectures. The dem
ated signal is
then output to the system MCU through a programmable GPIO or via the standard SPI
reading the
64-byte RX FIFO.
A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmit-
ter and receiver do not operate at the same time. The LO is generated by an integrated VCO and
Frac-
tional-N PLL synthesizer. The synthesizer is designed to support configurabl
data rates, output frequency
and frequency deviation at any frequency between 240–960 MHz. The transmit FSK data is modulated
directly into the
data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted
spectral content.
The PA output power of the Si1020/21/22/23/30/31/32/33 devices can be configured between –1 and
+20 dBm in 3 dB steps, while the PA output power of the S
4/25/26/27/34/35/36/37 devices can be
configured between –8 and +13 dBm in 3 dB steps. The PA is single-ended to allow for easy antenna
matching and low BOM cost. The PA incorporates automatic ramp-up and rampdown control to reduce
unwanted spectral spreading. The devices with +20
output power can also be used to compensate
for the reduced performance of a lower cost, lowe
performance antenna or antenna with size constraints
due to a small form-factor. Competing solutions r
quire large and expensive external PAs to achieve com-
parable performance. The EZRadioPRO tra
eivers support frequency hopping, TX/RX switch control,
and antenna diversity switch control to extend the link range and improve performance.
The EZRadioPRO peripheral also controls three GPIO pins: GPIO_0, GPIO_1, and GPIO_2. See Applica-
tion Note “AN415: EZRadioPRO Pro
ramming Guide“ for details on initializing and using the EZRadioPRO
peripheral.
Rev. 1.0
435
Si102x/3x
32.1. EZRadioPRO
Operating Modes
The EZRadioPRO transceiver provides several operating modes which can be used to optimize the power
consumption for a given application. Depending upon the system communication protocol, an optimal
trade-off between the radio wake time and power consumption can be achieved.
T
a
ble 32.1 summarizes the operating modes of the EZRadioPRO transceiver. In general, any given oper-
ating mode may be classified as an active mode or a power saving mode. The table indicates wh
block(s) are enabled (active) in each corresponding mode. With the exception of the SHUTDOWN mode
all can be dynamically selected by sending the appropriate commands over the SPI. An “X” in any cell
means that, in the given mode of operation, that block can be independently programmed to be either ON
or OF
F
,
w
ithout noticeably impacting the current consumption. The SPI circuit block includes t
SPI inter-
face hardware and the device register space. The 32 kHz OSC block includes the 32.7
z RC oscilla-
tor or 32.768 kHz crystal oscillator and wake-up timer. AUX (Auxiliary Blocks) include
temperature
sensor, general purpose ADC, and low-battery detector.
Table 32.1. EZRadioPRO Operating Modes
Mode
Name
Circuit Blocks
32 kHz OSC
AUX
Digital LDO
SPI
30 MHz
XTAL
PLL
PA
RX
I
VDD
SHUT-
DOWN
OFF (Regis-
ter contents
lost)
OFF
OFF
OFF
F
OFF
OFF OFF
15 nA
STANDBY ON
(Register
ON
ON
ON
ON
ON
ON
OFF
ON
X
X
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF OFF 450
nA
contents
retained)
SLEEP
OFF OFF
OFF OFF
1 µA
1 µA
SENSOR
READY
ON
X
X
OFF OFF 600
µA
OFF OFF 8.5
mA
TUNING
X
X
ON
TRANS-
MIT
X
X
ON
ON
ON
OFF 30
mA*
RECEIVE
ON
X
X
ON
ON
OFF
ON 18.5
mA
Note:
Using Si1024/25/26/27/34/35/36/37 at +13 dBm with recommended reference design. These power modes
are for the E
oPRO peripheral only and are independent of the MCU power modes.
436
Rev. 1.0
Si102x/3x
32.1.1. Operating Mode Control
There are four primary states in the EZRadioPRO transceiver radio state machine: SHUTDOWN, IDLE,
TX, and RX (see Figure 32.1). The SHUTDOWN state completely shuts down the radio to minimize current
consumption. There are five different configurations/options for the IDLE state which can be selected to
optimize the chip for the application. “Register 07h. Operating Mode and Function Control 1” controls
which operating mode/state is selected with the exception of SHUTDOWN which is controlled by the SDN
pin. The TX and RX state may be reached automatically from any of the IDLE states by setting t
txon/rxon bits in “Register 07h. Operating Mode and Function Control 1”.
T
a
ble 32.2 shows each of the
operating modes with the time required to reach either RX or TX mode as well as the current consumption
of each mode.
The transceiver includes a low-power digital regulated supply (LPLDO) which is inter
connected in
parallel to the output of the main digital regulator (and is available externally at the VR_D
). This com-
mon digital supply voltage is connected to all digital circuit blocks including the digital mode
, crystal oscil-
lator, SPI, and register space. The LPLDO has extremely low quiescent current consumption but limited
current supply capability; it is used only in the IDLE-STANDBY and IDLE-SLEEP modes. The main digital
regulator is automatically enabled in all other modes.
SHUTDOWN
DLE*
TX
RX
Five Different Options for IDLE
Figure 32.1. State Machine Diagram
Table 32.2. EZRadioPRO Operating Modes Response Time
te/Mode
Response Time to
Current in State /Mode
[µA]
TX
RX
Shut Down State
16.8 ms
16.8 ms
15 nA
Idle States:
Standby Mode
Sleep Mode
Sensor Mode
Ready Mode
Tune Mode
800 µs
800 µs
800 µs
200 µs
200 µs
800 µs
800 µs
800 µs
200 µs
200 µs
450 nA
1 µA
1 µA
800 µA
8.5 mA
TX State
RX State
NA
200 µs
NA
30 mA @ +13 dBm
18.5 mA
200 µs
Rev. 1.0
437
Si102x/3x
32.1.1.1. SHUTDOWN
State
The SHUTDOWN state is the lowest current consumption state of the device with nominally less than
15 nA of current consumption. The shutdown state may be entered by driving the SDN pin high. The SDN
pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents
of the registers are lost and there is no SPI access.
When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN. Aft
a POR, the device will be in READY mode with the buffers enabled.
32.1.1.1.1. IDLE
State
There are five different modes in the IDLE state which may be selected by “Register 07h. Ope
ing Mode
and Function Control 1″. All modes have a tradeoff between current consumption and
sponse time to
TX/RX mode. This tradeoff is shown in
T
a
ble 32.2. After the POR event, SWRESE
T
,
ing from the
SHUTDOWN state the chip will default to the IDLE-READY mode. After a POR event the i
rrupt registers
must be read to properly enter the SLEE
P
,
S
ENSOR, or STANDBY mode and to control the 32 kHz clock
correctly.
32.1.1.1.2. STANDBY
Mode
STANDBY mode has the lowest current consumption of the five IDLE states with only the LPLDO enabled
to maintain the register values. In this mode the registers can be accessed in both read and write mode.
The STANDBY mode can be entered by writing 0h to “Register 07h. Operating Mode and Function Control
1″. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the
minimum current consumption. Additionally, the ADC should n
e selected as an input to the GPIO in this
mode as it will cause excess current consumption.
32.1.1.1.3. SLEEP
Mode
In SLEEP mode the LPLDO is enabled along with t
ake-Up-Timer, which can be used to accurately
wake-up the radio at specified intervals. See “
.8.6. Wake-Up Timer and 32
kHz Clock Source” on
page 471 for more information on the Wake-U
-Timer. SLEEP mode is entered by setting enwt = 1 (40h) in
“Register 07h. Operating Mode and Function
trol 1″. If an interrupt has occurred (i.e., the nIRQ pin = 0)
the interrupt registers must be read to achieve the minimum current consumption. Also, the ADC should
not be selected as an input to the GPIO in this mode as it will cause excess current consumption.
32.1.1.1.4. SENSOR
Mode
In SENSOR mode either the Low Battery Detector,
T
e
mperature Sensor, or both may be enabled in addi-
tion to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 in
“Register 07h. Operating Mode and Function Control 1”. See “32.8.4.
T
e
mperature Sensor” on page 469
and “32.8.5. Low Battery Detector” on page 471 for more information on these features.
If an interrupt has
occurred (i.e., the n
Q pin = 0) the interrupt registers must be read to achieve the minimum current con-
sumption.
32.1.1.1.5. READY
Mode
READY M
e is designed to give a fast transition time to TX mode with reasonable current consumption.
In th
ode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX mode
by eli
inating the crystal start-up time. READY mode is entered by setting xton = 1 in “Register 07h. Oper-
ating Mode and Function Control 1″.
T
o
a
chieve the lowest current consumption state the crystal oscillator
buffer should be disabled in “Register 62h. Crystal Oscillator Control and
T
e
st.”
T
o
e
xit READY mode,
ufovr (bit 1) of this register must be set back to 0.
32.1.1.1.6. TUNE
Mode
In TUNE mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This
will give the fastest response to TX mode as the PLL will remain locked but it results in the highest current
consumption. This mode of operation is designed for frequency hopping spread spectrum systems
(FHSS). TUNE mode is entered by setting pllon = 1 in “Register 07h. Operating Mode and Function Con-
438
Rev. 1.0
Si102x/3x
trol 1″. It is not necessary to set xton to 1 for this mode, the internal state machine automatically enables
the crystal oscillator.
32.1.1.2. TX
State
The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in “Register 07h.
Operating Mode and Function Control 1″. A built-in sequencer takes care of all the actions required to tran-
sition between states from enabling the crystal oscillator to ramping up the PA. The following sequence
events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit.
1. Enable
the main digital LDO and the Analog LDOs.
2. Start
up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable
PLL.
4. Calibrate
VCO (this action is skipped when the skipvco bit is 1, default value is 0).
5. Wait
until PLL settles to required transmit frequency (controlled by an internal timer).
6. Activate
power amplifier and wait until power ramping is completed (controlled by an internal timer).
7. Transmit
packet.
Steps in this sequence may be eliminated depending on which IDLE mode the chip is configured to prior to
setting the txon bit. By default, the VCO and PLL are calibrated every
ime the PLL is enabled.
32.1.1.3. RX
State
The RX state may be entered from any of the IDLE modes when the rxon bit is set to 1 in “Register 07h.
Operating Mode and Function Control 1″. A built-in sequencer
s care of all the actions required to tran-
sition from one of the IDLE modes to the RX state. The following sequence of events will occur automati-
cally to get the chip into RX mode when going from STANDBY mode to RX mode by setting the rxon bit:
1. Enable
the main digital LDO and the Analog LDOs
2. Start
up crystal oscillator and wait until ready
ontrolled by an internal timer).
3. Enable
PLL.
4. Calibrate
VCO (this action is skipped when the skipvco bit is 1, default value is 0).
5. Wait
until PLL settles to required receive frequency (controlled by an internal timer).
6. Enable
receive circuits: LNA, mix
rs, and ADC.
7. Enable
receive mode in the digital modem.
Depending on the configuration of the radio all or some of the following functions will be performed auto-
matically by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet
handling (optional) including sync word, header check, and CRC.
32.1.1.4. Device
S
s
D7
D6
D5
D4
D3
D2
D1
D0 POR
Def.
Add R/W
Function/
Description
02
R
Device Status
ffovfl ffunfl
rxffem
headerr
freqerr
cps[1] cps[0]
—
The operational status of the EZRadioPRO peripheral can be read from “Register 02h. Device Status”.
Rev. 1.0
439
Si102x/3x
32.2. Interrupts
The EZRadioPRO peripheral is capable of generating an interrupt signal (nIRQ) when certain events
occur. The nIRQ pin is driven low to indicate a pending interrupt request.
The EZRadioPRO interrupt
does not have an internal interrupt vector. To use the interrupt, the nIRQ pin must be looped back
to an external interrupt input.
This interrupt signal will be generated when any one (or more) of the inter-
rupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain lo
until the Interrupt Status Register(s) (Registers 03h–04h) containing the active Interrupt Status bit is rea
The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be
enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h–06h). All
enabled interrupt bits will be cleared when the corresponding interrupt status register is read
the inter-
rupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the status m
stil
be read at
anytime in the Interrupt Status registers.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/
Description
03
04
R
R
Interrupt Status 1
ifferr
itxffafull
itxffaem
irxffafull
irssi
iext ipks
ipkvalid icrcerror
iwut ilb
ichiprdy ipor
—
—
Interrupt Status 2
iswdet ipreaval ipreainval
05 R/W
Interrupt Enable 1
enfferr entxffafull entxffaem enrxffafull
enext enpksent enpkvalid encrcerror
00h
01h
06 R/W
Interrupt Enable 2
enswdet enpreava enpreainval
enrss
nwut enlbd enchiprdy
enpor
See “AN440: EZRadioPRO Detailed Register Descriptions” for a complete list of interrupts.
32.3. System
Timing
The system timing for TX and RX modes is show
in Figures 32.2 and 32.3. The figures demonstrate tran-
sitioning from STANDBY mode to TX or RX
ode through the built-in sequencer of required steps. The
user only needs to program the desired mod
nd the internal sequencer will properly transition the part
from its current mode.
The VCO will automatically calibrate
t every frequency change or power up. The PLL T0 time is to allow
for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting
of 100 µs. The total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 µs. Under certain
applications, the PLL T0 time and the PLL CAL may be skipped for faster turn-around time. Contact appli-
cations support if faster turnaround time is desired.
440
Rev. 1.0
Si102x/3x
XTAL Settling
Time
TX Packet
600us
Figure 32.2. TX Timing
XTAL Settling
Time
RX Packet
600us
Figure 32.3. RX Timing
32.3
Frequency Control
For calculating the necessary frequency register settings it is recommended that customers use Silicon
Labs’ Wireless Design Suite (WDS) or the EZRadioPRO Register Calculator worksheet (in Microsoft
xcel) available on the product website. These methods offer a simple method to quickly determine the
correct settings based on the application requirements. The following information can be used to calcu-
lated these values manually.
32.3.2. Frequency Programming
In order to receive or transmit an RF signal, the desired channel frequency, f
, must be programmed
carrier
into the transceiver. Note that this frequency is the center frequency of the desired channel and not an LO
Rev. 1.0
441
Si102x/3x
frequency. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the ref-
rd
erence frequency and the clock of the (3
order)
∆Σ
modulator. This modulator uses modulo 64000 accu-
mulators. This design was made to obtain the desired frequency resolution of the synthesizer. The overall
division ratio of the feedback loop consist of an integer part (N) and a fractional part (F).In a generic sense,
the output frequency of the synthesizer is as follows:
f
OUT
10
MH
z
(
N
F
)
The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Off-
set (fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fine resolution and high loop band
dth of the
synthesizer, FSK modulation is applied inside the loop and is done by varying F according to t
e incoming
data; this is discussed further in “32.3.5. Frequency Deviation” on page 444. Also, a
ffset can be
added to fine-tune the carrier frequency and counteract crystal tolerance errors. For simpl
assume that
only the fc[15:0] register will determine the fractional component. The equation for selection of the carrier
frequency is shown below:
f
carrier
10
MH
z
(
hbsel
1
)
(
N
F
)
fc
[1
5
:
0
]
f
TX
10
MH
z
*(
hbsel
1
)
*(
fb
[
4
:
0
]
24
)
64000
D7
D6
D5
D
D3
D2
D1
D0 POR
Def.
Add R/W
Function/
Description
73 R/W
74 R/W
Frequency
Offset 1
fo[7]
fo[6]
fo[5]
fo[4]
fo[3]
fo[2]
fo[1] fo[0]
fo[9] fo[8]
fb[1] fb[0]
fc[9] fc[8]
fc[1] fc[0]
00h
00h
35h
BBh
80h
Frequency
Offset 2
75 R/W
Frequency Band
Select
sbsel
fc[14]
fc[6]
hbsel
fc[13]
fc[5]
fb[4]
fc[12]
fc[4]
fb[3]
fc[11]
fc[3]
fb[2]
fc[10]
fc[2]
76 R/W
Nominal Carrier
Frequency 1
fc[15]
fc[7]
77 R/W
Nominal Carrier
Frequency 0
The integer part (N) is de
ermined by fb[4:0]. Additionally, the output frequency can be halved by connect-
ing a ÷2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in “Regis-
ter 75h. Frequency
nd Select”. This effectively partitions the entire 240–960 MHz frequency range into
two separate band
gh Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of
fb[4:0] is from 0 to 23. If a higher value is written into the register, it will default to a value of 23. The integer
part has a fi
d offset of 24 added to it as shown in the formula above.
T
a
ble 32.3 demonstrates the selec-
tion of
b[4:
] for the corresponding frequency band.
After
election of the fb (N) the fractional component may be solved with the following equation:
f
TX
fc
[1
5
:
0
]
fb
[
4
:
0
]
24 *64000
10
MH
z
*(
hbsel
1)
fb and fc are the actual numbers stored in the corresponding registers.
442
Rev. 1.0
Si102x/3x
Table 32.3. Frequency Band Selection
fb[4:0] Value
N
Frequency Band
hbsel=0 hbsel=1
0
1
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
240–249.9 MHz
250–259.9 MHz
260–269.9 MHz
270–279.9 MHz
280–289.9 MHz
290–299.9 MHz
300–309.9 MHz
310–319.9 MHz
320–329.9 MHz
330–339.9 MHz
340–349.9 MHz
350–359.9 M
360–369.9 MHz
370–
9.9 MHz
80–389.9 MHz
390–399.9 MHz
400–409.9 MHz
410–419.9 MHz
420–429.9 MHz
430–439.9 MHz
440–449.9 MHz
450–459.9 MHz
460–469.9 MHz
470–479.9 MHz
480–499.9 MHz
500–519.9 MHz
520–539.9 MHz
540–559.9 MHz
560–579.9 MHz
580–599.9 MHz
600–619.9 MHz
620–
39
9 MHz
640
659.9 MHz
660–679.9 MHz
680–699.9 MHz
700–719.9 MHz
720–739.9 MHz
740–759.9 MHz
760–779.9 MHz
780–799.9 MHz
800–819.9 MHz
820–839.9 MHz
840–859.9 MHz
860–879.9 MHz
880–899.9 MHz
900–919.9 MHz
920–939.9 MHz
940–960 MHz
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
22
23
The
hip will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to
achieve the correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in
the RX Mixing architecture; therefore, no frequency reprogramming is required when using the same TX
equency and switching between RX/TX modes.
32.3.3. Easy Frequency Programming for FHSS
While Registers 73h–77h may be used to program the carrier frequency of the transceiver, it is often easier
to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also,
there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is
desirable to change frequency by programming a single register. Once the channel step size is set, the fre-
Rev. 1.0
443
Si102x/3x
quency may be changed by a single register corresponding to the channel number. A nominal frequency is
first set using Registers 73h–77h, as described above. Registers 79h and 7Ah are then used to set a chan-
nel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size
(fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency
Hopping Channel Select Register then selects channels based on multiples of the step size.
F
carrier
Fnom
fhs
[7
:
0
]
(
fhch
[7
:
0
]
10
kHz
)
For example: if the nominal frequency is set to 900 MHz using Registers 73h–77h and the channel step
size is set to 1 MHz using “Register 7Ah. Frequency Hopping Step Size”. For example, if th
“Register
79h. Frequency Hopping Channel Select” is set to 5d, the resulting carrier frequency wo
ld b
905 MHz.
Once the nominal frequency and channel step size are programmed in the registers, it i
necessary to
program the fhch[7:0] register in order to change the frequency.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
79 R/W
Frequency Hopping
fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0]
Channel Select
00h
00h
7A R/W Frequency
Hopping fhs[7]
Step Size
fhs[6]
fhs[5]
fhs[4]
hs[3]
fhs[2]
fhs[1]
fhs[0]
32.3.4. Automatic State Transition for Frequency Change
If registers 79h or 7Ah are changed in either TX or RX
ode, the state machine will automatically transition
the chip back to TUNE, change the frequency, and a
atically go back to either TX or RX. This feature
is useful to reduce the number of SPI command
equired in a Frequency Hopping System. This in turn
reduces microcontroller activity, reducing cur
ent consumption. The exception to this is during TX FIFO
mode. If a frequency change is initiated du
a TX packet, then the part will complete the current TX
packet and will only change the frequency for subsequent packets.
32.3.5. Frequency Deviation
The peak frequency deviation is configurable from ±0.625 to ±320 kHz. The Frequency Deviation (
∆
f) is
controlled by the Frequency Deviation Register (fd), address 71 and 72h, and is independent of the carrier
frequency setting. When enabled, regardless of the setting of the hbsel bit (high band or low band), the
resolution of the frequency deviation will remain in increments of 625 Hz. When using frequency modula-
tion the carrier frequency will deviate from the nominal center channel carrier frequency by ±
∆
f:
f
fd
[
8
:
0
]
625
Hz
f
fd
[8 : 0]
f = peak
deviation
625
Hz
444
Rev. 1.0
Si102x/3x
f
f
carrier
Time
Figure 32.4. Frequency Deviation
The previous equation should be used to calculate the desired frequency deviation. If desired, frequency
modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center fre-
quency; see “32.4.1. Modulation Type” on page 447 for furthe
ails.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
71 R/W Modulation
Mode trclk[1]
trclk[0] dtm
d[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0]
Control 2
00h
20h
72 R/W
Frequency Devia-
fd[7]
tion
fd[6]
fd[5]
fd[4]
fd[3] fd[2]
fd[1]
fd[0]
32.3.6. Frequency Offset Adjustment
When the AFC is disabled the frequency offset can be adjusted manually by fo[9:0] in registers 73h and
74h. It is not possible to have both AFC and offset as internally they share the same register. The fre-
quency offset adjustment and the AFC both are implemented by shifting the Synthesizer Local Oscillator
frequency. This register is a signed register so in order to get a negative offset it is necessary to take the
twos complement
positive offset number. The offset can be calculated by the following:
DesiredOffset
156.25
H
z
(
hbsel
1
)
fo
[
9
:
0
]
DesiredOffset
fo
[
9
:
0
]
156.25
H
z
(
hbsel
1)
The adjustment range in high band is ±160 kHz and in low band it is ±80 kHz. For example to compute an
offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of –50 kHz in high band
mode the fo[9:0] register should be set to 360h.
Rev. 1.0
445
Si102x/3x
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/
Description
73 R/W Frequency
Offset
74 R/W Frequency
Offset
fo[7]
fo[6]
fo[5]
fo[4]
fo[3]
fo[2]
fo[1] fo[0]
fo[9] fo[8]
00h
00h
32.3.7. Automatic Frequency Control (AFC)
All AFC settings can be easily obtained from the settings calculator. This is the recommended method to
program all AFC settings. This section is intended to describe the operation of the AFC in more detail to
help understand the trade-offs of using AFC.The receiver supports automatic frequency con
l (AFC) to
compensate for frequency differences between the transmitter and receiver reference f
ncies. These
differences can be caused by the absolute accuracy and temperature dependencies of t
erence crys-
tals. Due to frequency offset compensation in the modem, the receiver is tolerant to frequency offsets up to
0.25 times the IF bandwidth when the AFC is disabled. When the AFC is enabled, the received signal will
be centered in the pass-band of the IF filter, providing optimal sensitivity and selectivity over a wider range
of frequency offsets up to 0.35 times the IF bandwidth. The trade-off of rec
er sensitivity (at 1% PER)
versus carrier offset and the impact of AFC are illustrated in Figure 32.5.
Figure 32.5. Sensitivity at 1% PER vs. Carrier Frequency Offset
When AFC
s enabled, the preamble length needs to be long enough to settle the AFC. In general, one
byte
reamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened
from
0 bits to 32 bits. Note that with the AFC disabled, the preamble length must still be long enough to
settle the receiver and to detect the preamble (see “32.6.7. Preamble Length” on page 463). The AFC cor-
rects the detected frequency offset by changing the frequency of the Fractional-N PLL. When the preamble
detected, the AFC will freeze for the remainder of the packet. In multi-packet mode the AFC is reset at
the end of every packet and will re-acquire the frequency offset for the next packet. The AFC loop includes
a bandwidth limiting mechanism improving the rejection of out of band signals. When the AFC loop is
enabled, its pull-in-range is determined by the bandwidth limiter value (AFCLimiter) which is located in reg-
ister 2Ah.
AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
446
Rev. 1.0
Si102x/3x
The AFC Limiter register is an unsigned register and its value can be obtained from the EZRadioPRO Reg-
ister Calculator spreadsheet.
The amount of error correction feedback to the Fractional-N PLL before the preamble is detected is con-
trolled from afcgearh[2:0]. The default value 000 relates to a feedback of 100% from the measured fre-
quency error and is advised for most applications. Every bit added will half the feedback but will require a
longer preamble to settle.
The AFC operates as follows. The frequency error of the incoming signal is measured over a period of tw
bit times, after which it corrects the local oscillator via the Fractional-N PLL. After this correction, some time
is allowed to settle the Fractional-N PLL to the new frequency before the next frequency error is measured.
The duration of the AFC cycle before the preamble is detected can be programmed with shw
it[2:0]. It is
advised to use the default value 001, which sets the AFC cycle to 4 bit times (2 for mea
ent and 2 for
settling). If shwait[2:0] is programmed to 3’b000, there is no AFC correction output. It is
ed to use the
default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for settling).
The AFC correction value may be read from register 2Bh. The value read can be converted to kHz with the
following formula:
AFC Correction = 156.25Hz x (hbsel +1) x afc_corr[7: 0]
Frequency Correction
RX
Freq Offset Register
eq Offset Register
AFC Freq
Offset Register
TX
AFC disabled
AFC enabled
32.3.8. TX Data Rate Generator
The data rate is configurable between 0.123–256
bps. For data rates below 30 kbps the ”txdtrtscale” bit in
register 70h should be set to 1. When higher
ta rates are used this bit should be set to 0
.
The TX date rate is determined by the following formula in bps:
txdr
15:0
1 MHz
———————————————–
–
–
2
16 + 5
txdtrtscale
DR_TX (bps)
=
DR_TX(bps)
2
16 + 5
txdtrtscale
——————————————————————————–
txdr[15:0] =
1 MHz
For data rates high
an 100 kbps, Register 58h should be changed from its default of 80h to C0h. Non-
optimal modulation and increased eye closure will result if this setting is not made for data rates higher
than 100 kbps. The txdr register is only applicable to TX mode and does not need to be programmed for
RX mode.
e RX bandwidth which is partly determined from the data rate is programmed separately.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
6E R/W
TX Data Rate 1
txdr[15] txdr[14]
txdr[13] txdr[12]
txdr[11] txdr[10] txdr[9] txdr[8]
0Ah
3Dh
6F R/W
TX Data Rate 0
txdr[7]
txdr[6] txdr[5] txdr[4]
txdr[3]
txdr[2] txdr[1]
txdr[0]
32.4. Modulation
Options
32.4.1. Modulation Type
Rev. 1.0
447
Si102x/3x
The EZRadioPRO transceivers support three different modulation options: Gaussian Frequency Shift Key-
ing (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modu-
lation type as it provides the best performance and cleanest modulation spectrum. Figure
32.6
demonstrates the difference between FSK and GFSK for a Data Rate of 64 kbps. The time domain plots
demonstrate the effects of the Gaussian filtering. The frequency domain plots demonstrate the spectral
benefit of GFSK over FSK. The type of modulation is selected with the modtyp[1:0] bits in “Register 71h.
Modulation Mode Control 2″. Note that it is also possible to obtain an unmodulated carrier signal by setti
modtyp[1:0] = 00.
modtyp[1:0]
Modulation Source
00
01
10
11
Unmodulated Carrier
OOK
FSK
GFSK (enable TX Data CLK when direct mo
is used)
TX Modulation Time Domain Waveforms — FSK vs. GFSK
1.5
TX Modulation Spectrum — FSK vs GFSK (Continuous PRBS)
-20
1.0
0.5
-40
-60
0.0
-0.5
-1.0
-100
-20
-1.5
1.0
-40
-60
0.5
0.0
-80
-0.5
-1.0
-100
-250 -200 -150 -100
-50
0
50
100
150
200
250
0
50
100 150 200 250 300 350 400 450 500
t
me, usec
freq, KHz
DataRate
64000.0
TxDev
BT_Filter
0.5
ModIndex
1.0
32000.0
Figure 32.6. FSK vs. GFSK Spectrums
32.4.2. Mo
ulation Data Source
The
nsceiver may be configured to obtain its modulation data from one of three different sources: FIFO
mode, Direct Mode, and from a PN9 mode. In Direct Mode, the TX modulation data may be obtained from
several different input pins. These options are set through the dtmod[1:0] field in “Register 71h. Modulation
Mode Control 2″.
448
Rev. 1.0
Si102x/3x
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
71 R/W
Modulation
Mode
trclk[1] trclk[0] dtmod[1] dtmod[0] eninv
fd[8] modtyp[1] modtyp[0]
00h
Control 2
dtmod[1:0]
Data Source
00
01
10
11
Direct Mode using TX/RX Data via GPIO pin (GPIO configuration required)
Direct Mode using TX/RX Data via SDI pin (only when nSEL is high)
FIFO Mode
PN9 (internally generated)
32.4.2.1. FIFO
Mode
In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The FIFOs are
accessed via “Register 7Fh. FIFO Access,” and are most efficiently accessed with burst read/write opera-
tion.
In TX mode, the data bytes stored in FIFO memory are “packaged” together with other fields and bytes of
information to construct the final transmit packet structure
Th
other potential fields include the Pream-
ble, Sync word, Header, CRC checksum, etc. The configuration of the packet structure in TX mode is
determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler
Registers (see
T
a
ble 32.4 on page 462). If the Auto
c Packet Handler is disabled, the entire desired
packet structure should be loaded into FIFO mem
y; no other fields (such as Preamble or Sync word are
automatically added to the bytes stored in FIFO memory). For further information on the configuration of
the FIFOs for a specific application or pac
size, see “32.6. Data Handling and Packet Handler” on
page 458.
In RX mode, only the bytes of the received packet structure that are considered to be “data bytes” are
stored in FIFO memory. Which byte
of
he received packet are considered “data bytes” is determined by
the Automatic Packet Handler (if enabled), in conjunction with the Packet Handler Registers (see
T
a
ble 32.4 on page 462). If the Automatic Packet Handler is disabled, all bytes following the Sync word are
considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation
is not desired, the preamble detection threshold and Sync word still need to be programmed so that the RX
Modem knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the
received data may
be observed directly (in real-time) by properly programming a GPIO pin as the
RXDATA output pin; this can be quite useful during application development.
When in FI
mode, the chip will automatically exit the TX or RX State when either the ipksent or ipkvalid
interru
t oc
urs. The chip will return to the IDLE mode state programmed in “Register 07h. Operating
Mo
nd Function Control 1″. For example, the chip may be placed into TX mode by setting the txon bit,
but wi
h the pllon bit additionally set. The chip will transmit all of the contents of the FIFO and the ipksent
interrupt will occur. When this interrupt event occurs, the chip will clear the txon bit and return to TUNE
mode, as indicated by the set state of the pllon bit. If no other bits are additionally set in register 07h
besides txon initially), then the chip will return to the STANDBY state.
In RX mode, the rxon bit will be cleared if ipkvalid occurs and the rxmpk bit (RX Multi-Packet bit, SPI Reg-
ister 08h bit [4]) is not set. When the rxmpk bit is set, the part will not exit the RX state after successfully
receiving a packet, but will remain in RX mode. The microcontroller will need to decide on the appropriate
subsequent action, depending upon information such as an interrupt generated by CRC, packet valid, or
preamble detect.
Rev. 1.0
449
Si102x/3x
32.4.2.2. Direct
Mode
For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be
desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely.
In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in “real
time” (i.e., not stored in a register for transmission at a later time). A variety of pins may be configured for
use as the TX Data input function.
Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is
desired (only the TX Data input pin is required for FSK). Two options for the source of the TX Data are
available in the dtmod[1:0] field, and various configurations for the source of the TX Data Clo
k may be
selected through the trclk[1:0] field.
trclk[1:0]
TX/RX Data Clock Configuration
No TX Clock (only for FSK)
00
01
10
11
TX/RX Data Clock is available via GPIO (GPIO needs programming accordingly as well)
TX/RX Data Clock is available via SDO pin (only when nSE
s high)
TX/RX Data Clock is available via the nIRQ pin
The eninv bit in SPI Register 71h will invert the TX Data; this is most likely useful for diagnostic and testing
purposes.
In RX direct mode, the RX Data and RX Clock can be progr
ed for direct (real-time) output to GPIO
pins. The microcontroller may then process the RX data without using the FIFO or packet handler functions
of the RFIC. In RX direct mode, the chip must still acqu
re bit timing during the Preamble, and thus the pre-
amble detection threshold (SPI Register 35h) must s
e programmed. Once the preamble is detected,
certain bit timing functions within the RX Modem
hange their operation for optimized performance over
the remainder of the packet. It is not required that a Sync word be present in the packet in RX Direct mode;
however, if the Sync word is absent then the
yn bit in SPI Register 33h must be set, or else the bit tim-
ing and tracking function within the RX Modem will not be configured for optimum performance.
32.4.2.3. Direct
Synchronous Mod
In TX direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. In
direct synchronous mode, the RFIC is configured to provide a TX Clock signal as an output to the external
device that is providing the TX Data stream. This TX Clock signal is a square wave with a frequency equal
to the programmed data rate. The external modulation source (e.g., MCU) must accept this TX Clock sig-
nal as an input and respond by providing one bit of TX Data back to the RFIC, synchronous with one edge
of the TX Clock sign
. In this fashion, the rate of the TX Data input stream from the external source is con-
trolled by the progr
med data rate of the RFIC; no TX Data bits are made available at the input of the
RFIC until requested by another cycle of the TX Clock signal. The TX Data bits supplied by the external
source are t
nsmitted directly in real-time (i.e., not stored internally for later transmission).
All m
lation types (FSK/GFSK/OOK) are valid in TX direct synchronous mode. As will be discussed in
the n
xt section, there are limits on modulation types in TX direct asynchronous mode.
32.4.2.4. Direct
Asynchronous Mode
In TX direct asynchronous mode, the RFIC no longer controls the data rate of the TX Data input stream.
nstead, the data rate is controlled only by the external TX Data source; the RFIC simply accepts the data
applied to its TX Data input pin, at whatever rate it is supplied. This means that there is no longer a need
for a TX Clock output signal from the RFIC, as there is no synchronous “handshaking” between the RFIC
and the external data source. The TX Data bits supplied by the external source are transmitted directly in
real-time (i.e., not stored internally for later transmission).
450
Rev. 1.0
Si102x/3x
It is not necessary to program the data rate parameter when operating in TX direct asynchronous mode.
The chip still internally samples the incoming TX Data stream to determine when edge transitions occur;
however, rather than sampling the data at a pre-programmed data rate, the chip now internally samples
the incoming TX Data stream at its maximum possible oversampling rate. This allows the chip to accu-
rately determine the timing of the bit edge transitions without prior knowledge of the data rate. (Of course,
it is still necessary to program the desired peak frequency deviation.)
Only FSK and OOK modulation types are valid in TX Direct Asynchronous Mode; GFSK modulation is n
available in asynchronous mode. This is because the RFIC does not have knowledge of the supplied data
rate, and thus cannot determine the appropriate Gaussian lowpass filter function to apply to the incoming
data.
VDD_DIG
Px.x
VDD_RF
TX
Direct synchronous modulation. Full
control over the serial interface
g
interrupt. Bitrate clock and m
tion
via GPIO’s.
RXp
RXn
NC
Px.x
Matching
GPIO configuration
GP1 : TX DATA clock output
GP2 : T
DATA input
DataCLK
MOD(Data)
Figure 32.7. Direc
ynchronous Mode Example
Direct asynchronous FSK modulation.
Modulation data via GPIO2, no data
clock needed in this mode.
VDD_DIG
Px.x
VDD_RF
TX
RXp
RXn
NC
Match
g
GPIO configuration
GP2 : TX DATA input
MOD(Data)
Figure 32.8. Direct Asynchronous Mode Example
Rev. 1.0
451
Si102x/3x
32.4.2.5. Direct
Mode using SPI or nIRQ Pins
It is possible to use the EZRadioPRO serial interface signals and nIRQ as the modulation clock and data.
The MISO signal can be configured to be the data clock by programming trclk = 10. If the NSS signal is
LOW then the function of the MISO signal will be SPI data output. If the NSS signal is high and trclk[1:0] is
10 then during RX and TX modes the data clock will be available on the MISO signal. If trclk[1:0] is set to
11 and no interrupts are enabled in registers 05 or 06h, then the nIRQ pin can also be used as the TX/RX
data clock.
Note: The MISO and NSS signals are internal connections. The nIRQ signal is accessed through an
external package pin.
The MOSI signal can be configured to be the data source in both RX and TX modes if dtmod[
:0] = 01. In
a similar fashion, if NSS is LOW the MOSI signal will function as SPI data-in. If NSS
H then in TX
mode it will be the data to be modulated and transmitted. In RX mode it will be the recei
demodulated
data. Figure 32.9 demonstrates using MOSI and MISO as the TX/RX data and clock:
TX on
command
TX off
command
RX on
command
R
X
o
ff
command
TX mode
RX mode
NSS
SPI input
don’t care
don’t care
SPI input
MOD
i
nput
SPI in
u
t
re
don’t care
SPI input
Data output
SPI input
MOSI
MSIO
Data CLK
Output
Data CLK
Output
SPI output
SPI output
SPI output
SPI output
SPI output
Figure 32.9. Micr
controller Connections
If the MISO pin is not used for data clock then it may be programmed to be the interrupt function (nIRQ) by
programming Register 0Eh bit 3.
32.4.3. PN9 Mode
In this mode the TX data is generated internally using a pseudo-random (PN9 sequence) bit generator.
The primary purpose of this mode is for use as a test mode to observe the modulated spectrum without
having to provide data.
32.5. Internal
Functional Blocks
This section provid
n overview some of the key blocks of the internal radio architecture.
32.5.1. RX LNA
Depending
n the part, the input frequency range for the LNA is between 240–960 MHz. The LNA provides
gain
a noise figure low enough to suppress the noise of the following stages. The LNA has one step of
gain
ontrol which is controlled by the analog gain control (AGC) algorithm. The AGC algorithm adjusts the
gain of the LNA and PGA so the receiver can handle signal levels from sensitivity to +5 dBm with optimal
performance.
the Si1024/25/26/27/34/35/36/37, the TX and RX may be tied directly. See the TX/RX direct-tie refer-
power must be set.
452
Rev. 1.0
Si102x/3x
32.5.1.1. RX
I-Q Mixer
The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented
as an I-Q mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer
consists of two double-balanced mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs
are driven in quadrature, and separate I and Q Intermediate Frequency (IF) outputs drive the programma-
ble gain amplifier. The receive LO signal is supplied by an integrated VCO and PLL synthesizer operating
between 240–960 MHz. The necessary quadrature LO signals are derived from the divider at the VCO o
put.
32.5.2. Programmable Gain Amplifier
The programmable gain amplifier (PGA) provides the necessary gain to boost the signal l
el
nto the
dynamic range of the ADC. The PGA must also have enough gain switching to allow for
input signals
to ensure a linear RSSI range up to –20 dBm. The PGA has steps of 3 dB which are cont
by the AGC
algorithm in the digital modem.
32.5.2.1. ADC
The amplified IQ IF signals are digitized using an Analog-to-Digital Converte
ADC), which allows for low
current consumption and high dynamic range. The bandpass response of t
e ADC provides exceptional
rejection of out of band blockers.
32.5.3. Digital Modem
Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed
in the digital domain, resulting in reduced area while increasi
xibility. The digital modem performs the
following functions:
Channel selection filter
TX modulation
RX demodulation
AGC
Preamble detector
Invalid preamble detector
Radio signal strength indicator (R
SI)
Automatic frequency compensation (AFC)
®
Packet handling including EZMAC
features
Cyclic redundancy check (CRC)
The digital channel filter and demodulator are optimized for ultra low power consumption and are highly
configurable. Supp
d modulation types are GFSK, FSK, and OOK. The channel filter can be configured
to support bandwid
ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported
ranging from 0.123 up to 256 kbps. The AGC algorithm is implemented digitally using an advanced control
loop optimi
for fast response time.
The
igurable preamble detector is used to improve the reliability of the sync-word detection. The sync-
word
etector is only enabled when a valid preamble is detected, significantly reducing the probability of
false detection.
The received signal strength indicator (RSSI) provides a measure of the signal strength received on the
ned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel
power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT)
functionality.
Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital auto-
matic frequency control (AFC) in receive mode.
Rev. 1.0
453
Si102x/3x
A comprehensive programmable packet handler including key features of Silicon Labs’ EZMAC is inte-
grated to create a variety of communication topologies ranging from peer-to-peer networks to mesh net-
works. The extensive programmability of the packet header allows for advanced packet filtering which in
turn enables a mix of broadcast, group, and point-to-point communication.
A wireless communication channel can be corrupted by noise and interference, and it is therefore import-
ant to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect th
presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transm
ted packet and verified by the receiver to confirm that no errors have occurred. The packet handler and
CRC can significantly reduce the load on the microcontroller reducing the overall current consumption.
The digital modem includes the TX modulator which converts the TX data bits into the co
esponding
stream of digital modulation values to be summed with the fractional input to the sigm
ta modulator.
This modulation approach results in highly accurate resolution of the frequency deviation
aussian filter
is implemented to support GFSK, considerably reducing the energy in the adjacent channels. The default
bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be adjusted to other values.
32.5.4. Synthesizer
An integrated Sigma Delta (
Σ∆
) Fractional-N PLL synthesizer capable of op
rat
ng from 240–960 MHz is
provided on-chip. Using a
Σ∆
synthesizer has many advantages; it provides flexibility in choosing data
rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the
loop in the digital domain through the fractional divider which results in very precise accuracy and control
over the transmit deviation.
Depending on the part, the PLL and
–
modulator scheme is
signed to support any desired frequency
and channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band)
or 312.5 Hz (High band). The transmit data rate can
e programmed between 0.123–256 kbps, and the
frequency deviation can be programmed between ±
20 kHz. These parameters may be adjusted via
registers as shown in “32.3.1. Frequency Control
n page 441.
TX
Selectable
Divider
Fref = 10 M
PFD
CP
LPF
RX
VCO
N
TX
Modulation
Delta-
Sigma
Figure 32.10. PLL Synthesizer Block Diagram
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-
hip inductors. The output of the VCO is followed by a configurable divider which will divide down the sig-
nal to the desired output frequency band. The modulus of the variable divide-by-N divider stage is con-
trolled dynamically by the output from the
–
modulator. The tuning resolution is sufficient to tune to the
commanded frequency with a maximum accuracy of 312.5
Hz anywhere in the range between 240–
960 MHz.
454
Rev. 1.0
Si102x/3x
32.5.4.1. VCO
The output of the VCO is automatically divided down to the correct output frequency depending on the
hbsel and fb[4:0] fields in “Register 75h. Frequency Band Select”. In receive mode, the LO frequency is
automatically shifted downwards by the IF frequency of 937.5 kHz, allowing transmit and receive operation
on the same frequency. The VCO integrates the resonator inductor and tuning varactor, so no external
VCO components are required.
The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank w
automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this
might not be desirable so the VCO calibration may be skipped by setting the appropriate register.
32.5.4.2. Power
Amplifier
The Si1020/21/22/23/30/31/32/33 devices have an internal integrated power amplifi
) capable of
transmitting at output levels between +1 and +20 dBm. The Si1024/25/26/27/34/35/36/37
evices have a
PA which is capable of transmitting output levels between –8 to +13 dBm. The PA design is single-ended
and is implemented as a two stage class CE amplifier with a high efficiency when tran
mitting at maximum
power. The PA efficiency can only be optimized at one power level. Changing the output power by adjust-
ing txpow[2:0] will scale both the output power and current but the efficiency
ill not remain constant. The
PA output is ramped up and down to prevent unwanted spectral splatter.
With the Si1024/25/26/27/34/35/36/37 devices, the TX and RX may be tied directly. See the TX/RX direct-
tie reference design available on the
Silicon Labs website
for more details. When the direct tie is used, the
lna_sw bit in Register 6Dh, TX Power must be set to 1.
Rev. 1.0
455
Si102x/3x
32.5.4.3. Output
Power Selection
The output power is configurable in 3 dB steps with the txpow[2:0] field in “Register 6Dh. TX Power”. Extra
output power can allow the use of a cheaper smaller antenna, greatly reducing the overall BOM cost. The
higher power setting of the chip achieves maximum possible range, but of course comes at the cost of
higher TX current consumption. However, depending on the duty cycle of the system, the effect on battery
life may be insignificant.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/
Description
6D R/W
TX Power
reserved reserved reserved reserved lna_sw txpow[2]
txpow[1] tx
ow[0] 18h
txpow[2:0]
000
Si10x0/1 Output Power
+1 dBm
001
+2 dBm
010
+5 dBm
011
+8 dBm
100
+11 dBm
101
+14 dBm
110
+17 dBm
111
+20
m
txpow[2:0]
S
x2/3/4/5 Output
Power
000
001
010
011
00
101
110
111
–8 dBm
–5 dBm
–2 dBm
+1 dBm
+4 dBm
+7 dBm
+10 dBm
+13 dBm
456
Rev. 1.0
Si102x/3x
32.5.5. Crystal Oscillator
The transceiver includes an integrated 30
MHz crystal oscillator with a fast start-up time of less than
600 µs when a suitable parallel resonant crystal is used. The design is differential with the required crystal
load capacitance integrated on-chip to minimize the number of external components. By default, all that is
required off-chip is the 30 MHz crystal.
The crystal load capacitance can be digitally programmed to accommodate crystals with various loa
capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal lo
capacitance is programmed through the xlc[6:0] field of “Register 09h. 30 MHz Crystal Oscillator Load
Capacitance”. The total internal capacitance is 12.5
pF and is adjustable in approximately 127 steps
(97fF/step). The xtalshift bit provides a coarse shift in frequency but is not binary with xlc[6:0].
The crystal frequency adjustment can be used to compensate for crystal production
ces. Utilizing
the on-chip temperature sensor and suitable control software, the temperature depende
of the crystal
can be canceled.
The typical value of the total on-chip capacitance Cint can be calculated as follows:
Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift
Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by
the crystal can be calculated by adding the sum of all ext
rna
asitic PCB capacitances Cext to Cint. If
the maximum value of Cint (16.3
pF) is not sufficient, an external capacitor can be added for exact tuning.
Additional information on calculating Cext and crystal selection guidelines is provided in “AN417: Si4x3x
Family Crystal Oscillator.”
If AFC is disabled then the synthesizer frequenc
ay be further adjusted by programming the Frequency
Offset field fo[9:0]in “Register 73h. Frequenc
Offset 1″ and “Register 74h. Frequency Offset 2”, as dis-
cussed in “32.3.1. Frequency Control” on pa
1.
The crystal oscillator frequency is divided down internally and may be output to the microcontroller through
one of the GPIO pins for use as the
stem Clock. In this fashion, only one crystal oscillator is required for
the entire system and the BOM cost is reduced. The available clock frequencies and GPIO configuration
are discussed further in “32.8.2. Output Clock” on page 467.
The transceiver may also be driven with an external 30 MHz clock signal through the XOUT pin. When
driving with an external reference or using a TCXO, the XTAL load capacitance register should be set to 0.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Functi
escription
09 R/W
rystal Oscillator Load
Capacitance
xtalshift xlc[6]
xlc[5]
xlc[4]
xlc[3]
xlc[2]
xlc[1] xlc[0]
7Fh
32.5.6. Regulators
There are a total of six regulators integrated onto the transceiver. With the exception of the digital regulator,
ll regulators are designed to operate with only internal decoupling. The digital regulator requires an exter-
al 1
µ
F decoupling capacitor. All regulators are designed to operate with an input supply voltage from
+1.8 to +3.6 V. The output stage of the of PA is not connected internally to a regulator and is connected
directly to the battery voltage.
A supply voltage should only be connected to the VDD pins. No voltage should be forced on the digital reg-
ulator output.
Rev. 1.0
457
Si102x/3x
32.6. Data
Handling and Packet Handler
The internal modem is designed to operate with a packet including a 010101… preamble structure.
T
o
c
on-
figure the modem to operate with packet formats without a preamble or other legacy packet structures con-
tact customer support.
32.6.1. RX and TX FIFOs
Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 32.
“Register 7Fh. FIFO Access” is used to access both FIFOs. A burst write to address 7Fh will write data to
the TX FIFO. A burst read from address 7Fh will read data from the RX FIFO.
TX FIFO
RX FIFO
RX F
FO Almost Full
Threshold
TX FIFO Almost Full
Threshold
TX FIFO Almost Empty
Threshold
Figure 32
1. FIFO Thresholds
The TX FIFO has two programmabl
hresholds. An interrupt event occurs when the data in the TX FIFO
reaches these thresholds. The first threshold is the FIFO almost full threshold, txafthr[5:0]. The value in this
register corresponds to the desired threshold value in number of bytes. When the data being filled into the
TX FIFO crosses this threshold limit, an interrupt to the microcontroller is generated so the chip can enter
TX mode to transmit the contents of the TX FIFO. The second threshold for TX is the FIFO almost empty
threshold, txaethr[5:0]. When the data being shifted out of the TX FIFO drops below the almost empty
threshold an interr
t will be generated. If more data is not loaded into the FIFO then the chip
automatically exits
TX State after the ipksent interrupt occurs. The chip will return to the mode selected
by the remaining bits in SPI Register 07h. For example, the chip may be placed into TX mode by setting
the txon bit,
ut with the xton bit additionally set. For this condition, the chip will transmit all of the contents
of the
IFO and the ipksent interrupt will occur. When this interrupt event occurs, the chip will clear the txon
bit
eturn to READY mode, as indicated by the set state of the xton bit. If the pllon bit D1 is set when
entering TX mode (i.e., SPI Register 07h = 0Ah), the chip will exit from TX mode after sending the packet
and return to TUNE mode.
However, the chip will not automatically return to STANDBY mode upon exit from the TX state, in the event
he TX packet is initiated by setting SPI Register 07h = 08h (i.e., setting only txon bit D3). The chip will
instead return to READY mode, with the crystal oscillator remaining enabled. This is intentional; the sys-
tem may be configured such that the host MCU derives its clock from the MCU_CLK output of the RFIC
(through GPIO2), and this clock signal must not be shut down without allowing the host MCU time to pro-
cess any interrupt signals that may have occurred. The host MCU must subsequently perform a WRITE to
SPI Register 07h = 00h to enter STANDBY mode and obtain minimum current consumption.
458
Rev. 1.0
Si102x/3x
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/
Description
08 R/W Operating
&
Function
antdiv[2] antdiv[1]
antdiv[0]
rxmpk
autotx
enldm
ffclrrx
ffclrtx
00h
Control 2
7C R/W
7D R/W
TX FIFO
Control 1
Reserved Reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0]
Reserved Reserved
txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0]
04h
TX FIFO
Control 2
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold,
r[5:0]. When
the incoming RX data crosses the Almost Full Threshold an interrupt will be generated to t
microcontrol-
ler via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.
D7
D6
D5
D4
D3
D1
D0
POR
Def.
Add R/W
Function/
Description
7E R/W
RX FIFO
Control
Reserved Reserved rxafthr[5]
rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0]
37h
Both the TX and RX FIFOs may be cleared or reset with the
rtx and ffclrrx bits. All interrupts may be
enabled by setting the Interrupt Enabled bits in “Register 05h. I
rrupt Enable 1″ and “Register 06h. Inter-
rupt Enable 2.” If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin
but the bits will still be read correctly in the Interrupt S
us registers.
32.6.2. Packet Configuration
When using the FIFOs, automatic packet han
ling may be enabled for TX mode, RX mode, or both. “Reg-
ister 30h. Data Access Control” through “Re
4Bh. Received Packet Length” control the configuration,
status, and decoded RX packet data for Packet Handling. The usual fields for network communication
(such as preamble, synchronization word, headers, packet length, and CRC) can be configured to be auto-
matically added to the data payload
he fields needed for packet generation normally change infrequently
and can therefore be stored in registers. Automatically adding these fields to the data payload greatly
reduces the amount of communication between the microcontroller and the transceiver.
The general packet structure is shown in Figure 32.12. The length of each field is shown below the field.
The preamble pattern is always a series of alternating ones and zeros, starting with a zero. All the fields
have programmable lengths to accommodate different applications. The most common CRC polynominals
are available for se
on.
Data
CRC
Preamble
1-255 Bytes
1-4 Bytes
0 or 2
Bytes
Figure 32.12. Packet Structure
An overview of the packet handler configuration registers is shown in
T
a
ble 32.4.
Rev. 1.0
459
Si102x/3x
32.6.3. Packet Handler TX Mode
If the TX packet length is set the packet handler will send the number of bytes in the packet length field
before returning to IDLE mode and asserting the packet sent interrupt.
T
o
r
esume sending data from the
FIFO the microcontroller needs to command the chip to re-enter TX mode. Figure 32.13 provides an exam-
ple transaction where the packet length is set to three bytes.
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
This will be sent in the first transmission
}
}
}
This will be sent in the second transmission
This will be sent in the third transmission
Figure 32.13. Multiple Packets in TX Packet Handler
32.6.4. Packet Handler RX Mode
32.6.4.1. Packet
Handler Disabled
When the packet handler is disabled certain fields in the received packet are still required. Proper modem
operation requires preamble and sync when the FIFO is being used, as shown in Figure 32.14. Bits after
sync will be treated as raw data with no qualification. This mode allows for the creation of a custom packet
handler when the automatic qualification parameters are not s
ient. Manchester encoding is supported
but data whitening, CRC, and header checks are not.
Preamble
SYNC
DATA
Figure 32.14. Required RX Packet Structure with Packet Handler Disabled
32.6.4.2. Packet
Handler Enabled
When the packet handler is enabled, all the fields of the packet structure need to be configured. Register
contents are used to construct the h
ader field and length information encoded into the transmitted packet
when transmitting. The receive FIFO can be configured to handle packets of fixed or variable length with or
without a header. If multiple packets are desired to be stored in the FIFO, then there are options available
for the different fields that will be stored into the FIFO. Figure 32.15 demonstrates the options and settings
available when multiple packets are enabled. Figure 32.16 demonstrates the operation of fixed packet
length and correct/incorrect packets.
460
Rev. 1.0
Si102x/3x
RX FIFO Contents:
Transmission:
rx_multi_pk_en = 0
rx_multi_pk_en = 1
txhdlen = 0
txhdlen > 0
fixpklen fixpklen
Register
Data
H
eade
r
(
s)
L
ength
Register
Data
0
0
1
1
Data
H
L
H
FIFO
L
Data
Data
Data
Data
Data
Figure 32.15. Multiple Packets in RX Packet H
dler
Initial state
PK 1 OK
PK 2 OK
PK 3
PK 4 OK
ERROR
RX FIFO Add
r
.
RX FIFO Addr.
0
RX FIFO Addr.
RX FIFO Add
r
.
FIFO Add
r
.
Write
Pointer
0
0
0
0
H
H
H
H
L
L
L
L
Data
Data
Data
Data
Write
Pointer
H
L
H
L
Data
ta
Data
Write
Pointer
Write
Pointer
H
L
H
L
Data
Write
Pointer
Data
CRC
error
63
63
63
63
63
Figure 32.16. Multiple Packets in RX with CRC or Header Error
Rev. 1.0
461
Si102x/3x
Table 32.4. Packet Handler Registers
Add R/W Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
R/W
R
Data Access Control
EzMAC status
enpacrx
0
lsbfrst
rxcrc1
crcdonly
pksrch
skip2ph
pkrx
enpactx
pkvalid
encrc
crc[1]
pktx
crc[0]
8Dh
crcerror
pksent
R/W
R/W
R/W
Header Control 1
Header Control 2
Preamble Length
bcen[3:0]
hdch[3:0]
skipsyn
hdlen[2]
hdlen[1]
hdlen[0]
fixpklen
synclen[1] synclen[0] prealen[8]
22h
prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] pre
len[0] 08h
R/W Preamble
Detection Control
preath[4]
preath[3]
sync[30]
sync[22]
sync[14]
sync[6]
preath[2]
sync[29]
sync[21]
sync[13]
sync[5]
preath[1]
sync[28]
sync[20]
sync[12]
sync[4]
preath[0]
sync[27]
sync[19]
sync[11]
sync[3]
rssi_off[2] rssi_off[1]
i_off[0]
2Ah
2Dh
D4h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Sync Word 3
Sync Word 2
sync[31]
sync[23]
sync[15]
sync[7]
sync[26]
sync[18]
sync[10]
sync[2]
sy
5]
sy
sync[1]
txhd[25]
txhd[17]
txhd[9]
sync[24]
sync[16]
sync[8]
sync[0]
txhd[24]
txhd[16]
txhd[8]
Sync Word 1
Sync Word 0
Transmit Header 3
Transmit Header 2
Transmit Header 1
Transmit Header 0
Transmit Packet Length
Check Header 3
Check Header 2
Check Header 1
Check Header 0
Header Enable 3
Header Enable 2
Header Enable 1
Header Enable 0
Received Header 3
Received Header 2
Received Header 1
Received Header 0
Received Packet Length
txhd[31]
txhd[23]
txhd[15]
txhd[7]
txhd[30]
txhd[22]
txhd[14]
txhd[6]
txhd[29]
txhd[21]
txhd[13]
txhd[5]
txhd[28]
txhd[20]
txhd[12]
txhd[4]
txhd[27]
txhd[19]
txhd[11]
txhd[3]
txhd[26]
txhd[18
xhd
10]
txhd[2]
txhd[1]
txhd[0]
pklen[7]
chhd[31]
chhd[23]
chhd[15]
chhd[7]
hden[31]
hden[23]
hden[15]
hden[7]
rxhd[31]
rxhd[23]
rxhd[15]
rxhd[7
pklen[6]
chhd[30]
chhd[22]
chhd[14]
chhd[6]
hden[30]
hden[22]
hden[14]
hden[6]
rxhd[
rxhd[
rxhd[14]
rxhd[6]
pklen[5]
chhd[29]
chhd[21]
chhd[13]
chhd[5]
hden[29]
hde
hden
den[5]
rxhd[29]
rxhd[21]
rxhd[13]
rxhd[5]
pklen[4]
chhd[28]
chhd[20]
ch
chh
hden[28]
hden[20]
hden[12]
hden[4]
rxhd[28]
rxhd[20]
rxhd[12]
rxhd[4]
pklen[3]
chhd[27]
chhd[19]
chhd[11]
chhd[3]
hden[27]
hden[19]
hden[11]
hden[3]
rxhd[27]
rxhd[19]
rxhd[11]
rxhd[3]
pklen[2]
chhd[26]
chhd[18]
chhd[10]
chhd[2]
hden[26]
hden[18]
hden[10]
hden[2]
rxhd[26]
rxhd[18]
rxhd[10]
rxhd[2]
pklen[1]
chhd[25]
chhd[17]
chhd[9]
chhd[1]
hden[25]
hden[17]
hden[9]
hden[1]
rxhd[25]
rxhd[17]
rxhd[9]
pklen[0]
chhd[24]
chhd[16]
chhd[8]
chhd[0]
hden[24]
hden[16]
hden[8]
hden[0]
rxhd[24]
rxhd[16]
rxhd[8]
R
—
R
—
R
rxhd[1]
rxhd[0]
—
R
rxplen
]
rxplen[6]
rxplen[5]
rxplen[4]
rxplen[3]
rxplen[2]
rxplen[1]
rxplen[0]
—
32.6.5. Data Whitening, Manchester Encoding, and CRC
Data whitening can be used to avoid extended sequences of 0s or 1s in the transmitted data stream to
achieve a more uniform spectrum. When enabled, the payload data bits are XORed with a pseudo-random
sequence output from the built-in PN9 generator. The generator is initialized at the beginning of the pay-
load. The receiver
vers the original data by repeating this operation. Manchester encoding can be
used to ensure a dc-free transmission and good synchronization properties. When Manchester encoding is
used, the effective datarate is unchanged but the actual datarate (preamble length, etc.) is doubled due to
the nature
the encoding. The effective datarate when using Manchester encoding is limited to 128 kbps.
The
ementation of Manchester encoding is shown in Figure 32.18. Data whitening and Manchester
enco
ng can be selected with “Register 70h. Modulation Mode Control 1”. The CRC is configured via
“Register 30h. Data Access Control”. Figure 32.17 demonstrates the portions of the packet which have
Manchester encoding, data whitening, and CRC applied. CRC can be applied to only the data portion of
e packet or to the data, packet length and header fields. Figure 32.18 provides an example of how the
Manchester encoding is done and also the use of the Manchester invert (enmaniv) function.
462
Rev. 1.0
Si102x/3x
Manchester
Whitening
CRC
CRC
(Over data only)
Header/
Address
PK
Length
Preamble
Sync
CRC
Data
Figure 32.17. Operation of Data Whitening, Manchester Encoding, and CRC
Data before Man
hester
1
1
1
1
1
1
1
1
0
0
0
1
0
Preamble = 0xFF
First 4bits of the synch. word = 0x2
Dat
er Machester ( manppol = 1, enmaninv = 0)
Da
a after Machester ( manppol = 1, enmaninv = 1)
Data before Manchester
0
0
0
0
0
0
0
0
0
0
0
1
0
Preamble = 0x00
First 4bits of the synch. word = 0x2
Data after Machester ( manppol = 0, enmaninv = 0)
Data after Machester ( manppol = 0, enmaninv = 1)
Figure 32.18.
chester Coding Example
32.6.6. Preamble Detector
The EZRadioPRO transceiver has i
eg
ated automatic preamble detection. The preamble length is con-
figurable from 1–255 bytes using the prealen[7:0] field in “Register 33h. Header Control 2” and “Register
34h. Preamble Length”, as described in “32.6.2. Packet Configuration” . The preamble detection threshold,
preath[4:0] as set in “Register 35h. Preamble Detection Control 1”, is in units of 4 bits. The preamble
detector searches for a preamble pattern with a length of preath[4:0].
If a false preamble
tect occurs, the receiver will continuing searching for the preamble when no sync
word is detected. O
preamble is detected (false or real) then the part will then start searching for sync.
If no sync occurs then a timeout will occur and the device will initiate search for preamble again. The time-
out period i
defined as the sync word length plus four bits and will start after a non-preamble pattern is
recog
zed
fter a valid preamble detection. The preamble detector output may be programmed onto one
of t
PIO or read in the interrupt status registers.
32.6.7. Preamble Length
The preamble detection threshold determines the number of valid preamble bits the radio must receive to
ualify a valid preamble. The preamble threshold should be adjusted depending on the nature of the appli-
cation. The required preamble length threshold will depend on when receive mode is entered in relation to
the start of the transmitted packet and the length of the transmit preamble. With a shorter than recom-
mended preamble detection threshold the probability of false detection is directly related to how long the
receiver operates on noise before the transmit preamble is received. False detection on noise may cause
the actual packet to be missed. The preamble detection threshold is programmed in register 35h. For most
applications with a preamble length longer than 32 bits the default value of 20 is recommended for the pre-
Rev. 1.0
463
Si102x/3x
amble detection threshold. A shorter Preamble Detection Threshold may be chosen if occasional false
detections may be tolerated. When antenna diversity is enabled a 20-bit preamble detection threshold is
recommended. When the receiver is synchronously enabled just before the start of the packet, a shorter
preamble detection threshold may be used.
T
a
ble 32.5 demonstrates the recommended preamble detec-
tion threshold and preamble length for various modes.
It is possible to use the transceiver in a raw mode without the requirement for a 010101… preamble. Con
tact customer support for further details.
Table 32.5. Minimum Receiver Settling Time
Approximate Recommende
d
P
reamble
Recommende
Preamble
Mode
Receiver
Settling Time
1 byte
Length with 8-Bit
Detection Threshold
20 bits
Len
h 20-Bit
Detecti
hreshold
32 bits
(G)FSK AFC Disabled
(G)FSK AFC Enabled
(G)FSK AFC Disabled
+Antenna Diversity Enabled
(G)FSK AFC Enabled
+Antenna Diversity Enabled
OOK
2 byte
28 bits
40 bits
1 byte
—
64 bits
2 byte
2 byte
8 byte
—
3 byte
8 byte
4 byte
8 byte
OOK + Antenna Diversity
Enabled
Note:
The recommended preamble length and preamble detection threshold listed above are to achieve 0% PER.
They may be shortened when occasional packet err
are tolerable.
32.6.8. Invalid Preamble Detector
When scanning channels in a frequency hopping
ystem it is desirable to determine if a channel is valid in
the minimum amount of time. The preamble
ctor can output an invalid preamble detect signal. which
can be used to identify the channel as invalid. After a configurable time set in Register 60h[7:4], an invalid
preamble detect signal is asserted indicating an invalid channel. The period for evaluating the signal for
invalid preamble is defined as (inv_p
_th[3:0] x 4) x Bit Rate Period. The preamble detect and invalid pre-
amble detect signals are available in “Register 03h. Interrupt/Status 1” and “Register 04h. Interrupt/Status
2.”
32.6.9. Synchronization Word Configuration
The synchronization word length for both TX and RX can be configured in Reg 33h, synclen[1:0]. The
expected or transmitted sync word can be configured from 1 to 4 bytes as defined below:
synclen[1:0] = 00
Expected/Transmitted Synchronization Word (sync word) 3.
synclen[1:0] = 01—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2.
synclen
:0] = 10—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2,
f
ed by sync word 1.
sy
clen[1:0] = 1—Send/Expect Synchronization Word 3 first, followed by sync word 2, followed by sync
word 1, followed by sync word 0.
The sync is transmitted or expected in the following sequence: sync 3
sync 2
sync 1
sync 0. The sync
ord values can be programmed in Registers 36h–39h. After preamble detection the part will search for
sync for a fixed period of time. If a sync is not recognized in this period then a timeout will occur and the
search for preamble will be re-initiated. The timeout period after preamble detections is defined as the
value programmed into the sync word length plus four additional bits.
464
Rev. 1.0
Si102x/3x
32.6.10. Receive Header Check
The header check is designed to support 1–4 bytes and broadcast headers. The header length needs to
be set in register 33h, hdlen[2:0]. The headers to be checked need to be set in register 32h, hdch[3:0]. For
instance, there can be four bytes of header in the packet structure but only one byte of the header is set to
be checked (i.e., header 3). For the headers that are set to be checked, the expected value of the header
should be programmed in chhd[31:0] in Registers 3F–42. The individual bits within the selected bytes to be
checked can be enabled or disabled with the header enables, hden[31:0] in Registers 43–46. For examp
if you want to check all bits in header 3 then hden[31:24] should be set to FF but if only the last 4 bits are
desired to be checked then it should be set to 00001111 (0F). Broadcast headers can also be programmed
by setting bcen[3:0] in Register 32h. For broadcast header check the value may be either “
h” or the
value stored in the Check Header register. A logic equivalent of the header check for Header 3
s shown in
Figure 32.19. A similar logic check will be done for Header 2, Header 1, and Header 0
ed.
Example for Header 3
rxhd[31:24]
BIT
Equivalence
comparison
WISE
hden[31:24]
=
BIT
WISE
chhd[31:24]
header3_ok
bcen[3]
Equivalenc
comparis
FFh
=
hdch[3]
rxhd[31:24]
Figure 32.19. Header
32.6.11. TX Retransmission and Auto TX
The transceiver is
ble of automatically retransmitting the last packet loaded in the TX FIFO. Automatic
retransmission is set by entering the TX state with the txon bit without reloading the TX FIFO. This feature
is useful for beacon transmission or when retransmission is required due to the absence of a valid
acknowled
ment. Only packets that fit completely in the TX FIFO can be automatically retransmitted.
An
matic transmission function is available, allowing the radio to automatically start or stop a transmis-
sion depending on the amount of data in the TX FIFO.
When autotx is set in “Register 08. Operating & Function Control 2″, the transceiver will automatically enter
he TX state when the TX FIFO almost full threshold is exceeded. Packets will be transmitted according to
the configured packet length.
T
o
s
top transmitting, clear the packet sent or TX FIFO almost empty inter-
rupts must be cleared by reading register.
Rev. 1.0
465
Si102x/3x
32.7. RX
Modem Configuration
A Microsoft Excel parameter calculator or Wireless Development Suite (WDS) calculator is provided to
determine the proper settings for the modem. The calculator can be found on www.silabs.com or on the
32.7.1. Modem Settings for FSK and GFSK
The modem performs channel selection and demodulation in the digital domain. The channel filter band-
width is configurable from 2.6 to 620 kHz. The receiver data-rate, modulation index, and bandwidth are set
via registers 1C–25h. The modulation index is equal to 2 times the peak deviation divided by th
data rate
(Rb).
When Manchester coding is disabled, the required channel filter bandwidth is calculated
= 2Fd + Rb
where Fd is the frequency deviation and Rb is the data rate.
32.8. Auxiliary
Functions
The EZRadioPRO has some auxiliary functions that duplicate the directly
cessible MCU peripherals:
ADC, temperature sensor, and 32 kHz oscillator. These auxiliary functions a
e retained primarily for com-
patibility with the Si4430/1/2. The directly accessed MCU peripherals typically provide lower system cur-
rent consumption and better analog performance. However some of these EZRadioPRO auxiliary
functions offer features not directly duplicated in the MCU directly accessed peripherals, such as the Low
Duty Cycle Mode operation.
32.8.1. Smart Reset
The EZRadioPRO transceiver contains an enhanced integrated SMART RESET or POR circuit. The POR
circuit contains both a classic level threshold reset as
ll as a slope detector POR. This reset circuit was
designed to produce a reliable reset signal under any c
umstances. Reset will be initiated if any of the fol-
lowing conditions occur:
Initial power on, V
starts from gnd: res
active till V
reaches V
(see table);
DD DD
RR
When V
decreases below V
for any reason: reset is active till V
reaches V
;
RR
DD
LD
DD
A software reset via “Register 08
Operating Mode and Function Control 2”: reset is active for time
T
SWRST
On the rising edge of a V
glitch when the supply voltage exceeds the following time functioned limit:
DD
VDD nom.
VDD(t)
reset limit:
0.4V+t*0.2V/ms
actual VDD(t)
showing glitch
0.4V
Reset
T
P
t
t=0,
reset:
VDD starts to rise
Vglitch>=0.4+t*0.2V/ms
Figure 32.20. POR Glitch Parameters
466
Rev. 1.0
Si102x/3x
Table 32.6. POR Parameters
Symbol Comment
Parameter
Min
0.85
0.03
0.7
50
Typ
1.3
—
Max
1.75
300
1.3
470
—
Unit
V
Release Reset Voltage
VRR
SVDD
VLD
Power-On V
Slope
tested V
slope region
V/ms
V
DD
DD
Low V
Limit
VLD<VRR is guaranteed
1
DD
Software Reset Pulse
Threshold Voltage
Reference Slope
TSWRST
VTSD
k
—
us
—
0.4
0.2
16
V
—
—
V/ms
ms
V
Glitch Reset Pulse
TP
Also occurs after SDN, and
initial power on
5
5
DD
The reset will initialize all registers to their default values. The reset signal is also available for output and
use by the microcontroller by using the default setting for GPIO_0. The invert
reset signal is available by
default on GPIO_1.
32.8.2. Output Clock
The 30 MHz crystal oscillator frequency is divided down internally and may be output on GPIO2. This fea-
ture is useful to lower BOM cost by using only one crystal in the system. The output clock on GPIO2 may
be routed to the XTAL2 input to provide a synchronized clock
ce between the MCU and the EZRadio-
PRO peripheral. The output clock frequency is selectable from one of 8 options, as shown below. Except
for the 32.768 kHz option, all other frequencies are derived by dividing the crystal oscillator frequency. The
32.768 kHz clock signal is derived from an internal R
cillator or an external 32 kHz crystal. The default
setting for GPIO2 is to output the clock signal with a frequency of 1 MHz.
D7
D
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
0A R/W
Output Clock
clkt[1] clkt[0]
enlfc mclk[2]
mclk[1] mclk[0]
06h
mclk[2:0]
000
Modulation Source
30 MHz
001
15 MHz
010
10 MHz
011
4 MHz
100
3 MHz
101
2 MHz
110
1 MHz
111
32.768 kHz
Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz
clock can be automatically switched to become the output clock. This feature is called enable low fre-
quency clock and is enabled by the enlfc bit in “Register 0Ah. Microcontroller Output Clock.” When enlfc =
1 and the chip is in SLEEP mode then the 32.768 kHz clock will be provided regardless of the setting of
mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin in all IDLE,
Rev. 1.0
467
Si102x/3x
TX, or RX states. When the chip enters SLEEP mode, the output clock will automatically switch to
32.768 kHz from the RC oscillator or 32.768 XTAL.
Another available feature for the output clock is the clock tail, clkt[1:0] in “Register 0Ah. Microcontroller
Output Clock.” If the low frequency clock feature is not enabled (enlfc = 0), then the output is disabled in
SLEEP mode. Setting the clkt[1:0] field will provide additional cycles of the output clock before it shuts off.
clkt[1:0]
Modulation Source
0 cycles
00
01
10
11
128 cycles
256 cycles
512 cycles
If an interrupt is triggered, the output clock will remain enabled regardless of the selected mode. As soon
as the interrupt is read the state machine will then move to the selected mode. The minimum current con-
sumption will not be achieved until the interrupt is read. For instance, if th
EZRadioPRO peripheral is
commanded to SLEEP mode but an interrupt has occurred the 30 MHz XTA
will not be disabled until the
interrupt has been cleared.
32.8.3. General Purpose ADC
The EZRadioPRO peripheral includes an 8-bit SAR ADC independent of ADC0. It may be used for general
purpose analog sampling, as well as for digitizing the EZRad
O temperature sensor reading. In most
cases, the ADC0 subsystem directly accessible from the MCU will be preferred over the ADC embedded
inside the EZRadioPRO peripheral. Registers 0Fh “ADC Configuration”, 10h “Sensor Offset” and 4Fh
“Amplifier Offset” can be used to configure the ADC
eration. Details of these registers are in “AN440:
EZRadioPRO Detailed Register Descriptions.”
Every time an ADC conversion is desired, bi
7 “adcstart/adcdone” in Register 0Fh “ADC Configuration”
must be set to 1. The conversion time for th
DC is 350 µs. After the ADC conversion is done and the
adcdone signal is showing 1, then the ADC value may be read out of “Register 11h: ADC Value.” When the
ADC is doing its conversion, the adcstart/adcdone bit will read 0. When the ADC has finished its conver-
sion, the bit will be set to 1. A new A
C conversion can be initiated by writing a 1 to the adcstart/adcdone
bit.
The architecture of the ADC is shown in Figure 32.21. The signal and reference inputs of the ADC are
selected by adcsel[2:0] and adcref[1:0] in register 0Fh “ADC Configuration”, respectively. The default set-
ting is to read out the temperature sensor using the bandgap voltage (VBG) as reference. With the VBG
reference the input range of the ADC is from 0–1.02 V with an LSB resolution of 4 mV (1.02/255). Chang-
ing the ADC refere
will change the LSB resolution accordingly.
A differential multip
exer and amplifier are provided for interfacing external bridge sensors. The gain of the
amplifier is
lectable by adcgain[1:0] in Register 0Fh. The majority of sensor bridges have supply voltage
(VDD
ependent gain and offset. The reference voltage of the ADC can be changed to either V
/2 or
DD
V
/
A programmable V
dependent offset voltage can be added using soffs[3:0] in register 10h.
DD
DD
468
Rev. 1.0
Si102x/3x
Diff. MUX
Diff. Amp.
Input MUX
aoffs [4:0]
soffs [3:0]
adcsel [2:0]
adcgain [1:0]
GPIO0
GPIO1
GPIO2
8-bit ADC
Temperature Sensor
V
in
adc [7:
adcsel [2:0]
V
ref
0 -1020mV / 0-255
Ref MUX
V
DD
/ 3
DD
/ 2
V
V
BG
(1.2V)
adcref [1:0]
Figure 32.21. General Purpose ADC Architecture
Add R/W
Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
0F
10
11
R/W
R/W
R
ADC Configuration
adcstart/adcdone adcsel[2] adcs
adcsel[0] adcref[1]
adcref[0] adcgain[1]
adcgain[0]
00h
00h
—
Sensor Offset
ADC Value
soffs[3]
adc[3]
soffs[2]
adc[2]
soffs[1]
adc[1]
soffs[0]
adc[0]
adc[7]
adc[6]
adc
5]
adc[4]
32.8.4. Temperature Sensor
The EZRadioPRO peripheral includes an integrated on-chip analog temperature sensor independent of
the temperature sensor associated
ith ADC0. The temperature sensor will be automatically enabled
when the temperature sensor is selected as the input of the EZRadioPRO ADC or when the analog temp
voltage is selected on the analog test bus. The temperature sensor value may be digitized using the EZRa-
dioPRO general-purpose ADC and read out through “Register 10h. ADC Sensor Amplifier Offset.” The
range of the temperature sensor is configurable.
T
a
ble 32.7 lists the settings for the different temperature
ranges and performance.
To
u
se the
T
e
mp S
r:
1. Set
the input for ADC to the temperature sensor, “Register 0Fh. ADC Configuration”—adcsel[2:0] = 000
2. Set
the
erence for ADC, “Register 0Fh. ADC Configuration”—adcref[1:0] = 00
3. S
e temperature range for ADC, “Register 12h.
T
e
mperature Sensor Calibration”—tsrange[1:0]
4. Se
entsoffs = 1, “Register 12h.
T
e
mperature Sensor Calibration”
5. Trigger
ADC reading, “Register 0Fh. ADC Configuration”—adcstart = 1
. Read
temperature value—Read contents of “Register 11h. ADC Value”
Rev. 1.0
469
Si102x/3x
Add R/
W
Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
tsrange[1] tsrange[0] entsoffs
entstrim tstrim[3]
tstrim[2] vbgtrim[1]
vbgtrim[0]
12 R/W
T
e
mperature
20h
Sensor Control
tvoffs[7]
tvoffs[6]
tvoffs[5] tvoffs[4]
tvoffs[3]
tvoffs[2]
tvoffs[1]
tvoffs[0]
13 R/W
T
e
mperature Value
Offset
00h
Table 32.7. Temperature Sensor Range
entoff
tsrange[1]
tsrange[0]
Temp. range
Unit
Slope
DC8 LSB
0.5 °C
1 °C
1
1
0
0
1
1
1
0
1
0
1
0
–64 … 64
–64 … 192
0 … 128
°C
°C
°C
°F
°K
8 mV/°C
4 mV/°C
8 mV/°C
4
V/°F
3 mV/°K
1
0.5 °C
1 °F
1
–40 … 216
0 … 341
0*
1.333 °K
Note:
Absolute temperature mode, no temperature shift. This mode is only for test purposes. POR value of
EN_TOFF is 1.
The slope of the temperature sensor is very linear and monotonic. For absolute accuracy better than 10 °C
calibration is necessary. The temperature sensor may be calibrated by setting entsoffs = 1 in “Register
12h.
T
e
mperature Sensor Control” and setting the off
with the tvoffs[7:0] bits in “Register 13h.
T
e
mpera-
ture Value Offset.” This method adds a positive offset digitally to the ADC value that is read in “Register
11h. ADC Value.” The other method of calibratio
is
o use the tstrim which compensates the analog cir-
cuit. This is done by setting entstrim = 1 and
g the tstrim[2:0] bits to offset the temperature in “Register
12h.
T
e
mperature Sensor Control.” With this
ethod of calibration, a negative offset may be achieved.
With both methods of calibration better than ±3 °C absolute accuracy may be achieved.
The different ranges for the tempera
re sensor and ADC8 are demonstrated in Figure 32.22. The value of
the ADC8 may be translated to a temperature reading by ADC8Value x ADC8 LSB + Lowest
T
e
mperature
in
T
e
mp Range. For instance
or a tsrange = 00,
T
e
mp = ADC8Value x 0.5 – 64.
470
Rev. 1.0
Si102x/3x
Temperature Measurement with ADC8
300
250
200
150
100
Se
n
s
Range 0
Se
nge 1
Se
n
s
o
ange 2
Se
n
s
o
r Range 3
50
0
-40
-20
0
20
40
60
80
100
T
e
mperature [Celsius]
Figure 32.22. Temperatu
Ranges using ADC8
32.8.5. Low Battery Detector
The Low Battery Detector (LBD) feature of th
EZRadioPRO peripheral is not supported in the Si102x/3x.
Use ADC0 instead. Refer to “5. SAR ADC w
6-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode” on page 77 for details.
32.8.6. Wake-Up Timer and 32 kHz
ock Source
The EZRadioPRO peripheral contains an integrated wake-up timer independent of the SmaRTClock which
can be used to periodically wake the chip from SLEEP mode using the interrupt pin. The wake-up timer
runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in
SLEEP mode. If enwt = 1 in “Register 07h. Operating Mode and Function Control 1” when entering SLEEP
mode, the wake-up timer will count for a time specified defined in Registers 14–16h, “Wake Up Timer
Period”. At the exp
on of this period an interrupt will be generated on the nIRQ pin if this interrupt is
enabled. The softw
will then need to verify the interrupt by reading the Registers 03h–04h, “Interrupt
Status 1 & 2″. The wake-up timer value may be read at any time by the wtv[15:0] read only registers 17h–
18h.
The
ula for calculating the Wake-Up Period is the following:
32
M
2
R
WUT
ms
32.768
WUT Register
wtr[4:0]
Description
R Value in Formula
M Value in Formula
wtm[15:0]
Use of the D variable in the formula is only necessary if finer resolution is required than can be achieved by
using the R value.
Rev. 1.0
471
Si102x/3x
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/Description
14 R/W
Wake-Up Timer Period 1
wtr[4]
wtr[3]
wtr[2]
wtr[1] wtr[0]
03h
15 R/W
Wake-Up Timer Period 2
wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9]
wtm[8] 00h
16 R/W
Wake-Up Timer Period 3
wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1]
wtm[0]
17
18
R
R
Wake-Up Timer Value 1
wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9]
wtv[8]
Wake-Up Timer Value 2
wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1]
v[0]
—
—
There are two different methods for utilizing the wake-up timer (WUT) depending on if t
T interrupt is
enabled in “Register 06h. Interrupt Enable 2.” If the WUT interrupt is enabled then nIR
n will go low
when the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the
microcontroller clock output is available for the microcontroller to use to process the interrupt. The other
method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation
the chip will not change state until commanded by the microcontroller. The di
rent modes of operating the
WUT and the current consumption impacts are demonstrated in Figure 32.23.
A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in Register 07h
“Operating & Function Control 1”, GPIO0 is automatically reconfigured so that an external 32 kHz XTAL
may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so
only the XTAL should be connected to this pin with the XTAL
cally located as close to the pin as pos-
sible. Once the x32 ksel bit is set, all internal functions such as WU
T
,
m
icrocontroller clock, and LDC mode
will use the 32 kHz XTAL and not the 32 kHz RC oscillator.
The 32 kHz XTAL accuracy is comprised of both the
L parameters and the internal circuit. The XTAL
accuracy can be defined as the XTAL initial erro
XTAL aging + XTAL temperature drift + detuning from
the internal oscillator circuit. The error caused
y the internal circuit is typically less than 10 ppm.
472
Rev. 1.0
Si102x/3x
Interrupt Enable enwut
=
1(
R
eg 06h)
WUT Period
GPIOX
=
0
0001
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Ready
Sleep
Ready
Sleep
Ready
1.5 mA
Sleep
1.5 mA
1.5 mA
Current
Consumption
1 uA
1 uA
1 uA
Interrupt Enable enwut
=
0(
R
eg 06h)
WUT Period
GPIOX
=
0
0001
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Current
Consump
1 uA
Figure 32.23. WUT Interrupt and WUT Operation
32.8.7. Low Duty Cycle Mode
he Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is
available. The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid
preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT
period. If a valid preamble and sync are detected the receiver on period will be extended for the low duty
cycle mode duration (TLDC) to receive all of the packet. The WUT period must be set in conjunction with
the low duty cycle mode duration. The R value (“Register 14h. Wake-up Timer Period 1”) is shared
Rev. 1.0
473
Si102x/3x
between the WUT and the TLDC. The ldc[7:0] bits are located in “Register 19h. Low Duty Cycle Mode
Duration.” The time of the TLDC is determined by the formula below:
R
4
2
TLDC
ldc
[
7 : 0
]
ms
32
.
7
68
Figure 32.24. Low Duty Cycle Mode
32.8.8. GPIO Configuration
Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW
control, etc. can be routed to the GPIO pins as shown in the t
below. When in Shutdown mode all the
GPIO pads are pulled low.
Note:
The ADC should not be selected as an input to the G
IO in standby or sleep modes and will cause excess cur-
rent consumption.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/
Description
0B R/W
0C R/W
0D R/W
0E R/W
GPIO0
Configuration
gpio0drv[1] gpio0drv[0]
pup0
gpio1drv[1] gpio1drv[0]
pup1
gpio2drv[1] gpio2drv[0]
pup2
gpio0[4] gpio0[3]
gpio0[2] gpio0[1] gpio0[0]
00h
gpio1[4] gpio1[3]
gpio1[2] gpio1[1] gpio1[0]
00h
gpio2[4] gpio2[3]
gpio2[2] gpio2[1] gpio2[0]
00h
GPIO1
Configuration
GPIO2
Configuration
I/O Po
extitst[2] extitst[1]
extitst[0]
itsdo
dio2
dio1
dio0
00h
Configur
The GPIO
ttings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000
defaul
sett
g. The default settings for each GPIO are listed below:
GPIO
GPIO0
GPIO1
GPIO2
00000—Default Setting
POR
POR Inverted
Output Clock
For a complete list of the available GPIOs see “AN440: EZRadioPRO Detailed Register Descriptions”.
The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase
the drive strength and current capability of the GPIO by changing the driver size. Special care should be
474
Rev. 1.0
Si102x/3x
taken in setting the drive strength and loading on GPIO2 when the microcontroller clock is used. Excess
loading or inadequate drive may contribute to increased spurious emissions.
Pin 6, ANT may be used as an alternate to control a TR switch. Pin 6 is a hardwired version of GPIO set-
ting 11000, Antenna 2 Switch used for antenna diversity. It can be manually controlled by the antdiv[2:0]
bits in register 08h if antenna diversity is not used. See AN440, register 08h for more details.
32.8.9. Antenna Diversity
To
m
itigate the problem of frequency-selective fading due to multi-path propagation, some transceiver sys-
tems use a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the
transceiver enters RX mode the receive signal strength from each antenna is evaluated. Thi
valuation
process takes place during the preamble portion of the packet. The antenna with the st
ngest received
signal is then used for the remainder of that RX packet. The same antenna will also b
for the next
corresponding TX packet.
This chip fully supports antenna diversity with an integrated antenna diversity control algorithm. The
required signals needed to control an external SPDT RF switch (such as PIN diode or GaAs switch) are
available on the GPIOx pins. The operation of these GPIO signals is progra
mable to allow for different
antenna diversity architectures and configurations. The antdiv[2:0] bits are found in register 08h “Operating
& Function Control 2.” The GPIO pins are capable of sourcing up to 5 mA of current, so it may be used
directly to forward-bias a PIN diode if desired.
The antenna diversity algorithm will automatically toggle back and forth between the antennas until the
packet starts to arrive. The recommended preamble length for
mal antenna selection is 8 bytes. A spe-
cial antenna diversity algorithm (antdiv[2:0] = 110 or 111) is
cluded that allows for shorter preamble
lengths for beacon mode in TDMA-like systems where the arrival of the packet is synchronous to the
receiver enable. The recommended preamble length
obtain optimal antenna selection for synchronous
mode is 4 bytes.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W
Function/Description
08 R/W
Operating & Function
Control 2
antdiv[2] antdiv[1] antdiv[0] rxmpk
autotx enldm ffclrrx
ffclrtx
00h
Table 32.8. Antenna Diversity Control
antdiv[2:0]
000
RX/TX State
Non RX/TX State
GPIO Ant1
GPIO Ant2
GPIO Ant1
GPIO Ant2
0
1
0
1
1
0
1
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
001
010
011
00
101
110
111
Antenna Diversity Algorithm
Antenna Diversity Algorithm
Antenna Diversity Algorithm in Beacon Mode
Antenna Diversity Algorithm in Beacon Mode
32.8.10. RSSI and Clear Channel Assessment
Received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the
receiver is tuned. The RSSI value can be read from an 8-bit register with 0.5
dB resolution per bit.
Figure 32.25 demonstrates the relationship between input power level and RSSI value. The absolute value
of the RSSI will change slightly depending on the modem settings. The RSSI may be read at anytime, but
Rev. 1.0
475
Si102x/3x
an incorrect error may rarely occur. The RSSI value may be incorrect if read during the update period. The
update period is approximately 10 ns every 4 Tb. For 10 kbps, this would result in a 1 in 40,000 probability
that the RSSI may be read incorrectly. This probability is extremely low, but to avoid this, one of the follow-
ing options is recommended: majority polling, reading the RSSI value within 1 Tb of the RSSI interrupt, or
using the RSSI threshold described in the next paragraph for Clear Channel Assessment (CCA).
D7
D6
D5
D4
D3
D2
D1
D0
P
Def.
Add R/W
Function/Description
26
27
R
Received Signal Strength Indicator
rssi[7]
rssi[6]
rssi[5]
rssi[4]
rssi[3]
rssi[2]
rssi[1]
rssi[0]
—
R/W RSSI
Threshold for Clear Channel Indicator
rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] rssith[2] rss
th[1] rssith[0]
00h
For CCA, threshold is programmed into rssith[7:0] in “Register 27h. RSSI Threshold f
ear Channel
Indicator.” After the RSSI is evaluated in the preamble, a decision is made if the signal strength on this
channel is above or below the threshold. If the signal strength is above the programmed threshold then the
RSSI status bit, irssi, in “Register 04h. Interrupt/Status 2” will be set to 1. The RSSI status can also be
routed to a GPIO line by configuring the GPIO configuration register to GPIO
3:0] = 1110.
RSSI vs Input Power
250
200
150
100
50
0
-120
-100
-80
-60
-40
-20
0
20
In Pow [dBm]
Figure 32.25. RSSI Value vs. Input Power
32.9. Reference
Design
mended schematics, BOM, and layout. TX matching component values for the different frequency bands
can be found in the application notes “AN435: Si4032/4432 PA Matching” and “AN436:
i4030/4031/4430/4431 PA Matching.” RX matching component values for different frequency bands can
be found in “AN427: EZRadioPRO Si433x and Si443x RX LNA Matching.”
476
Rev. 1.0
Si102x/3x
1
2
1 3 D C L / 7 . P 6
1 3 D C L / 7 . P 6
8 D C L / 0 . P 4
7 D C L / 7 . P 3
0 3 D C L / 6 . P 6
6 D C L / 6 . P 3
9 2 D C L / 5 . P 6
5 D C L / 5 . P 3
8 2 D C L / 4 . P 6
4 D C L / 4 . P 3
7 2 D C L / 3 . P 6
3 D C L / 3 . P 3
6 2 D C L / 2 . P 6
2 D C L / 2 . P 3
5 2 D C L / 1 . P 6
1 D C L / 1 . P 3
4 2 D C L / 0 . P 6
0 D C L / 0 . P 3
3 2 D C L / 7 . P 5
3 M O C / 7 . P 2
2 2 D C L / 6 . P 5
2 M O C / 6 . P 2
1 M O C / 5 . P 2
0 M O C / 4 . P 2
R Q N I
2 1 D C L / 4 . P 4
2 1 D C L / 4 . P 4
1 3 D C L / 7 . P 6
2 1 D C L / 4 . P 4
D 1
D 5
A 1
A 2
B 1
A 3
B 2
A 4
B 3
A 5
B 4
A 6
B 5
A 7
B 6
A 8
B 7
A 9
B 8
A 1
B 9
A 1
B 1
A 1
B 1
A 1
A 1
D 6
D 2
D 4
D 8
4 C D A / X T / 4 . P 0
5 C D A / X R / 5 . P 0
3 1 D C L / 5 . P 4
8 D C L / 0 . P 4
7 D C L / 7 . P 3
0 3 D C L / 6 . P 6
6 D C L / 6 . P 3
9 2 D C L / 5 . P 6
5 D C L / 5 . P 3
8 2 D C L / 4 . P 6
4 D C L / 4 . P 3
7 2 D C L / 3 . P 6
3 D C L / 3 . P 3
6 2 D C L / 2 . P 6
2 D C L / 2 . P 3
5 2 D C L / 1 . P 6
1 D C L / 1 . P 3
4 2 D C L / 0 . P 6
0 D C L / 0 . P 3
3 2 D C L / 7 . P 5
3 M O C / 7 . P 2
2 2 D C L / 6 . P 5
2 M O C / 6 . P 2
1 M O C / 5 . P 2
0 M O C / 4 . P 2
X T / 4 . P 0
X R / 5 . P 0
8
7
2
6
1
5
0
4
9
3
8
2
7
1
6
0
5
9
4
8
3
A 3
A 3
B 2
A 3
B 2
A 3
B 2
A 3
B 1
A 3
B 1
A 3
B 1
A 3
B 1
A 3
B 1
A 2
B 1
A 2
B 1
A 2
1
3 1 D C L / 5 . P 4
R T S V N C / 6 .
4 1 D C L / 6 . P 4
E F R I 0 / 7 . 0 P
R 5
6 C D A / R T S V N C / 6 . P 0
4 1 D C L / 6 . P 4
7 C A
D E F
R I / / 7 . 0 P
5 1 D C L / 7 . P 4
2 . P
1
3 . P
1
P O
P O
P
P
N O
R 6
5 1 D C L / 7 . P 4
0
P / C 0 . P 1
0
P / C 0 . P 1
6 1 D C L / 0 . P 5
P / C 1 . P 1
6 1 D C L / 0 . P 5
P /
P 1
1
1
7 1 D C L / 1 . P 5
7 1
L / 1 . P 5
N O
D
D
G N
G N
3 L A T X / 2 . P 1
D
G N
4 L A T X / 3 . P 1
8 1 D C L / 2 . P 5
D C V L
2 . P
5
0
9 1 D C L / 3 . P 5
8 C D A / 4 . P 1
0 2 D C L / 4 .
5
C 9 D A 0 1 / N I T / 5 . 1 P
1 2 D C L / 5 . P 5
C 1 D 0 A 0 1 / N I T 6
G D
I
9 1 D C L / 3 . P 5
4 . P
1
0 2 D C L / 4 . P 5
S T C / 5 . P 1
1 2 D C L / 5 . P 5
6 . P
1
1
0
2
1
3
4
T U
X O
2
3
1
4
N X
I
D
D
G N
G N
1 1 C D A / 7
G I D _
7 . P
1
D A P E D _ G N
E 0
Rev. 1.0
477
Si102x/3x
1
2
A
1
2
C
1 3 D C L / 7 . P 6
1 3 D C L / 7 . P 6
8 D C L / 0 . P 4
7 D C L / 7 . P 3
0 3 D C L / 6 . P 6
6 D C L / 6 . P 3
9 2 D C L / 5 . P 6
5 D C L / 5 . P 3
8 2 D C L / 4 . P 6
4 D C L / 4 . P 3
7 2 D C L / 3 . P 6
3 D C L / 3 . P 3
6 2 D C L / 2 . P 6
2 D C L / 2 . P 3
5 2 D C L / 1 . P 6
1 D C L / 1 . P 3
4 2 D C L / 0 . P 6
0 D C L / 0 . P 3
3 2 D C L / 7 . P 5
3 M O C / 7 . P 2
2 2 D C L / 6 . P 5
2 M O C / 6 . P 2
1 M O C / 5 . P 2
0 M O C / 4 . P 2
R Q N I
2 1 D C L / 4 . P 4
2 1 D C L / 4 . P 4
1 3 D C L / 7 . P 6
2 1 D C L / 4 . P 4
D 1
D 5
A 1
A 2
B 1
A 3
B 2
A 4
B 3
A 5
B 4
A 6
B 5
A 7
B 6
A 8
B 7
A 9
B 8
A 1
B 9
A 1
B 1
A 1
B 1
A 1
A 1
D 6
D 2
D 4
D 8
4 C D A / X T / 4 . P 0
5 C D A / X R / 5 . P 0
3 1 D C L / 5 . P 4
8 D C L / 0 . P 4
7 D C L / 7 . P 3
0 3 D C L / 6 . P 6
6 D C L / 6 . P 3
9 2 D C L / 5 . P 6
5 D C L / 5 . P 3
8 2 D C L / 4 . P 6
4 D C L / 4 . P 3
7 2 D C L / 3 . P 6
3 D C L / 3 . P 3
6 2 D C L / 2 . P 6
2 D C L / 2 . P 3
5 2 D C L / 1 . P 6
1 D C L / 1 . P 3
4 2 D C L / 0 . P 6
0 D C L / 0 . P 3
3 2 D C L / 7 . P 5
3 M O C / 7 . P 2
2 2 D C L / 6 . P 5
2 M O C / 6 . P 2
1 M O C / 5 . P 2
0 M O C / 4 . P 2
X T / 4 . P 0
X R / 5 . P 0
8
7
2
6
1
5
0
4
9
3
8
2
7
1
6
0
5
9
4
8
3
7
2
6
5
A 3
A 3
B 2
A 3
B 2
A 3
B 2
A 3
B 1
A 3
B 1
A 3
B 1
A 3
B 1
A 3
B 1
A 2
B 1
A 2
B 1
A 2
B 1
A 2
A 2
3 1 D C L / 5 . P 4
R T S V N C / 6 . P 0
4 1 D C L / 6 . P 4
E F R I 0 / 7 . 0 P
6 C D A / R T S V N C / 6 . P 0
4 1 D C L / 6 . P 4
7 C A
D E F
R I / / 7 . 0 P
5 1 D C L / 7 . P 4
P O
N O
2 . P
1
3 . P
1
5 1 D C L / 7 . P 4
R 5
0
P / C 0 . P 1
0
P / C 0 . P 1
6 1 D C L / 0 . P 5
P / C 1 . P 1
6 1 D C L / 0 . P 5
P O
1
1
P / C 1 . P 1
7 1 D C L / 1 . P 5
7 1 D C L / 1 . P 5
D
D
G N
G N
R 6
3 L A T X / 2 . P 1
D
G N
4 L A T X / 3 . P 1
8 1 D C L / 2 . P 5
D C V L
8 1 D C L / 2 .
5
4
S J
0
9 1 D C L / 3 . P 5
8 C D A / 4 . P 1
0 2 D C L / 4 . P 5
C 9 D A 0 1 / N I T / 5 . 1 P
1 2 D C L / 5 . P 5
C 1 D 0 A 0 1 / N I T 6 / 1 P .
G D
I D
V D _
9 1
. P
5
P 5
6 .
1
0
2
1
3
4
T U
X O
2
3
1
4
N X
I
D
D
G N
G N
1 1 C D A / 7 . P 1
G I D
V R
7 . P
1
D 7
D 3
D A P E D _ G N
E 0
3
S J
2 _ O
I G
P
1 _ O
I G
P
0 _ O
I G
P
A _ T A
N
L C
2 C V
/ 2 O I G P
1 C V
/ 1 O I G P
478
Rev. 1.0
Si102x/3x
32.10. Application
Notes and Reference Designs
A comprehensive set of application notes and reference designs are available to assist with the develop-
ment of a radio system. A partial list of applications notes is given below.
For the complete list of application notes, latest reference designs and demos visit the
Silicon Labs website
.
AN361: Wireless MBUS Implementation using EZRadioPRO Devices
AN379: Antenna Diversity with EZRadioPRO
AN414: EZRadioPRO Layout Design Guide
AN415: EZRadioPRO Programming Guide
AN417: Si4x3x Family Crystal Oscillators
AN419: ARIB STD-T67 Narrow-Band 426/429 MHz Measured on the Si4431-A0
AN427: EZRadioPRO Si433x and Si443x RX LNA Matching
AN429: Using the DC-DC Converter on the F9xx Series MCU for Single Battery Operation with the
EZRadioPRO RF Devices
AN432: RX BER Measurement on EZRadioPRO with a Looped PN Sequ
e
AN435: Si4032/4432 PA Matching
AN436: Si4030/4031/4430/4431 PA Matching
AN437: 915 MHz Measurement Results and FCC Compliance
AN439: EZRadioPRO Quick Start Guide
AN440: Si4430/31/32 Register Descriptions
AN445: Si4431 RF Performance and ETSI Compliance
T
e
st Results
AN451: Wireless M-BUS Software Implementation
AN459: 950 MHz Measurement Results and ARIB
mpliance
AN460: 470 MHz Measurement Results for C
a
AN463: Support for Non-Standard Packet
uctures and RAW Mode
AN466: Si4030/31/32 Register Description
AN467: Si4330 Register Descriptions
AN514: Using the EZLink Refere
e Design to Create a Two-Channel PWM Motor Control Circuit
AN539: EZMacPRO Overview
32.11. Customer
Support
T
e
chnical support for the complete family of Silicon Labs wireless products is available by accessing the
wireless section of the Silicon Labs’ website at
www.silabs.com/wireless
. For MCU support, please visit
For answers to common questions please visit the wireless and mcu knowledge base at
Rev. 1.0
479
Si102x/3x
32.12. Register
Table and Descriptions
Table 32.9. EZRadioPRO Internal Register Descriptions
Add R/W
Function/Desc
Data
D4
dt[4]
vc[4]
headerr
irxffafull
irssi
enrxffafull
enrssi
POR
Default
D7
0
0
ffovfl
ifferr
iswdet
enfferr
enswdet
swres
D6
0
0
D5
0
0
D3
dt[3]
vc[3]
reserved
iext
D2
dt[2]
vc[2]
reserved
ipksent
ilbd
enpksent
enlbd
rxon
D1
dt[1]
vc[1]
D0
dt[0]
vc[0
cps[0
icrcerror
ipor
encrcerror
enpor
xton
00
01
02
03
04
05
06
07
R
R
R
R
R
Device Type
Device Version
Device Status
Interrupt Status 1
Interrupt Status 2
Interrupt Enable 1
Interrupt Enable 2
00111
07h
—
—
—
00h
03h
01h
ffunfl
rxffem
itxffaem
ipreainval
entxffaem
enpreainval
enwt
cps[1]
itxffafull
ipreaval
entxffafull
enpreaval
enlbd
ipkvalid
ichiprdy
enpkvalid
enchip
llon
iwut
R/W
R/W
enext
enwut
txon
R/W Operating
& Function Con-
x32ksel
trol 1
R/W Operating
& Function Con-
trol 2
08
09
antdiv[2]
xtalshft
antdiv[1]
xlc[6]
antdiv[0]
xlc[5]
rxmpk
xlc[4]
autotx
xlc[3]
enldm
xlc[2
xlc[1]
ffclrtx
xlc[0]
00h
7Fh
R/W
Crystal Oscillator Load
Capacitance
0A
0B
0C
0D
0E
0F
R/W Microcontroller
Output Clock
Reserved
gpio0drv[1]
gpio1drv[1]
gpio2drv[1]
Reserved
adcstart/
adc-
done
Reserved
gpio0drv[0]
gpio1drv[0]
gpio2drv[0]
extitst[2]
clkt[1]
pup0
pup1
pup2
extitst[1]
adcsel[1]
clkt[0]
gpio0[4]
gpio1[4]
gpio2[4]
extitst[0]
adcsel[0]
enlfc
gpio0[3]
gpio1[3]
gpio2[3]
itsdo
mclk[2]
gpio0
2]
gpio1[2]
gpio2[2]
dio2
mclk[1]
gpio0[1]
gpio1[1]
gpio2[1]
dio1
mclk[0]
gpio0[0]
gpio1[0]
gpio2[0]
dio0
06h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
GPIO0 Configuration
GPIO1 Configuration
GPIO2 Configuration
I/O Port Configuration
ADC Configuration
adcsel[2]
adcref[1]
adcref[0]
adcgain[1]
adcgain[0]
10
11
12
13
14
15
16
17
18
19
R/W ADC
Sensor Amplifier Offset
ADC Value
R/W
T
e
mperature
Sensor Control
R/W
T
e
mperature
Value Offset
Reserved
adc[7]
tsrange[1]
tvoffs[7]
Reserved
wtm[15]
wtm[7]
wtv[15]
wtv[7]
ldc[7]
Reserved
adc[6]
Reserved
adc[5]
Reserved
adc[4]
en
tvo
wtr[4]
wtm[12]
wtm[4]
wtv[12]
wtv[4]
adcoffs[3]
adc[3]
tstrim[3]
tvoffs[3]
wtr[3]
wtm[11]
wtm[3]
wtv[11]
wtv[3]
adcoffs[2]
adc[2]
tstrim[2]
tvoffs[2]
wtr[2]
wtm[10]
wtm[2]
wtv[10]
wtv[2]
adcoffs[1]
adc[1]
tstrim[1]
tvoffs[1]
wtr[1]
wtm[9]
wtm[1]
wtv[9]
adcoffs[0]
adc[0]
tstrim[0]
tvoffs[0]
wtr[0]
wtm[8]
wtm[0]
wtv[8]
00h
—
R
tsrange[0]
tvoffs[6]
Reserved
wtm[14]
wtm[6]
wtv[14]
wtv[6]
ldc[6]
entsoffs
tvoffs[5]
Reserved
wtm[13]
wtm[
wtv[
[5]
dc[5]
20h
00h
03h
00h
01h
—
R/W
R/W
R/W
R
Wake-Up Timer Period 1
Wake-Up Timer Period 2
Wake-Up Timer Period 3
Wake-Up Timer Value 1
Wake-Up Timer Value 2
R
wtv[1]
ldc[1]
wtv[0]
ldc[0]
—
00h
R/W Low-Duty
Cycle Mode Dura-
tion
ldc[4]
ldc[3]
ldc[2]
1A
R/W
Low Battery Detector
Threshold
Reserved
Reserve
Reserved
lbdt[4]
lbdt[3]
lbdt[2]
lbdt[1]
lbdt[0]
14h
1B
1C
1D
R
R/W
Battery Voltage Level
IF Filter Bandwidth
0
0
0
vbat[4]
ndec[0]
vbat[3]
filset[3]
vbat[2]
filset[2]
vbat[1]
filset[1]
matap
vbat[0]
filset[0]
ph0size
—
01h
40h
dwn3_bypass
afcbd
ndec[2]
enafc
ndec[1]
afcgearh[2]
R/W AFC
Loop Gearshift Over-
ride
afcgearh[1] afcgearh[0]
1p5 bypass
1E
1F
R/W
R/W
AFC Timing Control
Clock Recovery
Gearshift Override
Clock Recovery
Oversampling Ratio
Clock Recovery
Offset 2
Clock Recovery
Offset 1
Clock Rec
very
Offset 0
Cloc
covery
ming
oop Gain 1
lock Recovery
iming Loop Gain 0
Re
eived Signal Strength
Indicator
swait_timer[1] swait_timer[0]
shwait[2]
crfast[2]
shwait[1]
crfast[1]
shwait[0]
crfast[0]
anwait[2]
crslow[2]
anwait[1]
crslow[1]
anwait[0]
crslow[0]
0Ah
03h
Reserve
rxosr[7]
rxosr[10]
ncoff[15]
ncoff[7]
Reserved
rxosr[6]
rxosr[9]
ncoff[14]
ncoff[6]
Reserved
crgain[6]
rssi[6]
20
21
22
23
24
25
26
27
R/W
R/W
R/W
R/W
R/W
R/W
R
rxosr[5]
rxosr[8]
ncoff[13]
ncoff[5]
Reserved
crgain[5]
rssi[5]
rxosr[4]
stallctrl
rxosr[3]
ncoff[19]
ncoff[11]
ncoff[3]
crgain2x
crgain[3]
rssi[3]
rxosr[2]
ncoff[18]
ncoff[10]
ncoff[2]
rxosr[1]
ncoff[17]
ncoff[9]
ncoff[1]
crgain[9]
crgain[1]
rssi[1]
rxosr[0]
ncoff[16]
ncoff[8]
ncoff[0]
crgain[8]
crgain[0]
rssi[0]
64h
01h
47h
AEh
02h
8Fh
—
ncoff[12]
ncoff[4]
Reserved
crgain[7]
rssi[7]
rxncocomp
crgain[4]
rssi[4]
crgain[10]
crgain[2]
rssi[2]
R/W
RSSI Threshold for Clear
Channel
rssith[7]
rssith[6]
rssith[5]
rssith[4]
rssith[3]
rssith[2]
rssith[1]
rssith[0]
1Eh
Indicator
28
29
2A
2B
2C
2D
2E
2F
R
R
Antenna Diversity Register 1
Antenna Diversity Register 2
AFC Limiter
adrssi1[7]
adrssib[7]
Afclim[7]
afc_corr[9]
afc_corr[9]
ookcnt[7]
Reserved
adrssia[6]
adrssib[6]
Afclim[6]
afc_corr[8]
afc_corr[9]
ookcnt[6]
attack[2]
adrssia[5]
adrssib[5]
Afclim[5]
afc_corr[7]
ookfrzen
ookcnt[5]
attack[1]
adrssia[4]
adrssib[4]
Afclim[4]
afc_corr[6]
peakdeten
ookcnt[4]
attack[0]
adrssia[3]
adrssib[3]
Afclim[3]
adrssia[2]
adrssib[2]
Afclim[2]
adrssia[1]
adrssib[1]
Afclim[1]
adrssia[0]
adrssib[0]
Afclim[0]
afc_corr[2]
ookcnt[8]
ookcnt[0]
decay[0]
—
—
R/W
R
R/W
R/W
R/W
00h
00h
18h
BCh
26h
AFC Correction Read
OOK Counter Value 1
OOK Counter Value 2
Slicer Peak Hold
afc_corr[5] afc_corr[4] afc_corr[3]
madeten
ookcnt[3]
decay[3]
ookcnt[10]
ookcnt[2]
decay[2]
ookcnt[9]
ookcnt[1]
decay[1]
Reserved
480
Rev. 1.0
Si102x/3x
Table 32.9. EZRadioPRO Internal Register Descriptions (Continued)
Add R/W
Function/Desc
Data
D4
skip2ph
pkrx
POR
Default
D7
enpacrx
0
D6
lsbfrst
rxcrc1
D5
crcdonly
pksrch
D3
enpactx
pkvalid
D2
encrc
crcerror
D1
crc[1]
pktx
D0
crc[0]
pksent
30
31
R/W
R
Data Access Control
EzMAC status
8Dh
—
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
R/W
R/W
R/W
Header Control 1
Header Control 2
Preamble Length
bcen[3:0]
hdch[3:0]
0Ch
22h
08h
Ah
2Dh
D4h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
—
skipsyn
prealen[7]
preath[4]
sync[31]
sync[23]
sync[15]
sync[7]
txhd[31]
txhd[23]
txhd[15]
txhd[7]
pklen[7]
chhd[31]
chhd[23]
chhd[15]
chhd[7]
hden[31]
hden[23]
hden[15]
hden[7]
rxhd[31]
rxhd[23]
rxhd[15]
rxhd[7]
hdlen[2]
prealen[6]
preath[3]
sync[30]
sync[22]
sync[14]
sync[6]
hdlen[1]
prealen[5]
preath[2]
sync[29]
sync[21]
sync[13]
sync[5]
hdlen[0]
prealen[4]
preath[1]
sync[28]
sync[20]
sync[12]
sync[4]
txhd[28]
txhd[20]
txhd[12]
txhd[4]
pklen[4]
chhd[28]
chhd[20]
chhd[12]
chhd[4]
hden[28]
hden[20]
hden[12]
hden[4]
rxhd[28]
rxh
]
rx
rxhd
fixpklen
prealen[3]
preath[0]
sync[27]
sync[19]
sync[11]
sync[3]
txhd[27]
txhd[19]
txhd[11]
txhd[3]
pklen[3]
chhd[27]
chhd[19]
chhd[11]
chhd[3]
hden[27]
den[19
hden[11]
hden[3]
rxhd[27]
rxhd[19]
rxhd[11]
rxhd[3]
synclen[1]
prealen[2]
rssi_off[2]
sync[26]
sync[18]
sync[10]
sync[2]
synclen[0]
prealen[1]
rssi_off[1]
sync[25]
sync[17]
sync[9]
prealen[8
preale
rssi_off
sync[24]
sync[16]
sync[8]
R/W Preamble
Detection Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Sync Word 3
Sync Word 2
Sync Word 1
Sync Word 0
sync[
sync[0]
Transmit Header 3
Transmit Header 2
Transmit Header 1
Transmit Header 0
Transmit Packet Length
Check Header 3
Check Header 2
Check Header 1
Check Header 0
Header Enable 3
Header Enable 2
Header Enable 1
Header Enable 0
Received Header 3
Received Header 2
Received Header 1
Received Header 0
Received Packet Length
txhd[30]
txhd[22]
txhd[14]
txhd[6]
pklen[6]
chhd[30]
chhd[22]
chhd[14]
chhd[6]
hden[30]
hden[22]
hden[14]
hden[6]
rxhd[30]
rxhd[22]
rxhd[14]
rxhd[6]
txhd[29]
txhd[21]
txhd[13]
txhd[5]
pklen[5]
chhd[29]
chhd[21]
chhd[13]
chhd[5]
hden[29]
hden[21]
hden[13]
hden[5]
rxhd[29]
rxhd[21]
rxhd[13]
rxhd[5]
txhd[26]
txhd[18]
txhd[10]
txhd[2]
d[25
7]
9]
txhd[24]
txhd[16]
txhd[8]
d[1]
txhd[0]
pklen[2]
chh
[26]
chhd
18]
hhd[10]
c
hd[2]
hden[26]
hden[18]
hden[10]
hden[2]
rxhd[26]
rxhd[18]
rxhd[10]
rxhd[2]
pklen[1]
chhd[25]
chhd[17]
chhd[9]
chhd[1]
hden[25]
hden[17]
hden[9]
hden[1]
rxhd[25]
rxhd[17]
rxhd[9]
pklen[0]
chhd[24]
chhd[16]
chhd[8]
chhd[0]
hden[24]
hden[16]
hden[8]
hden[0]
rxhd[24]
rxhd[16]
rxhd[8]
45
46
47
48
R
R
R
R
—
—
—
—
49
4A
4B
4C-4E
4F
50-5F
60
rxhd[1]
rxhd[0]
rxplen[0]
rxplen[7]
rxplen[6]
rxplen[5]
rxplen[4]
rxplen[3]
rxplen[2]
rxplen[1]
Re
rved
adc8
R
ed
R/W
R/W
ADC8 Control
Reserved
Reserved
adc8[4]
adc8[3]
adc8[2]
adc8[1]
adc8[0]
10h
00h
Channel Filter Coefficient
Address
Inv_pre_th[3]
Inv_pre_th[2] In
re_th[1] Inv_pre_th[0]
chfiladd[3]
chfiladd[2]
chfiladd[1]
chfiladd[0]
61
62
Reserved
R/W
Crystal Oscillator/
Control
T
e
st
pwst[2]
pwst[1]
pwst[0]
Reserved
Reserved
txdr[13]
txdr[5]
clkhyst
enbias2x
enamp2x
bufovr
enbuf
24h
63-6C
6D
6E
6F
70
71
72
73
74
75
R/W
R/W
R/W
TX Power
TX Data Rate 1
TX Data Rate 0
Reserved
txdr[15]
txdr[7]
Reserved
trcl
[1]
fd[7]
fo[7]
Reserved
Reserved
fc[15]
eserved
tx
r[14]
txdr[6]
Reserved
trclk[0]
fd[6]
fo[6]
Reserved
sbsel
Reserved
txdr[12]
txdr[4]
Ina_sw
txdr[11]
txdr[3]
manppol
eninv
fd[3]
fo[3]
Reserved
fb[3]
fc[11]
txpow[2]
txdr[10]
txdr[2]
enmaninv
fd[8]
fd[2]
fo[2]
Reserved
fb[2]
fc[10]
txpow[1]
txdr[9]
txdr[1]
enmanch
modtyp[1]
fd[1]
fo[1]
fo[9]
fb[1]
fc[9]
txpow[0]
txdr[8]
txdr[0]
enwhite
modtyp[0]
fd[0]
fo[0]
fo[8]
fb[0]
fc[8]
18h
0Ah
3Dh
0Ch
00h
20h
00h
00h
75h
BBh
R/W Modulation
Mode Control 1
R/W Modulation
Mode Control 2
R/W
R/W
R/W
R/W
txdtrtscale
dtmod[1]
fd[5]
enphpwdn
dtmod[0]
fd[4]
Frequency Deviation
Frequency Offset 1
Frequency Offset 2
Frequency Band Sele
fo[5]
Reserved
hbsel
fo[4]
Reserved
fb[4]
76
R/W Nominal
Carrier Freq
fc[14]
fc[13]
fc[12]
1
77
R/W Nominal
Carrier Frequ
ncy
0
fc[7]
fc[6]
fc[5]
fc[4]
fc[3]
fc[2]
fc[1]
fc[0]
80h
78
79
Reserved
fhch[5]
R/W Fr
ncy
opping Chan-
nel Select
fhch[7]
fhs[7]
fhch[6]
fhs[6]
fhch[4]
fhs[4]
fhch[3]
fhs[3]
fhch[2]
fhs[2]
fhch[1]
fhs[1]
fhch[0]
fhs[0]
00h
00h
7A
R/W
quency Hopping Step
Size
fhs[5]
7B
7C
7D
7E
7F
Reserved
R/W
R/W
TX FIFO Control 1
TX FIFO Control 2
RX FIFO Control
FIFO Access
Reserved
Reserved
Reserved
fifod[7]
Reserved
Reserved
Reserved
fifod[6]
txafthr[5]
txaethr[5]
rxafthr[5]
fifod[5]
txafthr[4]
txaethr[4]
rxafthr[4]
fifod[4]
txafthr[3]
txaethr[3]
rxafthr[3]
fifod[3]
txafthr[2]
txaethr[2]
rxafthr[2]
fifod[2]
txafthr[1]
txaethr[1]
rxafthr[1]
fifod[1]
txafthr[0]
txaethr[0]
rxafthr[0]
fifod[0]
37h
04h
37h
—
Note:
Detailed register descriptions are available in “AN440: EZRadioPRO Detailed Register Descriptions.
Rev. 1.0
481
Si102x/3x
32.13. Required
Changes to Default Register Values
The following register writes should be performed during device initialization.
1. The
value 0x40 should be written to Register 59h.
2. If
the device will be operated in the 240–320 MHz or 480–640 MHz bands at a temperature above
60 °C, then Register 59h should be written to 0x43 and Register 5Ah should be written to 0x02.
482
Rev. 1.0
Si102x/3x
33. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 2 a
Timer 3 have a Capture Mode that can be used to measure the SmaRTClock, Comparator, or externa
clock period with respect to another oscillator. The ability to measure the Comparator period with respect
to another oscillator is particularly useful when interfacing to capacitive sensors.
Timer 0 and Timer 1 Modes:
13-bit counter/timer
Timer 2 Modes:
Timer
es:
16-bit timer with auto-reload
16-bit timer with auto-reload
16-bit counter/timer
8-bit counter/timer with auto-
reload
Two 8-bit timers with auto-reload
Two 8
bit timers with auto-reload
Two 8-bit counter/timers (Timer 0
only)
Timers 0 and 1 may be clocked by one of five sources, deter
ed by the Timer Mode Select bits (T1M
–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Sca
its define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 33.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-s
d clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12. Timer 2 may additionally be
clocked by the SmaRTClock divided by 8 or the
omparator0 output. Timer 3 may additionally be clocked
by the external oscillator clock source divide
8 or the Comparator1 output.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a fre-
quency of up to one-fourth the syste
clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Rev. 1.0
483
Si102x/3x
SFR Definition 33.1. CKCON: Clock Control
Bit
7
T3MH
R/W
0
6
T3ML
R/W
0
5
T2MH
R/W
0
4
T2ML
R/W
0
3
2
1
0
Name
Type
Reset
T1M
R/W
0
T0M
R/W
0
SCA[1:0]
R/W
0
0
SFR Page = 0x0; SFR Address = 0x8E
Bit
Name
Function
7
T3MH
Timer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
0: Timer 3 high byte uses the clock defined by the T3XCLK
t in TMR3CN.
1: Timer 3 high byte uses the system clock.
6
T3ML
Timer 3 Low Byte Clock Select.
Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined b
T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5
4
T2MH
Timer 2 High Byte Clock Select.
Selects the clock supplied to the
imer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the cl
ck defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses t
ystem clock.
T2ML
Timer 2 Low Byte Clock Select.
Selects the clock s
plied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3
2
T1M
T
Timer 1 Clock Select.
Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to 1.
0
er 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
Timer 0 Clock Select.
Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0 SCA[1:0]
Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Clock Prescaler:
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
484
Rev. 1.0
Si102x/3x
33.1. Timer
0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis-
ter (Section “17.5. Interrupt Register Descriptions” on page 234); Timer 1 interrupts can be enabled by set-
ting the ET1 bit in the IE register (Section “17.5.
Interrupt Register Descriptions” on page
234). Bot
counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1
–
T0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described below.
33.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describ
configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is config
in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4
–
TL0.0. The three upper bits of TL0 (TL0.7
–
TL0.5) are indeterminate a
d should be masked out or
ignored when reading. As the 13-bit timer register increments and overflo
s from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit (TMOD.2) selects the counter/timer’s clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer
0 input pin (T0) increm
the timer register (Refer to Section
“27.3. Priority Crossbar Decoder” on page 355 for information
n selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Ti
er 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 33.1).
Setting the TR0 bit (TCON.4) enables the timer w
en either GATE0 (TMOD.3) is logic 0 or the input signal
INT0 is active as defined by bit IN0PL in re
r IT01CF (see SFR Definition 17.7). Setting GATE0 to 1
allows the timer to be controlled by the exter
al input signal INT0 (see Section “17.5. Interrupt Register
Descriptions” on page 234), facilitating pulse width measurements
Table 33.1. Timer 0 Running Modes
TR0
GATE0
INT0
Counter/Timer
Disabled
0
X
0
1
1
X
X
0
1
1
Enabled
1
Disabled
1
Enabled
Note:
X = Don’t Care
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
alue before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 17.7).
Rev. 1.0
485
Si102x/3x
CKCON
TMOD
IT01CF
G
A
T
E
1
C
/
T
1
T
1
M
1
T
1
M
0
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
I
I
I
I
I
I
I
N
0
S
L
1
I
T
3
T
3
T
2
T
2
T
1
T
S S
0 C C
N
1
P
L
N
1
S
L
2
N
1
S
L
1
N
1
S
L
0
N
0
P
L
N
0
S
L
2
N
0
S
L
0
M M M M M M A A
L H
H
L
1 0
Pre-scaled Clock
0
1
0
1
SYSCLK
T0
Interrupt
TCLK
TL0
(5 bits)
TH0
(8 bits)
TR0
I
GATE0
IE0
IT0
Crossbar
IN0PL
XOR
INT0
Figure 33.1. T0 Mode 0 Block Diagram
33.1.2. Mode 1: 16-bit Counter/Timer
Mode 1
operation is the same as Mode
0, except that
he
ter/timer registers use all 16
bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
33.1.3. Mode 2: 8-bit Counter/Timer with Auto-Relo
d
Mode 2 configures Timer 0 and Timer 1 to operate as 8
t counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the r
oad value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TC
N.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt w
ccur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 op
ates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0
is active as defined by bit IN0PL in register IT01CF (see Section “17.6. External Interrupts INT0 and INT1”
on page 241 for details on the external input signals INT0 and INT1).
486
Rev. 1.0
Si102x/3x
CKCON
TMOD
IT01CF
G C T T G C T T
I I I I I I I I
N N N N N N N N
T T T T T T S S
3 3 2 2 1 0 C C
M M M M M M A A
A
/
1
1 A
/
0
0
T T M
M T T M M
1
1 1 1 0 0 0 0
E
1
1
1
0 E
0
0
1
0
P S S S P S S S
H L H L
1 0
L
L
2
L
1
L
0
L
L
2
L
1
L
0
Pre-scaled Clock
SYSCLK
0
1
0
1
T0
T
TR1
TCLK
TL0
(8 bits)
Interrupt
TF0
TR0
IE1
IT1
TR0
IE0
IT0
Crossbar
GATE0
TH0
R
ad
(8 bits)
IN0PL
XOR
INT0
Figure 33.2. T0 Mode 2 Block Diagram
33.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0
y)
In Mode
3, Timer
0 is configured as two sep
ate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the
er 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the syst
clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1.
H0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UAR
T
,
a
nd/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode set-
tings.
T
o
r
un Timer
hile Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2.
T
o
d
isable Timer 1,
configure it for Mod
Rev. 1.0
487
Si102x/3x
CKCON
TMOD
G C
T
1
T
1
G C
T
0
T
0
T T T T T T S S
3 3 2 2 1 0 C C
M M M M M M A A
A
T
E
1
/
A
T
E
0
/
T M M
1
T M M
0 1 0
1
0
H L H L
1 0
Pre-scaled Clock
0
1
TH0
(8 bits)
TR1
Inter
upt
Interrupt
TF1
TR1
TF0
TR0
IE1
SYSCLK
0
1
IT1
IE0
0
T0
TL0
(8 bits)
TR0
Crossbar
GATE0
IN0PL
XOR
INT0
Figure 33.3. T0 Mode 3 Blo
Diagram
488
Rev. 1.0
Si102x/3x
SFR Definition 33.2. TCON: Timer Control
Bit
7
6
5
4
3
IE1
R/W
0
2
IT1
R/W
0
1
IE0
R/W
0
0
IT0
R/W
0
Name
Type
Reset
TF1
R/W
0
TR1
R/W
0
TF0
R/W
0
TR0
R/W
0
SFR Page = All Pages; SFR Address = 0x88; Bit-Addressable
Bit
Name
Function
7
TF1
Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to th
imer 1 interrupt service
routine.
6
5
TR1
TF0
Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4
3
TR0
IE1
Timer 0 Run Control.
Timer 0 is enabled by set
ng this bit to 1.
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared
software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2
IT1
Interrup
1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
FR Definition 17.7).
INT1 is level triggered.
1: INT1 is edge triggered.
1
0
0
IT0
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 17.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
Rev. 1.0
489
Si102x/3x
SFR Definition 33.3. TMOD: Timer Mode
Bit
7
GATE1
R/W
0
6
5
4
3
GATE0
R/W
0
2
1
0
Name
Type
Reset
C/T1
R/W
0
T1M[1:0]
R/W
C/T0
R/W
0
T0M[1:0]
R/W
0
0
0
0
SFR Page = 0x0; SFR Address = 0x89
Bit
Name
Function
7
GATE1
Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is acti
as defined by bit IN1PL in
register IT01CF (see SFR Definition 17.7).
6
C/T1
Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4
T1M[1:0]
Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Time
01: Mode 1, 16-bit Counter/T
er
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Ina
3
GATE0
C/T0
Timer 0 Gate Control.
0: Timer 0 enab
when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 17.7).
2
Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0
T0M[1:0]
imer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counter/Timers
490
Rev. 1.0
Si102x/3x
SFR Definition 33.4. TL0: Timer 0 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TL0[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8A
Bit
Name
Function
7:0
TL0[7:0]
Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 33.5. TL1: Timer 1 Low Byte
Bit
7
6
5
4
2
1
0
Name
Type
Reset
TL1[7:0]
W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8B
Bit
Name
Function
7:0
TL1[7:0]
Timer 1 Low B
e.
The TL1 register is the low byte of the 16-bit Timer 1.
Rev. 1.0
491
Si102x/3x
SFR Definition 33.6. TH0: Timer 0 High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TH0[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8C
Bit
Name
Function
7:0
TH0[7:0]
Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 33.7. TH1: Timer 1 High Byte
Bit
7
6
5
4
2
1
0
Name
Type
Reset
TH1[7:0]
W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8D
Bit
Name
Function
7:0
TH1[7:0]
Timer 1 High B
e.
The TH1 register is the high byte of the 16-bit Timer 1.
492
Rev. 1.0
Si102x/3x
33.2. Timer
2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in Capture Mode to measure the SmaRTClock or
the Comparator 0 period with respect to another oscillator. The ability to measure the Comparator 0 period
with respect to the system clock is makes using
T
o
uch Sense Switches very easy.
Timer 2 may be clocked by the system clock, the system clock divided by 12, SmaRTClock divided by 8, o
Comparator 0 output. Note that the SmaRTClock divided by 8 and Comparator 0 output is synchronized
with the system clock.
33.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-relo
mer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8, or Comparator
output. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 33.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 inte
upts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if T
mer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
MMMMMMA A
T2XCLK[1:0]
00
H L H L
1 0
SYSCLK / 12
To ADC,
SMBus
To SMBus
TMR2H
TL2
Overflow
0
1
01
11
SmaRTClock / 8
Comparator 0
TCLK
TR2
TF2H
TMR2L
Interrupt
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
SYSCLK
T2XCLK
TMR2RLL TMR2RLH
Reload
Figure 33.4. Timer 2 16-Bit Mode Block Diagram
Rev. 1.0
493
Si102x/3x
33.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 33.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8
Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK
the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
T2MH
T2XCLK[1:0]
TMR2H Clock
Source
T2ML
T2XCLK[1:0]
TMR
Clock
Source
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
SmaRTClock / 8
Reserved
0
0
0
0
1
00
01
10
1
X
SY
LK / 12
SmaRTClock / 8
Reserved
Comparator 0
SYSCLK
Comparator 0
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer
2 interrupts are enabled (
), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LE
TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the T
er 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cl
d by software.
CKC
T T T T
3 3 2 2 1
C
T2XCLK[1:0]
MMMMMM A A
Reload
TMR2RLH
To SMBus
H L H L
1 0
SYSCLK / 12
00
0
01
11
SmaRTClock / 8
Comparator 0
TCLK
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
TMR2H
Interrupt
TR2
1
Reload
TMR2RLL
T2XCLK
SYSCLK
1
0
To ADC,
SMBus
TCLK
TMR2L
Figure 33.5. Timer 2 8-Bit Mode Block Diagram
3.2.3. Comparator 0/SmaRTClock Capture Mode
The Capture Mode in Timer 2 allows either Comparator 0 or the SmaRTClock period to be measured
against the system clock or the system clock divided by 12. Comparator 0 and the SmaRTClock period can
also be compared against each other. Timer 2 Capture Mode is enabled by setting TF2CEN to 1. Timer 2
should be in 16-bit auto-reload mode when using Capture Mode.
494
Rev. 1.0
Si102x/3x
When Capture Mode is enabled, a capture event will be generated either every Comparator 0 rising edge
or every 8 SmaRTClock clock cycles, depending on the T2XCLK1 setting. When the capture event occurs,
the contents of Timer
2
(TMR2H:TMR2L) are loaded into the Timer
2 reload registers
(TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 interrupts are enabled).
By recording the difference between two successive timer capture values, the Comparator 0 or SmaRT-
Clock period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster
than the capture clock to achieve an accurate reading.
For example, if T2ML = 1b, T2XCLK1 = 0b, and TF2CEN = 1b, Timer 2 will clock every SYSCLK and cap-
ture every SmaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two
successive captures is 5984, then the SmaRTClock clock is as follows:
24.5 MHz/(5984/8) = 0.032754 MHz or 32.754 kHz.
This mode allows software to determine the exact SmaRTClock frequency in self-oscilla
mode and the
time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the capaci-
tance of a
T
o
uch Sense Switch.
T2XCLK[1:0]
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
MMMMMM A A
SYSCLK / 12
Comparator 0
X0
H L H L
1 0
01
11
0
1
SmaRTClock / 8
T
TR2
TMR2L
TMR2H
Capture
SYSCLK
T2XCLK1
TF2CEN
TF2H
TF2L
Interrupt
TMR2RLL TMR2RLH
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK1
T2XCLK0
SmaRTClock / 8
Comparator 0
0
1
Figure 33.6. Timer 2 Capture Mode Block Diagram
Rev. 1.0
495
Si102x/3x
SFR Definition 33.8. TMR2CN: Timer 2 Control
Bit
7
TF2H
R/W
0
6
TF2L
R/W
0
5
TF2LEN
R/W
0
4
3
2
1
0
Name
Type
Reset
TF2CEN T2SPLIT
TR2
R/W
0
T2XCLK[1:0]
R/W
R/W
0
R/W
0
0
0
SFR Page = 0x0; SFR Address = 0xC8; Bit-Addressable
Bit
Name
Function
7
TF2H
Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0x
FF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the
Timer 2 interrupt service routine. This bit is not automatically cleared by hardware.
6
5
TF2L
Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows reg
ess of the Timer 2 mode. This bit is not
automatically cleared by hardware.
TF2LEN
Timer 2 Low Byte Interrupt E
ble.
When set to 1, this bit enables
er 2 Low Byte interrupts. If Timer 2 interrupts
are also enabled, an inter
pt will be generated when the low byte of Timer 2 over-
flows.
4
3
TF2CEN
T2SPLIT
Timer 2 Capture Enable.
When set to 1, this bit enables Timer 2 Capture Mode.
Timer 2 Split Mode Enable.
When set to 1, Timer 2 operates as two 8-bit timers with auto-reload. Otherwise,
Timer 2 operates in 16-bit auto-reload mode.
2
TR2
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
1:0 T2XCLK[1:0]
Timer 2 External Clock Select.
This bit selects the “external” and “capture trigger” clock sources for Timer 2. If
Timer 2 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK/12. Capture trigger is SmaRTClock/8.
01: External Clock is Comparator 0. Capture trigger is SmaRTClock/8.
10: External Clock is SYSCLK/12. Capture trigger is Comparator 0.
11: External Clock is SmaRTClock/8. Capture trigger is Comparator 0.
496
Rev. 1.0
Si102x/3x
SFR Definition 33.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR2RLL[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCA
Bit Name
Function
7:0 TMR2RLL[7:0]
Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 33.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit
7
6
5
4
2
1
0
Name
Type
Reset
TMR2RLH[7:0]
W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCB
Bit Name
Function
7:0 TMR2RLH[7:0]
Timer 2 Relo
Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
Rev. 1.0
497
Si102x/3x
SFR Definition 33.11. TMR2L: Timer 2 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR2L[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCC
Bit Name
7:0 TMR2L[7:0]
Timer 2 Low Byte.
Function
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value
SFR Definition 33.12. TMR2H Timer 2 High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TM
2H[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCD
Bit Name
7:0 TMR2H[7:0]
Timer 2 Low Byte.
Function
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
498
Rev. 1.0
Si102x/3x
33.3. Timer
3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR2CN.3) defines
the Timer 3 operation mode. Timer 3 can also be used in Capture Mode to measure the external oscillator
source or the SmaRTClock oscillator period with respect to another oscillator.
Timer 3 may be clocked by the system clock, the system clock divided by 12, external oscillator sour
divided by 8, or the SmaRTClock oscillator. The external oscillator source divided by 8 and SmaRTCloc
oscillator is synchronized with the system clock.
33.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reloa
imer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, external oscillator clock source divided by
maRTClock
oscillator. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, th
16-bit value in
the Timer 3 reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in
Figure 33.7, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled
(if EIE1.7 is set), an interrupt will be generated on each Timer 3 overflow. Ad
onally, if Timer 3 interrupts
are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be gen
rated each time the lower 8
bits (TMR3L) overflow from 0xFF to 0x00.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
T3XCLK[1:0]
MMM MM M A A
H L H L
1 0
SYSCLK / 12
External Clock / 8
SmaRTClock
00
To ADC
0
01
11
T
TR3
TF3H
TF3L
TMR3L
TMR3H
Interrupt
TF3LEN
TF3CEN
T3SPLIT
TR3
1
T3XCLK1
T3XCLK0
SYSCLK
TMR3RLL TMR3RLH
Reload
Figure 33.7. Timer 3 16-Bit Mode Block Diagram
Rev. 1.0
499
Si102x/3x
33.3.2. 8-Bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 33.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clo
source divided by 8, or the SmaRTClock. The Timer 3 Clock Select bits (T3MH and T3ML in CKCO
select either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in
TMR3CN), as follows:
T3MH
T3XCLK[1:0]
TMR3H Clock
Source
T3ML
T3XCLK[1:0]
R3L Clock
ource
0
0
0
0
1
00
01
10
11
X
SYSCLK / 12
SmaRTClock
Reserved
0
0
0
0
1
00
01
11
X
SYSCLK / 12
SmaRTClock
Reserved
External Clock / 8
SYSCLK
External Clock / 8
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00
e TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an int
upt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3L
N is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 in
upt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually clear
by software.
CKCO
T T T T T T S S
3 3 2 2 1 0 C C
T3XCLK[1:0]
M M M M M A A
Reload
TMR3RLH
H L H L
1 0
SYSCLK / 12
SmaRTClock
00
0
1
01
11
TCLK
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
TMR3H
Interrupt
TR3
External Clock / 8
Reload
T3XCLK1
T3XCLK0
TMR3RLL
SYSCLK
1
0
TCLK
TMR3L
To ADC
Figure 33.8. Timer 3 8-Bit Mode Block Diagram
33.3.3. SmaRTClock/External Oscillator Capture Mode
The Capture Mode in Timer 3 allows either SmaRTClock or the external oscillator period to be measured
against the system clock or the system clock divided by 12. SmaRTClock and the external oscillator period
can also be compared against each other.
500
Rev. 1.0
Si102x/3x
Setting TF3CEN to 1 enables the SmaRTClock/External Oscillator Capture Mode for Timer 3. In this mode,
T3SPLIT should be set to 0, as the full 16-bit timer is used.
When Capture Mode is enabled, a capture event will be generated either every SmaRTClock rising edge
or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the
contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL)
and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are enabled). By recording the differ
ence between two successive timer capture values, the SmaRTClock or external clock period can
determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture
clock to achieve an accurate reading.
For example, if T3ML = 1b, T3XCLK1 = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSC
K and cap-
ture every SmaRTClock rising edge. If SYSCLK is 24.5 MHz and the difference betwe
o successive
captures is 350 counts, then the SmaRTClock period is as follows:
350 x (1 / 24.5 MHz) = 14.2 µs.
This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or
the time between consecutive SmaRTClock rising edges, which is useful for
termining the SmaRTClock
frequency.
T3XCLK[1:0]
CKCON
T T T T T T S S
3
3
2
2
1
0 C C
M M M M M M A A
SYSCLK/12
External Clock/8
SmaRTClock
X0
01
11
H L H L
1 0
0
1
TCLK
TR3
TMR3L
TMR3H
Capture
SYSCLK
T3XCLK1
F
3C
N
TF3H
TF3L
Interrupt
TMR3RLL TMR3RLH
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK1
T3XCLK0
SmaRTClock
0
External Clock/8
1
Figure 33.9. Timer 3 Capture Mode Block Diagram
Rev. 1.0
501
Si102x/3x
SFR Definition 33.13. TMR3CN: Timer 3 Control
Bit
7
TF3H
R/W
0
6
TF3L
R/W
0
5
TF3LEN
R/W
0
4
3
2
1
0
Name
Type
Reset
TF3CEN T3SPLIT
TR3
R/W
0
T3XCLK[1:0]
R/W
R/W
0
R/W
0
0
0
SFR Page = 0x0; SFR Address = 0x91
Bit
Name
Function
7
TF3H
Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xF
F to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6
5
TF3L
Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows rega
s of the Timer 3 mode. This bit is not
automatically cleared by hardware.
TF3LEN
Timer 3 Low Byte Interrupt En
le.
When set to 1, this bit enables Ti
r 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt w
be generated when the low byte of Timer 3 overflows.
4
3
TF3CEN
T3SPLIT
Timer 3 SmaRTClock
rnal Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Capture Mode.
Timer 3 Split
de Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
2
TR3
Timer 3 Run Control.
imer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
MR3H only; TMR3L is always enabled in split mode.
1:0 T3XCLK[1:0]
Timer 3 External Clock Select.
This bit selects the “external” and “capture trigger” clock sources for Timer 3. If
Timer 3 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK /12. Capture trigger is SmaRTClock.
01: External Clock is External Oscillator/8. Capture trigger is SmaRTClock.
10: External Clock is SYSCLK/12. Capture trigger is External Oscillator/8.
11: External Clock is SmaRTClock. Capture trigger is External Oscillator/8.
502
Rev. 1.0
Si102x/3x
SFR Definition 33.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR3RLL[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x92
Bit Name
Function
7:0 TMR3RLL[7:0]
Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 33.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit
7
6
5
4
2
1
0
Name
Type
Reset
TMR3RLH[7:0]
W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x93
Bit Name
Function
7:0 TMR3RLH[7:0]
Timer 3 Relo
Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
Rev. 1.0
503
Si102x/3x
SFR Definition 33.16. TMR3L: Timer 3 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TMR3L[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x94
Bit
Name
Function
7:0
TMR3L[7:0]
Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In
8-bit mode, TMR3L contains the 8-bit low byte timer v
e.
SFR Definition 33.17. TMR3H Timer 3 High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
TM
3H[7:0]
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x95
Bit
Name
Function
7:0
TMR3H[7:0]
Timer 3 High Byte.
In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In
8-bit mode, TMR3H contains the 8-bit high byte timer value.
504
Rev. 1.0
Si102x/3x
34. Programmable
Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between seven sources: system clock, system clock divided
four, system clock divided by twelve, the external oscillator clock source divided by 8, SmaRTClock divide
by 8, Timer 0 overflows, or an external clock signal on the ECI input pin. Each capture/compare module
may be configured to operate independently in one of six modes: Edge-Triggered Capture, Software Timer,
High-Speed Output, Frequency Output, 8 to 11-Bit PWM, or 16-Bit PWM (each mode is descr
ed in Sec-
tion “34.3. Capture/Compare Modules” on page 508). The external oscillator clock opti
deal for real-
time clock (RTC) functionality, allowing the PCA to be clocked by a precision external o
tor while the
internal oscillator drives the system clock. The PCA is configured and controlled through the system con-
troller’s Special Function Registers. The PCA block diagram is shown in Figure 34.1
Important Note:
The PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset.
Access to certain PCA registers is restricted w
ile WDT mode is enabled
.
See Section 34.4 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
PCA
CLOCK
MUX
16-Bit Counter/Timer
ECI
SYSCLK
External Clock/8
SmaRTClock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Capture/Compare
Module 5 / WDT
Crossbar
Port I/O
Figure 34.1. PCA Block Diagram
Rev. 1.0
505
Si102x/3x
34.1. PCA
Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB).
Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2
–
CPS0 bits in the PCA0M
register select the timebase for the counter/timer as shown in
T
a
ble 34.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not a
tomatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must
ared by soft-
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal o
ion while the
CPU is in Idle mode.
Table 34.1. PCA Timebase Input Options
CPS2
CPS1
CPS0
Timebase
System clock divided by 12
0
0
0
0
0
0
1
1
0
1
0
1
System clock divided by 4
Timer 0 overflow
High-to-low transition
on
(max rate = system clock divided
by 4)
1
1
0
0
0
1
System clock
1
External oscil
or source divided by 8
2
1
1
1
0
1
SmaRTC
ck oscillator source divided by 8
1
Reserved
Notes:
1.
External oscillator source
ided by 8
is
synchronized with the system clock.
2.
SmaRTClock oscillator source divided by 8
is
synchronized with the system clock.
506
Rev. 1.0
Si102x/3x
IDLE
PCA0MD
PCA0CN
C
W W
C C C E
I
D D
P P P C
D
T L
S S S F
L
E C
2 1 0
K
C C C C C C C C
F R C C C C C C
F F F F F F
5 4 3 2 1 0
To SFR Bus
PCA0L
read
Snapshot
Register
SYSCLK/12
SYSCLK/4
000
001
0
Timer 0 Overflow
ECI
Overflow
010
011
100
To PCA Interrupt System
PCA0H
PCA0L
1
CF
SYSCLK
External Clock/8
SmaRTClock/8
To PCA Modules
101
110
Figure 34.2. PCA Counter/Timer Block Diagram
34.2. PCA0
Interrupt Sources
Figure 34.3 shows a diagram of the PCA interrupt tre
There are eight independent event flags that can
be used to generate a PCA0 interrupt. They are: the
in PCA counter overflow flag (CF), which is set
upon a 16-bit overflow of the PCA0 counter, an in
rmediate overflow flag (COVF), which can be set on an
overflow from the 8th, 9th, 10th, or 11th bit o
the PCA0 counter, and the individual flags for each PCA
channel (CCF0, CCF1, CCF2, CCF3, CCF4,
CCF5), which are set according to the operation mode of
that module. These event flags are always set when the trigger condition occurs. Each of these flags can
be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF
for C
F
,
E
COV for COV
F
,
a
nd ECCFn
or each CCFn). PCA0 interrupts must be globally enabled before any
individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by set-
ting the EA bit and the EPCA0 bit to logic 1.
Rev. 1.0
507
Si102x/3x
(for n = 0 to 5)
PCA0CPMn
PCA0CN
PCA0MD
PCA0PWM
P
E C C M T
P
E
W
C A A A O
W
C
M
O P P T G
M
C
1
M P N n n
n
F
C C C C C C C C
F R C C C C C C
F F F F F F
C WW
C C C E
I D
D P
P P C
D T L
S S S F
L E C
2 1 0
K
A
C E
C
C
L
L
S
S
E
E
L
L
1
0
R
O C
S
V O
E
F V
L
5 4 3 2 1 0
6
n n n
n
n
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
Set 8, 9, 10, or 11 bit Operation
EPCA0
0
1
PCA Counter/Timer 16-
bit Overflow
0
1
EA
ECCF0
Interrupt
Priority
Decoder
0
1
0
0
1
PCA Module 0
(CCF0)
ECCF1
ECCF2
ECCF3
ECCF4
ECCF5
0
1
PCA Module 1
(CCF1)
0
1
PCA Module 2
(CCF2)
0
1
PCA Module 3
(CCF3)
0
1
PCA Module 4
(CCF4)
0
1
PCA Module 5
(CCF5)
Figure 34.3. P
Interrupt Block Diagram
34.3. Capture/Compare
Mod
es
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit
pulse width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-
51 system controller. These registers are used to exchange data with a module and configure the module’s
mode of operation.
T
a
ble 34.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM registers
used to select the
capture/compare module’s operating mode. Note that all modules set to use 8, 9,
10, or 11-bit PWM
ode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module’s CCFn interrupt.
Ta
34.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode
PCA0CPMn
PCA0PWM
Bit Number
7 6 5 4 3 2 1 0 7 6 5
4–2 1–0
Capture triggered by positive edge on CEXn
Capture triggered by negative edge on CEXn
Capture triggered by any transition on CEXn
X X 1 0 0 0 0 A 0 X B XXX
XX
X X 0 1 0 0 0 A 0 X B XXX
XX
X X 1 1 0 0 0 A 0 X B XXX
XX
508
Rev. 1.0
Si102x/3x
Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode
PCA0CPMn
PCA0PWM
Software Timer
X C 0 0 1 0 0 A 0 X B XXX
XX
X C 0 0 1 1 0 A 0 X B XXX
XX
X C 0 0 0 1 1 A 0 X B XXX
XX
0 C 0 0 E 0 1 A 0 X B XXX
00
0 C 0 0 E 0 1 A D X B XXX
01
0 C 0 0 E 0 1 A D X
XXX 10
0 C 0 0 E 0 1 A D X B XXX
11
1 C 0 0 E 0 1 A 0 X B XXX
XX
High Speed Output
Frequency Output
8-Bit Pulse Width Modulator (Note 7)
9-Bit Pulse Width Modulator (Note 7)
10-Bit Pulse Width Modulator (Note 7)
11-Bit Pulse Width Modulator (Note 7)
16-Bit Pulse Width Modulator
Notes:
1.
X = Don’t Care (no functional difference for individual module if 1 or 0).
2.
A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3.
B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4.
C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, th
nerates a 0% duty cycle (output = 0).
5.
D = Selects whether the Capture/Compare register (0) o
the
uto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6.
E = When set, a match event will cause the CCFn
g for the associated channel to be set.
7.
All modules set to 8, 9, 10 or 11-bit PWM mode u
e same cycle length setting.
34.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CE
pin causes the PCA to capture the value of the PCA
counter/timer and load it into the corresponding module’s 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPN
bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to
igh transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused th
pture.
Rev. 1.0
509
Si102x/3x
PCA Interrupt
PCA0CPMn
PCA0CN
C C
C C C
F R
P
E C C M T
P
E
W
C A A A O
W
C
M
O P P T G
M
C
1
M P N n n
n
F
C C C
F F F
2 1 0
6
n n n
n
n
x
x
0 0 0
x
PCA0CPLn
P
0CPHn
0
1
CEXn
Capture
Port I/O
Crossbar
0
1
PCA
Timebase
PCA0L
PCA0H
Figure 34.4. PCA Capture Mode Diagram
Note:
The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
34.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module’s 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a m
occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic
1. An interrupt request
generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleare
by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by softwar
etting the ECOMn and MATn bits in the PCA0CPMn regis-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers
: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low by
e should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
510
Rev. 1.0
Si102x/3x
Write to
0
PCA0CPLn
ENB
Reset
Write to
PCA0CPHn
ENB
PCA Interrupt
1
PCA0CPMn
P
E C C M T
P
E
W
C A A A O
W
C
M
O P P T G
M
C
1
M P N n n
n
F
PCA0CN
C C
F R
C C C
C C C
F F F
2 1 0
PCA0CPLn
PCA0CPHn
6
n n n
n
n
x
0 0
0 0
x
1
Enable
Match
16-bit Comparator
PCA
Timebase
PCA0L
PCA0H
Figure 34.5. PCA Software Timer Mode Diagram
34.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn p
n is toggled each time a match occurs
between the PCA Counter and the module’s 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Co
are Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt fo
at module is enabled. The CCFn bit is not auto-
matically cleared by hardware when the CPU ve
ors to the interrupt service routine, and must be cleared
by software. Setting the TOGn, MATn, and
COMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the
sociated pin will retain its state, and not toggle on the next
match event.
Important Note About Capture/C
pare Registers
: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Rev. 1.0
511
Si102x/3x
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPMn
Write to
PCA0CPHn
P
E C C M T
P
E
W
C A A A O
W
C
M
O P P T G
M
C
1
M P N n n
n
F
ENB
1
6
n n n
n
n
x
0 0
0 x
PCA Interrupt
PCA0CN
C C
C C C
F R
C C C
F F F
2 1 0
PCA0CPLn
PCA0CPHn
0
1
Enable
Match
16-bit Comparator
TOGn
Toggle
0
CEXn
Crossbar
Port I/O
1
PCA
Timebase
PCA0L
PCA0H
Figure 34.6. PCA High-Spe
Output Mode Diagram
34.3.4. Frequency Output Mode
Frequency Output Mode produces a progra
able-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out-
put is toggled. The frequency of the square wave is then defined by Equation 34.1.
F
PCA
—————————————-
=
F
CEXn
2
PCA
0
CPHn
Note:
A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Equation 34.1. Square Wave Frequency Output
Where
F
is the frequency of the clock selected by the CPS2
–
0 bits in the PCA mode register,
PCA
PCA0MD.
e lower byte of the capture/compare module is compared to the PCA counter low byte; on a
matc
EXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Freq
ncy Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. The MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn flag for
the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for the chan-
el are equal.
512
Rev. 1.0
Si102x/3x
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPMn
P
E C C M T
P
E
W
C A A A O
W
C
M
O P P T G
M
C
1
M P N n n
n
F
Write to
PCA0CPHn
ENB
PCA0CPLn
8-bit Adder
PCA0CPHn
1
Adder
Enable
6
n n n
n
n
TOGn
x
0 0 0
x
Toggle
0
CEXn
8-bit
Comparator
match
Enable
Crossbar
Port I/O
1
PCA Timebase
PCA0L
Figure 34.7. PCA Frequency Output Mode
34.3.5. 8-Bit,
9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width m
dulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and
the setting of the PWM cycle length (8, 9, 10 or 11-bits). For bac
wards-compatibility with the 8-bit PWM
mode available on other devices, the 8-bit PWM mode opera
es slightly different than 9, 10 and 11-bit
PWM modes.
It is important to note that all channels confi
d for 8/9/10/11-bit PWM mode will use
the same cycle length.
It is not possible to configure one channel for 8-bit PWM mode and another for 11-
bit mode (for example). However, other PCA channels
an be configured to Pin Capture, High-Speed Out-
put, Software Timer, Frequency Output, or 16-bit PW
ode independently.
34.3.5.1. 8-Bit
Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8
PWM mode is varied using the module’s PCA0CPLn cap-
ture/compare register. When the value in the
w byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figur
4.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow
(falling edge), which
ill occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 34.2.
Important Note About Capture/Compare Registers
: When writing a 16-bit value to the PCA0 Cap-
ture/Comp
registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECO
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
256 –
PCA
0
CPHn
————————————————-
–
–
Duty Cycle
=
256
Equation 34.2. 8-Bit PWM Duty Cycle
Using Equation 34.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Rev. 1.0
513
Si102x/3x
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPHn
PCA0CPLn
Write to
PCA0CPHn
ENB
COVF
1
PCA0PWM
A
E C
R
C O
S
O V
E
V F
L
PCA0CPMn
C
C
L
L
S
S
E
E
L
L
1
0
P
E C C M T
P
E
W
C A A A O
W
C
M
O P P T G
M
C
1
M P N n n
n
F
6
n n n
n
n
0
x
0
0
0
0 0 x 0
x
8-bit
Comparator
match
SET
CLR
CEXn
Enable
S
R
Q
Q
Crossb
Port I/O
PCA Timebase
PCA0L
Overflow
Figure 34.8. PCA 8-Bit PWM Mode Diagram
34.3.5.2. 9/10/11-bit
Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM m
should be varied by writing to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in P
PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA
counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the outpu
CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 34.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the
LSEL bits in register PCA0PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn regis-
ter, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge)
occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur
every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM
Mode is given in E
on 34.3, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers
: When writing a 16-bit value to the
PCA0CPn
isters, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to
writing to PCA0CPHn sets ECOMn to 1.
2
N
–
PCA
0
CPn
——————————————-
Duty Cycle
=
2
N
Equation 34.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
514
Rev. 1.0
Si102x/3x
Write to
0
PCA0CPLn
R/W when
ARSEL = 1
ENB
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
PCA0PWM
Reset
A
E C
C
C
L
L
S
S
E
E
L
L
1
0
R
C O
S
O V
E
V F
L
Write to
PCA0CPHn
ENB
1
PCA0CPMn
x
R/W when
ARSEL = 0
P
E C C M T
P
E
W
C A A A O
W
C
M
O P P T G
M
C
1
M P N n n
n
F
(Capture/Compare)
Set “N” bits:
PCA0CPH:Ln
(right-justified)
01 = 9 bits
10 = 10 bits
11 = 11 bits
6
n n n
n
n
0
0 0 x 0
x
match
SET
CEXn
Enable
N-bit Comparator
S
R
Q
Q
Cros
Port I/O
CLR
PCA Timebase
PCA0H:L
Overflow of N
th
Bit
Figure 34.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
34.3.6. 16-Bit
Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. 1
PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/co
pare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counte
verflows, CEXn is asserted low.
T
o
o
utput a vary-
ing duty cycle, new value writes should be synchroni
with PCA CCFn match interrupts. 16-Bit PWM
Mode is enabled by setting the ECOMn, PWMn,
d PWM16n bits in the PCA0CPMn register. For a vary-
ing duty cycle, match interrupts should be en
bled (ECCFn = 1 AND MATn = 1) to help synchronize the
capture/compare register writes. If the MATn
s set to 1, the CCFn flag for the module will be set each
time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the
overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 34.4.
Important Note About Capture/Compare Registers
: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
65536 –
PCA
0
CPn
—————————————————-
Duty Cycle
=
65536
Equation 34.4. 16-Bit PWM Duty Cycle
Using Equ
ion 34.4,
the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.00
(PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Rev. 1.0
515
Si102x/3x
Write to
0
PCA0CPLn
ENB
Reset
Write to
PCA0CPHn
ENB
1
PCA0CPMn
P
E C C M T
P
E
W
C A A A O
W
C
M
O P P T G
M
C
PCA0CPHn
PCA0CPLn
1
M P N n n
n
F
n
6
n
1
n n n
0
0
x
0
x
SET
CLR
match
CEXn
Enable
16-bit Comparator
S
R
Q
Q
Crossbar
Port I/O
PCA Timebase
PCA0H
PCA0L
Overflow
Figure 34.10. PCA 16-Bit PWM Mode
34.4. Watchdog
Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 5. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified
limit. The WDT can be configured and enabled/disabled as ne
d by software.
With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The Mod-
ule 5 high byte is compared to the PCA counter high byte; the Module 5 low byte holds the offset to be
used when WDT updates are performed.
The watchd
imer is enabled on reset. Writes to some PCA
registers are restricted while the watchdog ti
er is enabled.
The WDT will generate a reset shortly
after code begins execution.
T
o
a
void this reset,
e WDT should be explicitly disabled (and optionally re-
configured and re-enabled if it is used in the
em).
34.4.1. Watchdog Timer Operation
While the WDT is enabled:
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2
–
CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 5 is forced into software timer mode.
Writes to the Mo
5 mode register (PCA0CPM5) are disabled.
While the W
T is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until t
WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
use
ftware has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while
the WDT is enabled, a reset will be generated.
T
o
p
revent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is
loaded into PCA0CPH5. (See Figure 34.11.)
516
Rev. 1.0
Si102x/3x
PCA0MD
C
W W
C C C E
D D
D
T
PCA0CPH5
I
P P P C
S S S F
2 1 0
L
L
E C
K
8-bit
Comparator
Match
Reset
Enable
PCA0L Overflow
PCA0CPL5
8-bit Adder
PCA0H
Adder
Enable
Write to
PCA0CPH2
Figure 34.11. PCA Module 5 with Watchdog Timer Enabled
Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the
0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 34.5, wher
PCA0L is the value of the PCA0L register
at the time of the update.
Offset
=
256
PCA
0
C
+
256 –
PCA
0
L
Equation 34.5. Watchdo
Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L
rflows while there is a match between PCA0CPH5 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is
enabled.
34.4.2. Watchdog Timer Usage
To
c
onfigure the WD
T
,
p
erform the following tasks:
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2
–
CPS0 bits).
Load PCA0CPL5 with the desired WDT update offset value.
Configure the P
dle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable
WDT by setting the WDTE bit to 1.
R
t the WDT timer by writing to PCA0CPH5.
The PCA clock source and idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 34.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles.
T
a
ble 34.3 lists some example tim-
eout intervals for typical system clocks.
Rev. 1.0
517
Si102x/3x
Table 34.3. Watchdog Timer Timeout Intervals
1
System Clock (Hz)
24,500,000
PCA0CPL5
Timeout Interval (ms)
255
128
32
32.1
16.2
4.1
24,500,000
24,500,000
2
255
257
3,062,500
2
128
32
129.5
33.1
3,062,500
2
3,062,500
32,000
32,000
32,000
255
128
32
2457
12384
3168
Notes:
1.
Assumes SYSCLK/12 as the PCA clock
ce, and a PCA0L value
of 0x00 at the update time.
2.
Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
518
Rev. 1.0
Si102x/3x
34.5. Register
Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 34.1. PCA0CN: PCA Control
Bit
7
CF
R/W
0
6
CR
R/W
0
5
CCF5
R/W
0
4
CCF4
R/W
0
3
CCF3
R/W
0
2
CCF2
R/W
0
1
CCF1
R/
0
0
CCF0
R/W
0
Name
Type
Reset
SFR Page = 0x0; SFR Address = 0xD8; Bit-Addressable
Bit
Name
Function
7
CF
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer ove
flows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by softwar
.
6
CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled
5:0 CCF[5:0]
PCA Module n Capture/C
mpare Flag.
These bits are set by hardw
e when a match or capture occurs in the associated PCA
Module n. When the CCFn interrupt is enabled, setting this bit causes the CPU to
vector to the PCA
errupt service routine. This bit is not automatically cleared by
hardware and mus
be cleared by software.
Rev. 1.0
519
Si102x/3x
SFR Definition 34.2. PCA0MD: PCA Mode
Bit
7
CIDL
R/W
0
6
WDTE
R/W
1
5
WDLCK
R/W
0
4
3
CPS2
R/W
0
2
CPS1
R/W
0
1
CPS0
R/W
0
0
Name
Type
Reset
ECF
R/W
0
R
0
SFR Page = 0x0; SFR Address = 0xD9
Bit
Name
Function
7
CIDL
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system co
oller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6
5
WDTE
Watchdog Timer Enable.
If this bit is set, PCA Module 5 is used as the watchdog timer.
0: Watchdog timer disabled.
1: PCA Module 5 enabled as watchdog time
WDLCK
Watchdog Timer Lock.
This bit locks/unlocks the watchdo
er enable. When WDLCK is set, the watchdog
timer may not be disabled until
e next system reset.
0: Watchdog timer enable unlo
ked.
1: Watchdog timer enable
ed.
4
Unused Read
= 0b, Write = don’t care.
3:1 CPS[2:0]
PCA Counter/Tim
r Pulse Select.
These bits se
ect the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
System clock
101: External clock divided by 8 (synchronized with the system clock)
110: SmaRTClock divided by 8 (synchronized with the system clock)
111: Reserved
0
ECF
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note:
When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified.
T
o
c
hange the
contents of the PCA0MD register, the watchdog timer must first be disabled.
520
Rev. 1.0
Si102x/3x
SFR Definition 34.3. PCA0PWM: PCA PWM Configuration
Bit
7
ARSEL
R/W
0
6
ECOV
R/W
0
5
COVF
R/W
0
4
3
2
1
0
Name
Type
Reset
CLSEL[1:0]
R/W
R
0
R
0
R
0
0
0
SFR Page = 0x0; SFR Address = 0xDF
Bit
Name
Function
7
ARSEL
Auto-Reload Register Select.
This bit selects whether to read and write the normal PCA capture/compare registers
(PCA0CPn), or the Auto-Reload registers at the same S
addresses. This function
is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other
modes, the Auto-Reload registers have no functio
.
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6
5
ECOV
COVF
Cycle Overflow Interrupt Enable.
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA int
rrupts.
1: A PCA interrupt will be generat
hen COVF is set.
Cycle Overflow Flag.
This bit indicates an over
of the 8th, 9th, 10th, or 11th bit of the main PCA counter
(PCA0). The specific bit us
d for this flag depends on the setting of the Cycle Length
Select bits. The bit can be set by hardware or software, but must be cleared by soft-
ware.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
4:2
Unused
Read = 000b; Write = don’t care.
1:0 CLSEL[1:0]
Cycle Length Select.
en 16-bit PWM mode is not selected, these bits select the length of the PWM
c
cle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which
are not using 16-bit PWM mode. These bits are ignored for individual channels config-
ured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
Rev. 1.0
521
Si102x/3x
SFR Definition 34.4. PCA0CPMn: PCA Capture/Compare Mode
Bit
7
6
ECOMn
R/W
0
5
CAPPn
R/W
0
4
CAPNn
R/W
0
3
MATn
R/W
0
2
TOGn
R/W
0
1
PWMn
R/W
0
0
ECCFn
R/W
0
Name
PWM16n
Type
R/W
0
Reset
SFR Address, Page: PCA0CPM0 = 0xDA
,
0x0; PCA0CPM1 = 0xDB
,
0x0; PCA0CPM2
C, 0x0
PCA0CPM3 = 0xDD
,
0x0; PCA0CPM4 = 0xDE
,
0x0; PCA0CPM5 =
E, 0x0
Bit
Name
Function
7
PWM16n
16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulatio
ode is enabled.
0: 8 to 11-bit PWM selected.
1: 16-bit PWM selected.
6
5
4
3
ECOMn
Comparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
CAPPn
Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
CAPNn
Capture Negative Function Enab
This bit enables the negative e
ge capture for PCA module n when set to 1.
MATn
Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module’s capture/compare register cause the CCFn
bit in PCA0MD re
ster to be set to logic 1.
2
1
0
TOGn
Toggle Func
ion Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module’s capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
a
in Frequency Output Mode.
PWMn
Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is
also set, the module operates in Frequency Output Mode.
ECCFn
Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note:
When the WDTE bit is set to 1, the PCA0CPM5 register cannot be modified, and module 5 acts as the
watchdog timer.
T
o
c
hange the contents of the PCA0CPM5 register or the function of module 5, the watchdog
timer must be disabled.
522
Rev. 1.0
Si102x/3x
SFR Definition 34.5. PCA0L: PCA Counter/Timer Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0[7:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0xF9
Bit Name
7:0 PCA0[7:0]
PCA Counter/Timer Low Byte.
Function
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note:
When the WDTE bit is set to 1, the PCA0L register cannot be modified by soft
are
T
o
c
hange the contents of
the PCA0L register, the watchdog Timer must first be disabled.
SFR Definition 34.6. PCA0H: PCA Counter/Timer
gh Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PC
[15:8]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = 0x0; SFR Address = 0x
Bit Name
7:0 PCA0[15:8]
PCA Counter/Timer High Byte.
Function
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot” register, whose contents
are updated only when the contents of PCA0L are read (see Section 34.1).
Note:
When the WD
bit is set to 1, the PCA0H register cannot be modified by software.
T
o
c
hange the contents of
the PCA0H register, the watchdog timer must first be disabled.
Rev. 1.0
523
Si102x/3x
SFR Definition 34.7. PCA0CPLn: PCA Capture Module Low Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0CPn[7:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Addresses: PCA0CPL0 = 0xFB
,
PCA0CPL1 = 0xE9
,
PCA0CPL2 = 0xEB,
PCA0CPL3 = 0xED
,
PCA0CPL4 = 0xFD
,
PCA0CPL5 = 0xD2
SFR Pages:
PCA0CPL0 = 0x0
,
PCA0CPL1 = 0x0
,
PCA0CPL2 = 0x0,
PCA0CPL3 = 0x0
,
PCA0CPL4 = 0x0
,
PCA0CPL5 = 0x0
Bit
Name
Function
7:0 PCA0CPn[7:0]
PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
This register address also allows access to the low byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit
in register PCA0PWM controls which
ter is accessed.
Note:
A write to this register will clear the module’s ECOMn bit to a 0.
SFR Definition 34.8. PCA0CPHn: PCA Capture Module High Byte
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
PCA0CPn[15:8]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Addresses: PCA0CPH0 = 0xFC
,
PCA0CPH1 = 0xEA
,
PCA0CPH2 = 0xEC,
P
CPH3 = 0xEE
,
PCA0CPH4 = 0xFE
,
PCA0CPH5 = 0xD3
SFR Pages:
PCA0CPH0 = 0x0
,
PCA0CPH1 = 0x0
,
PCA0CPH2 = 0x0,
PCA0CPH3 = 0x0
,
PCA0CPH4 = 0x0
,
PCA0CPH5 = 0x0
Bit
Name
Function
7:0 PCA0CPn[15:8]
PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
This register address also allows access to the high byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in
register PCA0PWM controls which register is accessed.
Note:
A write to this register will set the module’s ECOMn bit to a 1.
524
Rev. 1.0
Si102x/3x
35. C2
Interface
Si102x/3x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash program-
ming and in-system debugging with the production part installed in the end application. The C2 interface
uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the
device and a host system. See the C2 Interface Specification for details on the C2 protocol.
35.1. C2
Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 inter-
face. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.
C2 Register Definition 35.1. C2ADD: C2 Address
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
C2ADD[7:0]
R/W
0
0
0
0
0
0
0
0
Bit
Name
Fun
n
7:0 C2ADD[7:0]
C2 Address.
The C2ADD register is accessed
he C2 interface to select the target Data register
for C2 Data Read and Data W
te commands.
Address
0x00
Descr
tion
Select
he Device ID register for Data Read instructions.
Selects the Revision ID register for Data Read instructions.
0x01
0x02
Selects the C2 Flash Programming Control register for Data
Read/Write instructions.
0xB4
Selects the C2 Flash Programming Data register for Data
Read/Write instructions.
Rev. 1.0
525
Si102x/3x
C2 Register Definition 35.2. DEVICEID: C2 Device ID
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
DEVICEID[7:0]
R/W
0
0
0
1
0
1
0
0
C2 Address: 0x00
Bit Name
7:0 DEVICEID[7:0]
Device ID.
This read-only register returns the 8-bit device ID: 0x2A (Si102x/3x).
Function
C2 Register Definition 35.3. REVID: C2 Revision ID
Bit
7
6
5
4
2
1
0
Name
Type
Reset
REVID[7:0]
W
Varies
Varies
Varies
V
ries
Varies
Varies
Varies
Varies
C2 Address: 0x01
Bit Name
7:0 REVID[7:0]
Revision ID.
Function
This register indicates the MCU revision.
0x01: Rev A.
0x02: Rev B.
526
Rev. 1.0
Si102x/3x
C2 Register Definition 35.4. FPCTL: C2 Flash Programming Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
FPCTL[7:0]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0x02
Bit Name
7:0 FPCTL[7:0]
Flash Programming Control Register.
Function
This register is used to enable Flash programming via the C2 interface.
T
o
e
nable C2
Flash programming, the following codes must be written
order: 0x02, 0x01. Note
that once C2 Flash programming is enabled, a system reset must be issued to
resume normal operation.
C2 Register Definition 35.5. FPDA
T
:
C
2 Flash Pr
amming Data
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
FPDAT[7:0]
R/W
0
0
0
0
0
0
0
0
C2 Address: 0xB4
Bit Name
7:0 FPDAT[7:0]
C2 Flash Programming Data Register.
Function
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
de
0x06
0x07
0x08
0x03
Command
Flash Block Read
Flash Block Write
Flash Page Erase
Device Erase
Rev. 1.0
527
Si102x/3x
35.2. C2
Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely “borrow” the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolatio
configuration is shown in Figure 35.1.
C8051Fxxx
RST (a)
Input (b)
C2CK
C2D
Output (c)
C2 Interface Maste
Figure 35.1. Typic
2 Pin Sharing
The configuration in Figure 35.1 assumes the
ollowing:
1. The user input (b) cannot change state
le the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
528
Rev. 1.0
Si102x/3x
D
OCUMENT
C
HANGE
L
IST
Revision 0.3 to Revision 1.0
Updated part numbers to Revision B.
Updated device package mechanical spec and PCB land pattern.
Updated electrical specifications, including TBD values.
Updated EZRadioPro Version Code.
Removed support for EZRadioPro Low Battery Detect feature.
Deleted SFR Page Stack Example in Special Function Registers chapter.
Change description of SFRPGEN bit in SFRPGCN SFR definition.
Added paragraph to Flash chapter to explain lock byte behavior on 128 kB devices.
Corrected SFRPAGE in SPI1 SFR definitions.
Fixed inconsistencies in VIORF pin definitions.
Added note about IFBANK usage.
Fixed inconsistencies in description of reset behavior.
Added encryption/decryption times to SFR Definition.
Fixed inconsistencies in various SFR Definitions.
Rev. 1.0
529
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n Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
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provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
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