SKYWORKS-SILICON-LABS-SI4060-B1B-FMR
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Si4063/60
H
I
GH
–
P
E
RFORMANCE
,
L
O
W
–
C
U
RRENT
T
R
ANSMITTER
Features
Frequency range = 142–1050 MHz
Power supply = 1.8 to 3.6 V
Modulation
(G)FSK, 4(G)FSK, (G)MSK
OOK
Highly configurable packet handler
TX 64 byte FIFO
Low BOM
Low battery detector
T
e
mperature sensor
20-Pin QFN package
IEEE 802.15.4g compliant
Max output power
+20 dBm (Si4063)
+13 dBm (Si4060)
PA support for +27 or +30 dBm
Ultra low current powerdown modes
FCC Part 90 Mask D, FCC part 15.247,
15,231, 15,249, ARIB T-108, T-96, T-67,
China regulatory
ETSI Class-I Operation
30 nA shutdown, 50 nA standby
Data rate = 100 bps to 1 Mbps
Fast wake times
Pin Assignments
Applications
Smart metering
Remote control
Home security and alarm
T
e
lemetry
Garage and gate openers
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
20 19 18 17
SDN
NC
NC
TX
1
16
2
15 nSEL
14 SDI
13 SDO
12 SCLK
11 nIRQ
3
4
5
GND
PAD
Electronic shelf labels
NC
Description
6
7
8
9
10
Silicon Laboratories’ Si406x devices are high-performance, low-current
transmitters covering the sub-GHz frequency bands from 142 to 1050 MHz.
The radios are part of the EZRadioPRO
®
family, which includes a complete
line of transmitters, receivers, and transceivers covering a wide range of
applications. All parts offer extremely low active and standby current
consumption. The Si406x includes optimal phase noise performance for
narrow band applications, such as FCC Part90 and 169 MHz wireless Mbus.
The Si4063 offers exceptional output power of up to +20
dBm with
outstanding TX efficiency. The high output power allows extended ranges and
highly robust communication links. The Si4060 active mode TX current
consumption of 18
mA at +10
dBm coupled with extremely low standby
current and fast wake times ensure extended battery life in the most
demanding applications. The Si4063 can achieve up to +27
dBm output
power with built-in ramping control of a low-cost external FE
T
.
T
he devices
are compliant with all worldwide regulatory standards: FCC, ETSI, and ARIB.
All devices are designed to be compliant with 802.15.4g and WMbus smart
metering standards.
Patents pending
Rev 0.1 12/12
Copyright © 2012 by Silicon Laboratories
Si4063/60
Si4063/60
Functional Block Diagram
GPIO3 GPIO2
XIN XOUT
30 MHz XO
Loop
Filter
PFD / CP
VCO
FBDIV
Frac-N Div
LO
Gen
Bootup
OSC
TX DIV
SDN
nSEL
MODEM
SDI
ADC
Temp
FIFO
Packet
Handler
SDO
SCLK
nIRQ
sensor
PowerRamp
Cntl
PA
TX
LDOs
POR
LBD
PA
LDO
Digital
Logic
32K LP
OSC
VDD TXRAMP
VDD
GPIO0 GPIO1
Product
Freq. Range
Max Output
TX Current
Narrowband
Operation
Power
Si4063
Major bands
142–1050 MHz
+20 dBm
169 MHz: 70 mA
915 MHz: 85 mA
Si4060
Major bands
142–1050 MHz
+13 dBm
+10 dBm: 18 mA
2
Rev 0.1
Si4063/60
T
A
BLE OF
C
O
NTENTS
Section
Page
1. Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
1.1. Definition of Test Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
0
2. Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
1
3. Controller Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
2
3.1. Serial Peripheral Interface (SPI)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
2
3.2. Fast Response Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
4
3.3. Operating Modes and Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
4
3.4. Application Programming Interface (API)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
8
3.5. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
8
3.6. GPIO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
9
4. Modulation and Hardware Configuration Options
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
0
4.1. Modulation Types
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
0
4.2. Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
0
5. Internal Functional Blocks
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
1
5.1. Synthesizer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
1
5.2. Transmitter (TX)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
2
5.3. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
5
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
6
6.1. TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
6
6.2. Packet Handler
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
6
7. Auxiliary Blocks
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
7
7.1. Wake-up Timer and 32 kHz Clock Source
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
7
7.2. Low Duty Cycle Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
9
7.3. Temperature, Battery Voltage, and Auxiliary ADC
. . . . . . . . . . . . . . . . . . . . . . . . .
.
3
0
7.4. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
1
8. Pin Descriptions: Si4063/60
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
2
9. Ordering Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
4
10. Package Outline: Si4063/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
5
11. PCB Land Pattern: Si4063/60
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
7
12. Top Marking
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
9
12.1. Si4063/60 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
9
12.2. Top Marking Explanation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
9
Contact Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
0
Rev 0.1
3
Si4063/60
1. Electrical
Specifications
Table 1. DC Characteristics
1
Parameter
Symbol
Test Condition
Min Typ Max Unit
Supply Voltage
Range
V
1.8
—
—
—
3.3
3.6
—
—
—
V
DD
Power Saving Modes
I
RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF
30
nA
nA
nA
Shutdown
I
Register values maintained and RC
oscillator/WUT OFF
50
Standby
I
RC Oscillator/WUT ON and all register values main-
tained, and all other blocks OFF
900
SleepRC
SleepXO
2
I
Sleep current using an external 32 kHz crystal.
—
—
1.7
1
—
—
µA
µA
I
Low battery detector ON, register values maintained,
and all other blocks OFF
Sensor
-LBD
I
Crystal Oscillator and Main Digital Regulator ON,
all other blocks OFF
—
1.8
—
mA
Ready
TUNE Mode Current
I
TX Tune, High Performance Mode
—
—
8
—
—
mA
mA
Tune_TX
TX Mode Current
(Si4063)
I
+20 dBm output power, class-E match, 915 MHz,
3.3 V
85
TX_+20
+20 dBm output power, class-E match, 460 MHz,
3.3 V
—
—
—
75
70
18
—
—
—
mA
mA
mA
+20 dBm output power, square-wave match,
169 MHz, 3.3 V
TX Mode Current
(Si4060)
I
+10 dBm output power, Class-E match, 868 MHz,
TX_+10
2
3.3 V
Notes:
1.
All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the “Production
T
e
st Conditions” section of “1.1. Definition of
T
e
st Conditions” on page 10.
2.
Guaranteed by qualification. Qualification test conditions are listed in the “Qualification
T
e
st Conditions” section in “1.1.
Definition of
T
e
st Conditions” on page 10.
4
Rev 0.1
Si4063/60
Table 2. Synthesizer AC Electrical Characteristics
1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Synthesizer Frequency
F
850
—
1050 MHz
SYN
Range (
Si4063/60
)
420
284
142
—
—
—
525
350
175
—
MHz
MHz
MHz
Hz
—
Synthesizer Frequency
F
F
F
F
28.6
14.3
9.5
4.7
50
RES-960
RES-525
RES-350
RES-175
850–1050 MHz
420–525 MHz
283–350 MHz
142–175 MHz
2
Resolution
—
—
Hz
—
—
Hz
—
—
Hz
3
t
Measured from exiting Ready mode with
XOSC running to any frequency.
Including VCO Calibration.
—
—
µs
Synthesizer Settling Time
LOCK
3
L
(f )
F = 10 kHz, 460 MHz, High Perf Mode
F = 100 kHz, 460 MHz, High Perf Mode
F = 1 MHz, 460 MHz, High Perf Mode
F = 10 MHz, 460 MHz, High Perf Mode
—
—
—
—
–106
–110
–123
–130
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise
M
Notes:
1.
All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the “Production
T
e
st Conditions” section in “1.1. Definition of
T
e
st Conditions” on page 10.
2.
Default API setting for modulation deviation resolution is double the typical value specified.
3.
Guaranteed by qualification. Qualification test conditions are listed in the “Qualification
T
e
st Conditions” section in “1.1.
Definition of
T
e
st Conditions” on page 10.
Rev 0.1
5
Si4063/60
Table 3. Transmitter AC Electrical Characteristics
1
Parameter
TX Frequency
Range (Si4063/60)
Symbol
Test Condition
Min
Typ
Max
Unit
850
—
1050 MHz
420
284
142
—
—
—
525
350
MHz
MHz
F
TX
175
500
MHz
kbps
2,3
(G)FSK Data Rate
4(G)FSK Data Rate
DR
0.1
0.2
0.1
—
—
—
FSK
2,3
DR
1000 kbps
4FSK
2,3
OOK Data Rate
DR
f
—
120
—
—
—
—
—
—
—
—
kbps
MHz
kHz
kHz
kHz
Hz
OOK
960
525
350
175
Modulation Deviation
1.5
750
500
850–1050 MHz
420–525 MHz
283–350 MHz
142–175 MHz
850–1050 MHz
420–525 MHz
283–350 MHz
142–175 MHz
2
Range
f
—
f
—
f
—
250
Modulation Deviation
28.6
F
—
RES-960
RES-525
RES-350
RES-175
2,4
Resolution
14.3
9.5
F
F
F
—
Hz
—
Hz
4.7
—
Hz
Output Power Range
(Si4063)
P
–20
–40
—
—
—
+20
+13
—
dBm
dBm
dB
5
TX
Output Power Range
P
5
TX60
(Si4060)
2
TX RF Output Steps
Using switched current match within
6 dB of max power
P
P
0.1
1
RF_OUT
2
TX RF Output Level
–40 to +85
C
—
—
dB
RF_TEMP
Variation vs.
T
e
mperature
TX RF Output Level
Variation vs. Frequency
P
Measured across 902–928 MHz
—
0.5
—
dB
2
RF_FREQ
Transmit Modulation
Filtering
Gaussian Filtering Bandwith Time
Product
B*T
—
0.5
—
2
Notes:
1.
All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the “Production
T
e
st Conditions” section in “1.1. Definition of
T
e
st Conditions” on page 10.
2.
Guaranteed by qualification. Qualification test conditions are listed in the “Qualification
T
e
st Conditions” section in “1.1.
Definition of
T
e
st Conditions” on page 10.
3.
The maximum data rate is dependent on the XTAL frequency and is calculated as per the formula:
Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).
4.
Default API setting for modulation deviation resolution is double the typical value specified.
5.
Output power is dependent on matching components and board layout.
6
Rev 0.1
Si4063/60
Table 4. Auxiliary Block Specifications
1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
T
e
mperature Sensor
Sensitivity
TS
—
4.5
—
ADC
Codes/
°C
S
2
Low Battery Detector
Resolution
Microcontroller Clock
Output Frequency Range
LBD
—
50
—
—
mV
RES
F
Configurable to Fxtal or Fxtal
divided by 2, 3, 7.5, 10, 15, or
30 where Fxtal is the reference
XTAL frequency. In addition,
32.768 kHz is also supported.
Programmable setting
32.768K
Fxtal
Hz
MC
3
T
e
mperature Sensor
TEMP
—
3
—
ms
CT
2
Conversion
4
XTAL Range
XTAL
25
—
—
250
32
—
MHz
µs
Range
30 MHz XTAL Start-Up Time
t
Using XTAL and board layout in
reference design. Start-up time
will vary with XTAL type and
board layout.
30M
30 MHz XTAL Cap
Resolution
32 kHz XTAL Start-Up Time
32 kHz Accuracy using
30M
RES
—
70
—
fF
2
2
t
—
—
2
—
—
sec
ppm
32k
32KRC
2500
RES
2
Internal RC Oscillator
POR Reset Time
t
—
—
5
ms
POR
Notes:
1.
All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the “Production
T
e
st Conditions” section in “1.1. Definition of
T
e
st Conditions” on page 10.
2.
Guaranteed by qualification. Qualification test conditions are listed in the “Qualification
T
e
st Conditions” section in “1.1.
Definition of
T
e
st Conditions” on page 10.
3.
Microcontroller clock frequency tested in production at 1 MHz, 30 MHz and 32.768 kHz. Other frequencies tested in
bench characterization.
4.
XTAL Range tested in production using an external clock source (similar to using a TCXO).
Rev 0.1
7
Si4063/60
Table 5. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ, SDN)
1
Parameter
2,3
Symbol
Test Condition
0.1 x V
to 0.9 x V
,
DD
Min
Typ
Max
Unit
Rise Time
T
—
2.3
—
ns
RISE
DD
C =
10 p
F
,
L
DRV<1:0> = HH
3,4
Fall Time
T
0.9 x V
to 0.1 x V
—
2
—
ns
FALL
DD
DD,
C =
10 p
F
,
L
DRV<1:0> = HH
Input Capacitance
C
V
—
2
—
—
pF
V
IN
Logic High Level Input Voltage
Logic Low Level Input Voltage
Input Current
V
x 0.7
—
IH
DD
V
—
–10
1
—
V
x 0.3
DD
V
IL
I
0<V <
V
DD
—
10
10
—
—
—
—
—
—
—
—
—
—
—
—
—
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
IN
IN
Input Current If Pullup is Activated
I
V =
0 V
—
INP
IL
3
3
Drive Strength for Output Low
Level
I
DRV[1:0] = LL
—
—
—
—
—
—
—
—
—
—
—
—
6.66
5.03
3.16
1.13
5.75
4.37
2.73
0.96
2.53
2.21
1.7
OmaxLL
OmaxLH
OmaxHL
OmaxHH
I
I
DRV[1:0] = LH
DRV[1:0] = HL
3
3
I
DRV[1:0] = HH
3
Drive Strength for Output High
Level
I
DRV[1:0] = LL
DRV[1:0] = LH
DRV[1:0] = HL
OmaxLL
OmaxLH
OmaxHL
OmaxHH
3
3
3
I
I
I
DRV[1:0] = HH
3
Drive Strength for Output High
Level for GPIO0
I
DRV[1:0] = LL
DRV[1:0] = LH
DRV[1:0] = HL
OmaxLL
OmaxLH
OmaxHL
OmaxHH
3
3
3
I
I
I
DRV[1:0] = HH
DRV[1:0] = HL
DRV[1:0] = HL
0.80
—
Logic High Level Output Voltage
Logic Low Level Output Voltage
Notes:
V
V
x 0.8
DD
OH
V
—
—
V
x 0.2
DD
V
OL
1.
All specifications guaranteed by qualification. Qualification test conditions are listed in the “Qualification
T
e
st
Conditions” section in “1.1. Definition of
T
e
st Conditions” on page 10.
2.
8 ns is typical for GPIO0 rise time.
3.
Assuming VDD = 3.3
V
,
d
rive strength is specified at Voh (min) = 2.64 V and Vol(max) = 0.66 V at room temperature.
4.
2.4 ns is typical for GPIO0 fall time.
8
Rev 0.1
Si4063/60
Table 6. Absolute Maximum Ratings
Parameter
Value
Unit
V
V
to GND
–0.3, +3.6
–0.3, +8.0
–0.3, +6.5
DD
Instantaneous V
Sustained V
to GND on TX Output Pin
V
RF-peak
to GND on TX Output Pin
V
RF-peak
Voltage on Digital Control Inputs
Voltage on Analog Inputs
–0.3, V
+ 0.3
V
DD
–0.3, V
+ 0.3
V
DD
Operating Ambient
T
e
mperature Range T
–40 to +85
30
C
C
/
W
C
C
A
Thermal Impedance
JA
Junction
T
e
mperature T
+125
J
Storage
T
e
mperature Range T
–55 to +125
STG
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Power Amplifier may be damaged if switched on without proper load or termination connected. TX
matching network design will influence TX V
RF-peak
on TX output pin. Caution: ESD sensitive device.
Rev 0.1
9
Si4063/60
1.1. Definition
of Test Conditions
Production Test Conditions:
T =
+25 °C.
A
V
= +3.3 VDC.
DD
TX output power measured at 915 MHz.
External reference signal (XOUT) = 1.0 V
at 30 MHz, centered around 0.8 VDC.
PP
Production test schematic (unless noted otherwise).
All TX output levels are referred to the pins of the Si4063/60 (not the output of the RF module).
Qualification Test Conditions:
T
=
–40 to +85 °C (Typical T
=
25 °C).
A
A
V
= +1.8 to +3.6 VDC (Typical V
= 3.3 VDC).
DD
DD
All RF levels referred to the pins of the Si4063/60 (not the RF module).
10
Rev 0.1
Si4063/60
2. Functional
Description
The Si406x devices are high-performance, low-current, wireless ISM transmitters that cover the sub-GHz bands.
The wide operating voltage range of 1.8–3.6 V and low current consumption make the Si406x an ideal solution for
battery powered applications.
A single high precision local oscillator (LO) is used for transmit mode. The LO is generated by an integrated VCO
and
Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates from 100 bps
to 1 Mbps. The Si4063/60 operate in the frequency bands of 142–175, 283–350, 420–525, and 850–1050 MHz
with a maximum frequency accuracy step size of 28.6 Hz. The transmit FSK data is modulated directly into the
data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content.
The Si4063/60 contains a power amplifier (PA) that supports output power up to +20 dBm with very high efficiency,
consuming only 70 mA at 169 MHz and 85 mA at 915 MHz. The integrated +20 dBm power amplifier can also be
used to compensate for the reduced performance of a lower cost, lower performance antenna or antenna with size
constraints due to a small form-factor. Competing solutions require large and expensive external PAs to achieve
comparable performance. The Si4060 is designed to support single coin cell operation with current consumption
below 18
mA for +10
dBm output power. Two match topologies are available for the Si4060, Class-E and
switched-current. Class-E matching provides optimal current consumption, while switched-current matching
demonstrates the best performance over varying battery voltage and temperature with slightly higher current
consumption. The PA is single-ended to allow for easy antenna matching and low BOM cost. The PA incorporates
automatic ramp-up and ramp-down control to reduce unwanted spectral spreading. The Si406x family supports
frequency hopping to extend the link range and improve performance. A highly configurable packet handler allows
for autonomous encoding of nearly any packet structure. Additional system features, such as an automatic
wake-up timer, low battery detector, and 64 byte TX FIFOs, reduce overall current consumption and allows for the
use of lower-cost system MCUs. An integrated temperature sensor, power-on-reset (POR), and GPIOs further
reduce overall system cost and size. The Si406x is designed to work with an MCU, crystal, and a few passive
components to create a very low-cost system.
30 MHz
SDN
SDN
nSEL
SDI
1
2
3
15
14
13
NC
NC
SDO
SCLK
nIRQ
Si406x
L4
L3
L2
TX
4
5
12
11
NC
C1
C3
C4
C2
L1
VDD
C5
C6
C7
Figure 1. Si406x Application Example
Rev 0.1
11
Si4063/60
3. Controller
Interface
3.1. Serial
Peripheral Interface (SPI)
The Si406x communicates with the host MCU over a standard 4-wire serial peripheral interface (SPI): SCLK, SDI,
SDO, and nSEL. The SPI interface is designed to operate at a maximum of 10 MHz. The SPI timing parameters
are demonstrated in
T
a
ble 7. The host MCU writes data over the SDI pin and can read data from the device on the
SDO output pin. Figure 2 demonstrates an SPI write command. The nSEL pin should go low to initiate the SPI
command. The first byte of SDI data will be one of the firmware commands followed by n bytes of parameter data
which will be variable depending on the specific command. The rising edges of SCLK should be aligned with the
center of the SDI data.
Table 7. Serial Interface Timing Parameters
Symbol
Parameter
Min (ns)
Diagram
t
Clock high time
Clock low time
40
40
20
20
20
20
50
20
50
80
CH
t
CL
DS
DH
DD
SCLK
SDI
t
Data setup time
t
SS
t
CL
t
CH
t
DS
t
DH
t
DD
t
SH
t
DE
t
t
Data hold time
Output data delay time
Output enable time
Output disable time
Select setup time
Select hold time
Select high period
t
t
EN
SDO
DE
t
EN
t
SW
t
SS
SH
nSEL
t
t
SW
nSEL
SDO
SDI
FW Command
Param Byte 0
Param Byte n
SCLK
Figure 2. SPI Write Command
The Si406x contains an internal MCU which controls all the internal functions of the radio. For SPI read commands
a typical MCU flow of checking clear-to-send (CTS) is used to make sure the internal MCU has executed the
command and prepared the data to be output over the SDO pin. Figure 3 demonstrates the general flow of an SPI
read command. Once the CTS value reads FFh then the read data is ready to be clocked out to the host MCU. The
typical time for a valid FFh CTS reading is 20 µs. Figure 4 demonstrates the remaining read cycle after CTS is set
to FFh. The internal MCU will clock out the SDO data on the negative edge so the host MCU should process the
SDO data on the rising edge of SCLK.
12
Rev 0.1
Si4063/60
Firmware Flow
0xFF
Retrieve
Response
Send Command
Read CTS
CTS Value
0x00
NSEL
SDO
SDI
CTS
ReadCmdBuff
SCK
Figure 3. SPI Read Command—Check CTS Value
NSEL
SDO
SDI
Response Byte 0
Response Byte n
SCK
Figure 4. SPI Read Command—Clock Out Read Data
Rev 0.1
13
Si4063/60
3.2. Fast
Response Registers
The fast response registers are registers that can be read immediately without the requirement to monitor and
check CTS. There are four fast response registers that can be programmed for a specific function. The fast
response registers can be read through API commands, 0x50 for Fast Response A, 0x51 for Fast Response B,
0x53 for Fast Response C, and 0x57 for Fast Response D. The fast response registers can be configured by the
“FRR_CTL_X_MODE” properties.
The fast response registers may be read in a burst fashion. After the initial 16 clock cycles, each additional eight
clock cycles will clock out the contents of the next fast response register in a circular fashion. The value of the
FRRs will not be updated unless NSEL is toggled.
3.3. Operating
Modes and Timing
The primary states of the Si406x are shown in Figure 5. The shutdown state completely shuts down the radio to
minimize current consumption. Standby/Sleep, SPI Active, Ready, and TX Tune are available to optimize the
current consumption and response time to TX for a given application. The API commands, START_TX and
CHANGE_STATE, control the operating state with the exception of shutdown which is controlled by SDN, pin 1.
T
a
ble 8
shows each of the operating modes with the time required to reach TX mode as well as the current
consumption of each mode. The times in
T
a
ble 9 are measured from the rising edge of nSEL until the chip is in the
desired state. Note that these times are indicative of state transition timing but are not guaranteed and should only
be used as a reference data point. An automatic sequencer will put the chip into TX from any state. It is not
necessary to manually step through the states.
T
o
s
implify the diagram it is not shown but any of the lower power
states can be returned to automatically after TX.
Sleep
Shutdown
SPI Active
Ready
Tx Tune
Tx
Figure 5. State Machine Diagram
14
Rev 0.1
Si4063/60
Table 8. Operating State Response Time and Current Consumption*
Current in State
/Mode
State/Mode
Response Time to TX
Shutdown State
15 ms
30 nA
Standby State
Sleep State
SPI Active State
Ready State
440 µs
440 µs
340 µs
126 µs
58 µs
50 nA
900 nA
1.35 mA
1.8 mA
8 mA
TX Tune State
TX State
—
18 mA @ +10 dBm
Figure 6 shows the POR timing and voltage requirements. The power consumption (battery life) depends on the
duty cycle of the application or how often the part is in TX state. In most applications the utilization of the standby
state will be most advantageous for battery life but for very low duty cycle applications shutdown will have an
advantage. For the fastest timing the next state can be selected in the START_TX API commands to minimize SPI
transactions and internal MCU processing.
3.3.1. Power on Reset (POR)
A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state.
T
o
e
xecute this
process, VDD must ramp within 1ms and must remain applied to the device for at least 10ms. If VDD is removed,
then it must stay below 0.15V for at least 10ms before being applied again. Please see Figure x and
T
a
ble x for
details.
V
DD
V
R
R
H
V
R
R
L
Time
t
SR
t
P
O
RH
Figure 6. POR Timing Diagram
Rev 0.1
15
Si4063/60
Table 9. POR Timing
Variable
Description
Min
Typ
Max
Units
ms
ms
V
High time for VDD to fully settle POR circuit.
Low time for VDD to enable POR.
Voltage for successful POR
t
10
PORH
t
10
90%*Vdd
0
PORL
V
RRH
Starting Voltage for successful POR
Slew rate of VDD for successful POR
V
150
1
mV
ms
RRL
t
SR
3.3.2. Shutdown State
The shutdown state is the lowest current consumption state of the device with nominally less than 30 nA of current
consumption. The shutdown state may be entered by driving the SDN pin (Pin 1) high. The SDN pin should be held
low in all states except the shutdown state. In the shutdown state, the contents of the registers are lost and there is
no SPI access. When coming out of the shutdown state a power on reset (POR) will be initiated along with the
internal calibrations. After the POR the POWER_UP command is required to initialize the radio. The SDN pin
needs to be held high for at least 10us before driving low again so that internal capacitors can discharge. Not
holding the SDN high for this period of time may cause the POR to be missed and the device to boot up incorrectly.
If POR timing and voltage requirements cannot be met, it is highly recommended that SDN be controlled using the
host processor rather than tying it to GND on the board.
3.3.3. Standby State
Standby state has the lowest current consumption with the exception of shutdown but has much faster response
time to TX mode. In most cases standby should be used as the low power state. In this state the register values are
maintained with all other blocks disabled. The SPI is accessible during this mode but any SPI event, including FIFO
R/W, will enable an internal boot oscillator and automatically move the part to SPI active state. After an SPI event
the host will need to re-command the device back to standby through the “Change State” API command to achieve
the 50 nA current consumption. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be
read to achieve the minimum current consumption of this mode.
3.3.4. Sleep State
Sleep state is the same as standby state but the wake-up-timer and a 32 kHz clock source are enabled. The
source of the 32 kHz clock can either be an internal 32 kHz RC oscillator which is periodically calibrated or a
32 kHz oscillator using an external XTAL.The SPI is accessible during this mode but an SPI event will enable an
internal boot oscillator and automatically move the part to SPI active mode. After an SPI event the host will need to
re-command the device back to sleep. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers
must be read to achieve the minimum current consumption of this mode.
3.3.5. SPI Active State
In SPI active state the SPI and a boot up oscillator are enabled. After SPI transactions during either standby or
sleep the device will not automatically return to these states. A “Change State” API command will be required to
return to either the standby or sleep modes.
3.3.6. Ready State
Ready state is designed to give a fast transition time to TX state with reasonable current consumption. In this mode
the Crystal oscillator remains enabled reducing the time required to switch to TX mode by eliminating the crystal
start-up time.
3.3.7. TX State
The TX state may be entered from any of the state with the “Start TX” or “Change State” API commands. A built-in
sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to
ramping up the PA. The following sequence of events will occur automatically when going from standby to TX state.
1. Enable
internal LDOs.
2. Start
up crystal oscillator and wait until ready (controlled by an internal timer).
16
Rev 0.1
Si4063/60
3. Enable
PLL.
4. Calibrate
VCO/PLL.
5. Wait
until PLL settles to required transmit frequency (controlled by an internal timer).
6. Activate
power amplifier and wait until power ramping is completed (controlled by an internal timer).
7. Transmit
packet.
Steps in this sequence may be eliminated depending on which state the chip is configured to prior to commanding
to TX. By default, the VCO and PLL are calibrated every time the PLL is enabled. When the START_TX API
command is utilized the next state may be defined to ensure optimal timing and turnaround.
Figure 7 shows an example of the commands and timing for the START_TX command. CTS will go high as soon
as the sequencer puts the part into TX state. As the sequencer is stepping through the events listed above, CTS
will be low and no new commands or property changes are allowed. If the Fast Response (FRR) or nIRQ is used to
monitor the current state there will be slight delay caused by the internal hardware from when the event actually
occurs to when the transition occurs on the FRR or nIRQ. The time from entering TX state to when the FRR will
update is 5 µs and the time to when the nIRQ will transition is 13 µs. If a GPIO is programmed for TX state or used
as control for a transmit/receive switch (TR switch) there is no delay.
CTS
NSEL
SDI
START_TX
Current State
YYY State
Tx State
TXCOMPLETE_STATE
FRR
YYY State
Tx State
TXCOMPLETE_STATE
nIRQ
GPIOx – TX state
Figure 7. Start_TX Commands and Timing
Rev 0.1
17
Si4063/60
3.4. Application
Programming Interface (API)
An application programming interface (API), which the host MCU will communicate with, is embedded inside the
device. The API is divided into two sections, commands and properties. The commands are used to control the
chip and retrieve its status. The properties are general configurations which will change infrequently.
3.5. Interrupts
The Si406x is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal
will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) occur.
The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Registers. The nIRQ output signal
will then be reset until the next change in status is detected.
The interrupts sources are grouped into three groups: packet handler, chip status, and modem. The individual
interrupts in these groups can be enabled/disabled in the interrupt property registers, 0101, 0102, and 0103. An
interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well as
the individual interrupts in API property 0100.
Number
Command
Summary
Returns the interrupt status—packet handler, modem,
and chip
0x20
GET_INT_STATUS
0x21
0x22
0x23
GET_PH_STATUS
GET_MODEM_STATUS
GET_CHIP_STATUS
Returns the packet handler status.
Returns the modem status byte.
Returns the chip status.
Number
Property
Default
Summary
Enables interrupt groups for PH, Modem, and
Chip.
0x0100
INT_CTL_ENABLE
0x04
0x0101
0x0102
0x0103
INT_CTL_PH_ENABLE
INT_CTL_MODEM_ENABLE
INT_CTL_CHIP_ENABLE
0x00 Packet
handler interrupt enable property.
0x00 Modem
interrupt enable property.
0x04 Chip
interrupt enable property.
Once an interrupt event occurs and the nIRQ pin is low there are two ways to read and clear the interrupts. All of
the interrupts may be read and cleared in the “GET_INT_STATUS” API command. By default all interrupts will be
cleared once read. If only specific interrupts want to be read in the fastest possible method the individual interrupt
groups (Packet Handler, Chip Status, Modem) may be read and cleared by the “GET_MODEM_STATUS”,
“GET_PH_STATUS” (packet handler), and “GET_CHIP_STATUS” API commands.
The instantaneous status of a specific function maybe read if the specific interrupt is enabled or disabled. The
status results are provided after the interrupts and can be read with the same commands as the interrupts. The
status bits will give the current state of the function whether the interrupt is enabled or not.
The fast response registers can also give information about the interrupt groups but reading the fast response
registers will not clear the interrupt and reset the nIRQ pin.
18
Rev 0.1
Si4063/60
3.6. GPIO
Four general purpose IO pins are available to utilize in the application. The GPIO are configured by the
GPIO_PIN_CFG command in address 13h. For a complete list of the GPIO options please see the API guide.
GPIO pins 0 and 1 should be used for active signals such as data or clock. GPIO pins 2 and 3 have more
susceptibility to generating spurious in the synthesizer than pins 0 and 1. The drive strength of the GPIOs can be
adjusted with the GEN_CONFIG parameter in the GPIO_PIN_CFG command. By default the drive strength is set
to minimum. The default configuration for the GPIOs and the state during SDN is shown below in
T
a
ble 10.The
state of the IO during shutdown is also shown in
T
a
ble 10. As indicated previously in
T
a
ble 5, GPIO 0 has lower
drive strength than the other GPIOs.
Table 10. GPIOs
Pin
SDN State
POR Default
POR
GPIO0
GPIO1
GPIO2
GPIO3
nIRQ
0
0
CTS
0
0
POR
POR
resistive VDD pull-up
resistive VDD pull-up
High Z
nIRQ
SDO
SDO
SDI
SDI
Rev 0.1
19
Si4063/60
4. Modulation
and Hardware Configuration Options
The Si406x supports different modulation options and can be used in various configurations to tailor the device to
any specific application or legacy system for drop in replacement. The modulation and configuration options are set
in API property, MODEM_MOD_TYPE.
4.1. Modulation
Types
The Si406x supports five different modulation options: Gaussian frequency shift keying (GFSK), frequency-shift
keying (FSK), four-level GFSK (4GFSK), four-level FSK (4FSK), on-off keying (OOK). Minimum shift keying (MSK)
can also be created by using GFSK settings. GFSK is the recommended modulation type as it provides the best
performance and cleanest modulation spectrum. The modulation type is set by the “MOD_TYPE[2:0]” registers in
the “MODEM_MOD_TYPE” API property. A continuous-wave (CW) carrier may also be selected for RF evaluation
purposes. The modulation source may also be selected to be a pseudo-random source for evaluation purposes.
4.2. Hardware
Configuration Options
There are different receive demodulator options to optimize the performance and mutually-exclusive options for
how the TX data is transferred from the host MCU to the RF device.
4.2.1. TX Data Interface With MCU
There are two different options for transferring the data from the RF device to the host MCU. FIFO mode uses the
SPI interface to transfer the data, while direct mode transfers the data in real time over GPIO.
4.2.1.1. FIFO
Mode
In FIFO mode, the transmit data is stored in integrated FIFO register memory. The TX FIFO is accessed by writing
Command 66h followed directly by the data/clk that the host wants to write into the TX FIFO.
If the packet handler is enabled, the data bytes stored in FIFO memory are “packaged” together with other fields
and bytes of information to construct the final transmit packet structure. These other potential fields include the
Preamble, Sync word, Header, CRC checksum, etc. The configuration of the packet structure in TX mode is
determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler
properties. If the Automatic Packet Handler is disabled, the entire desired packet structure should be loaded into
FIFO memory; no other fields (such as Preamble or Sync word) will be automatically added to the bytes stored in
FIFO memory. For further information on the configuration of the FIFOs for a specific application or packet size,
see “6. Data Handling and Packet Handler” on page 26. The chip will return to the IDLE state programmed in the
argument of the “START TX” API command, TXCOMPLETE_STATE[3:0]. For example, the chip may be placed
into TX mode by sending the “START TX” command and by writing the 30h to the TXCOMPLETE_STATE[3:0]
argument. The chip will transmit all of the contents of the FIFO, and the ipksent interrupt will occur. When this event
occurs, the chip will return to the ready state as defined by TXCOMPLETE_STATE[3:0] = 30h.
4.2.1.2. Direct
Mode
For legacy systems that perform packet handling within the host MCU or other baseband chip, it may not be
desirable to use the FIFO. For this scenario, a Direct mode is provided, which bypasses the FIFOs entirely. In TX
Direct mode, the TX modulation data is applied to an input pin of the chip and processed in “real time” (i.e., not
stored in a register for transmission at a later time). Any of the GPIOs may be configured for use as the TX Data
input function. Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is
desired (only the TX Data input pin is required for FSK).
T
o
a
chieve direct mode, the GPIO must be configured in
the “GPIO_PIN_CFG” API command as well as the “MODEM_MOD_TYPE” API property. For GFSK,
“TX_DIRECT_MODE_TYPE” must be set to Synchronous. For 2FSK or OOK, the type can be set to asynchronous
or synchronous. The MOD_SOURCE[1:0] should be set to 01h for are all direct mode configurations.
20
Rev 0.1
Si4063/60
5. Internal
Functional Blocks
The following sections provide an overview to the key internal blocks and features.
5.1. Synthesizer
An integrated Sigma Delta (
) Fractional-N PLL synthesizer capable of operating over the bands from 142–175,
283–350, 420–525, and 850–1050 MHz for the Si406x. Using a
synthesizer has many advantages; it provides
flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is
applied directly to the loop in the digital domain through the fractional divider, which results in very precise
accuracy and control over the transmit deviation. The frequency resolution in the 850–1050 MHz band is 28.6 Hz
with more resolution in the other bands. The nominal reference frequency to the PLL is 30 MHz, but any XTAL
frequency from 25 to 32 MHz may be used. The modem configuration calculator in WDS will automatically account
for the XTAL frequency being used. The PLL utilizes a differential LC VCO with integrated on-chip inductors. The
output of the VCO is followed by a configurable divider, which will divide the signal down to the desired output
frequency band.
5.1.1. Synthesizer Frequency Control
The frequency is set by changing the integer and fractional settings to the synthesizer. The WDS calculator will
automatically provide these settings, but the synthesizer equation is shown below for convenience. The APIs for
setting the frequency are FREQ_CONTROL_INTE, FREQ_CONTROL_FRAC2, FREQ_CONTROL_FRAC1, and
FREQ_CONTROL_FRAC0.
fc_frac
2
19
2
freq_xo
outdiv
—————–
—————————
–
–
Hz
RF_channel
=
fc_inte
+
Note:
The fc_frac/2
19
value in the above formula has to be a number between 1 and 2.
Table 11. Output Divider (Outdiv) Values for the Si4063/60
Outdiv
Lower (MHz)
Upper (MHz)
175
24
12
8
142
284
420
850
350
525
4
1050
Rev 0.1
21
Si4063/60
5.1.1.1. EZ
Frequency Programming
In applications that utilize multiple frequencies or channels, it may not be desirable to write four API registers each
time a frequency change is required. EZ frequency programming is provided so that only a single register write
(channel number) is required to change frequency. A base frequency is first set by first programming the integer
and fractional components of the synthesizer. This base frequency will correspond to channel 0. Next, a channel
step
size
is
programmed
into
the
FREQ_CONTROL_CHANNEL_STEP_SIZE_1
and
FREQ_CONTROL_CHANNEL_STEP_SIZE_0 API registers. The resulting frequency will be:
RF Frequency
=
Base Frequency
+
Channel
Stepsize
The second argument of the START_TX is CHANNEL, which sets the channel number for EZ frequency
programming. For example, if the channel step size is set to 1 MHz, the base frequency is set to 900 MHz with the
INTE and FRAC API registers, and a CHANNEL number of 5 is programmed during the START_TX command, the
resulting frequency will be 905 MHz. If no CHANNEL argument is written as part of the START_TX command, it will
default to the previous value. The initial value of CHANNEL is 0; so, if no CHANNEL value is written, it will result in
the programmed base frequency.
5.2. Transmitter
(TX)
The Si4063 contains an integrated +20 dBm transmitter or power amplifier that is capable of transmitting from –20
to +20 dBm. The output power steps are less than 0.25 dB within 6 dB of max power but become larger and more
non-linear close to minimum output power. The Si4063 PA is designed to provide the highest efficiency and lowest
current consumption possible. The Si4060 is designed to supply +10 dBm output power for less than 20 mA for
applications that require operation from a single coin cell battery. The Si4060 can also operate with either class-E
or switched current matching and output up to +13 dBm TX power. All PA options are single-ended to allow for
easy antenna matching and low BOM cost. Automatic ramp-up and ramp-down is automatically performed to
reduce unwanted spectral spreading.
Chip’s TXRAMP pin is disabled by default to save current in cases where on-chip PA will be able to drive the
antenna. In cases where on-chip PA will drive the external PA, and the external PA needs a ramping signal,
TXRAMP is the signal to use.
T
o
e
nable TXRAM
P
,
s
et the API Property PA_MODE[7] = 1. TXRAMP will start to
ramp up, and ramp down at the SAME time as the internal on-chip PA ramps up/down.
The ramping speed is programmed by TC[3:0] in the PA_RAMP_EX API property, which has the following
characteristics:
TC
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
Ramp Time (µs)
2.0
2.1
2.2
2.4
2.6
2.8
3.1
3.4
3.7
4.1
4.5
5.0
6.0
22
Rev 0.1
Si4063/60
13.0
14.0
15.0
8.0
10.0
20.0
The ramping profile is close to a linear ramping profile with smoothed out corner when approaching Vhi and Vlo.
The TXRAMP pin can source up to 1
mA without voltage drooping. The TXRAMP pin’s sinking capability is
equivalent to a 10 k
pull-down resistor.
Vhi = 3 V when Vdd > 3.3 V. When Vdd < 3.3 V, the Vhi will be closely following the Vdd, and ramping time will be
smaller also.
Vlo = 0 V when NO current needed to be sunk into TXRAMP pin. If 10 µA need to be sunk into the chip, Vlo will be
10 µA x 10k = 100 m
V
.
Number
0x2200
0x2201
Command
PA_MODE
Summary
Sets PA type.
PA_PWR_LVL
Adjust TX power in fine steps.
Adjust TX power in coarse steps
and optimizes for different
match configurations.
0x2202
PA_BIAS_CLKDUTY
PA_TC
Changes the ramp up/down time
of the PA.
0x2203
5.2.1. Si4063: +20 dBm PA
The +20 dBm configuration utilizes a class-E matching configuration. Typical performance for the 900 MHz band
for output power steps, voltage, and temperature are shown in Figures 8–10. The output power is changed in 128
steps through PA_PWR_LVL API. For detailed matching values, BOM, and performance at other frequencies, refer
to the PA Matching application note.
TX Power vs. PA_PWR_LVL
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
-35
0
10 20 30 40 50 60 70 80 90
100 110 120
PA_PWR_LVL
Figure 8. +20 dBm TX Power vs. PA_PWR_LVL
Rev 0.1
23
Si4063/60
TX Power vs. VDD
22
20
18
16
14
12
10
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Supply Voltage (VDD)
Figure 9. +20 dBm TX Power vs. VDD
TX Power vs Temp
20.5
20
19.5
19
18.5
18
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (C)
Figure 10. +20 dBm TX Power vs. Temp
24
Rev 0.1
Si4063/60
5.3. Crystal
Oscillator
The Si406x includes an integrated crystal oscillator with a fast start-up time of less than 250 µs. The design is
differential with the required crystal load capacitance integrated on-chip to minimize the number of external
components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz, but the circuit is
designed to handle any XTAL from 25 to 32 MHz. If a crystal different than 30 MHz is used, the POWER_UP API
boot command must be modified. The WDS calculator crystal frequency field must also be changed to reflect the
frequency being used. The crystal load capacitance can be digitally programmed to accommodate crystals with
various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal
load capacitance is programmed through the GLOBAL_XO_TUNE API property. The total internal capacitance is
11 pF and is adjustable in 127 steps (70 fF/step). The crystal frequency adjustment can be used to compensate for
crystal production tolerances. The frequency offset characteristics of the capacitor bank are demonstrated in
Figure 11.
Figure 11. Capacitor Bank Frequency Offset Characteristics
Utilizing the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal
can be canceled.
A TCXO or external signal source can easily be used in place of a conventional XTAL and should be connected to
the XIN pin. The incoming clock signal is recommended to be peak-to-peak swing in the range of 600 mV to 1.4 V
and ac-coupled to the XIN pin. If the peak-to-peak swing of the TCXO exceeds 1.4
V peak-to-peak, then dc
coupling to the XIN pin should be used. The maximum allowed swing on XIN is 1.8 V peak-to-peak.
The XO capacitor bank should be set to 0 whenever an external drive is used on the XIN pin. In addition, the
POWER_UP command should be invoked with the TCXO option whenever external drive is used.
Rev 0.1
25
Si4063/60
6. Data
Handling and Packet Handler
6.1. TX
FIFOs
One 64-byte FIFO is integrated into the chip for TX as shown in Figure 12. Writing to command Register 66h loads
data into the TX FIFO. The TX FIFO has a threshold for when the FIFO is almost empty, which is set by the
“TX_FIFO_EMPTY” property. An interrupt event occurs when the data in the TX FIFO reaches the almost empty
threshold. If more data is not loaded into the FIFO, the chip automatically exits the TX state after the
PACKET_SENT interrupt occurs. The TX FIFO may be cleared or reset with the “FIFO_RESET” command.
TX FIFO
TX FIFO Almost
Empty Threshold
Figure 12. TX FIFO
6.2. Packet
Handler
When using the FIFOs, automatic packet handling may be enabled. The usual fields for network communication,
such as preamble, synchronization word, headers, packet length, and CRC, can be configured to be automatically
added to the data payload. The fields needed for packet generation normally change infrequently and can
therefore be stored in registers. Automatically adding these fields to the data payload in TX mode greatly reduces
the amount of communication between the microcontroller and Si406x. It also greatly reduces the required
computational power of the microcontroller. The general packet structure is shown in Figure 13. Any or all of the
fields can be enabled and checked by the internal packet handler.
P
r
e
a
m
b
l
e
1-255 Bytes
1-4 Bytes
Co
n
f
ig
Con
f
ig
Co
n
f
ig
Co
n
f
ig
Co
n
f
ig
0, 2, or 4
By
t
es
0, 2, or 4
By
t
es
0,
2
,
o
r 4
B
y
t
es
0, 2, or 4
Bytes
0, 2, or 4
Bytes
Figure 13. Packet Handler Structure
The fields are highly programmable and can be used to check any kind of pattern in a packet structure. The
general functions of the packet handler include the following:
Construction of Preamble field in TX mode
Construction of Sync field in TX mode
Construction of Data Field from FIFO memory in TX mode
Construction of CRC field (if enabled) in TX mode
Data whitening and/or Manchester encoding (if enabled) in TX mode
26
Rev 0.1
Si4063/60
7. Auxiliary
Blocks
7.1. Wake-up
Timer and 32 kHz Clock Source
The chip contains an integrated wake-up timer that can be used to periodically wake the chip from sleep mode. The
wake-up timer runs from either the internal 32 kHz RC Oscillator, or from an external 32 kHz XTAL.
The wake-up timer can be configured to run when in sleep mode. If WUT_EN = 1 in the GLOBAL_WUT_CONFIG
property, prior to entering sleep mode, the wake-up timer will count for a time specified defined by the
GLOBAL_WUT_R and GLOBAL_WUT_M properties. At the expiration of this period, an interrupt will be generated
on the nIRQ pin if this interrupt is enabled in the INT_CTL_CHIP_ENABLE property. The microcontroller will then
need to verify the interrupt by reading the chip interrupt status either via GET_INT_STATUS or a fast response
register. The formula for calculating the Wake-Up Period is as follows:
4
2
WUT_R
32
768
—————————–
WUT
=
WUT_M
ms
The RC oscillator frequency will change with temperature; so, a periodic recalibration is required. The RC oscillator
is automatically calibrated during the POWER_UP command and exits from the Shutdown state.
T
o
e
nable the
recalibration feature, CAL_EN must be set in the GLOBAL_WUT_CONFIG property, and the desired calibration
period should be selected via WUT_CAL_PERIOD[2:0] in the same API property. During the calibration, the
32 kHz RC oscillator frequency is compared to the 30 MHz XTAL and then adjusted accordingly. The calibration
needs to start the 30 MHz XTAL, which increases the average current consumption; so, a longer CAL_PERIOD
results in a lower average current consumption. The 32
kHz XTAL accuracy is comprised of both the XTAL
parameters and the internal circuit. The XTAL accuracy can be defined as the XTAL initial error + XTAL aging +
XTAL temperature drift + detuning from the internal oscillator circuit. The error caused by the internal circuit is
typically less than 10 ppm.
Rev 0.1
27
Si4063/60
Table 12. WUT Specific Commands and Properties
API Properties
Description
Requirements/Notes
WUT_EN—Enable/disable wake up timer.
WUT_LBD_EN—Enable/disable low battery detect
measurement on WUT interval.
WUT_LDC_EN:
GLOBAL_WUT_CONFIG
GLOBAL WUT configuration
0 = Disable low duty cycle operation.
2 = TX LDC operation
treated as wakeup START_TX
WUT state is used
CAL_EN—Enable calibration of the 32 kHz RC
oscillator
WUT_CAL_PERIOD[2:0]—Sets calibration period.
WUT_M—Parameter to set the actual wakeup time.
See equation above.
GLOBAL_WUT_M_15_8
GLOBAL_ WUT_M_7_0
GLOBAL_WUT_R
Sets HW WUT_M[15:8]
Sets HW WUT_M[7:0]
WUT_M—Parameter to set the actual wakeup time.
See equation above.
WUT_R—Parameter to set the actual wakeup time.
See equation above.
WUT_SLEEP:
Sets WUT_R[4:0]
Sets WUT_SLEEP to choose
WUT state
0 = Go to ready state after WUT
1 = Go to sleep state after WUT
WUT_LDC—Parameter to set the actual wakeup
time.
GLOBAL_WUT_LDC
Sets FW internal WUT_LDC
Table 13. WUT Related API Commands and Properties
Command/Property
Description
WUT Interrupt Enable
Requirements/Notes
CHIP_INT_STATUS_EN—Enables chip status
interrupt.
INT_CTL_ENABLE
Interrupt enable property
WUT_EN—Enables WUT interrupt.
INT_CTL_CHIP_ENABLE Chip
interrupt enable property
32 kHz Clock Source Selection
CLK_32K_SEL[2:0]—Configuring the source of
WU
T
.
GLOBAL_CLK_CFG
GPIO_PIN_CFG
START_TX
Clock configuration options
WUT Interrupt Output
GPIOx_MODE[5:0] = 14 and
NIRQ_MODE[5:0] = 39.
Host can enable interrupt on
WUT expire
TX Operation
START TX when wake up timer
expire
START = 1.
28
Rev 0.1
Si4063/60
7.2. Low
Duty Cycle Mode
The low duty cycle (LDC) mode is implemented to automatically wake-up the transmitter to send a packet. It allows
low average current polling operation by the Si406x for which the wake-up timer (WUT) is used. TX LDC operation
must be set via the GLOBAL_WUT_CONFIG property when setting up the WU
T
.
T
he LDC wake-up period is
determined by the following formula:
4
2
WUT_R
32
768
—————————–
LDC
=
WUT_LDC
ms
where the WUT_LDC parameter can be set by the GLOBAL_WUT_LDC property. The WUT period must be set in
conjunction with the LDC mode duration; for the relevant API properties, see the wake-up timer (WUT) section.
Figure 14. TX LDC Sequences
In TX LDC mode, the transmitter periodically wakes itself up to transmit a packet that is in the data buffer. If a
packet has been transmitted, nIRQ goes low if the option is set in the INT_CTL_ENABLE property. After
transmitting, the transmitter immediately returns to the WUT state and stays there until the next wake-up time
expires.
Rev 0.1
29
Si4063/60
7.3. Temperature,
Battery Voltage, and Auxiliary ADC
The Si406x family contains an integrated auxiliary ADC for measuring internal battery voltage, an internal
temperature sensor, or an external component over a GPIO. The ADC utilizes a SAR architecture and achieves
11-bit resolution. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the input
voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first
sending the GET_ADC_READING command and enabling the inputs that are desired to be read: GPIO, battery, or
temp. The temperature sensor accuracy at 25 °C is typically ±2 °C.
Command Stream
GET_ADC_READING
Command
7
6
5
4
3
2
1
0
CMD
0x14
ADC_EN
0
0
0
TEMPERATURE_EN BATTERY_VOLTAGE_EN
ADC_GPIO_
EN
ADC_GPIO_
PIN[1:0]
ADC_CFG
UDTIME[3:0]
GPIO_ATT[3:0]
Reply Stream
GET_ADC_READING Reply
CTS
7
6
5
4
3
2
1
0
CTS[7:0]
GPIO_ADC
GPIO_ADC[15:8]
GPIO_ADC[7:0]
BATTERY_ADC[15:8]
BATTERY_ADC[7:0]
TEMP_ADC[15:8]
TEMP_ADC[7:0]
Reserved
GPIO_ADC
BATTERY_ADC
BATTERY_ADC
TEMP_ADC
TEMP_ADC
RESERVED
RESERVED
Reserved
Parameters
TEMPERATURE_EN
0 = Do not perform ADC conversion of temperature. This will read 0 value in reply TEMPERATURE.
1 = Perform ADC conversion of temperature. This results in TEMP_ADC.
T
e
mp (°C) = TEMP_ADC[15:0] x 568/2560 – 297
BATTERY_VOLTAGE_EN
0 = Don’t do ADC conversion of battery voltage, will read 0 value in reply BATTERY_ADC
1 = Do ADC conversion of battery voltage, results in BATTERY_ADC. Vbatt = 3*BATTERY_ADC/1280
ADC_GPIO_EN
0 = Don’t do ADC conversion on GPIO, will read 0 value in reply
1 = Do ADC conversion of GPIO, results in GPIO_ADC. Vgpio = GPIO_ADC/GPIO_ADC_DIV where
GPIO_ADC_DIV is defined by GPIO_ATT selection.
ADC_GPIO_PIN[1:0] – Select GPIOx pin. The pin must be set as input.
0 = Measure voltage of GPIO0
1 = Measure voltage of GPIO1
2 = Measure voltage of GPIO2
30
Rev 0.1
Si4063/60
3 = Measure voltage of GPIO3
UDTIME[7:4] – ADC conversion Time = SYS_CLK / 12 / 2^(UDTIME + 1). Defaults to 0xC if ADC_CFG is 0.
Selecting shorter conversion times will result in lower ADC resolution and longer times will result in higher ADC
resolution.
GPIO_ATT[3:0] – Sets attenuation of gpio input voltage when vgpio measured. Defaults to 0xC if ADC_CFG is 0.
0x0 = ADC range 0 to 0.8
V
.
G
PIO_ADC_DIV = 2560
0x4 = ADC range 0 to 1.6
V
.
G
PIO_ADC_DIV = 1280
0x8 = ADC range 0 to 2.4
V
.
G
PIO_ADC_DIV = 853.33
0x9 = ADC range 0 to 3.6
V
.
G
PIO_ADC_DIV = 426.66
0xC = ADC range 0 to 3.2
V
.
G
PIO_ADC_DIV = 640
Response
GPIO_ADC[15:0] – ADC value of voltage on GPIO
BATTERY_ADC[15:0] – ADC value of battery voltage
TEMP_ADC[15:0] – ADC value of temperature sensor voltage
RESERVED[7:0] – RESERVED FOR FUTURE USE
RESERVED[7:0] – RESERVED FOR FUTURE USE
7.4. Low
Battery Detector
The low battery detector (LBD) is enabled and utilized as part of the wake-up-timer (WUT). The LBD function is not
available unless the WUT is enabled, but the host MCU can manually check the battery voltage anytime with the
auxiliary ADC. The LBD function is enabled in the GLOBAL_WUT_CONFIG API property. The battery voltage will
be compared against the threshold each time the WUT expires. The threshold for the LBD function is set in
GLOBAL_LOW_BATT_THRESH. The threshold steps are in increments of 50 mV, ranging from a minimum of
1.5 V up to 3.05 V. The accuracy of the LBD is ±3%. The LBD notification can be configured as an interrupt on the
nIRQ pin or enabled as a direct function on one of the GPIOs.
Rev 0.1
31
Si4063/60
8. Pin
Descriptions: Si4063/60
20 19 18 17
SDN
NC
NC
TX
1
16
2
15 nSEL
14 SDI
13 SDO
12 SCLK
11 nIRQ
3
4
5
GND
PAD
NC
6
7
8
9
10
Pin
Pin Name
I/0
Description
Shutdown Input Pin
.
0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode.
When SDN = 1, the chip will be completely shut down, and the contents of the
registers will be lost. Can be used to reset the chip
1
SDN
I
2
3
NC
NC
Transmit Output Pin.
4
TX
O
The PA output is an open-drain connection, so the L-C match must supply
VDD (+3.3 VDC nominal) to this pin.
No Connect. Not connected internally to any circuitry.
5
6
NC
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators.
VDD
VDD
O
The recommended VDD supply voltage is +3.3 V.
Programmable Bias Output with Ramp Capability for External FET PA.
7
TXRAMP
See “5.2. Transmitter (TX)” on page 22.
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators.
8
9
VDD
VDD
I/O
The recommended VDD supply voltage is +3.3 V.
GPIO0
General Purpose Digital I/O.
May be configured through the registers to perform various functions including:
Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect, etc.
10
GPIO1
I/O
General Microcontroller Interrupt Status Output.
When the Si406x exhibits any one of the interrupt events, the nIRQ pin will be
set low = 0. The Microcontroller can then determine the state of the interrupt
by reading the interrupt status. No external resistor pull-up is required, but it
may be desirable if multiple interrupt lines are connected.
11
nIRQ
O
32
Rev 0.1
Si4063/60
Pin
Pin Name
I/0
Description
Serial Clock Input.
0–VDD V digital input. This pin provides the serial data clock function for the
4-line serial data bus. Data is clocked into the Si406x on positive edge transi-
tions.
12
SCLK
I
0–VDD V Digital Output.
13
14
SDO
SDI
O
I
Provides a serial readback function of the internal control registers.
Serial Data Input.
0–VDD V digital input. This pin provides the serial data stream for the 4-line
serial data bus.
Serial Interface Select Input.
15
nSEL
I
0–VDD V digital input. This pin provides the Select/Enable function for the
4-line serial data bus.
Crystal Oscillator Output.
16
17
XOUT
XIN
O
I
Connect to an external 25 to 32 MHz crystal, or leave floating when driving
with an external source on XIN.
Crystal Oscillator Input.
Connect to an external 25 to 32 MHz crystal, or connect to an external source.
Connect to PCB ground.
18
19
GND
GND
I/O
GPIO2
General Purpose Digital I/O.
May be configured through the registers to perform various functions, including
Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect.
20
GPIO3
I/O
The exposed metal paddle on the bottom of the Si406x supplies the RF and cir-
cuit ground(s) for the entire chip. It is very important that a good solder connec-
tion is made between this exposed metal paddle and the ground plane of the
PCB underlying the Si406x.
PKG PADDLE_GND
GND
Rev 0.1
33
Si4063/60
9. Ordering
Information
1,2
Description
Package Type
Operating
Temperature
Part Number
QFN-20
Pb-free
ISM EZRadioPRO Transmitter
Si4063-Bxx-FM
Si4060-Bxx-FM
–40 to 85 °C
–40 to 85 °C
QFN-20
Pb-free
ISM EZRadioPRO Transmitter
Notes:
1.
Add an “(R)” at the end of the device part number to denote tape and reel option.
2.
For Bxx, the first “x” indicates the ROM version, and the second “x” indicates the FW version in OT
P
.
34
Rev 0.1
Si4063/60
10. Package
Outline: Si4063/60
Figure 15 illustrates the package details for the Si406x.
T
a
ble 14 lists the values for the dimensions shown in the
illustration.
2X
bbb C
A
D
D2
B
Pin 1
(
L
a
ser)
e
20
1
E2
2X
aaa C
2
0
x b
c
c
c C
d
d
d
C A B
eee C
S
E
ATING
P
L
ANE
C
Figure 15. 20-Pin Quad Flat No-Lead (QFN)
Rev 0.1
35
Si4063/60
Table 14. Package Dimensions
Min
0.80
0.00
Nom
0.85
Max
0.90
0.05
Dimension
A
A1
A3
b
0.02
0.20 REF
0.25
0.18
2.45
0.30
2.75
D
4.00 BSC
2.60
D2
e
0.50 BSC
4.00 BSC
2.60
E
E2
L
2.45
0.30
2.75
0.50
0.40
aaa
bbb
ccc
ddd
eee
0.15
0.15
0.10
0.10
0.08
Notes:
1.
All dimensions are shown in millimeters (mm) unless otherwise noted.
2.
Dimensioning and tolerancing per ANSI Y14.5M-1994.
3.
This drawing conforms to the JEDEC Solid State Outline MO-220,
Variation VGGD-8.
4.
Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
36
Rev 0.1
Si4063/60
11. PCB
Land Pattern: Si4063/60
Figure 16 illustrates the PCB land pattern details for the Si406x.
T
a
ble 15 lists the values for the dimensions shown
in the illustration.
Figure 16. PCB Land Pattern
Rev 0.1
37
Si4063/60
Table 15. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
3.90
3.90
Max
4.00
4.00
C1
C2
E
0.50 REF
X1
X2
Y1
Y2
0.20
2.55
0.65
2.55
0.30
2.65
0.75
2.65
Notes:
General
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
This land pattern design is based on IPC-7351 guidelines.
Solder Mask Design
3.
All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
4.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
5.
The stencil thickness should be 0.125 mm (5 mils).
6.
The ratio of stencil aperture to land pad size should be 1:1 for the
perimeter pads.
7.
A 2×2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be
used for the center ground pad.
Card Assembly
8.
A No-Clean, Type-3 solder paste is recommended.
9.
The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for small body components.
38
Rev 0.1
Si4063/60
12. Top
Marking
12.1. Si4063/60
Top Marking
12.2. Top
Marking Explanation
YAG Laser
Mark Method
1
1
40631B = Si4063 Rev 1B
40601B = Si4060 Rev 1B
Part Number
Line 1 Marking
Line 2 Marking
2
TTTTT = Internal Code
Internal tracking code.
YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and workweek of the mold date.
Line 3 Marking
Notes:
1.
The first letter after the part number is part of the ROM revision. The last letter indicates the firmware
revision.
2.
The first letter of this line is part of the ROM revision.
Rev 0.1
39
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Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and “Typical” parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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