SKYWORKS-SILICON-LABS-SI4745-C10-GM
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Si4740/41/42/43/44/45-C10
A
U
TOMOTIVE
A
M/FM R
A
DIO
R
E
CEIVER
Features
Worldwide FM band support
(64–108 MHz)
Worldwide AM band support
(520–1710 kHz)
LW band support (153–288 kHz)
(Si4742/43/44/45 only)
MW (520–1710 kHz) and
SW (2.3–30 MHz) support
(Si4742/43/44/45 only)
NOAA weather band support
(162.4–162.55 MHz) (Si4742/43 only)
FM multipath detection and mitigation
AM/FM noise blanker
AM and FM programmable
channel bandwidth filters
Digital FM stereo decoder
Advanced patented RDS/RBDS
processor (Si4741/43/45 only)
Automatic gain control (AGC)
Integrated AM and FM low-noise
amplifier (LNA)
Image-rejection mixer
Ordering Information:
Frequency synthesizer with
integrated voltage controlled
oscillator (VCO)
Low-IF conversion with no
external ceramic filters
See page 39.
Pin Assignments
(Si4742/43/44/45 only)
Received signal quality indicators (RSSI,
SNR, frequency offset, multi-path
interference)
AM and FM programmable seek tuning
AM and FM programmable soft mute
control
FM Hi-cut control (Si4742/43/44/45 only)
Power line noise rejection/AM lo-cut filter
FM programmable stereo-mono blend
3.0 to 3.6 V supply voltage
Programmable reference clock
AECQ-100 qualified
–40 to 85 ºC operation
Digital audio output (I
2
S)
(Si4741/43/45 only)
Si4740/41/42/43/44/45-C10-GM
(
T
o
p View)
24-pin 4 x 4 mm QFN package
Pb-free/RoHS compliant
24 23 22 21 20 19
FMI
RFGND
AGC1
NC
1
2
3
4
5
6
18 DFS
17 DOUT
16 LOUT
15 ROUT
14 GND
13 VDD
GND
PAD
Applications
OEM car audio systems
After-market car audio systems
GND
AMI
Description
7
8
9
10 11 12
The Si474x AM/FM receiver family is the most highly integrated automotive grade
and performance solution available.
Functional Block Diagram
Patents pending
Note:
T
o
e
nsure proper operation and
receiver performance, follow the
guidelines in “AN400: Si474x
AM/FM Receiver Layout Guide.”
Silicon Laboratories will evaluate
schematics and layouts for
qualified customers.
Si474x
RDS
DOUT
DFS
FMI
DIGITAL
AUDIO
LNA
AGC
WEAK
SIGNAL
CONDITION
DCLK
ADC
ADC
DAC
DAC
ROUT
LOUT
AMI
LNA
AGC
DSP
GND
AGC
VDD
GPO1-3
VIO
QUALITY
DETECTOR
3.0–3.6 V
LDO
AFC
CNTRL
GND
RST
Rev. 1.0 9/09
Copyright © 2009 by Silicon Laboratories
Si4740/41/42/43/44/45
Si4740/41/42/43/44/45-C10
2
Rev. 1.0
Si4740/41/42/43/44/45-C10
T
A
BLE OF
C
O
NTENTS
Section
Page
1. Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
2. Typical Application Schematic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
7
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
1
8
4. Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
0
4.1. Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
0
4.2. Block Diagram and Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
1
4.3. FM Receiver Front-end
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
2
4.4. AM Receiver Front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
2
4.5. Received Signal Qualifiers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
2
4.6. Digital Audio Interface (Si4741/43/45 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
2
4.7. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
4
4.8. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
6
4.9. Stereo DACs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
6
4.10. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
6
4.11. Seek and Valid Station Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
7
4.12. FM Hi-Cut Control (Si4742/43/44/45 only)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
7
4.13. AM/FM Noise Blanker (Si4742/43/44/45 only)
. . . . . . . . . . . . . . . . . . . . . . . . . . .
.
2
9
4.14. Programming Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
3
4.15. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
3
4.16. GPO 1–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
3
4.17. RDS/RBDS Advanced Processor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
3
4.18. Reference Clock
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
5
4.19. Control Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
5
5. Commands and Properties
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
7
6. Pin Descriptions: Si4740/41/42/43/44/45-C10-GM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
8
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
3
9
8. Package Markings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
1
8.1. Si4740/41/42/43/44/45-C10 Top Mark
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
1
8.2. Top Mark Explanation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
1
9. Package Outline: Si4740/41/42/43/44/45-C10 QFN
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
2
10. PCB Land Pattern: Si4740/41/42/43/44/45-C10 QFN
. . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
3
11. Additional Reference Resources
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
4
Document Change List
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
5
Contact Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
4
6
Rev. 1.0
3
Si4740/41/42/43/44/45-C10
1. Electrical
Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Test Condition
Min
3.0
2.7
10
Typ
—
Max
3.6
3.6
—
Unit
V
V
DD
Interface Supply Voltage
V
—
V
IO
DDRISE
Power Supply Powerup Rise Time
V
—
µs
µs
Interface Power Supply Powerup
Rise Time
V
10
—
—
IORISE
Ambient
T
e
mperature
T
–40
25
85
C
A
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at V
DD
= 3.3 V and 25
C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings
1,2
Parameter
Supply Voltage
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
V
DD
Interface Supply Voltage
V
V
IO
IN
3
Input Current
I
mA
V
3
Input Voltage
V
T
–0.3 to (V
+ 0.3)
IN
IO
Operating
T
e
mperature
Storage
T
e
mperature
–45 to 95
–55 to 150
0.4
C
C
OP
T
STG
4
RF Input Level
V
pK
Notes:
1.
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2.
The Si4740/41/42/43/44/45-C10 devices are high-performance RF integrated circuits with certain pins having an ESD
rating of < 2 kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3.
For input pins SCLK, SEN, SDIO, RS
T
,
R
CLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4.
At RF input pins, FMI and AMI.
4
Rev. 1.0
Si4740/41/42/43/44/45-C10
Table 3. DC Characteristics
(V
DD
= 3.0 to 3.6
V
,
V
IO
= 2.7 to 3.6
V
, T
A
= –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
—
Typ
26
Max
28.6
23
Unit
mA
mA
mA
FM Mode
Supply Current
I
I
FM
FM
AM
WB Mode
(Si4742/43 only)
Supply Current
—
20
AM Mode
Supply Current
I
—
19
23
Supplies and Interface
Interface Supply Current
I
—
—
—
300
6
400
12
µA
µA
µA
IO
1,2
Powerdown Current
I
PD
1
Interface Powerdown Current
I
SCLK, DFS, DCLK,
RCLK inactive
6
12
IO
3
High Level Input Voltage
V
0.7 x V
—
—
—
—
—
—
0.3 x V
10
V
V
IH
IO
3
Low Level Input Voltage
V
IL
IO
3
High Level Input Current
I
V
= V
= 3.6 V
–10
µA
µA
IH
IN
IO
3
Low Level Input Current
I
V
= 0 V,
IN
–10
10
IL
V
= 3.6 V
IO
4
High Level Output Voltage
V
I
= 500 µA
= –500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
OUT
IO
4
Low Level Output Voltage
V
I
0.2 x V
OL
IO
Notes:
1.
Specifications are guaranteed by characterization.
2.
Refer to Section “4.19. Control Interface” on page 35.
3.
For input pins SCLK, SEN, SDIO, RS
T
,
a
nd RCLK.
4.
For output pins SDIO, DFS, GPO1, GPO2, and GPO3.
Rev. 1.0
5
Si4740/41/42/43/44/45-C10
Table 4.
Reset Timing Characteristics
1,2,3
(V
DD
= 3.0 to 3.6
V
,
V
IO
= 2.7 to 3.6
V
, T
A
= –40 to 85 °C)
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST
t
SRST
GPO1, GPO2/INT Hold from RST
t
—
—
ns
HRST
Important Notes:
1.
When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RS
T
.
2.
When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RS
T
,
a
nd stays high until
after the first start condition.
3.
When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RS
T
.
4.
If GPO1 and GPO2 are actively driven by the user, then minimum t
SRST
is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum t
SRST
is 100 µs, to provide time for on-chip 1 M
devices (active while RST is low) to pull GPO1 high and
GPO2 low.
t
SRST
t
HRST
70%
RST
30%
70%
GPO1
30%
70%
GPO2
30%
Figure 1. Reset Timing Parameters for Busmode Select Method
6
Rev. 1.0
Si4740/41/42/43/44/45-C10
Table 5. 2-Wire Control Interface Characteristics
1,2,3
(V
DD
= 3.0 to 3.6
V
,
V
IO
= 2.7 to 3.6
V
, T
A
= –40 to 85 °C)
Parameter
Symbol Test
Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO
Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO
Hold
0.6
—
—
µs
HD:STA
(START)
SDIO Input to SCLK
Setup
t
t
100
0
—
—
—
—
900
—
ns
ns
µs
SU:DAT
4,5
SDIO Input to SCLK
Hold
HD:DAT
SU:STO
SCLK input to SDIO
Setup
t
0.6
(STOP)
STOP to START Time
SDIO Output Fall Time
t
1.3
—
—
—
µs
ns
BUF
t
250
f:OUT
C
b
———-
1pF
20
+
0.1
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
C
b
r:IN
———-
1pF
20
+
0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1.
When V
IO
= 0
V
,
S
CLK and SDIO are low impedance.
2.
When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RS
T
.
3.
When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RS
T
,
a
nd stays high
until after the first start condition.
4.
The Si474x delays SDIO by a minimum of 300 ns from the V
IH
threshold of SCLK to comply with the minimum t
HD:DAT
specification.
5.
The maximum t
HD:DAT
has only to be met when f
SCL
= 400 kHz. At frequencies below 400 kHz, t
HD:DAT
may be violated
as long as all other timing parameters are met.
Rev. 1.0
7
Si4740/41/42/43/44/45-C10
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
r:IN
t
f:IN
t
SP
t
SU:STO
t
BUF
70%
30%
SCLK
SDIO
70%
30%
t
f:IN,
t
f:OUT
START
t
HD:DAT
t
SU:DAT
t
r:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
D7-D0
D7-D0
SDIO
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.0
Si4740/41/42/43/44/45-C10
Table 6. 3-Wire Control Interface Characteristics
(V =
3.0 to 3.6
V
, V
=
2
.7 to 3.6
V
, T
A
= –40 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
20
10
10
2
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLK
Setup
SDIO Input to SCLK
Hold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLK
Hold
t
—
ns
HSEN
SCLK
to SDIO Output Valid
SCLK
to SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall Time
t
Read
Read
25
25
10
ns
CDV
t
2
ns
CDZ
t ,
t
—
ns
R
F
Note:
When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RS
T
.
70%
SCLK
30%
t
R
t
F
t
HSDIO
t
HIGH
t
LOW
t
HSEN
t
S
70%
30%
t
S
SEN
A6-A5,
R/W,
A4-A1
70%
30%
A7
A0
D15
D14-D1
D0
SDIO
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
70%
SCLK
SEN
30%
t
HSDIO
t
CDV
t
HSEN
t
S
t
CDZ
70%
30%
t
S
70%
30%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
Si4740/41/42/43/44/45-C10
Table 7. SPI Control Interface Characteristics
(V =
3.0 to 3.6
V
, V
=
2
.7 to 3.6
V
, T
A
= –40 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
15
10
5
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLK
Setup
SDIO Input to SCLK
Hold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLK
Hold
t
—
ns
HSEN
SCLK
to SDIO Output Valid
SCLK
to SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall Time
t
Read
Read
2
25
25
10
ns
CDV
t
2
ns
CDZ
t ,
t
—
ns
R
F
Note:
When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RS
T
.
70%
SCLK
30%
t
R
t
F
t
HIGH
t
LOW
t
HSDIO
t
HSEN
70%
30%
t
S
SEN
t
S
70%
30%
C7
C6
–C1
C0
D7
D6
–D1
D0
SDIO
Control Byte In
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
70%
30%
SCLK
t
CDV
t
S
t
HSEN
t
HSDIO
70%
30%
t
S
SEN
t
CDZ
70%
30%
SDIO
C7
C6
–C1
C0
D7
D6
–D1
D0
16 Data Bytes Out
(SDIO or GPO1)
Bus
Turnaround
Control Byte In
Figure 7. SPI Control Interface Read Timing Parameters
10
Rev. 1.0
Si4740/41/42/43/44/45-C10
Table 8. Digital Audio Interface Characteristics
(V =
3.0 to 3.6
V
, V
= 2.7 to 3.6 V, T
A
= –40 to 85 °C)
DD
IO
Parameter
Symbol Test
Condition
Min
26
10
10
5
Typ
—
Max
1000
—
Unit
ns
DCLK Cycle Time
t
DCT
DCH
DCLK Pulse Width High
t
—
ns
DCLK Pulse Width Low
t
—
—
ns
DCL
DFS Set-up Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
t
—
—
ns
SU:DFS
HD:DFS
t
5
—
—
ns
DOUT Propagation Delay from DCLK Falling
Edge
t
0
—
12
ns
PD:DOUT
t
DCH
t
DCL
DCLK
t
DCT
DFS
t
HD:DFS
t
SU:DFS
DOUT
t
PD:OUT
Figure 8. Digital Audio Interface Timing Parameters, I
2
S Mode
Rev. 1.0
11
Si4740/41/42/43/44/45-C10
Table 9. FM Receiver Characteristics
1,2
(V =
3.0 to 3.6
V
, V
=
2
.7 to 3.6
V
, T
A
= 25 °C)
DD
IO
Parameter
Test Condition
Min
Typ
Max
Unit
FM Receiver
Specifications Referred to Si4740/41/42/43/44/45-C10 Application Circuit Input
Input Frequency
64
10
—
—
—
—
—
108
200
3
MHz
kHz
FM Frequency Steps
3,4,5,6,7
Sensitivity
(S+N)/N = 26 dB
2
µV EMF
µV EMF
8
RDS Sensitivity
f = 2 kHz, RDS BLER < 5%
6
9
8
f = 2 kHz
RDSSYNC = 1
10 sec
3.8/60
—
µV EMF/
RDS
BLER%
RDS Synchronization Persistence
8
f = 2 kHz
RDSSYNC = 1
10 sec
—
5.9/10
—
µV EMF/
RDS
BLER%
RDS Synchronization Stability
8
f = 2 kHz
RF input = 60 dBµV EMF
—
—
90
—
—
ms
ms
RDS Synchronization Time
8
f = 2 kHz
105
RDS PI Lock Time
RF input = 60 dBµV EMF
6,8,9
LNA Input Resistance
3
4
4
5
—
6
k
pF
6,8,9
LNA Input Capacitance
3,4,7
Input IP3
400 and 800 kHz blockers
m = 0.3
100
40
37
38
60
53
72
–1
105
55
55
50
70
58
80
—
—
—
—
—
—
—
90
1
dBµV EMF
dB
3,4,6,8,9
AM Suppression
8
Image Rejection
f = 22.5 kHz
dB
Adjacent Channel Selectivity
Alternate Channel Selectivity
±200 kHz
dB
±400 kHz
dB
3,4,5,6,8
Strong Signal Distortion
RF Level 120 dBµV EMF
dB SINAD
mVRMS
dB
3,4,6,9
Audio Output Voltage
3,6,9,10
Audio Output L/R Imbalance
Notes:
1.
Additional testing information is available in application note, “AN388:Si470X/1X/2X/3X/4X Evaluation Board
T
e
st
Procedure.” Volume = maximum for all tests.
T
e
sted at F
= 98 MHz.
RF
2.
T
o
e
nsure proper operation and receiver performance, follow the guidelines in “AN400: Si474x AM/FM Receiver Layout
Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3.
F
= 1 kHz, 75 µs de-emphasis, MONO = enabled unless noted otherwise.
MOD
4.
f = 22.5 kHz.
5.
B =
300 Hz to 15 kHz.
AF
6.
f =
76 to 108 MHz.
RF
7.
AGC is disabled.
8.
Guaranteed by characterization.
9.
Measured at V
10.
f = 75 kHz.
11.
L = 1, R = 0.
= 60 dBµV
.
EMF
EMF
12.
At LOUT and ROUT pins.
12
Rev. 1.0
Si4740/41/42/43/44/45-C10
Table 9. FM Receiver Characteristics
1,2
(Continued)
(V =
3.0 to 3.6
V
, V
=
2
.7 to 3.6
V
, T
A
= 25 °C)
DD
IO
Parameter
Test Condition
–3 dB
Min
—
Typ
—
Max
30
—
Unit
Hz
kHz
dB
dB
%
8
Audio Frequency Response Low
8
Audio Frequency Response High
–3 dB
15
35
56
—
—
3,6,9,10,11
Audio Stereo Separation
45
—
3,4,5,6,9
Audio SNR
63
—
3,4,5,6,9
Audio THD
0.1
75
0.5
80
54
0.9
—
8
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
70
45
0.7
—
µs
µs
V
50
12
8
Audio Common Mode Voltage
Audio Common Mode Voltage
Audio Output Load Resis-
0.8
0.5 x V
—
High-Z mode
Single-ended
V
IO
10
—
k
8,10,12
tance
Audio Output Load Capaci-
tance
Single-ended
RCLK tolerance = 100 ppm
From powerdown
—
—
—
50
60
pF
8,10,12
8,12
Seek/Tune Time
40
ms/
channel
8
Powerup Time
—
–
3
—
—
110
3
ms
dB
FM RSSI Offset
Input levels of 8 and 60 dBµV
EMF
Notes:
1.
Additional testing information is available in application note, “AN388:Si470X/1X/2X/3X/4X Evaluation Board
T
e
st
Procedure.” Volume = maximum for all tests.
T
e
sted at F
= 98 MHz.
RF
2.
T
o
e
nsure proper operation and receiver performance, follow the guidelines in “AN400: Si474x AM/FM Receiver Layout
Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3.
F
= 1 kHz, 75 µs de-emphasis, MONO = enabled unless noted otherwise.
MOD
4.
f = 22.5 kHz.
5.
B =
300 Hz to 15 kHz.
AF
6.
f =
76 to 108 MHz.
RF
7.
AGC is disabled.
8.
Guaranteed by characterization.
9.
Measured at V
10.
f = 75 kHz.
11.
L = 1, R = 0.
= 60 dBµV
.
EMF
EMF
12.
At LOUT and ROUT pins.
Rev. 1.0
13
Si4740/41/42/43/44/45-C10
Table 10. WB Receiver Characteristics
1
(Si4742/43 only)
(V =
3.0 to 3.6
V
, V
=
2
.7 to 3.6
V
, T
= 25 °C)
DD
IO
A
Parameter
Input Frequency
Symbol
Test Condition
Min
162.4
—
Typ
—
Max
162.55
—
Unit
MHz
µV EMF
dB
F
RF
2,3,4,5
SINAD = 12 dB
±25 kHz
Mono
0.65
55
Sensitivity
40
—
Adjacent Channel Selectivity
2,3,4,5,6
35
45
—
dB
Audio S/N
7
Audio Frequency Response Low
–3 dB
—
—
300
—
Hz
7
Audio Frequency Response High
–3 dB
15
—
kHz
Notes:
1.
T
o
e
nsure proper operation and receiver performance, follow the guidelines in “AN400: Si474x AM/FM receiver Layout
Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2.
F
= 1 kHz.
MOD
3.
f = 3 kHz.
4.
BAF = 300 Hz to 15 kHz, A-weighted.
5.
F =
162.5 MHz.
RF
6.
Measured at V
= 60 dBµV EM
F
.
EMF
7.
Guaranteed by characterization.
14
Rev. 1.0
Si4740/41/42/43/44/45-C10
Table 11. AM Receiver Characteristics
1
(V =
3.0 to 3.6
V
, V
=
2
.7 to 3.6
V
, T
=
2
5 °C)
DD
IO
A
Parameter
Test Condition
Min
Typ
Max
Unit
AM Receiver
Specifications referred to Si4740/41/42/43/44/45 application circuit with 15pF/62pF antenna dummy,
voltages at antenna dummy input.
Input Frequency
Frequency Steps
AM/MW
AM/LW
520
144
2.3
1
—
—
1710
288
30
kHz
kHz
MHz
kHz
dBuV
dBuV
dB
2
AM/SW
—
—
10
34
—
3,5
Sensitivity
(S+N)/N=26 dB
—
25
99
53
0.1
0.2
55
40
60
—
6
IP3
40 and 80 kHz Offset
—
3,4,7,8
Audio SNR
50
—
—
3,4,6,7,8
Audio THD
0.5
1
%
6,7,8
Strong Signal THD
RF input level 120 dBµV EMF
RF input level 120 dBµV EMF
—
%
6,7,8
Strong Signal SINAD
53
—
—
dB
6
Power Supply Rejection Ratio
ΔV =
100 mVRMS, 100 Hz
—
dB
DD
3,4
Audio Output Voltage
54
—
67
110
mVRMS
ms
6
Powerup Time
From powerdown
Notes:
1.
T
o
e
nsure proper operation and receiver performance, follow the guidelines in “AN400: Si474x AM/FM receiver Layout
Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2.
Contact Silicon Labs for additional details on shortwave operation and performance.
3.
FMOD = 1 kHz, 30% modulation, 2 kHz channel filter.
4.
Measured at V
= 74 dBµ
V
.
5.
fRF = 520 to 1710 kHz.
6.
Guaranteed by characterization.
7.
BAF = 300 Hz to 15 kHz.
8.
fRF = 520 kHz.
Rev. 1.0
15
Si4740/41/42/43/44/45-C10
AM Antenna Dummy
15 pF
50
Ant+
Ant–
Signal
Generator
50
62 pF
Figure 9. AM Test Circuit
Table 12. Reference Clock
(V =
3.0 to 3.6
V
, V
=
2
.7 to 3.6
V
, T
A
= –40 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
Typ
32.768
—
Max
Unit
kHz
ppm
RCLK Supported Frequencies
RCLK Frequency
T
o
lerance
31.130
–100
40,000
100
16
Rev. 1.0
Si4740/41/42/43/44/45-C10
2. Typical
Application Schematic
Optional: Si4742/43
WBRX Optimization
C2
L2
L5
Optional: Additional ESD Protection
VDD
GPO1/AGC2
GPO2/INTb
GPO3/DCLK
U2
L1
R3
C12
C8
U1
Si4740/41/42/43/44/45
Optional:
Si4742/43
LW Support
VDD
Q5
1
2
3
4
5
6
18
17
16
15
14
13
L9
NC/DFS
NC/DOUT
LOUT
ROUT
FMI
NC/DFS
NC/DOUT
LOUT
ROUT
VDD
RFGND
AGC1
NC
GND1
AMI
Antenna+
Antenna-
R10
GND
VDD
R6
C9
L3
C1
AMb
PAD
GND PAD
C5
R7
L6
Q2
Q1
VIO
L10
RCLK
SDIO
SCLK
SENb
RSTb
C3
L7
VIO
C10
R1
L8
C4
VIO
VIO
Optional:
Passive Only
Antenna Attn
U4
L4
14
U3
Optional: FM
5
2
U5
Intrusion Filter
C7
Q3
1
4
R11
4
2
1
R5
3
5
Optional: Additional
ESD Protection
3
GPO1/AGC2
6
8
R4
Optional:
Mains Trap
10
13
9
11
ACTIVE/PASSIVE ATTN
Optional:
R8
Software Selectible
Active/Passive
Antenna Attn
12
7
Q4
R9
Notes:
1.
Place C1 close to V
pin.
DD
2.
All grounds connect directly to GND plane on PCB.
3.
T
o
e
nsure proper operation and receiver performance, follow the guidelines in “AN400: Si474x AM/FM Receiver Layout
Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
Rev. 1.0
17
Si4740/41/42/43/44/45-C10
3. Bill
of Materials
Table 13. Si4740/41/42/43/44/45-C10 Bill of Materials
Reference
C1
Description
Manufacturer
Venkel
Part Number
C0402X7R250-223JNE
C0402C0G500-180JNE
C0402C0G500-271JNE
C0402X7R160-183JNE
C0603X7R160-474JNE
C0402X7R500-122JNE
C1206X5R063-107MNE
PE-0603CD121JTT
1008PS-224KL
CA
P
,
22 n
F
,
±
5%, 0402,X7R
CA
P
,
18 p
F
,
±
5%, 0402,COG
CA
P
,
270 p
F
,
±
5%, 0402,COG
CA
P
,
18 n
F
,
±
5%, 0402,X7R
CA
P
,
0.47 µ
F
,
±
5%, 0603,X7R
CA
P
,
1200 p
F
,
±
5%, 0402,X7R
CA
P
,
1
00 µ
F
,
±
20%, 1206, X5R
IND, 120 nH, ±5%, 0603
IND,220 µH, ±10%, 1008
IND,1 mH, ±20%, LPS4018
IND,33 µH, ±10%, 0805
FE
T
,
SM,SOT-23
C2
Venkel
C3
Venkel
C4
Venkel
C5,C8,C9
C7
Venkel
Venkel
C12
L1
Venkel
Pulse
L3
Coilcraft
Coilcraft
Coilcraft
NXP
L4
LPS4018-105ML
L10
0805PS-333KL
Q1,Q2
Q3
BF862
NPN,SM,SOT-23
Fairchild Semi
Venkel
MMBTH10
R1
RES,10 MΩ, ±5%, 0603
RES,10 Ω, ±1%, 0402
CR0603-16W-106JT
CR0402-16W-10R0FT
CR0402-16W-2490FT
CR0402-16W-472JT
Si4740/41/42/43/44/45-C10
R3
Venkel
R4,R6,R7
R5
RES,249 Ω, ±1%, 0402
RES,4.7 kΩ, ±5%, 0402
QFN-24, SM
Venkel
Venkel
U1
Silicon Laboratories
Optional: Additional ESD Protection
U2,U4
ESD DIODE ARRA
Y
,
S
M
California Micro Device
CM1213
Optional: Without WBRX Optimization
L2
L5
IND, 33 nH, ±5%, 0603
Pulse
PE-0603CD330JTT
CR0603-16W-000T
RES, 0
, 0603
Venkel
Optional: Si4742/43 WBRX Optimization
L2
L5
IND, 100 nH, ±5%, 0603
IND, 150 nH, ±5%, 0603
Pulse
Pulse
PE-0603CD101JTT
PE-0603CD151JTT
Optional: Passive Only Antenna Attenuation
U5 BUFFER,
SOT-23
Optional: FM Intrusion on AM
TI
SN74LVC1G17DBV
C10
CA
P
,
3.9 p
F
,
±
0.25 p
F
,
0
402,COG
IND, 6.8 µH, ±10%, 0805
Venkel
C0402C0G500-3R9CNE
0805PS-682KL
L6,L7
Coilcraft
Note:
Specific part numbers are provided as a reference to the Si4743-C EVB. Other suppliers may be substituted.
18
Rev. 1.0
Si4740/41/42/43/44/45-C10
Table 13. Si4740/41/42/43/44/45-C10 Bill of Materials (Continued)
Reference
Description
Manufacturer
Part Number
Optional: Mains Trap on AM
L8
IND,47 mH, ±6%, L7PD
RES,10 kΩ,±5%,0402
T
o
ko
#388BN-1211Z
R11
Venkel
CR0402-16W-103JT
Optional: Software Selectable Active/Passive Antenna Attenuation
R8
R9
Q4
U3
RES,1 Ω, ±1%, 0402
RES,249 Ω, ±1%, 0402
NPN,SM,SOT-23
Venkel
Venkel
CR0402-16W-1R00FT
CR0402-16W-2490FT
MMBTH10
Fairchild Semi
TI
QUAD GATE, 14TSSOP
SN74LVC02APW
Optional: Si4742/43/44/45 LW Support
L9
R10
Q5
IND, 2.7 mH, ±10%, 0807
RES,249 Ω, ±1%, 0402
PN
P
,
S
M, SOT-23
Coilcraft
Venkel
RFB0807-272L
CR0402-16W-2490FT
MMBTH81
Fairchild Semi
Note:
Specific part numbers are provided as a reference to the Si4743-C EVB. Other suppliers may be substituted.
Rev. 1.0
19
Si4740/41/42/43/44/45-C10
The Si474x products are feature-rich solutions,
providing both highly automated performance,
according to Silicon Laboratories’ recommended
settings, and extensive flexibility for customized audio
and system performance. Programmable algorithms
include advanced seek with multiple signal qualifiers
and thresholds in all supported bands, FM stereo blend
rates and thresholds, soft mute characteristics, multi-
path detection and mitigation, AM/FM noise blankers,
and selectable FM Hi-cut filters. The part accepts
programmable reference clock values. The IC provides
audio output in standard line-level analog audio using
high fidelity stereo DACs or digital audio format.
4. Description
4.1. Introduction
The Si474x AM/LW/SW/FM/WB receiver family offers
100% CMOS receiver integrated circuits (IC), providing
the full receive functionality from antenna to audio for
use in the automotive market. The family includes a
portfolio of highly integrated receivers for primary
AM/FM receivers that support worldwide broadcast
audio bands and corresponding attributes including
AM/FM and “college bands” down to 64
MHz, long
wave, NOAA weather band, and dedicated companion
RDS background receivers. The entire portfolio is layout
The Si4741, Si4743, Si4745, and all other family parts
ending with an odd number, offer a fully-integrated
preprocessor for the European Radio Data System
(RDS) and the North American Radio Broadcast Data
System (RBDS). The RDS preprocessor includes all
symbol decoding, advanced error-correction, detailed
visibility to block-error rates (BLER), synchronization
status and times, and complete, decoded and error-
corrected RDS group presentation. The Si474x RDS-
enabled parts also offer several modes of operation for
various applications which require more or less visibility
to the RDS status and group data.
compatible and is offered in
a
very small
4 x 4 x 0.85 mm
24-pin QFN package. Refer to “7.
Ordering Guide” on page 39 for the corresponding part
numbers.
The Si474x family implements Silicon Laboratories’
proven and internationally patented digital low
intermediate frequency (low-IF) receiver architecture.
Silicon Labs has shipped over 100 million broadcast
audio receivers worldwide using this architecture. The
low-IF architecture delivers superior performance while
integrating the great majority of external components
required by competing solutions.
Table 14. Si4740/41/42/43/44/45 Product Family
Feature
FM band coverage
Si4740
Si4741
Si4742
Si4743
Si4744
Si4745
FM RDS reception
AM band coverage
LW band coverage
SW band coverage
WB (w/o SAME) band coverage
FM multi-path detection and
stereo/mono blend mitigation
Advanced stereo-mono blend
Advanced soft mute
Hi-cut
FM noise blanker
AM noise blanker
2
Digital audio I S
20
Rev. 1.0
Si4740/41/42/43/44/45-C10
4.2. Block
Diagram and Functional Description
Si474x
RDS
DOUT
DFS
FMI
DIGITAL
AUDIO
LNA
AGC
WEAK
SIGNAL
CONDITION
DCLK
ADC
ADC
DAC
DAC
ROUT
LOUT
AMI
LNA
AGC
DSP
GND
AGC
VDD
GND
GPO1-3
VIO
QUALITY
DETECTOR
3.0–3.6 V
LDO
AFC
CNTRL
RST
Figure 10. Functional Block Diagram
The Si474x IC family integrates the voltage controlled
quadrature mixers which downconvert the received
oscillator (VCO) and frequency synthesizer and accepts
signal from RF to low-I
F
,
f
ilter for out-of-band interferers,
a wide range of programmable reference clocks
and perform a transfer function to shift the tuned
(RCLK). The frequency synthesizer generates the
frequency to dc. A pair of PGAs filters the mixer output
quadrature local oscillator signal used to downconvert
from interferers and amplifies the signal again before
the RF input to a low intermediate frequency. The VCO
delivering it to two high resolution ADCs. The ADCs
frequency is locked to the RCLK and adjusted with an
generate high dynamic range signals and deliver them
automatic frequency control (AFC) servo loop during
to the digital core for additional processing.
reception. The VCO frequency is modified according to
the programmed target frequency.
The digital core consists of a DS
P
,
8
051 MCU core,
memory access controller, control interface circuitry,
The Si474x family uses a digital low-IF architecture that
and general programming interface functionality.
integrates the entire receive chain for AM MW, AM LW,
The MCU works in conjunction with the DSP to provide
AM SW, FM, and weather band, and eliminates the
access to signal quality indicators and system behavior,
requirement for expensive external ceramic filters found
as well as managing the IC control interface and
in competing solutions. The IC also integrates the
communication with the host processor.
majority of external components and performs all
The Si474x digital core performs channel selection and
processing in an on-chip digital signal processor (DSP)
filtering for all supported worldwide bands. The digital
and 8051 microcontroller (MCU) core.
core calibrates tuning and performs AM/FM
The analog chains for AM and FM include dedicated
demodulation and FM stereo MPX audio processing.
low-noise amplifiers (LNA), automatic gain control
The digital core also performs signal quality processing
(AGC), image-reject quadrature mixers, programmable
including received signal strength indicators, impulse
gain amplifiers (PGA), and a set of delta-sigma analog-
detection, SNR calculations, volume control, mute, and
additional digital filtering. The Si4740 supports FM de-
to-digital converters (ADCs).
The FM and AM LNA blocks receive wide-band
emphasis of 50 or 75 µs.
frequency inputs at the FMI and AMI input pins
The stereo digital audio signal is then converted back to
respectively. For AM, an on-chip varactor and resistor
Left (L) and Right (R) analog with a pair of high
array control the gain of the external AM antenna
resolution, digital-to-analog converters (DACs) and is
network. For FM, the external network is designed to
available as line-level audio on the LOUT and ROUT
provide a small boost to the FM band.
pins. Additionally, the stereo digital audio is also
2
The LNA gain is dynamically controlled by the AGC
provided via an I S interface (Si4741/43/45 only). The
loop, contingent on the RF peak detectors and signal
device supports I C-compatible 2-wire control interface
2
strength. Each receive path continues to dedicated
and SPI 3-wire control interface.
Rev. 1.0
21
Si4740/41/42/43/44/45-C10
4.3. FM
Receiver Front-end
4.6. Digital
Audio Interface
(Si4741/43/45 only)
The Si474x family integrates the entire FM receive
chain from antenna to audio out. The FM band is
received on the FMI pin via an input coupling network
with the recommended application circuit. This input
coupling network isolates the FM band for best
performance. The LNA supports US, Europe, Japan,
OIR
T
,
a
nd Rest of World FM broadcast bands (64 to
The digital audio interface operates in slave mode and
supports three different audio data formats:
2
I S
Left-Justified
DSP Mode
108 MHz).
The AGC circuit automatically controls the
LNA gain to optimize sensitivity and rejection of strong
interferers. For testing purposes, the AGC can be
disabled. Refer to “AN388: Si470X/1X/2X/3X/4X
Evaluation Board
T
e
st Procedure” for Si474x testing
procedures.
4.6.1. Audio Data Formats
2
In I S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
4.4. AM
Receiver Front-end
In Left-Justified mode, by default the MSB is captured
on the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
The Si474x family provides an integrated LNA, which
works in conjunction with an external cascode amplifier
to provide an AM receive chain from antenna to audio
out. There are very few external components and no
manual alignment required. The AM signal is received
on the AMI pin via a cascode amplifier external circuit.
The cascode circuit degeneration is automatically
adjusted via the AGC pin as shown in Section “2.
Typical Application Schematic” on page 17. The amount
of degeneration depends on the signal strength. An
additional GPO1 signal is used to attenuate the signal
via a shunt for very strong signal handling when the
signal exceeds the AGC pin degenerative control of the
cascode amplifier stage.
In DSP mode, the DFS becomes a pulse with a width of
one DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
4.5. Received
Signal Qualifiers
A tuned signal’s quality can vary with the environmental
conditions, time of day, and position of the antenna
among many other factors.
T
o
a
dequately manage the
audio output and avoid unpleasant audible effects to the
end-user, the Si474x monitors and provides indicators
of the signal quality, allowing the host processor to
perform additional processing if required by the
customer. The Si474x monitors and reports a set of
standard industry signal quality metrics including RSSI,
SNR, and multi-path interference on FM signals.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
4.6.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz.
As with other Si474x features, how these variables are
used to improve audio performance can be left to the
Silicon Labs on-chip algorithms (recommended), or they
can be brought out for host-processor instructions.
22
Rev. 1.0
Si4740/41/42/43/44/45-C10
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
I
2
S
RIGHT CHANNEL
(OMODE = 0000)
1 DCLK
1 DCLK
n-2
DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 11. I
2
S Digital Audio Format
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
n-2
Left-Justified
(OMODE = 0110)
DOUT
1
2
3
n-2
n-1
n
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 12. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DOUT
1
2
3
2
n-1
n
(OMODE = 1100)
(OMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1
st
rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DOUT
1
3
n-1
n
1
3
n-1
n
(MSB at 2
nd
rising edge)
MSB
LSB
MSB
LSB
Figure 13. DSP Digital Audio Format
Rev. 1.0
23
Si4740/41/42/43/44/45-C10
subtracting the (L+R) and (L–R) signals, respectively.
4.7. Stereo
Audio Processing
4.7.2. Stereo-Mono Blending
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
Adaptive noise suppression is employed to gradually
developed in 1961, and is used worldwide.
T
o
day’s
combine the stereo (L–R) audio signal to a mono (L+R)
MPX signal format consists of left + right (L+R) audio,
audio signal as the signal quality degrades to maintain
left – right (L–R) audio, a 19
kHz pilot tone, and
optimum sound fidelity under varying reception
RDS/RBDS data as shown in Figure 14 below.
conditions. Three metrics, received signal strength
indicator (RSSI), signal-to-noise ratio (SNR), and multi-
path interference, are monitored simultaneously in
forcing a blend from stereo to mono. The metric which
reflects the minimum signal quality takes precedence
and the signal is blended appropriately.
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
Left – Right
RDS/
RBDS
All three metrics have programmable stereo/mono
thresholds and attack/release rates as shown in the
T
a
ble 15 and
T
a
ble 16.
If a metric falls below its mono threshold, the signal is
blended from stereo to full mono. If all metrics are
above their respective stereo thresholds, then no action
is taken to blend the signal. If a metric falls between its
mono and stereo thresholds, then the signal is blended
to the level proportional to the metric’s value between its
mono and stereo thresholds, with an associated attack
and release rate. Figure 15, “Stereo-Mono Blend Based
on Active Monitoring of RSSI, SNR, and Multi-Path
Interference,” on page 25 illustrates the stereo-mono
blend. Stereo/mono status can be monitored with the
FM_RSQ_STATUS command.
0
15 19 23
38
53 57
Frequency (kHz)
Figure 14. MPX Signal Spectrum
4.7.1. Stereo Decoder
The Si4740/41/42/43/44/45-C10’s integrated stereo
decoder automatically decodes the MPX signal using
DSP techniques. The 0 to 15
kHz (L+R) signal is the
mono output of the FM tuner. Stereo is generated from
the (L+R), (L–R), and a 19 kHz pilot tone. The pilot tone
is used as a reference to recover the (L–R) signal. The
left and right channels are obtained by adding and
Table 15. Blend Threshold Properties
RSSI
SNR
FM_BLEND_RSSI_STEREO_THRESHOLD
FM_BLEND_SNR_STEREO_THRESHOLD
FM_BLEND_RSSI_MONO_THRESHOLD
FM_BLEND_SNR_MONO_THRESHOLD
Multi-path interference
FM_BLEND_MULTIPATH_STEREO_THRESHOLD FM_BLEND_MULTIPATH_MONO_THRESHOLD
Table 16. Blend Attack/Release Rate Properties
RSSI
SNR
FM_BLEND_RSSI_ATTACK_RATE
FM_BLEND_SNR_ATTACK_RATE
FM_BLEND_RSSI_RELEASE_RATE
FM_BLEND_SNR_RELEASE_RATE
FM_BLEND_MULTIPATH_RELEASE_RATE
Multi-path interference
FM_BLEND_MULTIPATH_ATTACK_RATE
24
Rev. 1.0
Si4740/41/42/43/44/45-C10
100%
0%
RSSI
Stereo level
RSSI
Blend attack rate/
Blend release rate
RSSI
Mono Stereo
RSSI
SNR
MP
Thld
Thld
100%
0%
SNR
SNR
Stereo level
Min gain level
with
associated
attack or
SNR
Blend attack rate/
Blend release rate
release rate
Mono
Thld
Stereo
Thld
100%
0%
MP
Stereo level
Multi-path
Interference
(MP)
MP
Blend attack rate/
Blend release rate
Stereo Mono
Thld Thld
L-R gain = F
–
L-R
+
+
(1+F )R + (1-F )L
(1+F )L + (1-F )R
+
+
L+R
+
Figure 15. Stereo-Mono Blend Based on Active Monitoring of RSSI, SNR, and Multi-Path
Interference
Rev. 1.0
25
Si4740/41/42/43/44/45-C10
4.8. De-emphasis
4.9. Stereo
DACs
De-emphasis is a technique used by FM broadcasters
High-fidelity stereo digital-to-analog converters (DACs)
to improve the signal-to-noise ratio of FM receivers by
drive analog audio signals onto the LOUT and ROUT
reducing the effects of high-frequency interference and
pins. The audio output may be muted. Volume is
noise. When the FM signal is transmitted, a pre-
adjusted digitally with the RX_VOLUME property. It is
emphasis filter is applied to accentuate the high audio
necessary that the volume be maintained at maximum
frequencies. The Si474x incorporates a de-emphasis
levels to ensure the highest dynamic range audio
filter which attenuates high frequencies to restore a flat
outputs to the external audio processing stage in a car
frequency response. Two time constants are used in
radio.
various regions. The de-emphasis time constant is
programmable to 50 or 75
µs and is set by the
4.10. Soft
Mute
FM_DEEMPHASIS property.
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. This process is shown conceptually in
Figure 16.
The Si474x triggers soft mute feature by
monitoring the SNR metric. The SNR threshold for
activating soft mute is programmable, as are soft mute
attenuation levels and attack and release rates. The
Si474x provides the soft mute feature in FM and AM
bands.
Maximum
Attenuation
SNR
Soft mute
threshold
Figure 16. Soft Mute Based on Active Monitoring of SNR
26
Rev. 1.0
Si4740/41/42/43/44/45-C10
4.11. Seek
and Valid Station Qualification
4.12. FM
Hi-Cut Control
(Si4742/43/44/45 only)
The seek function will search up or down the selected
frequency band for a valid channel. A valid channel is
qualified according to a series of programmable signal
indicators and thresholds. The seek function can be
made to stop at the band edge and provide an interrupt,
or wrap the band and continue seeking until arriving at
the original departure frequency. The device sets
interrupts with found valid stations, or if the seek results
in zero found valid stations, the device indicates failure
and again sets an interrupt.
Hi-cut control is employed on audio outputs with
degradation of the signal due to low SNR and/or multi-
path interference. Two metrics, SNR and multi-path
interference, are monitored concurrently in forcing hi-cut
of the audio outputs. Programmable minimum and
maximum thresholds are available for both metrics. The
transition frequency for hi-cut is also programmable with
up to seven hi-cut filter settings. A single set of attack
and release rates for hi-cut are programmable for both
metrics from a range of 2 ms to 64 s. Figure 17, “FM Hi-
Cut Based on Active Monitoring of SNR and Multi-Path
Interference,” illustrates hi-cut. The level of hi-cut
applied can be monitored with the FM_RSQ_STATUS
command. Hi-cut can be disabled by setting the hi-cut
filter setting to the default audio bandwidth of 15 kHz.
The Si474x seek functionality is performed completely
on-chip or can be brought out to a companion
processor. The Si474x can provide base values for
signal quality variables to a companion processor for
qualification or can further process the base values to
qualify valid or invalid stations.
The Si474x uses RSSI, SNR, and AFC to qualify
stations. Most of these metrics have programmable
thresholds to tailor the seek function to the subjective
tastes of customers.
RSSI is employed first to screen all possible candidate
stations. SNR and AFC are subsequently used in
screening the RSSI qualified stations. The more
thresholds the system engages, the higher the
confidence that any found stations will indeed be valid
broadcast stations; however, the more challenging
levels the thresholds are set to, the longer the overall
seek time as more stations and more qualifiers will be
assessed. It is recommended that RSSI be set to a mid-
level threshold in conjunction with an SNR threshold set
to a level delivering acceptable audio performance. This
trade-off will eliminate very low RSSI stations whilst
keeping the seek time to acceptable levels. Generally,
the time to auto-scan and store valid channels for an
entire AM or FM band with all thresholds engaged is
very short depending on the band content.
Seek is initiated using the FM_SEEK_START or
AM_SEEK_START commands. The RSSI and SNR
threshold settings are adjustable using properties.
Rev. 1.0
27
Si4740/41/42/43/44/45-C10
SNR
Cutoff
15 kHz
frequency
level
SNR
Prog.
cutoff
SNR
Min cutoff freq
level with
associated
attack or
SNR
High
Thld
Lo
Thld
release rate
20 kHz
15 kHz
Attack & Release rate
Multi-path
Cutoff
frequency
level
Multi-path
Interference
(MP)
Multi-path
interference
Prog.
cutoff
MP
High
Thld
Trigger
Thld
L+R
L-R
Figure 17. FM Hi-Cut Based on Active Monitoring of SNR and Multi-Path Interference
28
Rev. 1.0
Si4740/41/42/43/44/45-C10
4.13.1. FM Noise Blanker Property Settings
4.13. AM/FM
Noise Blanker
(Si4742/43/44/45 only)
The FM noise blanker detection threshold property sets
the level threshold for detection of the noise
impulses/spikes in dB from a range of 1
dB to 90
dB
above the noise floor. The FM noise blank rate property
sets the maximum rate in Hz at which the noise blanker
is triggered from a range of 100 Hz to 6400 Hz. The FM
noise blank interval property sets the noise blanking
interval in microseconds at which the original samples
are replaced by interpolated “clean” samples from a
range of 8 µs to 48 µs. The FM noise blanker IIR filter
property sets the noise floor bandwidth from a range of
390 Hz
to 2480
Hz. This property sets the rms noise
floor above which the noise impulse level detect
threshold is set for noise impulse detection. The FM
noise blank delay property sets the delay in
microseconds in applying impulse blanking to the
original samples, which allows for insertion and
alignment of the blanked samples with the original
sampled signal. The range of values for FM noise
blanker delay is 125 µs to 219 µs.
In an automotive environment, noise spikes from engine
ignition and/or various other electrical sources can
significantly impair and disrupt the audio output. The
Si4742/43/44/45 includes a noise blanker to mitigate or
eliminate these noise spikes and audible artifacts.
Figure 18
shows a conceptual flow chart for the
Si4742/43/44/45 noise blanking function. The
Si4742/43/44/45 offers five properties for configuring
the AM and FM noise blankers including detection
threshold, blanking interval, trigger rate, noise-floor
bandwidth, and delay. Each property is configurable for
adopting customers to refine and apply unique noise-
blank behavior.
Multi-path
Inteference
Detection
FM
Pilot PLL
Demod
HPF
Pilot notch
filter
L
Noise
impulse
blanker
Audio
Filter
&
Stereo
Decode
R
Hi-cut
Figure 18. Illustration of Noise Blanker in FM Signal Path
Rev. 1.0
29
Si4740/41/42/43/44/45-C10
FM MPX waveform with
noise impulses
FM MPX waveform after
noise blanker
FM noise
blanker delay is
set to calibrate
the delay from
the noise
blanker for
proper time
alignment and
insertion of
blanked
samples into
original signal.
Noise impulse threshold
Noise floor threshold
MPX waveform after HPF stage
Figure 19. Illustration of FM Noise Blanker Property Settings for Proper Detection of Noise
Impulses (FM MPX waveforms are offset vertically for illustration purposes)
30
Rev. 1.0
Si4740/41/42/43/44/45-C10
4.13.2. AM Noise Blanker Property Settings
The AM noise blanker detection threshold property sets
bandwidth from a range of 300
Hz to 2480
Hz. This
the level threshold for detection of the noise property
sets the rms noise floor above which the noise
impulses/spikes in dB from a range of 1
dB to 90
dB impulse
level detect threshold is set for noise impulse
above the noise floor. The AM noise blank rate property
detection. The AM noise blank delay property sets the
sets the maximum rate in Hz at which the noise blanker
delay in microseconds in applying impulse blanking to
is triggered from a range of 100 Hz to 6400 Hz. The AM
the original samples, which allows for insertion and
noise blank interval property sets the blanking interval in
alignment of the blanked samples with the original
microseconds at which the original samples are
sampled signal. The range of values for the AM noise
replaced by previous samples using a “sample and
blanker delay is 125 µs to 219 µs.
hold” scheme from a range of 15 µs to 110 µs. The AM
noise blanker IIR filter property sets the noise floor
HPF/Impulse
Noise
Detector
I/Q
Audio
Noise
Blanker
Channel
Filter
AM
Demod
Figure 20. Illustration of Noise Blanker in AM Signal Path.
Rev. 1.0
31
Si4740/41/42/43/44/45-C10
AM waveform
with noise impulses
AM waveform
after noise blanker
AM noise blank
delay is set to
calibrate the
delay from the
noise blanker
for proper time
alignment and
insertion of
blanked
samples into
original signal.
Noise impulse threshold
Noise floor threshold
AM waveform after HPF
Figure 21. Illustration of AM Noise Blanker Property Settings for Proper Detection of Noise
Impulses (AM Waveforms are Offset Vertically for Illustration Purposes)
32
Rev. 1.0
Si4740/41/42/43/44/45-C10
synchronization at very noisy signal levels, and
excellent sensitivity at industry-standard block error rate
(BLER) levels (5%).
4.14. Programming
Section
To
e
ase development time and offer maximum
customization, the Si474x provides a simple and
powerful software interface to program the receiver. The
device is programmed using commands, arguments,
properties, and responses.
The Si4741/43/45’s strong synchronization performance
in very noisy/low SNR environments minimizes the
number of instances of lost synchronization. Other less
robust tuners must attempt to resynchronize in low SNR
environments, resulting in lost data and lengthy delays
in reestablishing data reception. The Si4741/43/45
maintains synchronization to the RDS transmission,
despite high BLER. This results in fewer dropped
connections, minimal resynchronization time, and
greater data reliability in low SNR environments.
Figure 22
illustrates the benefits of the Si4741/43/45
robust synchronization persistence.
To
p
erform an action, the user writes a command byte
and associated arguments causing the chip to execute
the given command. Commands control actions such as
powerup, powerdown, or tune to a station. Arguments
are specific to a given command and are used to modify
the command.
Properties are a special command + argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
properties are de-emphasis, RSSI seek threshold, and
soft mute attenuation.
The Si4741/43/45 decoder additionally provides more
reliable data decoding performance in low carrier to
noise (CNR) environments. This results in very low
decoder implementation loss figures and substantial
Responses provide information and are echoed after a
command + arguments are issued and processed. All
commands provide a one-byte status update indicating
interrupt and clear-to-send status information.
improvements
over
other
RDS
standard
implementations.
Figure 23
illustrates the Si4741/43/45 RDS decoder
performance. The decoder failure probability drops
significantly when compared to a standard RDS
decision-based decoder for given energy per bit/noise
For a detailed description of the commands and properties
for the Si474x, see “AN332: Si47xx Programming Guide”
and “AN344: Si4706/07/4x Programming Guide.”
density (E
/N ).
b
o
4.15. Reset,
Powerup, and Powerdown
The Si4741/43/45 report RDS decoder synchronization
status and detailed bit errors for each RDS block. The
range of reportable bit errors detected and corrected are
0, 1-2, 3-5, and “not correctable.” More than five errors
indicates that the corresponding block information word
is non-correctable.
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset. The powerup mode powers up the
device and provides mode selection. Mode selections
include AM, FM, or WB receiver and analog or digital
audio output. A powerdown mode is available to reduce
power consumption when the part is idle. Putting the
device in powerdown mode will disable analog and
digital circuitry while keeping the bus active.
The Si4741/43/45 also provides highly configurable
interrupts based on RDS-driven events and conditions.
The default settings provide an interrupt when RDS is
synchronized and when RDS group data has been
received. The configurable interrupts can be set to
provide frequent interrupts down to a single received
block with BLER. The configurable interrupts also can
be set to provide very infrequent interrupts, buffering up
to 25 complete RDS groups (100 blocks) with BLER by
block in the on-chip FIFO. The Si4741/43/45 also
provides configurable interrupts on changes or receipt
of the key RDS blocks A and B. This flexibility allows
adopters to either conduct extensive RDS data
processing on the host or reserve the host processor in
power-saving modes with minimal RDS interrupts,
allowing the Si4741/43/45 to perform RDS processing
on-chip. Interrupt configuration and thresholds are
covered in “AN332: Si47xx Programming Guide” and
“AN344: Si4706/07/4x Programming Guide,” offered
under NDA.
4.16. GPO
1–3
The GPO 1–3 pins can be set to output a constant low
or high output, or optionally be set to provide a
hardware interrupt to the controller such as scan
complete, stereo/mono indicator, and RDS/RBDS. After
reset and POWER_UP into AM receiver mode, GPO1 is
reserved for AM AGC external attenuator control.
4.17. RDS/RBDS
Advanced Processor
The Si4741/43/45 implements an advanced, patented,
high-performance RDS processor for demodulation,
symbol decoding, block synchronization, error
detection, and error correction. The RDS decoder
applies advanced decoding and statistical decision
techniques
to
provide
very
high-performance
Rev. 1.0
33
Si4740/41/42/43/44/45-C10
Si4741/43/45 advanced RDS decoder
with persistent synchronization
delivers data during “dead time”
Re-synchronization time in
traditional RDS decoder
SNR
time
SNR at which traditional RDS decoder
declares block decoding failure and
Sync loss.
SNR at which Si4741/43/45 decoder
declares Sync loss.
Figure 22. Illustrative Si4741/43/45 Advanced RDS Synchronization
Decoder Failure Probability
1.E+00
1.E-01
1.E-02
1.E-03
1.E-04
RDS standard limits
Standard-compliant advanced decoder (Silabs generation 1)
Si474x advanced decoder
0
1
2
3
4
5
6
Eb/N0
Figure 23. Si4741/43/45 Decoder Performance
34
Rev. 1.0
Si4740/41/42/43/44/45-C10
4.19.1. 2-Wire Control Interface Mode
4.18. Reference
Clock
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RS
T
,
a
nd stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RS
T
.
The Si4740/41/42/43/44/45-C10 reference clock is
programmable, supporting RCLK frequencies in
T
a
ble 12.
Refer to
T
a
ble
3, “DC Characteristics,” on
page 5
for switching voltage levels and
T
a
ble
9, “FM
Receiver Characteristics,” on page
12 for frequency
tolerance information.
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
4.19. Control
Interface
A serial port slave interface is provided, which allows an
high. Next, the user drives an 8-bit control word serially
external controller to send commands to the Si474x and
on SDIO, which is captured by the device on rising
receive responses from the device. The serial port can
edges of SCLK. The control word consists of a 7-bit
operate in three bus modes: 2-wire mode, 3-wire mode,
device address, followed by a read/write bit (read = 1,
or SPI mode. The Si474x selects the bus mode by
write = 0). The Si474x acknowledges the control word
sampling the state of the GPO1 and GPO2 pins on the
by driving SDIO low on the next falling edge of SCLK.
rising edge of RS
T
.
T
he GPO1 pin includes an internal
Although the Si474x will respond to only a single device
pull-up resistor, which is connected while RST is low.
address, this address can be changed with the SEN pin
The GPO2 pin includes an internal pull-down resistor,
(note that the SEN pin is not used for signaling in 2-wire
which is connected while RST is low. Therefore, it is
mode). When SEN = 0, the 7-bit device address is
only necessary for the user to actively drive pins which
0010001b. When SEN = 1, the address is 1100011b.
differ from these states. See
T
a
ble 17.
For write operations, the user then sends an 8-bit data
byte on SDIO, which is captured by the device on rising
edges of SCLK. The Si474x acknowledges each data
byte by driving SDIO low for one cycle, on the next
Table 17. Bus Mode Select on Rising Edge of
RST
falling edge of SCLK. The user may write up to 8 data
bytes in a single 2-wire transaction. The first byte is a
command, and the next seven bytes are arguments.
Bus Mode
2-Wire
SPI
GPO1
GPO2
1
0
1
1 (must drive)
0
For read operations, after the Si474x has acknowledged
the control byte, it will drive an 8-bit data byte on SDIO,
changing the state of SDIO on the falling edge of SCLK.
The user acknowledges each data byte by driving SDIO
low for one cycle, on the next falling edge of SCLK. If a
data byte is not acknowledged, the transaction will end.
The user may read up to 16 data bytes in a single, 2-
wire transaction. These bytes contain the response data
from the Si474x.
3-Wire
0 (must drive)
After the rising edge of RS
T
,
t
he pins GPO1 and GPO2
are used as general purpose output (O) pins. After reset
and POWER_UP into AM receiver mode, GPO1 is
reserved for AM AGC external attenuator control. In any
bus mode, commands may only be sent after VIO and
VDD supplies are applied.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer
to
T
a
ble 5, “2-Wire Control Interface Characteristics,” on
page 7;
Figure 2,
“2-Wire Control Interface Read and
Write Timing Parameters,” on page 8, and Figure 3, “2-
Wire Control Interface Read and Write Timing Diagram,”
on page 8.
Rev. 1.0
35
Si4740/41/42/43/44/45-C10
4.19.2. 3-Wire Control Interface Mode
4.19.3. SPI Control Interface Mode
When selecting 3-wire mode, the user must ensure that
When selecting SPI mode, the user must ensure that a
a rising edge of SCLK does not occur within 300
ns rising
edge of SCLK does not occur within 300
ns
before the rising edge of RS
T
.
before the rising edge of RS
T
.
The 3-wire bus mode uses the SCLK, SDIO and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 3-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
SPI bus mode uses the SCLK, SDIO, and SEN pins for
read/write operations. The system controller can
choose to receive read data from the device on either
SDIO or GPO1. In AM Receiver mode, only SIDIO is
available; GPO1 is reserved for AM AGC external
attenuator control. A transaction begins when the
system controller drives SEN = 0. The system controller
For write operations, the control word is followed by a
then pulses SCLK eight times, while driving an 8-bit
16-bit data word, which is captured by the device on
control byte serially on SDIO. The device captures the
rising edges of SCLK.
data on rising edges of SCLK. The control byte must
have one of five values:
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si474x will drive the 16-bit read data word serially
on SDIO, changing the state of SDIO on each rising
edge of SCLK.
0x48 = write a command (controller drives 8
additional bytes on SDIO).
0x80 = read a response (device drives one
additional byte on SDIO).
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
0xC0 = read a response (device drives 16 additional
bytes on SDIO).
0xA0 = read a response (device drives one
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xA
F
.
additional byte on GPO1).
0xE0 = read a response device drives 16 additional
bytes on GPO1).
For write operations, the system controller must drive
exactly eight data bytes (a command and seven
arguments) on SDIO after the control byte. The data is
captured by the device on the rising edge of SCLK.
For details on timing specifications and diagrams, refer
to
T
a
ble 6, “3-Wire Control Interface Characteristics,” on
page 9; Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
For read operations, the controller must read exactly 1
byte (STATUS) after the control byte or exactly 16 data
bytes (STATUS and RESP1–RESP15) after the control
byte. The device changes the state of SDIO (or GPO1, if
specified) on the falling edge of SCLK. Data must be
captured by the system controller on the rising edge of
SCLK.
Keep SEN low until all bytes have transferred. A
transaction may be aborted at any time by setting SEN
high and toggling SCLK high and then low. Commands
will be ignored by the device if the transaction is
aborted.
For details on timing specifications and diagrams, refer
to Figure 6 and Figure 7 on page 10.
36
Rev. 1.0
Si4740/41/42/43/44/45-C10
5. Commands
and Properties
Refer to
“AN332: Si47xx Programming Guide” and “AN344: Si4706/07/4x Programming Guide.”
Rev. 1.0
37
Si4740/41/42/43/44/45-C10
6. Pin
Descriptions: Si4740/41/42/43/44/45-C10-GM
24 23 22 21 20 19
FMI
RFGND
AGC1
NC
1
2
3
4
5
6
18 DFS
17 DOUT
16 LOUT
15 ROUT
14 GND
13 VDD
GND
PAD
GND
AMI
7
8
9
10 11 12
Table 18. Si4740/41/42/43/44/45-C10-GM Pin Descriptions
Pin Number(s)
Name
FMI
Description
FM RF inputs. FMI should be connected to the antenna trace.
RF ground. Connect to ground plane on PCB.
Automatic gain control. See “2. Typical Application Schematic” on page 17.
No connect. Leave floating.
1
2
RFGND
AGC1
NC
3
4, 22–24
5, 14, GND PAD
GND
AMI
Ground. Connect to ground plane on PCB.
AM RF input.
6
7
RST
Device reset (active low) input.
8
SEN
Serial enable input (active low).
9
SCLK
SDIO
RCLK
Serial clock input.
10
11
12
13
15
16
Serial data input/output.
External reference oscillator input.
I/O supply voltage.
V
IO
V
Supply voltage. May be connected directly to battery.
Right audio line output.
DD
ROUT
LOUT
Left audio line output.
Digital output data in digital output audio mode (Si4741/43/45 only). No connect
if not used.
17
18
19
DOUT
DFS
Digital frame synchronization input in digital output mode (Si4741/43/45 only).
No connect if not used.
General purpose output/Digital bit synchronous clock input in digital output
mode (Si4741/43/45 only).
GPO3/DCLK
20
21
GPO2/INT General
purpose output/interrupt pin.
GPO1/AGC2 General
purpose output/AM external attenuator control.
38
Rev. 1.0
Si4740/41/42/43/44/45-C10
7. Ordering
Guide
1,2
Description
Package
Type
Operating
Temperature
Part Number
Si4740-C10-AM
Si4741-C10-AM
AM/FM Broadcast Automotive Radio Receiver
4 x 4 x 0.825 24-pin QFN,
AEC-Q100 qualification, IMDS Registration,
PPAP documentation
QFN
Pb-free
–40 to 85 °C
AM/FM Broadcast Automotive Radio Receiver
with RDS/RBDS
QFN
Pb-free
–40 to 85 °C
4 x 4 x 0.825 24-pin QFN,
AEC-Q100 qualification, IMDS Registration,
PPAP documentation
Si4742-C10-AM
Si4743-C10-AM
AM/FM/LW/SW/WB Broadcast
Automotive Radio Receiver
4 x 4 x 0.825 24-pin QFN,
AEC-Q100 qualification, IMDS Registration,
PPAP documentation
QFN
Pb-free
–40 to 85 °C
–40 to 85 °C
AM/FM/LW/SW/WB Broadcast Automotive Radio
Receiver with RDS/RBDS
QFN
Pb-free
4 x 4 x 0.825 24-pin QFN,
AEC-Q100 qualification, IMDS Registration,
PPAP documentation
Si4744-C10-AM
Si4745-C10-AM
AM/FM/SW/LW Broadcast Automotive Radio Receiver
4 x 4 x 0.825 24-pin QFN,
QFN
Pb-free
–40 to 85 °C
–40 to 85 °C
AEC-Q100 qualification, IMDS Registration,
PPAP documentation
AM/FM/SW/LW Broadcast Automotive Radio Receiver
with RDS/RBDS
QFN
Pb-free
4 x 4 x 0.825 24-pin QFN,
AEC-Q100 qualification, IMDS Registration,
PPAP documentation
Si4740-C10-GM
Si4741-C10-GM
AM/FM Broadcast Automotive Radio Receiver
4 x 4 x 0.825 24-pin QFN
QFN
Pb-free
–40 to 85 °C
–40 to 85 °C
AM/FM Broadcast Automotive Radio Receiver
with RDS/RBDS
QFN
Pb-free
4 x 4 x 0.825 24-pin QFN
Si4742-C10-GM
AM/FM/LW/SW/WB Broadcast
Automotive Radio Receiver
4 x 4 x 0.825 24-pin QFN
QFN
Pb-free
–40 to 85 °C
Notes:
1.
Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
2.
AM numbered devices receive full automotive quality production status, including AEC-Q100 qualification, registration
Rev. 1.0
39
Si4740/41/42/43/44/45-C10
1,2
Description
Package
Type
Operating
Temperature
Part Number
Si4743-C10-GM
AM/FM/LW/SW/WB Broadcast Automotive Radio
Receiver with RDS/RBDS
QFN
Pb-free
–40 to 85 °C
4 x 4 x 0.825 24-pin QFN
Si4744-C10-GM
Si4745-C10-GM
AM/FM/SW/LW Broadcast Automotive Radio Receiver
4 x 4 x 0.825 24-pin QFN
QFN
Pb-free
–40 to 85 °C
–40 to 85 °C
AM/FM/SW/LW Broadcast Automotive Radio Receiver
with RDS/RBDS
QFN
Pb-free
4 x 4 x 0.825 24-pin QFN
Notes:
1.
Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
2.
AM numbered devices receive full automotive quality production status, including AEC-Q100 qualification, registration
with International Material Data System (iMDS), and Part Production Approval Process (PPAP) documentation. PPAP
40
Rev. 1.0
Si4740/41/42/43/44/45-C10
8. Package
Markings
8.1. Si4740/41/42/43/44/45-C10
Top Mark
4740C10
YYWWRF
AIXX
4741C10
YYWWRF
AIXX
4742C10
YYWWRF
AIXX
4743C10
YYWWRF
AIXX
4744C10
YYWWRF
AIXX
4745C10
YYWWRF
AIXX
Figure 24. Si4740/41/42/43/44/45-C10 Top Mark
8.2. Top
Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Customer Part Number
(Right-justify)
4740 = Si4740
4741 = Si4741
4742 = Si4742
4743 = Si4743
4744 = Si4744
4745 = Si4745
C = Part revision C
10 = Firmware revision 1.0
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the year and
workweek of the mold date.
R = Die Rev
F = Wafer Fab
First two characters of the Manufacturing Code from the
Assembly Purchase Order form.
Circle = 0.5 mm Diameter
Pin 1 Identifier.
(Bottom-Left Justified)
A = Assembly House
I = Internal Code
Last four characters of the Manufacturing Code from the
Assembly Purchase Order form.
XX = Serial Lot Number
Rev. 1.0
41
Si4740/41/42/43/44/45-C10
9. Package
Outline: Si4740/41/42/43/44/45-C10 QFN
Figure 25
illustrates the package details for the Si4740/41/42/43/44/45-C10.
T
a
ble
19 lists the values for the
dimensions shown in the illustration.
Figure 25. 24-Pin Quad Flat No-Lead (QFN)
Table 19. Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
A
A1
b
0.02
0.25
D
4.00 BSC
2.10
D2
e
2.00
2.20
0.50 BSC
4.00 BSC
2.10
E
E2
L
2.00
0.30
0.03
—
2.20
0.50
0.08
0.10
0.10
0.08
0.10
0.10
0.40
L1
aaa
bbb
ccc
ddd
eee
0.05
—
—
—
—
—
—
—
—
—
Notes:
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
Dimensioning and
T
o
lerancing per ANSI Y14.5M-1994.
3.
This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VGGD-8.
4.
Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
42
Rev. 1.0
Si4740/41/42/43/44/45-C10
10. PCB
Land Pattern: Si4740/41/42/43/44/45-C10 QFN
Figure 26 illustrates the PCB land pattern details for the Si4740/41/42/43/44/45-C10-GM.
T
a
ble 20 lists the values
for the dimensions shown in the illustration.
Figure 26. PCB Land Pattern
Table 20. Dimensions for PCB Land Pattern
Dimension
Min
Max
Dimension
Min
Max
e
E
0.50 BSC.
GE
GD
X
2.93
2.93
—
—
—
3.62 RE
F
.
3.62 RE
F
.
D
0.28
E2
D2
2.00
2.00
2.20
2.20
Y
0.69 REF
ZE
ZD
4.31
4.31
—
—
Notes: General
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
Dimensioning and
T
o
lerancing is per the ANSI Y14.5M-1994 specification.
3.
This Land Pattern Design is based on IPC-SM-782 guidelines.
4.
All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder
Mask Design
1.
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil
Design
1.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
2.
The stencil thickness should be 0.125 mm (5 mils).
3.
The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4.
A 2 x 2 array of 0.90 mm square openings on 1.15 mm pitch should be used for the center
ground pad.
Notes: Card
Assembly
1.
A No-Clean, Type-3 solder paste is recommended.
2.
The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.0
43
Si4740/41/42/43/44/45-C10
11. Additional
Reference Resources
Si47xx Customer Support Site:
This site contains all application notes, evaluation
board schematics and layouts, and evaluation
software. NDA is required for access.
T
o
r
equest
send user’s first and last name, company, NDA
reference number, and mysilabs user name to
fminfo@silabs.com. Silicon Labs recommends an all
lower case user name.
44
Rev. 1.0
Si4740/41/42/43/44/45-C10
D
OCUMENT
C
HANGE
L
IST
Revision 0.1 to Revision 0.2
Added FM Hi-cut description.
Added AM/FM Noise Blanker description.
Updated “2. Typical Application Schematic”.
Updated “3. Bill of Materials”.
Added Digital Audio Output section.
Removed crystal oscillator support.
Updated block diagram.
Updated pinout diagram.
Updated “7. Ordering Guide”.
Added package marking sections.
Updated package outline section.
Updated PCB land pattern section.
Revision 0.2 to Revision 0.3
Updated
T
a
ble 1 and updated Figures 3 and 12 to
reflect supply voltage change to 3.6 V max.
Updated
T
a
ble 11.
Updated Section “3. Bill of Materials”.
Updated Section “7. Ordering Guide”
Updated Section “8.1. Si4740/41/42/43/44/45-C10
T
o
p Mark”
Updated Section “8.2.
T
o
p Mark Explanation”
.
Revision 0.3 to Revision 0.5
Added SW band support to Features list.
Updated
T
a
ble 1 and all other figures and tables to
reflect supply voltage change to 3.6 V max.
Added Si4744/45 details.
Updated
T
a
ble 14
Updated
T
a
ble 3,
T
a
ble 9, and
T
a
ble 11
Revision 0.5 to Revision 0.8
Updated
T
a
ble 1 and all figures and tables to reflect.
VIO change to 2.7 V min.
Updated
T
a
ble 9,
T
a
ble 10, and
T
a
ble 13.
Revision 0.8 to Revision 1.0
Numerous updates and corrections.
Rev. 1.0
45
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Connected.
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.
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Quality
Support and Community
community.silabs.com
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and “Typical”
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without
further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior
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Such changes will not alter the specifications or the performance
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Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to
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