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WT32i BLUETOOTH AUDIO MODULE
DATA SHEET
Monday, 18 March 201
Version 1.3.1
VERSION HISTORY
VERSION
COMMENT
1.0
First version
Added example how to protect the battery by shutting down the regulators
certain voltage level
1.1
1.2
Fixed PCM pin numbering
1.21
1.22
1.23
1.24
1.3
Design check list added
UART brake signal updated
Chapter 9.3.1 added
Added note to reset section
Updated order codes and added more information about iWRAP versions.
Fixed one wrong build number
1.3.1
Silicon Labs
TABLE OF CONTENTS
1
2
3
4
5
Design Check List…………………………………………………………………………………………………………………………6
WT32i Product Numberin
g
.
……………………………………………………………………………………………………………7
Block diagram………………………………………………………………………………………………………………………………8
Pinout and Terminal Description …………………………………………………………………………………………………….9
Electrical Characteristics ………………………………………………………………………………………………………….
5.1
Absolute Maximum Ratings …………………………………………………………………………………………………. 12
Recommended Operating Condition
s
.
…………………………………………………………………….
…………. 12
Digital Terminals…………………………………………………………………………………………
……………….. 12
Audio Characteristics ……………………………………………………………………………………
………………. 13
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.5
5.5.1
5.5.2
5.6
ADC……………………………………………………………………………………………………………………………. 13
DAC……………………………………………………………………………………………………………………………. 14
A2DP Codecs………………………………………………………………………
….
……………………………….. 14
RF Characteristics………………………………………………………………………………………………………………. 16
RF Transceiver ……………………………………………………………………………………………………………. 16
Antenna Characteristic
s
.
…………………………………….
……………………………………………………….. 17
Current Consumption ……………………………………………….
………………………………………………………. 20
6
Power Control and Regulation …………………………….
…………………………………………………………………….. 21
6.1
6.2
6.2.1
Protecting the Battery by Configuring the Modu
o Turn Off at Certain Voltage ………………………… 23
Rese
t
.
…………………………………………………
….
………………………………………………………………………. 24
Internal POR ………………………….
…………………………………………………………………………….. 24
7
8
Battery Charger ………………………………………………………………………………………………………………………… 26
GPIO and AIO Functions………….
…………………………………………………………………………………………….. 27
8.1
iWRAP supported GPIO Function
s
.
………………………………………………………………………………………. 27
Outputting Internal Clocks……………………………………………………………………………………………………. 27
Auxiliary ADC …
…………………………………………………………………………………………………………………. 28
Software I2C
erface ………………………………………………………………………………………………………… 28
8.2
8.3
8.4
9
Serial Interfaces………………………………………………………………………………………………………………………… 29
9.1 UAR
nterface…………………………………………………………………………………………………………………… 29
9.
Resetting Through UART Break Signa
l
.
………………………………………………………………………….. 30
UART Configuration While Reset is Activ
e
.
……………………………………………………………………… 30
UART Bypass Mode …………………………………………………………………………………………………….. 30
9.1.2
9.1.3
.2
9.3
USB Interfac
e
.
……………………………………………………………………………………………………………………. 31
Programming and Debug Interface (SPI)……………………………………………………………………………….. 32
9.3.1
Multi-slave Operatio
n
.
…………………………………………………………………………………………………… 32
Audio Interface
s
.
……………………………………………………………………………………………………………………. 33
Stereo Audio Codec Interface………………………………………………………………………………………… 33
10
10.1
10.1.1 ADC…………………………………………………………………………………………………………………………….
33
Silicon Labs
10.1.2 DAC…………………………………………………………………………………………………………………………….
35
10.1.3 Microphone
Input …………………………………………………………………………………………………………. 36
10.1.4 Line
Input ……………………………………………………………………………………………………………………. 37
10.1.5 Output
Stag
e
.
………………………………………………………………………………………………………………. 38
10.1.6 Mono
Operation …………………………………………………………………………………………………………… 40
10.1.7 Side
Tone………………………………………………………………………………………………………………….
10.2
PCM Interface ……………………………………………………………………………………………………………… 40
I2S Interface………………………………………………………………………………………………………………… 40
IEC 60958 Interfac
e
.
……………………………………………………………………………..
………………… 42
Design Guidelines…………………………………………………………………………………………..
………………. 44
Audio Layout Guide ……………………………………………………………………………………………………… 44
10.3
10.4
11
11.1
11.1.1 EMC
Consideration
s
.
……………………………………………………………………………………………………. 44
11.1.2 Choosing
Capacitors and Resistors ……………………………………….
….
……………………………….. 44
11.2
11.3
12
RF Layout Guid
e
.
……………………………………………………….
……..
………………………………………. 45
Example Application Schematics……………………………………………………………………………………. 48
Physical Dimensions………………………………………………………………………………………………………………. 52
Soldering Recommendations…………………………………
.
….
……………………………………………………… 54
Packag
e
.
………………………………………………………………………………………………………………………………. 55
Certification Guidance for an End Product Using
2i …………………………………………………………….. 57
Bluetooth End Product Listing…………
….
………………………………………………………………………. 57
CE Approval of an End-Product..
…………………………………………………………………………….. 57
FCC Certification of an End Product……………………………………………………………………………….. 58
13
14
15
15.1
15.2
15.3
15.3.1 Co-location
with Other T
nsmitters ……………………………………………………………………………….. 59
15.4
15.5
16
IC Certification of an End Product ………………………………………………………………………………….. 59
MIC Japan Certification of an End Product………………………………………………………………………. 59
WT32i Certifications……………………………………………………………………………………………………………….. 59
Bluetoot
…………………………………………………………………………………………………………………… 59
CE ……………………………………………………………………………………………………………………………… 59
C……………………………………………………………………………………………………………………………. 60
IC……………………………………………………………………………………………………………………………….. 61
16.1
16.2
16.3
16.4
16.
.1 IC………………………………………………………………………………………………………………………………..
61
16.5
MIC Japan…………………………………………………………………………………………………………………… 62
KCC (South-Korea
)
.
……………………………………………………………………………………………………… 62
Qualified Antenna Types for WT32i-E …………………………………………………………………………….. 62
6.6
16.7
Silicon Labs
WT32i
Bluetooth
®
Audio Module
DESCRIPTION
KEY FEATURES:
WT32i is an audio specific
Bluetooth
3.0
module with excellent radio frequency
performance and enhanced audio features,
enabling a best in class
Bluetooth
audio
•
•
Bluetooth
3.0 compliant
Excellent Radio Performance
o
Transmit power: +6.5 dBm
o
Receiver sensitivity: -90 dBm
o
Link budget: 96.5
B
experience.
In
addition
to
a
certified
Bluetooth
radio and software stack,
WT32i also contains a DSP, stereo audio
codec, and battery charger making it ideal
for fixed and portable
audio applications.
•
•
Integrated chip ante
or U.FL
antenna connector
WT32i
includes
Bluegiga’s
iWRAP6
Bluetooth
stack software which
implements A2DP, AVRCP v.1.5 profiles
and supports
aptX
®
and AAC audio codecs
for stereo audio applications. For hands-free
Audio features
o
Integ
ed DSP
o
16-bit stereo codec
o
44.1kHz ADC, 48kHz DAC
applications
iWRAP6
software
also
supports HFP
v.1.6, HSP, MAP and
PBAP and CVC
®
echo cancellation software.
For data communications to Android and
o
Analog, I2S, PCM, SPDIF, and
microphone interfaces
iOS
applications
iWRAP6
also
o
Optional aptX
®
and AAC stereo
implements
Bluetooth
Serial Port Profile
(SPP) and Apple iAP profiles.
WT32i is an
ideal solution for developers who want to
quickly integrate the latest
Bluetooth
audio
technologies without the time and co
ts
typically involved with a
Bluetooth
a
chipset design.
audio codecs
o
Optional
cancellation
CVC
®
echo
o
Wide Band Speech
Built-in battery charger
UART host interface
•
•
•
•
•
•
•
APPLICATIONS:
802.11 co-existence interface
10 software programmable IO pins
Operating voltage: 1.8V to 3.6V
Temperature range: -40C to +85C
•
•
•
•
Stereo speakers and sound bars
Hi-Fi devices
Hands-free kits
Stereo h
ets
Bluetooth
, CE, FCC, IC,
Korea
and
Japan qualified
•
Integrated iWRAP6
Bluetooth
stack
o
13
Bluetooth
profiles
o
Apple
iAP1
and
iAP2
compatibility
Figure 1: WT32i Bluetooth Audio Module
Silicon Labs
1 Design
Check List
POWERING THE MODULE
➢
Make sure that VRE_ENA is connected correctly
➢
Use iWRAP command SET CONTROL VREGEN
command to configure the VREG_ENA pin
according to the HW
Battery Voltage
(2.7
V
.
..4.4V)
VDD_BAT
VREG_ENA
VDD_IO
➢
Reserve test points for SPI interface for
IN
LDO
(1.8
V
.
..3.6V)
On/Off cntrl
EN
debugging and FW updates
➢
The internal power on reset does not work
properly if the host pulls the reset line low during
boot. To prevent this, place a diode to the reset
input.
Battery Voltage
(2.7
V
.
..4.4V)
DD
BAT
VREG_ENA
VDD_IO
IN
LDO
(1.8
V
.
..3.6V)
Host CPU
On/Off cntrl
E
WT32i
GPIO
Reset
RF LAYOUT
➢
Make sure that the layout for the antenna is done
as instrcucted.
Board edge
Min 15mm
Min 15mm
6mm
GN
plane indentation max 5.9 mm
GND plane indentation 2mm
AUDIO D
SIGN AND LAYOUT
➢
See the example schematics on pages 49 -52
➢
Avoid
ing single ended audio traces. Always
e d
ferential audio signaling when possible
e solid GND plane and make sure that all the
GND pins are connected to it by placing a GND
via right next to any GND pins.
➢
When routing single ended audio traces, make
sure that the return current (i.e. GND) follows the
traces all the way from start to the end
Differential audio tarces are routed
e
symmetrically and parallel
➢
DO NOT COMPROMISE AUDIO ROUTING
Silicon Labs
2 WT32i
Product Numbering
Product code
Description
WT32i Bluetooth Module with internal chip antenna and iWRAP 6.1.0 (build
1022)
Bluetooth
software
WT32i-A-AI61
WT32i Bluetooth Module with internal chip antenna and aptX® audio codec
capable iWRAP 6.1.0 (build 1024)
Bluetooth
software.
WT32i-A-AI61-APTX
WT32i-A-AI61IAP
WT32i Bluetooth Module with internal chip antenna and A
iAP capable
iWRAP 6.1.0 (build 1055)
Bluetooth
software. Available
Apple MFI
information.
WT32i Bluetooth Module with U.FL connector and iWRAP 6.1.0 (build
1022)
Bluetooth
software
WT32i-E-AI61
WT32i Bluetooth Module with U.FL connector and aptX® audio codec
capable iWRAP 6.1.0 (build 1024)
Bluetooth
software.
WT32i-E-AI61-APTX
WT32i Bluetooth Module with
L connector and Apple iAP capable
iWRAP 6.1.0 (build 1055)
Blueto
h
software. Available only to Apple MFI
information.
WT32i-E-AI61IAP
DKWT32i-A
WT32i developmen
kit
Silicon Labs
3 Block
diagram
Flash
BC05-MM
RAM
UART/USB
PIO
A
Out
PCM/I
2
S
SPI
Baseband
DSP
Balanced
filtter
2.4
GHz
Radio
Antenna
I/O
MCU
Kalimba DSP
Reset
circuitry
XTAL
Figure 2: Block Diagram o
WT32i
BC05-MM
The
BlueCore®5
-Multimedia External is a single-ch
p radio and baseband IC for Bluetooth 2.4GHz systems. It
provides a fully compliant Bluetooth v3.0 sp
cation system for data and voice. BlueCore5-Multimedia
External contains the Kalimba DSP coprocess
with double the MIPS of BlueCore3-Multimedia External,
supporting enhanced audio applications.
XTAL
Ther reference clock of WT32i is generated with 26 MHz crystal. All BC05-MM internal digital clocks are
generated using a phase locked loop, which is locked to the frequency of either the 26 MHz crystal or an
internally generated watchdog clock frequency of 1kHz.
RESET CIRCUITRY
The internal reset cir
y keeps BC05-MM in reset during boot in order for the supply voltages to stabilize.
This is to prevent corruption of the flash memory during booting. Please see chapter 6.1 for more detailed
description.
BALANCED
ILTER
The in
nal balanced filter provides optimal impedance matching and band pass filtering in order to achieve
lowest possible in-band and out-of-band emissions.
ANTENNA
antenna is a ceramic chip antenna with high efficiency. The antenna is insensitive to surrounding
dielectric materials and requires only a small clearance underneath which makes it compatible with previous
WT32I designs and well suitable for designs with high density.
FLASH
16 Mbit flash memory is used for storing the Bluetooth protocol stack and Virtual Machine applications. It can
also be used as an optional external RAM for memory-intensive applications.
Silicon Labs
4 Pinout
and Terminal Description
AUDIO_OUT_P_LEFT
AUDIO_OUT_N_LEFT
GND
50
49
48
47
46
1
AUDIO_OUT_P_RIGHT
AUDIO_OUT_N_RIG
T
VREG_ENA
2
GND
3
45 AUDIO_IN_N_LE
44 AUDIO_IN_P_LEFT
GND
GND
AIO0
AIO1
PIO0
PIO1
PIO2
PIO3
4
5
43
42
GND
6
AUDIO_IN_N_RIGHT
7
41 AUDIO_IN_P_RIGHT
40 MIC_
S
8
9
39
38
37
GND
10
VDD_CHG
VDD_BAT
USB_D- 11
USB_D+ 12
36 LED0
13
14
35
34
PIO9
SPI_MOSI
SPI_MISO
PIO10
UART_RXD 15
UART_TXD 16
VDD_IO 17
33 SPI_CLK
32 SPI_NCSB
GND
31
Figure 3:
WT32i
Pin Number
Pin Name
Pad Type
Description
SW configurable enable pin for the
internal regulators
1
VR
ENA
Input
GND
2-4, 18, 31,
39, 43, 48
GND
GND
1.7V – 3.6V power supply for the serial
interfaces and GPIOs
37
38
VDD_IO
Power supply
2.7V – 4.4V supply voltage for the
internal regulators and output of the
battery charger
Power supply / Charger
output
VDD_BAT
VDD_CHG
Nominal 5V supply voltage for the
battery charger
Power supply
Table 1: Supply
Terminal
Descriptions
Silicon Labs
Page 9 of 63
Pin
Number
Pin Name
Pin Type
Description
Active high reset. If not used, leave floating. When
connected, make sure that the reset is either pulled
high or floating (connected to high impedance)
during boot.
19
RESET
RESET
AIO0 and AIO1 can be used to rea
the voltage
level through the internal A
er to iWRAP
User Guide for details). AIO
can also be
configured to be used as general digital IO pins
through PS settings. Internal clocks can be routed
out through AIO pins by setting corresponding PS
settings. Note that
AIO pins are powered from
internal 1.5V supply so the maximum voltage level
of the AIO pins is 1.5V.
5
6
7
AIO0
AIO1
PIO0
Configurable I/O
8
9
PIO1
PIO2
PIO3
PIO9
PIO10
PIO8
PIO7
PIO6
PIO5
PIO4
General purpose IO’s can be configured with
iWRAP for various functions. Each IO can be
configured individually as output or input with
strong or weak pull-up/-down. Using particular PS
setting GPIO pins can be used to implement WiFi
co-existence signaling between WT32i and a WiFi
radio. Software I2C interface can be implemented
for slow I2C functions such as configuring external
audio codec or display.
10
13
14
22
23
24
25
26
Configurable CMOS I
O
11
12
USB_D-
USB_D+
I/O
I/O
USB data minus
USB data plus with selectable internal 1.5k pull-up
resistor
CMOS Input, weak internal
pull-down
15
16
20
21
U
RT_RXD
UART_TXD
UART_NRTS
UART_NCTS
UART data input
UART data output
CMOS output, tristate,
weak internal pull-up
CMOS output, tristate,
weak internal pull-up
UART request to send, active low
UART clear to send, active low
CMOS Input, weak internal
pull-down
CMOS Input, weak internal
pull-down
32
33
SPI_NCSB
SPI_CLK
SPI chip select
SPI clock
CMOS Input, weak internal
pull-down
Silicon Labs
Page 10 of 63
CMOS Input, weak internal
pull-down
34
35
SPI_MISO
SPI_MOSI
SPI data input
SPI data output
CMOS output, tristate,
weak internal pull-down
36
LED0
Open drain output
LED driver
Table 2:
Terminal
Descriptions
Pin
Number
Pin Name
Pin Type
Descripti
40
41
42
44
45
46
47
49
50
MIC_BIAS
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
AUDIO_IN_P_RIGHT
AUDIO_IN_N_RIGHT
AUDIO_IN_P_LEFT
AUDIO_IN_N_LEFT
AUDIO_OUT_N_RIGHT
AUDIO_OUT_P_RIGHT
AUDIO_OUT_N_LEFT
AUDIO_OUT_P_LEFT
CMOS input, weak
internal pull-down
27
28
PCM_IN / I2S IN
PCM or I2S data input
PCM or I2S data output
CMOS outp
istate,
weak int
al pull-down
PCM_OUT / I2S_OUT
PCM sync or I2S word select. WT32i can
operate as a PCM/I2S master providing the
sync or as a slave receiving the sync
B
tional, weak
internal down
29
30
PCM_SYNC / I2S_WS
PCM_CLK / I2S_SCK
PCM or I2S clock. WT32i can operate as a
PCM/I2S master providing the clock or as
a slave receiving the clock.
Bidirectional, weak
internal down
Table 3: Audio Terminal Descriptions
Silicon Labs
Page 11 of 63
5 Electrical
Characteristics
5.1 Absolute
Maximum Ratings
Min
Max
Unit
°C
°C
V
Storage temperature range
Operating temperature range
VDD_IO
-40
-40
+85
+85
-0.4
3.6
VDD_BAT
-0.4
4.4
V
VDD_CHG
-0.4
6.5
V
Digital Terminal voltages
AIO voltages
VSS – 0.4V
VSS – 0.4V
VDD + 0.4V
1.9V
V
V
Table 4: Absolute Maximum Ratings
5.2 Recommended
Operating Conditions
M
Max
Unit
°C
°C
V
V
V
Storage temperature range
Operating temperature range
VDD_IO
-40
-40
1.7
2.7
0
+85
+85
3.6
4.4
6.5
VDD_BAT
VDD_CHG
Digital Terminal voltages
AIO voltages
0
0
VDD
1.5V
V
V
Table 5: Recommended Operating Conditions
5.3 Digital
Terminals
Input/Ou
Characteristic
V
I
input logic level low
Min
Max
Unit
V
V
V
-0.3
0.625 x VDD
0
0.25 x VDD
VDD + 0.3
0.125
IL
input logic level high
output logic level low, I
OL
= 4.0mA
OL
output logic level high, I
OL
= -4.0mA
Strong pull-up
0.75 x VDD
VDD
-10
100
-0.2
5
V
-100
10
-5
µA
µA
µA
µA
Strong pull-down
Weak pull-up
Weak pull-down
0.2
Table 6: Digital Terminal Characteristics
Silicon Labs
Page 12 of 63
5.4 Audio
Characteristics
5.4.1
ADC
Parameter
Conditions
Min
Typ
Max
Unit
Resolution
–
–
–
–
–
16
Bits
kHz
Input Sample
Rate, F
sample
8
44.1
F
sample
8kHz
–
–
79
77
–
–
dB
dB
11.025kHz
Signal to Noise
Ratio, SNR
16kHz
22.050kHz
32kHz
–
–
–
–
–
–
–
–
76
76
–
–
–
–
–
–
–
–
–
dB
dB
75
dB
44.1kHz
75
dB
Input full scale at maximum gain (differential)
Input full scale at minimum gain (differential)
3dB Bandwidth
4
mV rms
mV rms
kHz
20
Microphone mode input impedance
THD+N @ 30mV rms input
6.0
0.04
kHz
%
Table 7
ADC characteristics
Silicon Labs
Page 13 of 63
5.4.2
DAC
Parameter
Conditions
Min
Typ
Max
Unit
Resolution
–
–
–
–
–
16
48
Bits
kHz
Output Sample
Rate, F
sample
8
F
sample
8kHz
–
–
95
95
–
–
dB
dB
11.025kHz
Signal to Noise
Ratio, SNR
16kHz
22.050kHz
32kHz
–
–
95
95
95
95
750
–
–
dB
dB
–
–
–
dB
44.1kHz
–
–
dB
Output Full Voltage Swing (differential)
–
–
mV rms
Ω
Resistive
16
–
O.C.
500
0.1
0.01
Allowed Load
Capacitive
pF
THD+N 16Ω Load
THD+N 100Ω Load
–
–
%
–
%
Table 8: DAC C
acteristics
5.4.3
A2DP Codecs
5.4.3.1 SBC
SBC codec is the default codec used f
r B
uetooth A2DP connections. Any Bluetooth device supporting A2DP
audio profile supports SBC codec. SBC was originally design to provide reasonable good audio quality while
keeping low computational complexity. SBC does not require high bit rates. Thus it works sufficiently with
Bluetooth where the bandwidth and the processing power are limited.
5.4.3.2 aptX
®
The aptX is widely u
n high quality audio devices. aptX can provide dynamic range up to 120 dB and it
has the shortest coding delay (<2ms) than other coding algorithms. Using aptX
®
the whole system latency can
be reduced significantly because unlike SBC, it does not require buffering the audio. SBC reproduces a limited
audio band w
th whereas aptX
®
encode the entire frequency range of audio.
aptX
®
more robust and resilient coding scheme than SBC and thus re-transmits does not occur as with
SBC.
Both SBC and aptX
®
have flat frequency response up to 14 kHz. Up to 14 kHz both algorithms produce good
lity audio with very little distortion. At frequencies higher than 14 kHz the benefit of aptX
®
becomes
vious. SBC exhibits increasing attenuation with increasing frequency but aptX
®
retains high reproduction
quality.
aptX
®
requires purchasing a license for each Bluetooth address and the license agreement must be done with
CSR. The combination of aptX
®
license and the Bluetooth address is programmed into the module in the
module production line.
Silicon Labs
Page 14 of 63
Figure 4: Frequency response of aptX and SBC codecs
5.4.3.3 AAC
AAC (Advanced Audio Coding) achieves better sound quality than MP3 and it is the default audio format for
YouTube and iPhone among others. AAC has long la
y (>100ms) compared to aptX
®
. Because of high
processing capacity requirement for encoding, WT32i does not support AAC as A2DP source. Thus WT32i
can be used for receiving (A2DP sink) AAC (from iPhone for example) but it cannot transmit AAC coded
audio.
Silicon Labs
Page 15 of 63
5.5 RF
Characteristics
5.5.1
RF Transceiver
Transceiver characteristic
Min
Typ
Max
Unit
8
dB
dBm
dB
Maximum transmit power
Minimum transmit power
5
6.5
-17
Transmit power stability over the temperature range
+/- 0.5
Transmit power variation within the BT band
RT
1
dB
-90
dBm
-40C
+85C
RT
-40C
+85C
Sensitivity DH1
-91
-86
-83
-8
-80
dBm
dBm
dBm
dBm
dBm
Sensitivity 3DH5
Table 9: Transceiver characteristics
Table 10: Power control of WT32i
Silicon Labs
Page 16 of 63
Min
Typ
Max
Band /
Frequency
Limit by the Standard
(AVG / PEAK)
Standard
(AVG /
(AVG /
(AVG /
PEAK) PEAK) PEAK)
Unit
2nd harmonic
3rd harmonic
50 / 61
54 / 74
54 / 74
dBuV/m
dBuV/m
< 40 /
50
Band edge
2390MHz
54 / 74
54 / 74
dBuV/m
dBuV/m
FCC part 15
transmitter
spurious
Band edge
2483.5MHz
emissions
Band edge
2400MHz
-20
dBc
(conducted)
Band edge
2483.5MHz
(conducted)
-20
-30
dBc
Band edge
2400MHz
ETSI EN 300
328 transmitter
spurious
dBm
2nd harmonic
3rd harmonic
-35
-30
-30
dBm
dBm
emissions
<-40
(2400 – 2479)
MHz
-47
dBm
ETSI EN 300
328 receiver
spurious
(1600 – 1653)
MHz
-47
dBm
emissions
Table 11: WT32i-A spurious emissions
Note
: All the emissions tested with ma
imum 8 dBm TX power
5.5.2
Antenna Characteristics
Note: Antenna characteristics may vary depending on the mother board layout. Following characteristics have
been measured using
KWT32i
•
•
Anten
efficiency -3.5 dB (45%)
ak gain 0 dBi
Silicon Labs
Page 17 of 63
0 dB
-5 dB
-10 dB
-15 dB
-20 dB
Figure 5: Top view radiati
n pattern of DKWT32i
–
dB
-4 dB
-6 dB
-8 dB
-10 dB
-12 dB
-14 dB
Figure 6: Side view radiation pattern of DKWT32i
Silicon Labs
Page 18 of 63
-1 dB
-2 dB
-3 dB
-4 dB
-5 dB
-6 dB
-7 dB
-8 dB
-9 dB
-10 dB
-11 dB
-12 dB
Figure 7: Front view radiation pattern
Silicon Labs
Page 19 of 63
5.6 Current
Consumption
Operation Mode
SET BT PAGEMODE 0 2000 0
Peak
Average
Unit
2.0
2.0
2.0
2.0
2.1
2.1
SET BT PAGEMODE 0 2000 1
SET BT PAGEMODE 0 2000 2
SET BT PAGEMODE 1 2000 0
SET BT PAGEMODE 1 2000 1
SET BT PAGEMODE 1 2000 2
SET BT PAGEMODE 2 2000 0
SET BT PAGEMODE 2 2000 1
SET BT PAGEMODE 2 2000 2
SET BT PAGEMODE 3 2000 0
SET BT PAGEMODE 3 2000 1
SET BT PAGEMODE 3 2000 2
SET BT PAGEMODE 4 2000 0
SET BT PAGEMODE 4 2000 1
SET BT PAGEMODE 4 2000 2
SET BT PAGEMODE 0 2
0
SET BT PAGEMODE 0 2000 1
SET BT PAGEMODE 0 2000 2
SET BT PAGEM
1 2000 0
SET BT PAG
MODE 1 2000 1
SET BT
GEMODE 1 2000 2
SET BT PAGEMODE 2 2000 0
SET BT PAGEMODE 2 2000 1
ET BT PAGEMODE 2 2000 2
SET BT PAGEMODE 3 2000 0
SET BT PAGEMODE 3 2000 1
SET BT PAGEMODE 3 2000 2
SET BT PAGEMODE 4 2000 0
SET BT PAGEMODE 4 2000 1
SET BT PAGEMODE 4 2000 2
SET BT SNIFF 0 20 1 8
12
2.1
23
Idle
mA
32
2.3
2.2
23
2.3
2.2
0.08
0.08
0.08
0.18
0.18
0.18
23.5
0.31
0.19
23
12
Sleep
mA
0.4
0.29
23
32
0.4
0.29
4.7
3.9
2.5
3.6
2.5
28
Connected, Sniff disabled
Conn
cted + Sniff, Master
Co
cted + Sniff, Master
Connected + Sniff, Slave
Connected + Sniff, Slave
A2DP Audio Streaming
SET BT SNIFF 40 20 1 8
SET BT SNIFF 1000 20 1 8
SET BT SNIFF 40 20 1 8
SET BT SNIFF 1000 20 1 8
A2DP SINK, INTERNAL CODEC
75
70
mA
A2DP Audio Streaming
A2DP SOURCE, INTERNAL CODEC
23
Table 12: Current consumption of WT32i
Silicon Labs
Page 20 of 63
6 Power
Control and Regulation
WT32i contains an internal battery charger and a switch mode regulator that is mainly used for internal blocks
of the module. The module can be powered from a single 3.3 V supply provided that VDD_CHG is floating.
Alternatively the module can be powered from a battery connected to VDD_BAT and using an external
regulator for VDD_IO. 1.8 V to 3.3 V supply voltage for VDD_IO can be used to give desired signal levels for
the digital interfaces of the module. USB, however, requires 3.3 V for proper operation and thus, when US
s
in use, 3.3 V for VDD_IO is required.
VDD_CHG
In
Battery Charger
Out
AIO
RF
Core
Audio
VDD_BAT
Switch mode
1.8V regulator
Linear 1.5V
regulator
VREG_ENA
Flash
PIO
USB
VDD_IO
UART
PCM
Figure
Power supply configuration of WT32i
VDD_ENA is software configurable enable pin for the internal regulators. Using iWRAP the enable pin can be
configured to
1. Latch
on the internal regulators at the rising edge
2. Turn
the regul
rs on at rising edge and turn off the regulators at falling edge
3. Latch
the regulators on at the rising edge and turn off the regulators at the following rising edge
GPIO c
be
onfigured to control an external regulator.
Silicon Labs
Page 21 of 63
Battery Voltage
(2.7
V
.
..4.4V)
VDD_BAT
ON/OFF
Button
VREG_ENA
VDD_IO
IN
LDO
(1.8
V
.
..3.6V)
EN
100k
100k
C1
4u7
GPIO (holds the external LDO on)
Figure 9: Example of making a power on/off button using the latch feature of the internal regulators
iWRAP Example:
Creating an on/off button with PI
2 holding the external regulator on
“SET CONTROL VREGEN 2 4”
(PIO is defined with a bit mask. 4 in hexadecimal is 100 in binary corresponding to PIO2)
NOTE:
With the configuration shown above, when doing a SW reset for the module C1 will hold the enable pin
of the external regulator high until iWRAP has booted. This will prevent the module from turning off during
reset. When resetting through the reset pin one has to make sure that the enable pin is held high as long as
the reset pin is held active.
Figure 10 sh
ws an example how to arrange power control when on/off button is not implemented.
VREG_ENA
n must not be connected to VDD_IO because leakage from VDD_BAT to VDD_IO will prevent
VREG
A to fall low enough to turn off the internal regulators.
Silicon Labs
Page 22 of 63
Battery Voltage
(2.7
V
.
..4.4V)
VDD_BAT
VREG_ENA
VDD_IO
IN
LDO
(1.8
V
.
..3.6V)
On/Off cntrl
EN
Battery Voltage
(2.7
V
.
..4.4V)
VDD_BAT
VREG_ENA
VDD_IO
IN
O
(1.8
V
.
..3.6V)
On/Off cntrl
EN
Figure 10: Correct and wrong connection for the power on/off control
6.1 Protect
ng the Battery by Configuring the Module to Turn Off at Certain
Volt
ge
It is im
rtant not to let the battery be drained to voltages below 2.8V. In iWRAP it is possible to define certain
level when the module turns off the regulators.
RAP Example:
Configure WT32i to start sending low battery warning at 3.4V, turn off at 3.3V and cease
the low battery warning at 4.0V. Set PIO0 to indicate low batter
“SET CONTROL BATTERY 3400 3300 4000 10”
Silicon Labs
Page 23 of 63
6.2 Reset
WT32i may be reset from several sources: reset pin, power on reset, a UART break character or through
software configured watchdog timer.
At reset, the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-state.
The chip status after a reset is as follows:
•
•
Warm Reset: data rate and RAM data remain available
Cold Reset: data rate and RAM data are not available
Table 13
shows the pin states of WT32i on reset. Pull-up (PU) and pull-down (PD) default to weak values
unless specified otherwise.
NOTE: In order to make reset work properly VREG_ENA pin (1st pin of WT32i modu
s to be driven
high for the time of reset.
No Core Vo
age
Pin Name / Group
I/O Type
Full Chip Reset
Rese
USB
Digital bi-directional
Digital input with PD
N/A
N/A
PD
UART_RX
UART_CTS
UART_TX
UART_RTS
SPI_MOSI
SPI_CLK
PD
PU
Digital output with PU
Digital input with
PU
PD
PU
PD
PU
Digital tristate o
put with
PD
SPI_MISO
SPI_CS
PCM_IN
Digital i
with PU
Digital input with PD
PCM_CLK
PCM_SYNC
Dig
bi-directional with PD
PD
PD
PD
PD
Digital tri-state output with
PD
PCM_OUT
GPIO
Digital bi-directional with
PU/PD
Table 13: Pin states on reset
6.2.1
Internal POR
WT32i
two internal POR circuits. One is internally to the BC5 chip. In BC5 the power on reset occurs
when t
core supply voltage (output of the internal 1.5V regulator) falls below typically 1.26V and is released
when VDD_CORE rises above typically 1.31V.
nother POR circuit is embedded to the module and it keeps the module in reset until supply voltages have
bilized. This is to prevent corruption of the internal flash memory during boot. The embedded POR is
Because the POR is based on a simple RC time constant it will not work if the supply voltage ramps very
slowly or if the reset pin is not connected to high impedance. It is recommended that the power ramp will not
take more than 10 msec. If the reset pin is connected to a host it is good to place a diode between the host
and the module as shown in Figure 12. A diode will prevent the host from pulling the reset low before the
internal flash has its supply stabilized.
Silicon Labs
Page 24 of 63
WT32i
Reset BC05
22nF
BC05
Reset
220k
Figure 11: Em
dded POR of WT32i
Host CPU
WT32i
GPIO
Reset
Figure 12: An example how to connect CPU GPIO to the reset pin of the module
Silicon Labs
Page 25 of 63
7 Battery
Charger
The battery charger is a constant current / constant voltage charger circuit, and is suitable for lithium
ion/polymer batteries only. It shares a connection to the battery terminal, VDD_BAT, with the switch-mode
regulator. The charger is initially calibrated by Bluegiga Technologies to have V
float
= 4.15V – 4.2 V.
The constant current level can be varied to allow charging of different capacity batteries. WT32i allows a
number of different currents to be used in the battery charger hardware. Values written to PS key 0x
CHARGER_CURRENT in the range 1..15 specify the charger current from 40..135mA in even steps. Values
outside the valid 0..15 range result in no change to the charging current. The default charging current (Key =
0) is nominally 40mA. Setting 0 is interprete
d as “no
–
change” so
it will be ignored
The charger enters various states of operation as it charges a battery. These are shown b
:
•
•
•
•
Off: entered when the charger is disconnected.
Trickle Charge: entered when the battery voltage is below 2.9V.
Fast Charge – Constant Current: entered when the battery voltage is above 2.9V.
Fast Charge – Constant Voltage: entered when the battery has reached V
float
, the charger
switches mode to maintain the cell voltage at V
float
voltage
y adjusting the constant
charge current.
•
Standby: this is the state when the battery is fully charged and no charging takes place.
When a voltage is applied to the charger input terminal VDD_CHG, and the battery is not fully charged, the
charger will operate and a LED connected to the terminal LED0 will illuminate. By default, until the firmware is
running, the LED will pulse at a low-duty cycle to minimize curre
nsumption.
The battery charger circuitry auto-detects the presence of a power source, allowing the firmware to detect
when the charger is powered. Therefore, when the c
arger supply is not connected to VDD_CHG, the
terminal must be left open circuit. The VDD_CHG pin,
n not connected, must be allowed to float and not
be pulled to a power rail. When the battery char
is not enabled, this pin may float to a low undefined
voltage. Any DC connection will increase current c
nsumption of the device. Capacitive components such as
diodes, FETs, and ESD protection, may be con
ed.
The battery charger is designed to operate with a permanently connected battery. If the application permits
the charger input to be connected while the battery is disconnected, the VDD_BAT pin voltage may become
unstable. This, in turn, may cause
mage to the internal switch-mode regulator. Connecting a 470
μ
F
capacitor to VDD_BAT limits these oscillations thus preventing damage.
WARNING:
Use good consideration for battery safety. Do not charge with too much current. Do not charge when the
temperature is above
C or below 0°C.
WT32i is initially calibrated to stop charging when battery voltage is
at 4.2 V. Do not try to c
arge batteries above 4.2 V. Do not short circuit the battery or discharge below 1.5 V.
Silicon Labs
Page 26 of 63
8 GPIO
and AIO Functions
8.1 iWRAP
supported GPIO Functions
Various GPIO functions are supported by iWRAP. These include:
•
•
Setting each GPIO state individually
Binding certain iWRAP commands to GPIO to trigger the command at either the rising or falling edge
of the GPIO
•
•
•
•
•
Carrier detect signal to indicate an active Bluetooth connection
Implementing RS232 modem signals
iWRAP ready indicator to signal to a host that iWRAP is ready to use
UART bypass mode to route UART signals to GPIO pins instead of iWRAP
Driving low frequency pulsed signal from a GPIO
Some of the functions are FW dependent. Refer to latest iWRAP user manual for the detailed information
about the GPIO functions.
8.2 Outputting
Internal Clocks
Internal clocks can be routed to either AIO0 or AIO1 by
tting PS Keys. To route internal clock to AIO0 set
PSKEY_AMUX_AIO0 to 0x00fe. Following table s
ws how to set the PSKEY_AMUX_CLOCK to get certain
frequency from AIO0.
AMUX_CLOCK
Freq (MHz) @ AIO0
0x001
0x0004
0x0013
0x0017
0x0003
0x0016
0x0007
0x0011
0x0006
0x0002
0x0009
0x0005
1
2
3
4
6
6.5
8
12
13
16
24
32
Table 14: Selectable internal clock frequencies from AIO0
iWRAP does not support this feature. To use this feature either the particular PS Keys must be set to each
module separately or then ask for custom FW from Bluegiga.
Silicon Labs
Page 27 of 63
8.3 Auxiliary
ADC
Simple iWRAP command can be used to read the ADC output from either of the two AIO pins. Refer to latest
iWRAP user manual for the detailed information.
8.4 Software
I2C Interface
PIO6 and PIO7 can be used to form a master I
²
C interface. The interface is formed using software to
these lines. Therefore it is suited only to relatively slow functions such as driving a dot matrix LCD, keyboard
scanner or configuring external audio codec. I
2
C interface requires a custom FW.
PIO
I2C Signal
PIO6
PIO7
SCL
SDA
Table 15: I2C Interface of WT32i
Silicon Labs
Page 28 of 63
9 Serial
Interfaces
9.1 UART
Interface
WT32i has a standard UART serial interface that provides a simple mechanism for communicating with other
serial devices using the RS232 protocol. UART configuration parameters, such as baud rate, parity and stop
bits can be configured with an iWRAP command.
The hardware flow control is enabled by default. HW flow control can be disabled in HW by connecting
UART_NCTS to GND and leaving UART_NRTS floating.
Parameter
Possib
alues
1200 baud (≤2%Error)
9600 (≤1%Error)
Minimum
Maximum
Baud rate
4Mbaud (≤1%Error)
Flow control
Parity
RTS/CTS or None
None, Odd, Even
Number of stop bits
Bits per byte
1 or 2
8
Table 16: Possible UART settings
iWRAP Example:
Configuring local UART to 9600bps, 8 data bits, no parity and 1 stop bit
SET CONTROL BAUD 9600, 8N1
(9600 = baud rate, N = No parity, 1 = 1 stop bit)
Baud Rate
Error
1200
2400
1.73%
1.73%
1.73%
-0.82%
0.45%
-0.18%
0.03%
0.14%
0.03%
0.03%
-0.02%
0.00%
-0.01%
0.00%
0.00%
0.00%
4800
9600
19200
38400
57600
76800
115200
230400
460800
921600
1382400
1843200
2764800
3686400
Table 17: Standard Baud Rates
Silicon Labs
Page 29 of 63
9.1.1
Resetting Through UART Break Signal
The UART interface can reset WT32i on reception of a break signal. A break is identified by a continuous logic
low (0V) on the UART_RX terminal. If t
BRK
is longer than the value (in microseconds), defined by
PSKEY_HOSTIO_UART_RESET_TIMEOUT, (0x1a4), a reset occurs. Values below 1000 are treated as zero
and values above 255000 are truncated to 255000. This feature allows a host to initialise the system to a
known state. Also, WT32i can emit a break character that may be used to wake the host.
Default PSKEY_HOSTIO_UART_RESET_TIMEOUT setting in WT32i is zero, which means that this featu
disabled. To use this feature, either the PS setting has to be changed for each module separately or ask for
modules with custom FW with appropriate settings.
9.1.2
UART Configuration While Reset is Active
The UART interface for WT32i is tristate while the chip is being held in reset. This allows
he user to daisy
chain devices onto the physical UART bus. The constraint on this method is that any devices connected to
this bus must tristate when WT32i reset is de-asserted and the firmware begins to run.
9.1.3
UART Bypass Mode
Alternatively, for devices that do not tristate the UART bus, the UART bypass mode on WT32i can be used.
The default state of WT32i after reset is de-asserted; this is for the host UART bus to be connected to the
WT32i UART, thereby allowing communication to WT32i via the UART. All UART bypass mode connections
are implemented using CMOS technology and have signalling le
of 0V and VDD_IO.
The bypass mode is enabled with a simple iWRAP command. When in bypass mode, the module is
automatically set into deep sleep state indefinitely. Ph
sical reset is required to return to normal operation
mode. The current consumption of a module in bypass
e is equal to a module in standby (idle) mode.
It is important for the host to ensure a clean Blue
oth disconnection of any active links before the bypass
mode is invoked. Therefore, it is not possible to
ave active Bluetooth links while operating the bypass mode.
RESET
PIO4
PIO5
PIO6
PIO7
UART_TX
UART_RTS
UART_CTS
UART_RX
TX
RXD
CTS
Host
processor
RTS
Another
device
RTS
CTS
RX
Test
UART
interface
WT32i
Figure 13: UART bypass architecture
Silicon Labs
Page 30 of 63
9.2 USB
Interface
WT32i has a full-speed (12Mbps) USB interface for communicating with other compatible digital devices. The
USB interface on WT32i acts as an USB peripheral, responding to requests from a master host controller.
WT32i can be used as bus-powered or self-powered device. See the WT_USB_Design_Guide available in the
Bluegiga techforum for details about the SW and HW configuration of the USB interface.
WT32i
VDD_IO
VDD_IO
VDD_BAT
Figure 14: Bus-powered WT32i device configuration
Silicon Labs
Page 31 of 63
WT32i
VDD_IO
VDD_IO
Figure 15: Self powere
WT32i device configuration
9.3 Programming
and Debug Interface (SPI)
The synchronous serial port interface (SPI) is for interfacing with other digital devices. The SPI port can be
used for system debugging. It can also be used for programming the Flash memory. SPI interface is
connected by using the MOSI, MISO, CSB and CLK pins.
SPI interface cannot be used for any application purposes.
9.3.1
Multi-sl
Operation
WT32i should not be connected in a multi-slave arrangement by simple parallel connection of slave MISO
lines. When
T32i is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead, WT32i outputs 0
if the p
ssor is running or 1 if it is stopped.
Silicon Labs
Page 32 of 63
10 Audio Interfaces
10.1 Stereo Audio Codec Interface
Stereo audio CODEC operates from an internal 1.5V power supply. It uses fully differential architecture in
analog signal path for the best possible common mode noise rejection while effectively doubling the signal
amplitude.
The stereo audio bus standard I2S is supported and a software I2C interface can be implemented using
GPIOs to configure an external audio CODEC.
Figure 16: Stereo CODEC input and output stages
10.1.1 ADC
The ADC consis
s of two second-order sigma-delta converters and gain stages. The gain stage consists of
digital and analog gain stages which are controlled by iWRAP. The optimal combination of digital and analog
gain is automatically selected by iWRAP. The analog gain stage consist selectable 24 dB preamplifier for
selecti
icrophone or line input levels and an amplifier which can be configured in 3 dB steps. The iWRAP
gain se
ction values are shown in the Table 19.
Fol
owing sample rates are supported
•
•
•
•
•
•
•
8kHz
11.025kHz
16kHz
22.05kHz
24kHz
32kHz
44.1kHz
Silicon Labs
Page 33 of 63
Preamp ON = 24 dB gain (MIC input)
Preamp OFF = 0 dB gain (line input)
iWRAP Gain Setting
(-27…39)dB
Table 18: ADC amplifier block diagram
ADC Gain (dB)
Preamp OFF
(Line input mode)
-27
ADC GAIN (dB)
Preamp ON
(MIC input mode)
Gain Setting In iWRAP
-3
0
0
1
-24
-21
-18
-15
-1
-6
-3
0
3
3
6
9
2
3
4
5
6
7
8
9
A
B
C
D
E
12
15
18
21
24
27
30
33
36
39
42
45
48
51
54
57
60
63
6
9
12
15
18
21
24
27
30
33
36
39
F
10
11
12
13
14
15
16
Table 19: ADC Gain Selection In iWRAP
RAP Example:
Setting line input with 0 dB gain
“SET CONTROL PREAMP 0”
”SET CONTROL GAIN
9 x
”
(x is the DAC gain)
Silicon Labs
Page 34 of 63
10.1.2 DAC
The DAC consists of two second-order sigma-delta converters and gain stages. The gain stage consists of
digital and analog gain stages which are controlled by iWRAP. The optimal combination of digital and analog
gain is automatically selected by iWRAP. The analog gain stage consist selectable 24 dB preamplifier for
selecting microphone or line input levels and an amplifier which can be configured in 3 dB steps. The iWRAP
Following sample rates are supported
•
•
•
•
•
•
•
•
8kHz
11.025kHz
16kHz
22.05kHz
24kHz
32kHz
44.1kHz
48kHz
Gain Setting In iWRAP
DAC Gain (dB)
0
1
-42
-39
-36
-33
-30
-27
-24
-21
-18
-15
-12
-9
2
3
4
5
6
7
8
9
A
B
C
D
E
-6
-3
0
F
3
10
11
12
13
14
15
16
6
9
12
15
18
21
24
Table 20: DAC gain selection in iWRAP
iWRAP Example:
Setting output with 0 dB gain
”SET CONTROL GAIN x E” (x is the ADC gain)
Silicon Labs
Page 35 of 63
10.1.3 Microphone
Input
Figure 17
shows the recommended microphone biasing. The microphone bias, MIC_BIAS, derives its power
from the VDD_BAT and requires 1uF capacitor on its output (C1).
The input impedance at AUDIO_IN_P_LEFT and AUDIO_IN_N_LEFT is typically 6kohm and C5 and C4 are
typically 1uF. If bass roll-off is required to limit the wind noise on the microphone then C4 and C5 should be
150 nF.
R2 sets the microphone load impedance and is normally in the range of 1k
Ω
to 2k
Ω
R1, C2 and C3 improve the supply rejection by decoupling supply noise from the microphone. Values should
be selected as required. R1 can be connected or to the MIC_BIAS output (which is ground re
renced and
provides good rejection of the supply) as shown in
Figure 17.
MIC_BIAS is configured to pro
ide bias only
when the microphone is required. R1 may also be connected to a convenient supply, in
case the bias
network is permanently enabled.
MIC_BIAS
WT32
C1
R1
R2
AUDIO_I
_P_LEFT
AUDIO_IN_N_LEFT
C5
C
C2
C3
MI
Figure 17: Microphone connection to audio input
The MIC_BIAS is like any voltage regulator and requires a minimum load to maintain regulation. The
MIC_BIAS maintains regulation within the limits 0.200mA to 1.230mA. If the microphone sits below these
limits, then the microp
ne output must be pre-loaded with a large value resistor to ground.
The audio input is intended for use in the range from 1
μ
A @ 94dB SPL to about 10
μ
A @ 94dB SPL. With
biasing resistors R1 and R2 equal to 1k
Ω
, this requires microphones with sensitivity between about
–
40dBV
and
–
60dBV.
Table
sts the possible voltage and current setting in iWRAP for the MIC_BIAS.
Setting in iWRAP
Voltage (V)
Current (mA)
0.200
0.280
0
1
2
3
4
5
1.71
1.76
1.82
1.87
1.95
2.02
0.340
0.420
0.480
0.530
Silicon Labs
Page 36 of 63
0.610
0.670
0.750
0.810
0.860
0.950
1.000
1.090
1.140
1.230
6
7
8
2.10
2.18
2.32
2.43
2.56
2.69
2.90
3.08
3.33
3.57
9
A
B
C
D
E
F
Table 21: MIC_BIAS settings in iWRAP
10.1.4 Line
Input
Line input mode is selected by setting the ADC preamplifier off (see chapter
1
.1)
. In the line input mode the
input impedance varies from 6k to 30 kohm depending on the gain setting.
Figure 18
and Figure 19 show examples of line input connection with WT32i. The maximum line level rms
voltage can vary from 0.3 up to 1.6 Vrms depending on the application, while the maximum for WT32i is
0.4Vrms (0.8Vrms differential). Thus it may be necessary to use a voltage divider (R1 and R2) at the input to
attenuate the incoming signal. C1 and C2 are typically 1uF cera
X7R or film type capacitors.
It is a good practice to place a LC (22nH + 15pF) filter close to each input to filter out any RF noise that might
couple to the audio traces.
WT32i
C1
R1
AUDIO_IN_P_LEFT
AUDIO_IN_N_LEFT
Line input
R2
C2
Figure 18: Single ended line input example
Silicon Labs
Page 37 of 63
WT32i
C1
C2
R1
AUDIO_IN_P_LEFT
AUDIO_IN_N_LEFT
Line input P
Line input N
R2
Figure 19: Differential line in
example
10.1.5 Output
Stage
The output stage digital circuitry converts the sign
rom 16-bit per sample, linear PCM of variable sampling
frequency to bit stream, which is fed into the a
alogue output circuitry. The output stage circuit comprises a
DAC with gain setting and class AB output stag
mplifier.
The output is available as a differential signal between AUDIO_OUT_N_LEFT and AUDIO_OUT_P_LEFT for
left channel and AUDIO_OUT_N_RIGH
and AUDIO_OUT_P_RIGHT for right channel.
The output stage is capable of driving a speaker directly when its impedance is at least 16
Ω
.
Figure 20 show an example of differentially connected speaker and Figure 21 show an example of speaker
connected single-ended. Differential (balanced) connection provides perfect common mode rejection ratio with
effectively 3 dB higher amplitude so it is recommended to use differential signaling always when possible.
Silicon Labs
Page 38 of 63
WT32i
AUDIO_OUT_P_LEFT
AUDIO_OUT_N_LEFT
Figure 20: Differentially conne
speaker
WT32i
AUDIO_OUT_P_LEFT
AUDIO_OUT_N_LEFT
C1
Figure 21: Single-ended speaker connection
Silicon Labs
Page 39 of 63
10.1.6 Mono
Operation
Mono operation is a single-channel operation of the stereo codec. The left channel represents the single mono
channel for audio in and audio out. In mono operation the right channel is the auxiliary mono channel that may
be used in dual mono channel operation. Dual mono feature is FW dependent and iWRAP does not generally
support it.
10.1.7 Side
Tone
In some applications it is necessary to implement side tone. This involves feeding an attenuated version of the
microphone signal to the earpiece. The WT32i codec contains side tone circuitry to do this. There is no
iWRAP support for the side tone but the side tone is configurable through PS Keys. To impleme
t a side tone,
either the PS setting has to be programmed for each module separately or ask for mod
ith custom FW
with appropriate settings.
The side tone hardware is configured through the following PS Keys:
•
•
•
•
PSKEY_SIDE_TONE_ENABLE
PSKEY_SIDE_TONE_GAIN
PSKEY_SIDE_TONE_AFTER_ADC
PSKEY_SIDE_TONE_AFTER_DAC
10.2 PCM Interface
The audio PCM interface supports continuous transmis
n and reception of PCM encoded audio data over
Bluetooth.
PCM is a standard method used to digi
audio, particularly voice, for transmission over digital
communication channels. Through its PCM inter
ce, WT32i has hardware support for continual transmission
and reception of PCM data, so reducing processor overhead. WT32i offers a bidirectional digital audio
interface that routes directly into the ba
band layer of the on-chip firmware. It does not pass through the HCI
protocol layer.
Hardware on WT32i allows the data to be sent to and received from a SCO connection.
Using HCI FW up to 3 SCO connections can be supported by the PCM interface at any one time. However
iWRAP supports only 1 SCO connection at a time.
WT32i can operate
the PCM interface master generating PCM_SYNC and PCM_CLK or as a PCM
interface slave accep
externally generated PCM_SYNC and PCM_CLK. WT32i is compatible with various
clock formats, including Long Frame Sync, Short Frame Sync and GCI timing environments.
WT32i suppo
s 13-bit or 16-bit linear, 8-bit
μ
-law or A-law companded sample formats, and can receive and
transm
any selection of 3 of the first four slots following PCM_SYNC. The PCM configuration options are
enable
by setting the PS Key PSKEY_PCM_CONFIG32. Please contact Bluegiga technical support for
details about the PCM configuration.
.3 I2S Interface
The digital audio interface supports the industry standard formats for I
2
S, left-justified or righ justified. The
interface shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its
usage. The internal representation of audio samples within WT32i is 16-bit and data on SD_OUT is limited to
16-bit per channel.
WT32i is not capable of generating the master clock for I
2
S, so when configured as a master, it can only be
used with a codec that is capable of producing the master clock from the SCK.
Silicon Labs
Page 40 of 63
I2S CODEC
MCLK Generator
ASI
SCK
WS
WT32i
I2S_IN
I2S_OUT
Figure 22: I
2
S scheme for WT32i
Bit
Mask
Name
Description
D[0]
0x0001
0x0002
CONFIG_JUSTIF
_FORMAT
0 for left justified, 1 for right justified.
For left justified formats: 0 is MSB of SD
data occurs in the first SCLK period
following WS transition. 1 is MSB of SD
data occurs in the second SCLK period.
D[1]
D[2]
CONFIG_L
T_JUSTIFY_DELAY
C
NFIG_CHANNEL_POLARITY
For 0, SD data is left channel when WS
is high. For 1 SD data is right channel.
0x0004
0x0008
For 0, 17-bit SD data is rounded down
to 16bits. For 1, the audio attenuation
defined in CONFIG_AUDIO_ATTEN is
applied over 24bits with saturated
rounding. Requires
D[3]
CONFIG_AUDIO_ATTEN_EN
CONFIG_16_BIT_CROP_EN to be 0.
D[7:4]
D[9:8]
0x00F0
0x0300
CONFIG_AUDIO_ATTEN
Attenuation in 6dB steps.
Resolution of data on SD_IN, 00=16bit,
01=20bit, 10=24bit, 11=Reserved. This
is required for right justified format and
with left justified LSB first.
CONFIG_JUSTIFY_RESOLUTION
For 0, 17-bit SD_IN data is rounded
down to 16bits. For 1 only the most
significant 16bits of data are received.
D[10]
0x0400
CONFIG_16_BIT_CROP_EN
Table 22: PSKEY_DIGITAL_AUDIO_CONFIG
Silicon Labs
Page 41 of 63
Figure 23: Digital Audio Interface Modes
10.4 IEC 60958 Interface
The IEC 60958 inter
is a digital audio interface that uses bi-phase coding to minimize the DC content of
the transmitted signal and allows the receiver to decode the clock information from the transmitted signal. The
IEC 60958 specification is based on the 2 industry standards:
•
•
ES/
BU
Sony and Philips interface specification SPDIF
The interface is compatible with IEC 60958-1, IEC 60958-3 and IEC 60958-4.
e SPDIF interface signals are SPDIF_IN and SPDIF_OUT and are shared no the PCM interface pins. The
ut and output stages of the SPDIF pins can interface to:
•
•
75
Ω
coaxial cable with an RCA connector, see Figure 24
An optical link that uses Toslink optical components
Silicon Labs
Page 42 of 63
DC bias for the comparator input
3V3
10K, 50V, 0.063W
R15
Impedance matching to 75 ohm
3
1
+
–
5
SPDIF_IN
C2
U3
COMPARATOR_TLV3501AIDBVT
10000pF/25V/
X
7
R
Comparator (Tpd max 10ns)
3V3
D1
13
ESD_PROTECTION
U1-C
R1
5
3
1
6
4
2
560R, 50V, 0.063W
DC block
74HC14D
U1-B
2
1
3
U1-D
R2
J2
ESD_PROTE
T
I
ON
13
9
8
SPDIF_OUT
RCA_RED
560R, 50V, 0.063W
74HC14D
U1-A
74HC14D
D2
C1
R3
2
560R, 50V, 0.063W
0.15uF/10V/
X
5
R
1
74HC14D
J1
RCA_RED
Buffering required to drive 75 ohm load
Impedance matching to 75 ohm
Figure 24: Example circuit for SPDIF interface (co-axial)
Silicon Labs
Page 43 of 63
11 Design Guidelines
This chapter shows briefly the most important points to consider when making a design with WT32i. Please
refer to the DKWT32i datasheet for detailed description of the development board design.
11.1 Audio Layout Guide
11.1.1 EMC
Considerations
To avoid RF noise coupling top the audio t
races it is extremely important to make sure that the
aren’t
GND
loops in the audio traces. Audio layout can not be compromised. RF noise that couples to aud
o signal lines
usually demodulates down to audio band causing very unpleasant whining noise.
Noise couples to signals lines either through a parasitic capacitance or by coupling to a loop. The noise that
couples to a loop is proportional to the area of the loop and to the electromagnetic field flowing through the
loop. Thus the noise can be minimized in two ways. Minimizing the field strength flowing through the loop by
placing the signal lines far from the RF source or most importantly minimize t
size of the loop by keeping
the trace as short as possible and making sure that the path for the retur
current (usually GND) is low
impedance and follows the forward current all the way as close as possible. GND vias must be placed right
next to the any component GND pins and solid GND plane must follow the trace all the way from start to the
end. When using fully differential signals they should be routed as differential pairs, parallel and symmetrically.
No
couples through a
parasitic capacitance
EM field couples to a
loop
R
RL
Figure 25: Noise coupling schemes
11.1.2 Choosing
Capacitors and Resistors
Metal film resistors h
lower noise than carbon resistors which makes them more suitable for high quality
audio.
Non-linearity
capacitors within the audio path will have an impact on the audio quality at the frequencies
where the impedance of the capacitors become dominant. At higher frequencies the amplitude is not
deter
d by the value of the capacitors but at the lower frequencies the impact of the capacitors will be
seen.
Ceramic capacitors should be X5R or X7R type capacitors with relative high voltage rating. The higher the
pacitance value, the lower is the frequency where the non-linearity will start to have an impact. Thus it is not
ad idea to select the capacitors value bigger than necessary from the frequency response point of view.
For optimal audio quality the best selection is to use film capacitors. Film capacitors have excellent linearity
and they are non-polarized which makes them perfect choice for using in audio path. The drawback of film
capacitors is bigger physical size and higher cost.
Figure 26 shows a modulation distortion measurement when using different type of capacitors in the audio
paths. Modulation distortion measures the amount of distortion between two closely located sine waves. The
Silicon Labs
Page 44 of 63
difference between the different capacitors is obvious at low frequencies where the impedance of the
capacitor is dominant.
Figure 26: Modulation di
ion with different type of capacitors
11.2 RF Layout Guide
The chip antenna of WT32i requires only a small metal clearance area directly under the antenna. The
antenna operation is dependent on the GND planes on both sides of the antenna. Minimum 15mm of GND
plane must be placed on both sides of the module and the GND plane of the motherboard must reach under
the edges of the module as shown in the Figure 27.
Silicon Labs
Page 45 of 63
Board edge
Min 15mm
Min 15mm
6mm
GND plane indentation max 5.9 mm
GND plane indentation 2mm
Figure 27: Recommended layout for WT32i
Figure 28: Poor layouts for WT32i
Use good layout practices to avoid excessive noise coupling to supply voltage traces or sensitive analog
signal traces. If using overlapping ground planes use stitching vias separated by max 3 mm to avoid emission
from the edges of the PCB. Connect all the GND pins directly to a solid GND plane and make sure that there
is a low impedance path for the return current following the signal and supply traces all the way from start to
the end.
Silicon Labs
Page 46 of 63
A good practice is to dedicate one of the inner layers to a solid GND plane and one of the inner layers to
supply voltage planes and traces and route all the signals on top and bottom layers of the PCB. This
arrangement will make sure that any return current follows the forward current as close as possible and any
loops are minimized.
Signals
GND
Power
Signa
Figure 29:
Typical 4-layer PCB construction
Overlapping GND layers without
GND stitching vias
erlapping GND layers with
ND stitching vias shielding the
RF energy
Figure 30:
Use of stitching vias to avoid
issions from the edges of the PCB
Silicon Labs
Page 47 of 63
11.3 Example Application Schematics
Fig
e 31: Example schematic with on/off button, silicon microphone and stereo speakers
Silicon Labs
Page 48 of 63
NOTE: Differential audio pro
v
i
des e
x
cellent common mode rejection and effecti
v
e
ly d
uples the
amplitude. Thus it is strongly recommendable to use differential instead of single ended
hen e
v
e
r possible
C26
2TIP
330uF/6.3V/20%/TAN/ESR
m
C28
3
1
RING
SLEEVE
J2
SJ-3523-SMT-TR
330uF/6.3V/20%/TAN/ESR
5V0
C24
1uF/X7R
1uF/X7R
MOD4
WT32I
2
1
2.2K
50V, 0.0
50
C25
AUDIO_OUT_P_LEFT
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
AUDIO_OUT_N_LEFT
AGND
C22
15pF
ON/OFF_CNTRL_FROM_HOST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
AUDIO_OUT_P_RIGHT
AUDIO_OUT_N_RIGHT
AUDIO_IN_N_LEFT
AUDIO_IN_P_LEFT
AGND
AUDIO_IN_N_RIGHT
AUDIO_IN_P_RIGH
MIC_BIAS
C20
1uF/X7R
1uF/X7R
GND
GND
GND
AIO0
AIO1
PIO0
PIO1
PIO2
PIO3
USB_DN
USB_DP
PIO9
PIO10
RXD
R12
R17
1
2
2
2
3
1
1
TIP
2
15nH
15nH
L4
L3
7.5K, 50V, 0.063W
2.2K, 50V, 0.063W
RING
C21
R15
1
SLEEVE
7.5K, 50V, 0.063W
GND
VDD_CHG
VDD_BAT
LED0
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_CS
J3
SJ-3523-SMT-TR
C19
15pF
3V3
U2
TPS79933
TXD
3V3
1
3
5
4
IN
EN
OUT
NR
GND
3V3
J1
1
2
3
4
5
6
MISO
3V3
CLK
MOSI
CSB
GND
Line le
v
e
l input can be as high as 4.37
V
p
p.
V
o
ltage di
v
i
der is used to drop this down to
below 1
V
p
p to a
v
o
id saturation of WT32 input
D1
RESET_FROM_HOST
During boot the diode will pre
v
e
nt the host pulling reset low
before the internal flash has its supply
v
o
ltage stabilised
Figure 32: Example schematic with single ended line input, single ended output and with on/off control from a host
Silicon Labs
Page 49 of 63
Figure 33: Exam
chematic for connecting external audio PA to the stereo audio output
Silicon Labs
Page 50 of 63
3V3
MOD1
WT32I
50
49
48
47
46
45
44
43
42
41
40
3
3
37
36
35
34
33
32
31
AUDIO_OU
T
_
P_LEFT
AUDIO_OU
T
_
N_LEFT
A
G
ND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
AUDIO_OU
T
_
P_RIGHT
AUDIO_OU
T
_N_RIGHT
AUDIO_IN_N_LEFT
AUDIO_IN_P_LEFT
A
G
ND
AUDIO_IN_N_RIGHT
AUDIO_IN_P_RIGH
M
I
C_BIAS
GND
GND
GND
AIO0
AIO1
PIO0
PIO1
PIO2
PIO3
USB_DN
USB_DP
PIO9
PIO10
RXD
V
3
GND
VDD_CHG
VDD_BAT
LED0
SPI_
M
O
S
I
SPI_
M
I
SO
SPI_CLK
SPI
CS
3V3
3V3
TXD
3V3
J7
D
1
2
3
4
5
6
5
4
1
2
3
VDD
MR
RST
VSS
RST
Debug header
U10
MCP1319
PIO7/I2C_SDA
PIO6/I2C_SCL
I2S_SDIN
I2S_SDOUT
I2S_WS
3V3
SW1
I2S_SCK
R38
4.7K, 50V, 0.063W, 5%
R40
3V3
4.7K, 50V, 0.063W, 5%
25
18
24
15
AVDD_DAC
DRVDD
DRVDD
MICBIAS
10
MIC1L/LINE1L
2
1
12
13
MIC2L/LINE2L
MIC2R/LINE2R
7
IOV
D
D
DVDD
32
U18
C36
1
M
,
5
0V, 0.1W, 5%
RCA_
W
H
I
TE
2
1
14
16
MIC3L/LINE3L
MIC3R/LINE3R
R46
1uF/16V/20%
C35
DV
AVSS_
AVSS_D
DRV
11
1uF/16V/20%
MIC1R/LINE1R
2
1
34
35
36
G
N
D
ND
1
M
,
5
0V, 0.1W, 5%
U15
2
2
1
1
O
U
T
IN
U9
T
L
V320A
I
C
32
RCA_RED
R49
U8
AP7313
2
1
U11
RCA_RED
C
330uF/6.3V/20%
A
N/ESR<10m
C34
2
1
A
N/ESR<10mohm
U12
RCA_WHITE
Figure 34: Example schematic with an external I2S codec
Silicon Labs
Page 51 of 63
12 Physical Dimensions
23.9 (+/-0.2) mm
Model: WT32i-A
FCC ID: QOQWT32I
IC: 5123A-BGTWT32I
KCC-CRM-BGT-WT32I
3.35 mm
Ant
R
209-JXXXXX
5.6 (+/-0.2) mm
17.9 (+/-0.1) mm
23.9 (+/-0.2) mm
Figure 35: Physical dimensions of WT32i
Silicon Labs
Page 52 of 63
Figure 36: Pin dimensions of W
i, top view
Figure 37: Recommended PCB land pattern for WT32i
Silicon Labs
Page 53 of 63
13 Soldering Recommendations
WT32i is compatible with industrial standard reflow profile for Pb-free solders. The reflow profile used is
dependent on the thermal mass of the entire populated PCB, heat transfer efficiency of the oven and
particular type of solder paste used. Consult the datasheet of particular solder paste for profile configurations.
Bluegiga Technologies will give following recommendations for soldering the module to ensure reliable solder
joint and operation of the module after soldering. Since the profile used is process and layout dependent
optimum profile should be studied case by case. Thus following recommendation should be taken as a
starting point guide.
–
–
–
Refer to technical documentations of particular solder paste for profile configurations
Avoid using more than one flow.
Reliability of the solder joint and self-alignment of the component are dependent on the solder volume.
Minimum of 150
m stencil thickness is recommended.
–
–
Aperture size of the stencil should be 1:1 with the pad size.
A low residue, “no clean” solder paste should be used due to low mounted height of the component.
Figure 38: Reference reflow profile
Silicon Labs
Page 54 of 63
14 Package
Figure 39: Carrier tape dimensions
Silicon Labs
Page 55 of 63
Figure 40: Reel dimensions
Silicon Labs
Page 56 of 63
15 Certification Guidance for an End Product Using WT32i
15.1 Bluetooth End Product Listing
The Bluetooth SIG requires for every commercially available product implementing Bluetooth technology to
listed on the Bluetooth SIG End Product Listing (EPL).
For the details on how to make the end product listing, please refer to the
Bluetooth End Product
isting Guide
15.2 CE Approval of an End-Product
When placing the CE logo to an end-product the manufacturer declares that the product is in conformity with
the requirements of the R&TTE directive. The minimum requirements for placing the CE logo to an end-
product are
•
Declaration of Conformity signed by the manufacturer. The perso
who signs the DoC must be
traceable
•
Generation of a technical construction file including
o
Technical information about the product
o
Test reports for all the relevant standards required to demonstrate that the product meets the
requirements of the R&TTE directive
The end-product manufacturer is fully responsible f
r the compliance of the end-product. The modules test
reports can partly be used to demonstrate the com
iance but typically all the radiated tests must be r
e
-tested
with the end product. All the conducted RF te
an be inherited from the modules test reports because the
conducted RF characteristics are not dependen
the installation of the module.
Modules test
results can be
inherited to the
end product test
report
Tested with
the module
Test required for
the end product
Standard
Description
Module fully
tested
EN 300 328
RF emissions
Radiated test cases
Yes (partly)
All the test cases
relevant for the end
product
EN 301 489-1
EN 301 489-17
EMC immunity and
emissions
Only EM field
immunity tested
No
Not tested. The
module is
Evaluation required
in case of multiple
radios in co-
compliant
Human exposure to
EM fields
EN 62479
EN 60950
without testing
because the TX
power is less
than 20 mW
Not tested
No
No
location.
because there
aren’t any test
cases that
Full evaluation with
the end product
Safety
would concern
the module
Table 23: CE standards summary for WT32i
Silicon Labs
Page 57 of 63
Note: Because all the radiated emissions must be tested with the end product in any case and because the
end product manufacturer is fully responsible for the compliance of the end product, any antenna can be
selected for WT32i-E, not just the antenna type that Bluegiga has used in the CE approvals.
15.3 FCC Certification of an End Product
In FCC there are three different levels of product authorization:
•
VERIFICATION
o
Required for digital devices. The end product manufacturer verifies device to FCC rules by
performing the required tests and maintains the records in case of questions
•
DECLARATION OF CONFORMITY
o
Required for computer peripherals and receivers. The product man
urer tests the
emissions in a FCC recognized lab according to the relevant standards, maintains the records
in case of questions and creates DoC which is supplied with the device. FCC logo must be
placed on the product. The information about the DoC is shown in the user manual
•
CERTIFICATION
o
Required for most of the radio products. The radio has i
s own FCC ID and gets listed in FCC
product.
When using modular certified module, re-certification with the
product is not needed provided that the
conditions shown in the modules grant are fulfilled. The end pr
ct manufacturer is still responsible for the
DoC or the Verification of the end product as required.
The limitations and restrictions related to the modular c
ication of WT32i are described in the FCC grant of
the module. If the conditions mentioned in the grant
re met, then only labelling the end product with
“Contains: QOQWT32I” is r
equired.
If the conditions are not met, then there are thr
ptions to remove the restriction for the end product:
•
Class 2 Permissive Change
o
Can be done either by
egiga or an agent authorized by Bluegiga.
o
The FCC ID of WT32i remains unchanged and the end product labelling requirements do not
change
•
Change of ID
o
Can be done by authorization of Bluegiga
o
The FC
D of WT32i is changed.
o
The end product is labelled according to the new FCC ID of the module (“Contains:
XXXYYYY”)
o
NOTE: Bluegiga will not deliver modules with custom labelling.
New certification of the end product
•
o
Done by the end product manufacturer
o
Test reports of the module can be used to reduce the amount of testing
When using WT32i-E, only the antenna types approved with the module can be used. WT32i-E is certified
with a standard 2 dBi dipole. Any other type of antenna will require authorisation either through C2PC,
Change of ID or new certification.
Silicon Labs
Page 58 of 63
15.3.1 Co-location
with Other Transmitters
Co-location means co-transmission, not physical co-location. The radios are not considered to be in colocation
when the physical separation is more than 20 cm or if the transmissions overlap less than 30 seconds.
When two or more radios are in co-location human exposure must be evaluated as the sum of TX powers
from all the radios transmitting simultaneously. The FCC grant of WT32i does not allow co-location so it wil
require authorization through C2PC, Change of ID or a new certification.
15.4 IC Certification of an End Product
IC certification is much like FCC. In IC there are two types of product authorizations:
•
•
Verification
Certification
When using a modular certified WT32i all that is needed, provided that WT32i is the only radio in the design,
is labelling the end product with “Contains IC: 5123ABGTWT32I”. Th
e responsibility for the radio certification
remains with Bluegiga but the end product manufacturer is still responsible for
e verification of the remaining
parts of the product.
Two main differences that are good to be aware of are:
•
•
If the TX power is less than 20 mW human exposure evalua
ion is not required
The test reports are valid for 1 year from the certification
15.5 MIC Japan Certification of an End
duct
WT32i has MIC Japan type certification and i
can be used directly in the end product without need for
recertification of the end product. Currently the
ren’t any labelling requirements for an end product using a
certified module but it is recommended to place some indication to the product that it contains certified radio
module.
16 WT32i Certifications
16.1 Bluetooth
WT32i is qualified
Bluetooth 3.0 Controller Subsystem with QDID 49552. By combining with a
prequalified Host Subs
tem WT32i will make a complete Bluetooth end product without any further testing.
Listing an end product will require purchasing a declaration ID from Bluetooth SIG. Declaration ID is required
only for certa
combination
of QDID’s and it is only needed to pay once. After receiving the declaration ID
,
multipl
oducts can be listed with the same combination of QDID’s
under the same declaration ID. If one of
the QD
’s under the Declaration ID is changed, then new declaration ID will be required.
.2 CE
WT32i is in conformity with the essential requirements and other relevant requirements of the R&TTE
Directive (1999/5/EC). The product is conformity with the following standards and/or normative documents.
•
•
EMC (immunity only) EN 301 489-17 V2.1.1
Radiated emissions EN 300 328 V1.8.1
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•
Safety EN60950-1:2006+A11:2009+A1:2010+A12:2011
16.3 FCC
WT32i complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) this device may not cause harmful interference, and
(2) this device must accept any interference received, including interference
hat may
cause undesired operation.
Any changes or modifications not expressly approved by Bluegiga Technolo
ould void the
user’s authority to operate the equipment.
FCC RF Radiation Exposure Statement:
This equipment complies with FCC radiation exposure limits set forth for an un
ont
olled environment. End
users must follow the specific operating instructions for satisfying RF exposure compliance. This transmitter
meets both portable and mobile limits as demonstrated in the RF Exposure Analysis. This transmitter must not
be co-located or operating in conjunction with any other antenna or transmitter except in accordance with FCC
multi-transmitter product procedures.
OEM Responsibilities to comply with FCC Regulations
The WT32i module has been certified for integration int
ducts only by OEM integrators under the following
condition:
•
The transmitter module must not be co
cated or operating in conjunction with any other antenna or
transmitter except in accordance with F
multi-transmitter product procedures.
As long as the two conditions above are met, further transmitter testing will not be required. However, the
OEM integrator is still responsible fo
sting their end-product for any additional compliance requirements
required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.).
IMPORTANT NOTE:
In the event that these conditions can not be met (for certain configurations or co-
location with another transmitter), then the FCC and Industry Canada authorizations are no longer considered
valid and the FCC ID and IC Certification Number can not be used on the final product. In these
circumstances, the
integrator will be responsible for re-evaluating the end product (including the
transmitter) and obtaining a separate FCC and Industry Canada authorization.
If deta
ble antennas are used:
This radio transmitter has been approved by FCC to operate with a 2.7 dBi dipole antenna. Any antenna of the
same type and with equal or less gain can be used with WT32i-E without retesting. Antennas of a different
type or higher gain will require authorization from FCC.
End Product Labeling
The WT32i module is labeled with its own FCC ID. If the FCC ID is not visible when the module is installed
inside another device, then the outside of the device into which the module is installed must also display a
label referring to the enclosed module.
In that case, the final end product must be labeled in a visible area
with the following:
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Page 60 of 63
“
Contains Transmitter Module FCC ID: QOQWT32I
”
or
“
Contains FCC ID: QOQWT32I
”
The OEM integrator has to be aware not to provide information to the end user regarding how to inst
remove this RF module or change RF related parameters in the user manual of the end product
16.4 IC
IC Statements:
WT32i complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following
two conditions: (1) this device may not cause interference, and (2) this devic
must accept any interference,
including interference that may cause undesired operation of the device.
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and
maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio
interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically
radiated power (e.i.r.p.) is not more than that necessary for succ
ul communication.
End Product Labeling
The WT32i module is labeled with its own IC Certif
tion Number. If the IC Certification Number is not visible
when the module is installed inside another device
then the outside of the device into which the module is
installed must also display a label referring to
enclosed module.
In that case, the final end product must
be labeled in a visible area with the following:
“
Contains Transmitter Module IC: 5123A-BGTWT32I
”
or
“
Contains IC: 5123A-BGTWT32I
”
The OEM integrator
to be aware not to provide information to the end user regarding how to install or
remove this RF module or change RF related parameters in the user manual of the end product
If deta
ble antennas are used:
This radio transmitter (identify the device by certification number, or model number ifCategory II) has been
approved by Industry Canada to operate 2.7 dBi dipole antenna. Antenna types other than this, having a gain
eater than 2.7 dBi, are strictly prohibited for use with this device.
16.4.1 IC
Déclaration d’IC
:
Ce dispositif est conforme aux normes RSS exemptes de licence d’Industrie Canada. Son fonctionnement est
assujetti aux deux conditions suivantes : (1) ce dispositif ne doit pas provoquer de perturbation et (2) ce
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Page 61 of 63
dispositif doit accepter toute perturbation, y compris les perturbations qui peuvent entraîner un fonctionnement
non désiré du dispositif.
Selon les
réglementations d’Industrie Canada, cet émetteur radio ne doit fonctionner qu’avec une antenne
d’une typologie spécifique et d’un gain maximum (ou inférieur) approuvé pour l’émetteur par Industrie
Canada. Pour réduire les éventuelles perturbations radioélectriques nuisibles à d’autres utilisateurs, le type
d’antenne et son gain doivent être choisis de manière à ce que la puissance isotrope rayonnée équivalente
(P.I.R.E.) n’excède pas les valeurs nécessaires pour obtenir une communication convenable.
Étiqu
etage du produit final
Le module WT32I
est étiqueté avec sa propre identification FCC et son propre numéro de cert
ation IC. Si
l’identification FCC et le numéro de certification IC ne sont pas visibles lorsque le m
le est installé à
l’intérieur d’un autre dispositif, la partie externe du dispositif dans lequel le modu
installé devra
également présenter une étiquette faisant référence au module inclus. Dans ce cas, le prod
final devra être
étiqueté sur une zone visible avec les informations su
ivantes :
« Contient module émetteur IC
: 5123A-BGTWT32I
»
ou
«
Contient IC : 5123A-BGTWT32I
»
Dans le guide d’utilisation du produit final, l’intégrateur OEM
s’abstenir de fournir des informations à
l’utilisateur final portant sur les procédures à
suivre pour installer ou retirer ce module RF ou pour changer les
paramètres RF.
16.5 MIC Japan
WT32i is has MIC Japan type approval with certification number 209-J00089. WT32i is certified as a module
and it can be integrated into an end
duct without a need for additional MIC radio certification of the end
product.
16.6 KCC (South-Korea)
WT32i has modular certification in South-Korea with certification ID MSIP-CRM-BGT-WT32i
16.
7
Q
ualified Antenna Types for WT32i-E
This device h
s been designed to operate with a 2.7 dBi dipole antenna.
Any antenna of the same type and
the sa
r less gain can be used without additional application to FCC.
Silicon Labs
Page 62 of 63
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Disclaimer
Silicon Labs intends to provide customers wit
e latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs prod
cts. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and “Typical”
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice to the pro
information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information.
Without prior notification,
on L
bs may update product firmware during the manufacturing process for security or reliability reasons.
Such changes will not alter the specifications or the
performance of the pro
Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant
any license to design or
bricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket
approval is required or Life Support Systems without the specific written consent of Silicon Labs. A “Life Support System” is any product or system intended to support or sustain life and/or
health, which, if i
ails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon
Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering
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con Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such
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