STMicroelectronics-EMIF06-1005M12
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EMIF06-1005M12
6-line I
P
A
D™
low capacitance EMI filter and ESD protection in micro QFN package
Features
12
11
1
2
■
EMI symmetrical (I/O) low-pass filter
■
High efficiency in EMI filtering: -34 dB at
10
9
3
4
5
6
GND
frequencies from 900 MHz to 1.8 GHz
■
Very low PCB space consumption:
8
2.5 mm x 1.5 mm
7
■
Very thin package: 0.6 mm max
Micro QFN 2.5 mm x 1.5 mm
(bottom view)
■
High efficiency in ESD suppression on inputs
pins (IEC 61000-4-2 level 4)
■
High reliability offered by monolithic integration
Figure 1.
Pin configuration (top view)
■
High reduction of parasitic elements through
1 Input
Output 12
Output 11
Output 10
Output 9
Output 8
Output 7
integration and wafer level packaging
■
Lead-free package
2 Input
Complies with following standards:
3 Input
4 Input
5 Input
6 Input
■
IEC 61000-4-2 level 4 input and output pins
– 15
kV (air discharge)
– 8
kV (contact discharge)
■
MIL STD 883G – Method 3015-7 Class 3B
(all pins)
Applications
Where EMI filtering in ESD sensitive equipment is
required:
Figure 2.
Basic cell configuration
■
LCD and camera for mobile phones
■
Computers and printers
■
Communication systems
■
MCU boards
100
Ω
Input
Output
Description
Typical line capacitance = 45 pF @ 0 V
EMIF06-1005M12 is a 6-line, highly integrated
device designed to suppress EMI/RFI noise in all
systems exposed to electromagnetic interference.
This filter includes ESD protection circuitr
y
,
w
hich
prevents damage to the application when
subjected to ESD surges up to 15 kV on the input
pins.
TM: IPAD is a trademark of STMicroelectronics
February 2008
Rev 3
1/10
Characteristics
EMIF06-1005M12
1
Characteristics
Table 1.
Symbol
Absolute ratings (limiting values at T
= 25 °C unless otherwise specified)
amb
Parameter
Value
Unit
ESD IEC 61000-4-2, air discharge
ESD IEC 61000-4-2, contact discharge
15
15
V
PP
kV
T
j
Junction temperature
125
°C
°C
°C
T
op
T
stg
Operating temperature range
Storage temperature range
-40 to + 85
-55 to +150
Table 2.
Symbol
Electrical characteristics (T
= 25 °C)
amb
Parameter
I
V
BR
I
RM
V
RM
V
CL
R
d
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
I
F
V
BR
V
CL
V
F
V
RM
Clamping voltage
V
I
RM
I
R
Dynamic resistance
Peak pulse current
I
PP
R
I/O
C
line
Series resistance between Input & Output
Input capacitance per line
I
PP
Symbol
V
BR
Test conditions
Min.
Typ.
Max.
Unit
I
R
= 1 mA
6
8
10
1.5
200
110
52
V
V
F
I
RM
I
F
= 10 mA
0.5
1.0
V
RM
= 3 V per line
T
o
lerance 10ꢀ
nA
Ω
R
I/O
C
line
90
38
100
45
V
LINE
= 0 V dc, V
OSC
= 30 m
V
, F = 1
M
Hz
pF
Figure 3.
S21 attenuation measurement
Figure 4.
Analog cross talk measurements
dB
dB
0.00
– 10.00
– 20.00
– 30.00
– 40.00
– 50.00
– 60.00
– 70.00
– 80.00
– 90.00
– 100.00
0.00
–
1
0.00
–
2
0.00
–
3
0.00
–
4
0.00
F (Hz)
F (Hz)
100.0k
1.0M
10.0M
100.0M
1.0G
1.0M 3.0M 10.0M
30.0M 100.0M
300.0M 1.0G
3.0G
2/10
EMIF06-1005M12
Ordering information scheme
Figure 5.
ESD response to IEC 61000-4-2
(+15 kV air discharge) on one input
(V )
and on one output (V
Figure 6.
ESD response to IEC 61000-4-2
(- 15 kV air discharge) on one input
)
(V )
and on one output (V
)
in
out
in
out
Figure 7.
Line capacitance versus reverse voltage applied (typical value)
C
LINE
(pF)
50.00
45.00
40.00
35.00
30.00
25.00
20.00
15.00
10.00
5.00
0.00
V
LINE
(V)
0
1
2
3
4
5
2
Ordering information scheme
Figure 8.
Ordering information scheme
EMIF yy
–
xxx z
Mx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
Package
Mx =
Micro QFN x leads
3/10
Package information
EMIF06-1005M12
3
Package information
●
Epoxy meets UL94, V0
®
In order to meet environmental requirements, ST offers these devices in ECO
P
A
CK
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECO
P
A
CK is an ST trademark. ECO
P
A
CK specifications are available at
Table 3.
QFN 2.5 x 1.5 package dimensions
Dimensions
Millimeters
D
N
Ref
inches
E
MIN TYP
MAX MIN TYP MAX
A
A1
b
0.50 0.55 0.60 0.20 0.22 0.24
0.00 0.02 0.05 0.00 0.01 0.02
0.15 0.18 0.25 0.06 0.07 0.10
1
2
A
A1
D
2.50
1.70 1.80 1.90 0.67 0.71 0.75
1.50 0.59
0.30 0.40 0.50 0.12 0.16 0.24
0.40 0.16
0.98
D2
D2
E
1
2
L
k
E2
e
E2
N
b
k
0.20
0.08
e
L
0.25 0.30 0.35 0.10 0.12 0.14
Figure 9.
Footprint
Figure 10.
Marking
0.40
0.20
Dot: Pin 1
Identification
X = Marking
YWW= Data code
(Y=year
0.60
0.25
0.40
2.10
WW= week
XY
ww
1.80
4/10
EMIF06-1005M12
Figure 11.
Tape and reel specification
Package information
4.00+/-0.1
f
1.5 +/- 0.1
2.0+/-0.05
XY
ww
XY
ww
XY
ww
1.70
4.00
0.75
User direction of unreeling
Note:
Product marking may be rotated by 90° for assembly plant differentiation. In no case should
this product marking be used to orient the component for its placement on a PCB. Only pin 1
mark is to be used for this purpose.
5/10
Recommendation on PCB assembly
EMIF06-1005M12
4
Recommendation on PCB assembly
4.1
Stencil opening design
1. General
recommendation on stencil opening design
a) Stencil
opening dimensions: L (Length), W (Width), T (Thickness).
Figure 12.
Stencil opening dimensions
L
T
W
b) General
design rule
Stencil thickness (T) = 75 ~ 125 µm
W
—
–
–
Aspect Ratio =
≥
1.5
T
L
×
W
—————————
Aspect Area
=
≥
0.66
2T
(
L + W
)
2. Reference
design
a) Stencil
opening thickness: 100 µm
b) Stencil
opening for central exposed pad: Opening to footprint ratio is 50ꢀ.
c) Stencil
opening for leads: Opening to footprint ratio is 90ꢀ.
Figure 13.
Recommended stencil window position
5 µm
5 µm
15 µm
0.40
0.20
0.60
0.25
190 µm
200 µm
15 µm
0.40
2.10
1800 µm
50 µm
50 µm
1.80
400 µm
1224 µm
Footprint
Stencil window
Footprint
288 µm
288 µm
6/10
EMIF06-1005M12
Recommendation on PCB assembly
4.2
Solder paste
1. Halide-free
flux qualification ROL0 according to ANSI/J-STD-004.
2. “No
clean” solder paste is recommended.
3. Offers
a high tack force to resist component movement during high speed
4. Solder
paste with fine particles: powder particle size is 20-45 µm.
4.3
Placement
1. Manual
positioning is not recommended.
2. It
is recommended to use the lead recognition capabilities of the placement system, not
the outline centering
3. Standard
tolerance of
0.05 mm is recommended.
4. 3.5
N placement force is recommended.
T
o
o much placement force can lead to
squeezed out solder paste and cause solder joints to short.
T
o
o low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
T
o
i
mprove the package placement accurac
y
, a
b
ottom side optical control should be
performed with a high resolution tool.
6. For
assembl
y
, a
p
erfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
4.4
PCB design preference
1.
T
o
c
ontrol the solder paste amount, the closed via is recommended instead of open
vias.
2. The
position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow awa
y
.
7/10
Recommendation on PCB assembly
EMIF06-1005M12
4.5
Reflow profile
Figure 14.
ST ECO
P
ACK® recommended soldering reflow profile for PCB mounting
Temperature (°C)
260°C max
255°C
220°C
180°C
2°C/s recommended
125 °C
6°C/s max
3°C/s max
0
0
1
2
3
4
5
6
7
Time (min)
10-30 sec
90 to 150 sec
90 sec max
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
8/10
EMIF06-1005M12
Ordering information
5
Ordering information
Table 4.
Ordering information
Order code
Marking
Package
Micro QFN
Weight
Base qty
3000
Delivery mode
EMIF06-1005M12
F
(1)
6 mg
T
a
pe and reel (7”)
1. The
marking can be rotated by 90° to differentiate assembly location
6
Revision history
Table 5.
Date
Document revision history
Revision
Changes
3-Jul-2006
1-Feb-2007
1
2
Initial release.
Added note on marking rotation in section 3. Package information.
Reformatted to current standards. Updated ECO
P
A
CK statement.
04-Feb-2008
3
9/10
EMIF06-1005M12
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